# HG changeset patch # User pellion # Date 2015-01-15 15:45:13 # Node ID 5ac3ea1d915fba7fcf883e5fb60e0463d5a4ffc6 # Parent 6448706d4a4ecf65b04a0dc806f36ad0235c9440 (MINI-LFR) WFP_MS_0-1-39 => Correction of the time of waveform picker's buffer diff --git a/designs/MINI-LFR_WFP_MS/testbench.vhd b/designs/MINI-LFR_WFP_MS/testbench.vhd --- a/designs/MINI-LFR_WFP_MS/testbench.vhd +++ b/designs/MINI-LFR_WFP_MS/testbench.vhd @@ -202,6 +202,7 @@ BEGIN X"4000D000"); UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); + UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); message_simu <= "4 - GO GO GO !!"; UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -188,6 +188,8 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + BEGIN -- beh ----------------------------------------------------------------------------- @@ -429,12 +431,15 @@ BEGIN -- beh IF run = '0' THEN fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); ELSE - IF arbiter_time_out_new(I) = '0' THEN + IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; END IF; END IF; END IF; END PROCESS; + + fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE + fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); lpp_waveform_fsmdma_I: lpp_waveform_fsmdma PORT MAP ( @@ -442,7 +447,7 @@ BEGIN -- beh rstn => rstn, run => run, - fifo_buffer_time => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I), + fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I), fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), fifo_empty => empty(I),