| @@ -1,435 +1,436 | |||||
| 1 | VHDLIB=../.. |
|
1 | VHDLIB=../.. | |
| 2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
2 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
| 3 |
|
3 | |||
| 4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
| 5 | TOP=TB |
|
5 | TOP=TB | |
| 6 |
|
6 | |||
| 7 | CMD_VLIB=vlib |
|
7 | CMD_VLIB=vlib | |
| 8 | CMD_VMAP=vmap |
|
8 | CMD_VMAP=vmap | |
| 9 | CMD_VCOM=@vcom -quiet -93 -work |
|
9 | CMD_VCOM=@vcom -quiet -93 -work | |
| 10 |
|
10 | |||
| 11 | ################## project specific targets ########################## |
|
11 | ################## project specific targets ########################## | |
| 12 |
|
12 | |||
| 13 | all: |
|
13 | all: | |
| 14 | @echo "make vsim" |
|
14 | @echo "make vsim" | |
| 15 | @echo "make libs" |
|
15 | @echo "make libs" | |
| 16 | @echo "make clean" |
|
16 | @echo "make clean" | |
| 17 | @echo "make vcom_grlib vcom_lpp vcom_tb" |
|
17 | @echo "make vcom_grlib vcom_lpp vcom_tb" | |
| 18 |
|
18 | |||
| 19 | run: |
|
19 | run: | |
| 20 | @vsim work.TB -do run.do |
|
20 | @vsim work.TB -do run.do | |
| 21 | # @vsim work.TB |
|
21 | # @vsim work.TB | |
| 22 | # @vsim lpp.lpp_lfr_ms |
|
22 | # @vsim lpp.lpp_lfr_ms | |
| 23 |
|
23 | |||
| 24 | vsim: libs vcom run |
|
24 | vsim: libs vcom run | |
| 25 |
|
25 | |||
| 26 | libs: |
|
26 | libs: | |
| 27 | @$(CMD_VLIB) modelsim |
|
27 | @$(CMD_VLIB) modelsim | |
| 28 | @$(CMD_VMAP) modelsim modelsim |
|
28 | @$(CMD_VMAP) modelsim modelsim | |
| 29 | @$(CMD_VLIB) modelsim/techmap |
|
29 | @$(CMD_VLIB) modelsim/techmap | |
| 30 | @$(CMD_VMAP) techmap modelsim/techmap |
|
30 | @$(CMD_VMAP) techmap modelsim/techmap | |
| 31 | @$(CMD_VLIB) modelsim/grlib |
|
31 | @$(CMD_VLIB) modelsim/grlib | |
| 32 | @$(CMD_VMAP) grlib modelsim/grlib |
|
32 | @$(CMD_VMAP) grlib modelsim/grlib | |
| 33 | @$(CMD_VLIB) modelsim/gaisler |
|
33 | @$(CMD_VLIB) modelsim/gaisler | |
| 34 | @$(CMD_VMAP) gaisler modelsim/gaisler |
|
34 | @$(CMD_VMAP) gaisler modelsim/gaisler | |
| 35 | @$(CMD_VLIB) modelsim/work |
|
35 | @$(CMD_VLIB) modelsim/work | |
| 36 | @$(CMD_VMAP) work modelsim/work |
|
36 | @$(CMD_VMAP) work modelsim/work | |
| 37 | @$(CMD_VLIB) modelsim/lpp |
|
37 | @$(CMD_VLIB) modelsim/lpp | |
| 38 | @$(CMD_VMAP) lpp modelsim/lpp |
|
38 | @$(CMD_VMAP) lpp modelsim/lpp | |
| 39 | @echo "libs done" |
|
39 | @echo "libs done" | |
| 40 |
|
40 | |||
| 41 |
|
41 | |||
| 42 | clean: |
|
42 | clean: | |
| 43 | @rm -Rf modelsim |
|
43 | @rm -Rf modelsim | |
| 44 | @rm -Rf modelsim.ini |
|
44 | @rm -Rf modelsim.ini | |
| 45 | @rm -Rf *~ |
|
45 | @rm -Rf *~ | |
| 46 | @rm -Rf transcript |
|
46 | @rm -Rf transcript | |
| 47 | @rm -Rf wlft* |
|
47 | @rm -Rf wlft* | |
| 48 | @rm -Rf *.wlf |
|
48 | @rm -Rf *.wlf | |
| 49 | @rm -Rf vish_stacktrace.vstf |
|
49 | @rm -Rf vish_stacktrace.vstf | |
| 50 | @rm -Rf libs.do |
|
50 | @rm -Rf libs.do | |
| 51 |
|
51 | |||
| 52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb |
|
52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb | |
| 53 |
|
53 | |||
| 54 |
|
54 | |||
| 55 | vcom_tb: |
|
55 | vcom_tb: | |
| 56 | ## $(CMD_VCOM) lpp lpp_memory.vhd |
|
56 | ## $(CMD_VCOM) lpp lpp_memory.vhd | |
| 57 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd |
|
57 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd | |
| 58 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd |
|
58 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd | |
| 59 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
|
59 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd | |
| 60 | $(CMD_VCOM) work TB.vhd |
|
60 | $(CMD_VCOM) work TB.vhd | |
| 61 | @echo "vcom done" |
|
61 | @echo "vcom done" | |
| 62 |
|
62 | |||
| 63 | vcom_grlib: |
|
63 | vcom_grlib: | |
| 64 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd |
|
64 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd | |
| 65 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd |
|
65 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd | |
| 66 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd |
|
66 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd | |
| 67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd |
|
67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd | |
| 68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd |
|
68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd | |
| 69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd |
|
69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd | |
| 70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd |
|
70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd | |
| 71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd |
|
71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd | |
| 72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd |
|
72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd | |
| 73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd |
|
73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd | |
| 74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd |
|
74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd | |
| 75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd |
|
75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd | |
| 76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd |
|
76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd | |
| 77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd |
|
77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd | |
| 78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd |
|
78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd | |
| 79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd |
|
79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd | |
| 80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd |
|
80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd | |
| 81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd |
|
81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd | |
| 82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd |
|
82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd | |
| 83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd |
|
83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd | |
| 84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd |
|
84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd | |
| 85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd |
|
85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd | |
| 86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd |
|
86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd | |
| 87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd |
|
87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd | |
| 88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd |
|
88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd | |
| 89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd |
|
89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd | |
| 90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd |
|
90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd | |
| 91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd |
|
91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd | |
| 92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd |
|
92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd | |
| 93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd |
|
93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd | |
| 94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd |
|
94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd | |
| 95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd |
|
95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd | |
| 96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd |
|
96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd | |
| 97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd |
|
97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd | |
| 98 | @echo "vcom grlib done" |
|
98 | @echo "vcom grlib done" | |
| 99 |
|
99 | |||
| 100 | vcom_gaisler: |
|
100 | vcom_gaisler: | |
| 101 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd |
|
101 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd | |
| 102 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd |
|
102 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd | |
| 103 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd |
|
103 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd | |
| 104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd |
|
104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd | |
| 105 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd |
|
105 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd | |
| 106 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd |
|
106 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd | |
| 107 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd |
|
107 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd | |
| 108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd |
|
108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd | |
| 109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd |
|
109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd | |
| 110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd |
|
110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd | |
| 111 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd |
|
111 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd | |
| 112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd |
|
112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd | |
| 113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd |
|
113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd | |
| 114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd |
|
114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd | |
| 115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd |
|
115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd | |
| 116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd |
|
116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd | |
| 117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd |
|
117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd | |
| 118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd |
|
118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd | |
| 119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd |
|
119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd | |
| 120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd |
|
120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd | |
| 121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd |
|
121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd | |
| 122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd |
|
122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd | |
| 123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd |
|
123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd | |
| 124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd |
|
124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd | |
| 125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd |
|
125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd | |
| 126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd |
|
126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd | |
| 127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd |
|
127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd | |
| 128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd |
|
128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd | |
| 129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd |
|
129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd | |
| 130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd |
|
130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd | |
| 131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd |
|
131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd | |
| 132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd |
|
132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd | |
| 133 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd |
|
133 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd | |
| 134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd |
|
134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd | |
| 135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd |
|
135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd | |
| 136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd |
|
136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd | |
| 137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd |
|
137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd | |
| 138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd |
|
138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd | |
| 139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd |
|
139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd | |
| 140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd |
|
140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd | |
| 141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd |
|
141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd | |
| 142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd |
|
142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd | |
| 143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd |
|
143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd | |
| 144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd |
|
144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd | |
| 145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd |
|
145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd | |
| 146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd |
|
146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd | |
| 147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd |
|
147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd | |
| 148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd |
|
148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd | |
| 149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd |
|
149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd | |
| 150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd |
|
150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd | |
| 151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd |
|
151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd | |
| 152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd |
|
152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd | |
| 153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd |
|
153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd | |
| 154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd |
|
154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd | |
| 155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd |
|
155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd | |
| 156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd |
|
156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd | |
| 157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd |
|
157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd | |
| 158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd |
|
158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd | |
| 159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd |
|
159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd | |
| 160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd |
|
160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd | |
| 161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd |
|
161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd | |
| 162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd |
|
162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd | |
| 163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd |
|
163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd | |
| 164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd |
|
164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd | |
| 165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd |
|
165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd | |
| 166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd |
|
166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd | |
| 167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd |
|
167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd | |
| 168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd |
|
168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd | |
| 169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd |
|
169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd | |
| 170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd |
|
170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd | |
| 171 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd |
|
171 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd | |
| 172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd |
|
172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd | |
| 173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd |
|
173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd | |
| 174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd |
|
174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd | |
| 175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd |
|
175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd | |
| 176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd |
|
176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd | |
| 177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd |
|
177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd | |
| 178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd |
|
178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd | |
| 179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd |
|
179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd | |
| 180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd |
|
180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd | |
| 181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd |
|
181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd | |
| 182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd |
|
182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd | |
| 183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd |
|
183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd | |
| 184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd |
|
184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd | |
| 185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd |
|
185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd | |
| 186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd |
|
186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd | |
| 187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd |
|
187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd | |
| 188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd |
|
188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd | |
| 189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd |
|
189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd | |
| 190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd |
|
190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd | |
| 191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd |
|
191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd | |
| 192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd |
|
192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd | |
| 193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd |
|
193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd | |
| 194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd |
|
194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd | |
| 195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd |
|
195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd | |
| 196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd |
|
196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd | |
| 197 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd |
|
197 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd | |
| 198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd |
|
198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd | |
| 199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd |
|
199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd | |
| 200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd |
|
200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd | |
| 201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd |
|
201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd | |
| 202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd |
|
202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd | |
| 203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd |
|
203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd | |
| 204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd |
|
204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd | |
| 205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd |
|
205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd | |
| 206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd |
|
206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd | |
| 207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd |
|
207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd | |
| 208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd |
|
208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd | |
| 209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd |
|
209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd | |
| 210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd |
|
210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd | |
| 211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd |
|
211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd | |
| 212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd |
|
212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd | |
| 213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd |
|
213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd | |
| 214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd |
|
214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd | |
| 215 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd |
|
215 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd | |
| 216 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd |
|
216 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd | |
| 217 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd |
|
217 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd | |
| 218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd |
|
218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd | |
| 219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd |
|
219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd | |
| 220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd |
|
220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd | |
| 221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd |
|
221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd | |
| 222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd |
|
222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd | |
| 223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd |
|
223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd | |
| 224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd |
|
224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd | |
| 225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd |
|
225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd | |
| 226 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd |
|
226 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd | |
| 227 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd |
|
227 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd | |
| 228 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd |
|
228 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd | |
| 229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd |
|
229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd | |
| 230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd |
|
230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd | |
| 231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd |
|
231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd | |
| 232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd |
|
232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd | |
| 233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd |
|
233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd | |
| 234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd |
|
234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd | |
| 235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd |
|
235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd | |
| 236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd |
|
236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd | |
| 237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd |
|
237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd | |
| 238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd |
|
238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd | |
| 239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd |
|
239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd | |
| 240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd |
|
240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd | |
| 241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd |
|
241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd | |
| 242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd |
|
242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd | |
| 243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd |
|
243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd | |
| 244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd |
|
244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd | |
| 245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd |
|
245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd | |
| 246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd |
|
246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd | |
| 247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd |
|
247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd | |
| 248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd |
|
248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd | |
| 249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd |
|
249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd | |
| 250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd |
|
250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd | |
| 251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd |
|
251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd | |
| 252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd |
|
252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd | |
| 253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd |
|
253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd | |
| 254 | @echo "vcom gaisler done" |
|
254 | @echo "vcom gaisler done" | |
| 255 |
|
255 | |||
| 256 | vcom_techmap: |
|
256 | vcom_techmap: | |
| 257 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd |
|
257 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd | |
| 258 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd |
|
258 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd | |
| 259 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd |
|
259 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd | |
| 260 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd |
|
260 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd | |
| 261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd |
|
261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd | |
| 262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd |
|
262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd | |
| 263 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd |
|
263 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd | |
| 264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd |
|
264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd | |
| 265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd |
|
265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd | |
| 266 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd |
|
266 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd | |
| 267 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd |
|
267 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd | |
| 268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd |
|
268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd | |
| 269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd |
|
269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd | |
| 270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd |
|
270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd | |
| 271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd |
|
271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd | |
| 272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd |
|
272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd | |
| 273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd |
|
273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd | |
| 274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd |
|
274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd | |
| 275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd |
|
275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd | |
| 276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd |
|
276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd | |
| 277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd |
|
277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd | |
| 278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd |
|
278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd | |
| 279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd |
|
279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd | |
| 280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd |
|
280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd | |
| 281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd |
|
281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd | |
| 282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd |
|
282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd | |
| 283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd |
|
283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd | |
| 284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd |
|
284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd | |
| 285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd |
|
285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd | |
| 286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd |
|
286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd | |
| 287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd |
|
287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd | |
| 288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd |
|
288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd | |
| 289 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd |
|
289 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd | |
| 290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd |
|
290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd | |
| 291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd |
|
291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd | |
| 292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd |
|
292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd | |
| 293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd |
|
293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd | |
| 294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd |
|
294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd | |
| 295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd |
|
295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd | |
| 296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd |
|
296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd | |
| 297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd |
|
297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd | |
| 298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd |
|
298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd | |
| 299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd |
|
299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd | |
| 300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd |
|
300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd | |
| 301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd |
|
301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd | |
| 302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd |
|
302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd | |
| 303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd |
|
303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd | |
| 304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd |
|
304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd | |
| 305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd |
|
305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd | |
| 306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd |
|
306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd | |
| 307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd |
|
307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd | |
| 308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd |
|
308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd | |
| 309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd |
|
309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd | |
| 310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd |
|
310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd | |
| 311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd |
|
311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd | |
| 312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd |
|
312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd | |
| 313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd |
|
313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd | |
| 314 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd |
|
314 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd | |
| 315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd |
|
315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd | |
| 316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd |
|
316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd | |
| 317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd |
|
317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd | |
| 318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd |
|
318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd | |
| 319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd |
|
319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd | |
| 320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd |
|
320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd | |
| 321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd |
|
321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd | |
| 322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd |
|
322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd | |
| 323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd |
|
323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd | |
| 324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd |
|
324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd | |
| 325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd |
|
325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd | |
| 326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd |
|
326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd | |
| 327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd |
|
327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd | |
| 328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd |
|
328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd | |
| 329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd |
|
329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd | |
| 330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd |
|
330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd | |
| 331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd |
|
331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd | |
| 332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd |
|
332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd | |
| 333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd |
|
333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd | |
| 334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd |
|
334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd | |
| 335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd |
|
335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd | |
| 336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd |
|
336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd | |
| 337 | @echo "vcom techmap done" |
|
337 | @echo "vcom techmap done" | |
| 338 |
|
338 | |||
| 339 | vcom_lpp: |
|
339 | vcom_lpp: | |
| 340 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
340 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd | |
| 341 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
341 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |
| 342 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
|
342 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |
| 343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
|
343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |
| 344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
|
344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |
| 345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
|
345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |
| 346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
| 347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
| 348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
| 349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
| 350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
| 351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
| 352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
| 353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
| 354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
| 355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
| 356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
| 357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
| 358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
| 359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
| 360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
| 361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
| 362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
| 363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
| 364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
| 365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
| 366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
| 367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
| 368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
| 369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
| 370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
| 371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |
| 372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
| 373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
| 374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |
| 375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd |
|
375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |
| 376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
| 377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd |
|
377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |
| 378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd |
|
378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |
| 379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd |
|
379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |
| 380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd |
|
380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |
| 381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd |
|
381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |
| 382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
| 383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd |
|
383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |
| 384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd |
|
384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |
| 385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd |
|
385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |
| 386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd |
|
386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |
| 387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd |
|
387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |
| 388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd |
|
388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd | |
| 389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd |
|
389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd | |
| 390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd |
|
390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd | |
| 391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
|
391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd | |
| 392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd |
|
392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd | |
| 393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
|
393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |
| 394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
|
394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |
| 395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd |
|
395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd | |
| 396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd |
|
396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd | |
| 397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |
| 398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd |
|
398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd | |
| 399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
|
|
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |||
| 400 | @echo "vcom lpp done" |
|
401 | @echo "vcom lpp done" | |
| 401 |
|
402 | |||
| 402 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
403 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
| 403 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
404 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
| 404 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
405 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
| 405 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
406 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
| 406 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
| 407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
| 408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
| 409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
| 410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
| 411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
| 412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
| 413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
| 414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
| 415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
| 416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
| 417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
| 418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
| 419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
| 420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
| 421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
| 422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
| 423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
| 424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
| 425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
| 426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
| 427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
428 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
| 428 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
|
429 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |
| 429 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
|
430 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |
| 430 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
|
431 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd | |
| 431 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd |
|
432 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd | |
| 432 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd |
|
433 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd | |
| 433 | # @echo "vcom lpp done" |
|
434 | # @echo "vcom lpp done" | |
| 434 |
|
435 | |||
| 435 | #include Makefile_vcom_lpp |
|
436 | #include Makefile_vcom_lpp | |
| @@ -1,151 +1,158 | |||||
| 1 | onerror {resume} |
|
1 | onerror {resume} | |
| 2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
| 3 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen |
|
3 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen | |
| 4 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata |
|
4 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata | |
| 5 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen |
|
5 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen | |
| 6 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata |
|
6 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata | |
| 7 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen |
|
7 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen | |
| 8 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata |
|
8 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata | |
| 9 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen |
|
9 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen | |
| 10 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full |
|
10 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full | |
| 11 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full |
|
11 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full | |
| 12 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty |
|
12 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty | |
| 13 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren |
|
13 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren | |
| 14 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect |
|
14 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect | |
| 15 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect |
|
15 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect | |
| 16 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/more_16data |
|
|||
| 17 | add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
16 | add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
| 18 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen |
|
17 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen | |
| 19 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full |
|
18 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full | |
| 20 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full |
|
19 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full | |
| 21 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty |
|
20 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty | |
| 22 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren |
|
21 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren | |
| 23 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen |
|
22 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen | |
| 24 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk |
|
23 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk | |
| 25 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full |
|
24 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full | |
| 26 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full |
|
25 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full | |
| 27 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty |
|
26 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty | |
| 28 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren |
|
27 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren | |
| 29 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/more_16data |
|
|||
| 30 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull |
|
28 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull | |
| 31 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s |
|
29 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s | |
| 32 | add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
30 | add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
| 33 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen |
|
31 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen | |
| 34 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full |
|
32 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full | |
| 35 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full |
|
33 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full | |
| 36 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty |
|
34 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty | |
| 37 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren |
|
35 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren | |
| 38 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel |
|
36 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel | |
| 39 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft |
|
37 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft | |
| 40 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload |
|
|||
| 41 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im |
|
|||
| 42 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re |
|
|||
| 43 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid |
|
|||
| 44 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset |
|
|||
| 45 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart |
|
|||
| 46 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0 |
|
38 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0 | |
| 47 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1 |
|
39 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1 | |
| 48 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2 |
|
40 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2 | |
| 49 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y |
|
|||
| 50 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong |
|
|||
| 51 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy |
|
|||
| 52 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid |
|
|||
| 53 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im |
|
|||
| 54 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re |
|
|||
| 55 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray |
|
|||
| 56 | add wave -noupdate /tb/lpp_lfr_ms_1/status_channel |
|
41 | add wave -noupdate /tb/lpp_lfr_ms_1/status_channel | |
| 57 |
add wave -noupdate |
|
42 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
| 58 |
add wave -noupdate |
|
43 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
| 59 |
add wave -noupdate |
|
44 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray | |
| 60 |
add wave -noupdate |
|
45 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray | |
| 61 |
add wave -noupdate |
|
46 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray | |
| 62 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load |
|
47 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load | |
| 63 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory |
|
48 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory | |
| 64 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full |
|
49 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full | |
| 65 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty |
|
50 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty | |
| 66 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full |
|
51 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full | |
| 67 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata |
|
52 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata | |
| 68 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen |
|
53 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen | |
| 69 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked |
|
54 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked | |
| 70 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata |
|
55 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata | |
| 71 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren |
|
56 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren | |
| 72 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto |
|
57 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto | |
| 73 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done |
|
58 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done | |
| 74 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start |
|
59 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start | |
| 75 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data |
|
60 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data | |
| 76 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty |
|
61 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty | |
| 77 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren |
|
62 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren | |
| 78 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data |
|
63 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data | |
| 79 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full |
|
64 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full | |
| 80 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen |
|
65 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen | |
| 81 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1 |
|
66 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1 | |
| 82 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2 |
|
67 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2 | |
| 83 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res |
|
68 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res | |
| 84 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state |
|
69 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state | |
| 85 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty |
|
70 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty | |
| 86 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full |
|
71 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full | |
| 87 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata |
|
72 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata | |
| 88 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen |
|
73 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen | |
| 89 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect |
|
74 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect | |
| 90 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s |
|
75 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s | |
| 91 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect |
|
76 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect | |
| 92 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s |
|
77 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s | |
| 93 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray |
|
78 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
| 94 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect |
|
79 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect | |
| 95 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s |
|
80 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s | |
| 96 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect |
|
81 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect | |
| 97 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s |
|
82 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s | |
| 98 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
83 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
| 99 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 |
|
84 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 | |
| 100 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end |
|
85 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end | |
| 101 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_new |
|
|||
| 102 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 |
|
86 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 | |
| 103 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end |
|
87 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end | |
| 104 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_new |
|
|||
| 105 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready |
|
88 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready | |
| 106 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready |
|
89 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready | |
| 107 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing |
|
90 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing | |
| 108 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data |
|
91 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data | |
| 109 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty |
|
92 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty | |
| 110 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren |
|
93 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren | |
| 111 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status |
|
94 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status | |
| 112 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr |
|
95 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr | |
| 113 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data |
|
96 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data | |
| 114 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done |
|
97 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done | |
| 115 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren |
|
98 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren | |
| 116 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid |
|
99 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid | |
| 117 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst |
|
100 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst | |
| 118 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_0 |
|
|||
| 119 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_1 |
|
|||
| 120 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1 |
|
101 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1 | |
| 121 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2 |
|
102 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2 | |
| 122 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_0 |
|
|||
| 123 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_1 |
|
|||
| 124 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1 |
|
103 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1 | |
| 125 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2 |
|
104 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2 | |
| 126 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state |
|
105 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state | |
| 127 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type |
|
106 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type | |
| 128 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre |
|
107 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre | |
| 129 | add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type |
|
108 | add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type | |
| 130 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok |
|
109 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok | |
| 131 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty |
|
110 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty | |
| 132 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo |
|
111 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo | |
|
|
112 | add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error | |||
|
|
113 | add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full | |||
|
|
114 | add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write | |||
|
|
115 | add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1 | |||
|
|
116 | add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2 | |||
|
|
117 | add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res | |||
|
|
118 | add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp | |||
|
|
119 | add wave -noupdate -expand -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl | |||
|
|
120 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse | |||
|
|
121 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen | |||
|
|
122 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata | |||
|
|
123 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren | |||
|
|
124 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata | |||
|
|
125 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty | |||
|
|
126 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full | |||
|
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127 | add wave -noupdate -expand -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full | |||
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128 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(128) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(129) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(130) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(131) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(132) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(133) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(134) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(135) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(136) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(137) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(138) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(139) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(140) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(141) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(142) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(143) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(144) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(145) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(146) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(147) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(148) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(149) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(150) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(151) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(152) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(153) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(154) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(155) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(156) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(157) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(158) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(159) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(160) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(161) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(162) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(163) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(164) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(165) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(166) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(167) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(168) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(169) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(170) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(171) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(172) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(173) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(174) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(175) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(176) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(177) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(178) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(179) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(180) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(181) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(182) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(183) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(184) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(185) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(186) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(187) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(188) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(189) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(190) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(191) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(192) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(193) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(194) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(195) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(196) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(197) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(198) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(199) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(200) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(201) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(202) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(203) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(204) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(205) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(206) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(207) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(208) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(209) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(210) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(211) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(212) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(213) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(214) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(215) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(216) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(217) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(218) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(219) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(220) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(221) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(222) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(223) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(224) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(225) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(226) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(227) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(228) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(229) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(230) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(231) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(232) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(233) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(234) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(235) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(236) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(237) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(238) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(239) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(240) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(241) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(242) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(243) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(244) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(245) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(246) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(247) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(248) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(249) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(250) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(251) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(252) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(253) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(254) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(255) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |||
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129 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |||
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130 | add wave -noupdate -expand -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult | |||
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131 | add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1 | |||
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132 | add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2 | |||
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133 | add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res | |||
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134 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add | |||
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135 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr | |||
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136 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load | |||
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137 | add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1 | |||
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138 | add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2 | |||
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139 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res | |||
| 133 | TreeUpdate [SetDefaultTree] |
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140 | TreeUpdate [SetDefaultTree] | |
| 134 |
WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44 |
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141 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {10435060000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {99992359332 ps} 0} | |
| 135 | configure wave -namecolwidth 469 |
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142 | configure wave -namecolwidth 469 | |
| 136 | configure wave -valuecolwidth 112 |
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143 | configure wave -valuecolwidth 112 | |
| 137 | configure wave -justifyvalue left |
|
144 | configure wave -justifyvalue left | |
| 138 | configure wave -signalnamewidth 0 |
|
145 | configure wave -signalnamewidth 0 | |
| 139 | configure wave -snapdistance 10 |
|
146 | configure wave -snapdistance 10 | |
| 140 | configure wave -datasetprefix 0 |
|
147 | configure wave -datasetprefix 0 | |
| 141 | configure wave -rowmargin 4 |
|
148 | configure wave -rowmargin 4 | |
| 142 | configure wave -childrowmargin 2 |
|
149 | configure wave -childrowmargin 2 | |
| 143 | configure wave -gridoffset 0 |
|
150 | configure wave -gridoffset 0 | |
| 144 | configure wave -gridperiod 1 |
|
151 | configure wave -gridperiod 1 | |
| 145 | configure wave -griddelta 40 |
|
152 | configure wave -griddelta 40 | |
| 146 | configure wave -timeline 0 |
|
153 | configure wave -timeline 0 | |
| 147 | configure wave -timelineunits ps |
|
154 | configure wave -timelineunits ps | |
| 148 | update |
|
155 | update | |
| 149 |
WaveRestoreZoom {10 |
|
156 | WaveRestoreZoom {10434939916 ps} {10435778196 ps} | |
| 150 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
|
157 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 | |
| 151 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
|
158 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 | |
| @@ -1,301 +1,328 | |||||
| 1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
| 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 4 | -- |
|
4 | -- | |
| 5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
| 6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
| 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
| 8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
| 9 | -- |
|
9 | -- | |
| 10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
| 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
| 14 | -- |
|
14 | -- | |
| 15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
| 16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
| 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
| 19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
| 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
| 21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
| 22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
| 23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
| 24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
| 25 | LIBRARY lpp; |
|
25 | LIBRARY lpp; | |
| 26 | USE lpp.general_purpose.ALL; |
|
26 | USE lpp.general_purpose.ALL; | |
| 27 | --TODO |
|
27 | --TODO | |
| 28 | --terminer le testbensh puis changer le resize dans les instanciations |
|
28 | --terminer le testbensh puis changer le resize dans les instanciations | |
| 29 | --par un resize sur un vecteur en combi |
|
29 | --par un resize sur un vecteur en combi | |
| 30 |
|
30 | |||
| 31 |
|
31 | |||
| 32 | ENTITY MAC IS |
|
32 | ENTITY MAC IS | |
| 33 | GENERIC( |
|
33 | GENERIC( | |
| 34 | Input_SZ_A : INTEGER := 8; |
|
34 | Input_SZ_A : INTEGER := 8; | |
| 35 | Input_SZ_B : INTEGER := 8; |
|
35 | Input_SZ_B : INTEGER := 8; | |
| 36 | COMP_EN : INTEGER := 0 -- 1 => No Comp |
|
36 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
| 37 |
|
37 | |||
| 38 | ); |
|
38 | ); | |
| 39 | PORT( |
|
39 | PORT( | |
| 40 | clk : IN STD_LOGIC; |
|
40 | clk : IN STD_LOGIC; | |
| 41 | reset : IN STD_LOGIC; |
|
41 | reset : IN STD_LOGIC; | |
| 42 | clr_MAC : IN STD_LOGIC; |
|
42 | clr_MAC : IN STD_LOGIC; | |
| 43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
| 48 | ); |
|
48 | ); | |
| 49 | END MAC; |
|
49 | END MAC; | |
| 50 |
|
50 | |||
| 51 |
|
51 | |||
| 52 |
|
52 | |||
| 53 |
|
53 | |||
| 54 | ARCHITECTURE ar_MAC OF MAC IS |
|
54 | ARCHITECTURE ar_MAC OF MAC IS | |
| 55 |
|
55 | |||
|
|
56 | ||||
|
|
57 | SIGNAL clr_MAC_s : STD_LOGIC; | |||
|
|
58 | SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
59 | ||||
| 56 | SIGNAL add, mult : STD_LOGIC; |
|
60 | SIGNAL add, mult : STD_LOGIC; | |
| 57 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
61 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 58 |
|
62 | |||
| 59 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
63 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 60 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
64 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 61 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
65 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 62 |
|
66 | |||
| 63 | SIGNAL MACMUXsel : STD_LOGIC; |
|
67 | SIGNAL MACMUXsel : STD_LOGIC; | |
| 64 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
68 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 65 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
69 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 66 |
|
70 | |||
| 67 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
71 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 68 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
72 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 69 |
|
73 | |||
| 70 | SIGNAL MACMUX2sel : STD_LOGIC; |
|
74 | SIGNAL MACMUX2sel : STD_LOGIC; | |
| 71 |
|
75 | |||
| 72 | SIGNAL add_D : STD_LOGIC; |
|
76 | SIGNAL add_D : STD_LOGIC; | |
| 73 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
77 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
| 74 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
78 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
| 75 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
79 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); | |
| 76 | SIGNAL MACMUXsel_D : STD_LOGIC; |
|
80 | SIGNAL MACMUXsel_D : STD_LOGIC; | |
| 77 | SIGNAL MACMUX2sel_D : STD_LOGIC; |
|
81 | SIGNAL MACMUX2sel_D : STD_LOGIC; | |
| 78 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; |
|
82 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; | |
| 79 | SIGNAL clr_MAC_D : STD_LOGIC; |
|
83 | SIGNAL clr_MAC_D : STD_LOGIC; | |
| 80 | SIGNAL clr_MAC_D_D : STD_LOGIC; |
|
84 | -- SIGNAL clr_MAC_D_D : STD_LOGIC; | |
| 81 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
85 | -- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 82 |
|
86 | |||
| 83 | SIGNAL load_mult_result : STD_LOGIC; |
|
87 | SIGNAL load_mult_result : STD_LOGIC; | |
| 84 | SIGNAL load_mult_result_D : STD_LOGIC; |
|
88 | SIGNAL load_mult_result_D : STD_LOGIC; | |
| 85 |
|
89 | |||
| 86 | BEGIN |
|
90 | BEGIN | |
| 87 |
|
91 | |||
| 88 |
|
92 | |||
| 89 |
|
93 | |||
| 90 |
|
94 | |||
| 91 | --============================================================== |
|
95 | --============================================================== | |
| 92 | --=============M A C C O N T R O L E R========================= |
|
96 | --=============M A C C O N T R O L E R========================= | |
| 93 | --============================================================== |
|
97 | --============================================================== | |
| 94 | MAC_CONTROLER1 : MAC_CONTROLER |
|
98 | MAC_CONTROLER1 : MAC_CONTROLER | |
| 95 | PORT MAP( |
|
99 | PORT MAP( | |
| 96 | ctrl => MAC_MUL_ADD, |
|
100 | ctrl => MAC_MUL_ADD_s, | |
| 97 | MULT => mult, |
|
101 | MULT => mult, | |
| 98 | ADD => add, |
|
102 | ADD => add, | |
| 99 | LOAD_ADDER => load_mult_result, |
|
103 | LOAD_ADDER => load_mult_result, | |
| 100 | MACMUX_sel => MACMUXsel, |
|
104 | MACMUX_sel => MACMUXsel, | |
| 101 | MACMUX2_sel => MACMUX2sel |
|
105 | MACMUX2_sel => MACMUX2sel | |
| 102 |
|
106 | |||
| 103 | ); |
|
107 | ); | |
| 104 | --============================================================== |
|
108 | --============================================================== | |
| 105 |
|
109 | |||
| 106 |
|
110 | |||
| 107 |
|
111 | |||
| 108 |
|
112 | |||
| 109 | --============================================================== |
|
113 | --============================================================== | |
| 110 | --=============M U L T I P L I E R============================== |
|
114 | --=============M U L T I P L I E R============================== | |
| 111 | --============================================================== |
|
115 | --============================================================== | |
| 112 | Multiplieri_nst : Multiplier |
|
116 | Multiplieri_nst : Multiplier | |
| 113 | GENERIC MAP( |
|
117 | GENERIC MAP( | |
| 114 | Input_SZ_A => Input_SZ_A, |
|
118 | Input_SZ_A => Input_SZ_A, | |
| 115 | Input_SZ_B => Input_SZ_B |
|
119 | Input_SZ_B => Input_SZ_B | |
| 116 | ) |
|
120 | ) | |
| 117 | PORT MAP( |
|
121 | PORT MAP( | |
| 118 | clk => clk, |
|
122 | clk => clk, | |
| 119 | reset => reset, |
|
123 | reset => reset, | |
| 120 | mult => mult, |
|
124 | mult => mult, | |
| 121 | OP1 => OP1_2C, |
|
125 | OP1 => OP1_2C, | |
| 122 | OP2 => OP2_2C, |
|
126 | OP2 => OP2_2C, | |
| 123 | RES => MULTout |
|
127 | RES => MULTout | |
| 124 | ); |
|
128 | ); | |
| 125 | --============================================================== |
|
129 | --============================================================== | |
| 126 |
|
130 | |||
| 127 | PROCESS (clk, reset) |
|
131 | PROCESS (clk, reset) | |
| 128 | BEGIN -- PROCESS |
|
132 | BEGIN -- PROCESS | |
| 129 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
133 | IF reset = '0' THEN -- asynchronous reset (active low) | |
| 130 | load_mult_result_D <= '0'; |
|
134 | load_mult_result_D <= '0'; | |
| 131 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
135 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 132 | load_mult_result_D <= load_mult_result; |
|
136 | load_mult_result_D <= load_mult_result; | |
| 133 | END IF; |
|
137 | END IF; | |
| 134 | END PROCESS; |
|
138 | END PROCESS; | |
| 135 |
|
139 | |||
| 136 | --============================================================== |
|
140 | --============================================================== | |
| 137 | --======================A D D E R ============================== |
|
141 | --======================A D D E R ============================== | |
| 138 | --============================================================== |
|
142 | --============================================================== | |
| 139 | adder_inst : Adder |
|
143 | adder_inst : Adder | |
| 140 | GENERIC MAP( |
|
144 | GENERIC MAP( | |
| 141 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
145 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
| 142 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
146 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
| 143 | ) |
|
147 | ) | |
| 144 | PORT MAP( |
|
148 | PORT MAP( | |
| 145 | clk => clk, |
|
149 | clk => clk, | |
| 146 | reset => reset, |
|
150 | reset => reset, | |
| 147 | clr => clr_MAC_D, |
|
151 | clr => clr_MAC_D, | |
| 148 | load => load_mult_result_D, |
|
152 | load => load_mult_result_D, | |
| 149 | add => add_D, |
|
153 | add => add_D, | |
| 150 | OP1 => ADDERinA, |
|
154 | OP1 => ADDERinA, | |
| 151 | OP2 => ADDERinB, |
|
155 | OP2 => ADDERinB, | |
| 152 | RES => ADDERout |
|
156 | RES => ADDERout | |
| 153 | ); |
|
157 | ); | |
| 154 |
|
158 | |||
| 155 | --============================================================== |
|
159 | --============================================================== | |
| 156 | --===================TWO COMPLEMENTERS========================== |
|
160 | --===================TWO COMPLEMENTERS========================== | |
| 157 | --============================================================== |
|
161 | --============================================================== | |
| 158 | gen_comp : IF COMP_EN = 0 GENERATE |
|
162 | gen_comp : IF COMP_EN = 0 GENERATE | |
| 159 | TWO_COMPLEMENTER1 : TwoComplementer |
|
163 | TWO_COMPLEMENTER1 : TwoComplementer | |
| 160 | GENERIC MAP( |
|
164 | GENERIC MAP( | |
| 161 | Input_SZ => Input_SZ_A |
|
165 | Input_SZ => Input_SZ_A | |
| 162 | ) |
|
166 | ) | |
| 163 | PORT MAP( |
|
167 | PORT MAP( | |
| 164 | clk => clk, |
|
168 | clk => clk, | |
| 165 | reset => reset, |
|
169 | reset => reset, | |
| 166 |
clr => |
|
170 | clr => '0',--clr_MAC, | |
| 167 | TwoComp => Comp_2C(0), |
|
171 | TwoComp => Comp_2C(0), | |
| 168 | OP => OP1, |
|
172 | OP => OP1, | |
| 169 | RES => OP1_2C |
|
173 | RES => OP1_2C | |
| 170 | ); |
|
174 | ); | |
| 171 |
|
175 | |||
| 172 | TWO_COMPLEMENTER2 : TwoComplementer |
|
176 | TWO_COMPLEMENTER2 : TwoComplementer | |
| 173 | GENERIC MAP( |
|
177 | GENERIC MAP( | |
| 174 | Input_SZ => Input_SZ_B |
|
178 | Input_SZ => Input_SZ_B | |
| 175 | ) |
|
179 | ) | |
| 176 | PORT MAP( |
|
180 | PORT MAP( | |
| 177 | clk => clk, |
|
181 | clk => clk, | |
| 178 | reset => reset, |
|
182 | reset => reset, | |
| 179 |
clr => |
|
183 | clr => '0',--clr_MAC, | |
| 180 | TwoComp => Comp_2C(1), |
|
184 | TwoComp => Comp_2C(1), | |
| 181 | OP => OP2, |
|
185 | OP => OP2, | |
| 182 | RES => OP2_2C |
|
186 | RES => OP2_2C | |
| 183 | ); |
|
187 | ); | |
|
|
188 | ||||
|
|
189 | ||||
|
|
190 | clr_MACREG_comp : MAC_REG | |||
|
|
191 | GENERIC MAP(size => 1) | |||
|
|
192 | PORT MAP( | |||
|
|
193 | reset => reset, | |||
|
|
194 | clk => clk, | |||
|
|
195 | D(0) => clr_MAC, | |||
|
|
196 | Q(0) => clr_MAC_s | |||
|
|
197 | ); | |||
|
|
198 | ||||
|
|
199 | MAC_MUL_ADD_REG : MAC_REG | |||
|
|
200 | GENERIC MAP(size => 2) | |||
|
|
201 | PORT MAP( | |||
|
|
202 | reset => reset, | |||
|
|
203 | clk => clk, | |||
|
|
204 | D => MAC_MUL_ADD, | |||
|
|
205 | Q => MAC_MUL_ADD_s | |||
|
|
206 | ); | |||
|
|
207 | ||||
| 184 |
|
|
208 | END GENERATE gen_comp; | |
| 185 |
|
209 | |||
| 186 | no_gen_comp : IF COMP_EN = 1 GENERATE |
|
210 | no_gen_comp : IF COMP_EN = 1 GENERATE | |
| 187 | OP2_2C <= OP2; |
|
211 | OP2_2C <= OP2; | |
| 188 | OP1_2C <= OP1; |
|
212 | OP1_2C <= OP1; | |
|
|
213 | ||||
|
|
214 | clr_MAC_s <= clr_MAC; | |||
|
|
215 | MAC_MUL_ADD_s <= MAC_MUL_ADD; | |||
| 189 | END GENERATE no_gen_comp; |
|
216 | END GENERATE no_gen_comp; | |
| 190 | --============================================================== |
|
217 | --============================================================== | |
| 191 |
|
218 | |||
| 192 | clr_MACREG1 : MAC_REG |
|
219 | clr_MACREG1 : MAC_REG | |
| 193 | GENERIC MAP(size => 1) |
|
220 | GENERIC MAP(size => 1) | |
| 194 | PORT MAP( |
|
221 | PORT MAP( | |
| 195 | reset => reset, |
|
222 | reset => reset, | |
| 196 | clk => clk, |
|
223 | clk => clk, | |
| 197 | D(0) => clr_MAC, |
|
224 | D(0) => clr_MAC_s, | |
| 198 | Q(0) => clr_MAC_D |
|
225 | Q(0) => clr_MAC_D | |
| 199 | ); |
|
226 | ); | |
| 200 |
|
227 | |||
| 201 | addREG : MAC_REG |
|
228 | addREG : MAC_REG | |
| 202 | GENERIC MAP(size => 1) |
|
229 | GENERIC MAP(size => 1) | |
| 203 | PORT MAP( |
|
230 | PORT MAP( | |
| 204 | reset => reset, |
|
231 | reset => reset, | |
| 205 | clk => clk, |
|
232 | clk => clk, | |
| 206 | D(0) => add, |
|
233 | D(0) => add, | |
| 207 | Q(0) => add_D |
|
234 | Q(0) => add_D | |
| 208 | ); |
|
235 | ); | |
| 209 |
|
236 | |||
| 210 | OP1REG : MAC_REG |
|
237 | OP1REG : MAC_REG | |
| 211 | GENERIC MAP(size => Input_SZ_A) |
|
238 | GENERIC MAP(size => Input_SZ_A) | |
| 212 | PORT MAP( |
|
239 | PORT MAP( | |
| 213 | reset => reset, |
|
240 | reset => reset, | |
| 214 | clk => clk, |
|
241 | clk => clk, | |
| 215 | D => OP1_2C, |
|
242 | D => OP1_2C, | |
| 216 | Q => OP1_2C_D |
|
243 | Q => OP1_2C_D | |
| 217 | ); |
|
244 | ); | |
| 218 |
|
245 | |||
| 219 |
|
246 | |||
| 220 | OP2REG : MAC_REG |
|
247 | OP2REG : MAC_REG | |
| 221 | GENERIC MAP(size => Input_SZ_B) |
|
248 | GENERIC MAP(size => Input_SZ_B) | |
| 222 | PORT MAP( |
|
249 | PORT MAP( | |
| 223 | reset => reset, |
|
250 | reset => reset, | |
| 224 | clk => clk, |
|
251 | clk => clk, | |
| 225 | D => OP2_2C, |
|
252 | D => OP2_2C, | |
| 226 | Q => OP2_2C_D |
|
253 | Q => OP2_2C_D | |
| 227 | ); |
|
254 | ); | |
| 228 |
|
255 | |||
| 229 | MULToutREG : MAC_REG |
|
256 | MULToutREG : MAC_REG | |
| 230 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) |
|
257 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) | |
| 231 | PORT MAP( |
|
258 | PORT MAP( | |
| 232 | reset => reset, |
|
259 | reset => reset, | |
| 233 | clk => clk, |
|
260 | clk => clk, | |
| 234 | D => MULTout, |
|
261 | D => MULTout, | |
| 235 | Q => MULTout_D |
|
262 | Q => MULTout_D | |
| 236 | ); |
|
263 | ); | |
| 237 |
|
264 | |||
| 238 | MACMUXselREG : MAC_REG |
|
265 | MACMUXselREG : MAC_REG | |
| 239 | GENERIC MAP(size => 1) |
|
266 | GENERIC MAP(size => 1) | |
| 240 | PORT MAP( |
|
267 | PORT MAP( | |
| 241 | reset => reset, |
|
268 | reset => reset, | |
| 242 | clk => clk, |
|
269 | clk => clk, | |
| 243 | D(0) => MACMUXsel, |
|
270 | D(0) => MACMUXsel, | |
| 244 | Q(0) => MACMUXsel_D |
|
271 | Q(0) => MACMUXsel_D | |
| 245 | ); |
|
272 | ); | |
| 246 |
|
273 | |||
| 247 | MACMUX2selREG : MAC_REG |
|
274 | MACMUX2selREG : MAC_REG | |
| 248 | GENERIC MAP(size => 1) |
|
275 | GENERIC MAP(size => 1) | |
| 249 | PORT MAP( |
|
276 | PORT MAP( | |
| 250 | reset => reset, |
|
277 | reset => reset, | |
| 251 | clk => clk, |
|
278 | clk => clk, | |
| 252 | D(0) => MACMUX2sel, |
|
279 | D(0) => MACMUX2sel, | |
| 253 | Q(0) => MACMUX2sel_D |
|
280 | Q(0) => MACMUX2sel_D | |
| 254 | ); |
|
281 | ); | |
| 255 |
|
282 | |||
| 256 | MACMUX2selREG2 : MAC_REG |
|
283 | MACMUX2selREG2 : MAC_REG | |
| 257 | GENERIC MAP(size => 1) |
|
284 | GENERIC MAP(size => 1) | |
| 258 | PORT MAP( |
|
285 | PORT MAP( | |
| 259 | reset => reset, |
|
286 | reset => reset, | |
| 260 | clk => clk, |
|
287 | clk => clk, | |
| 261 | D(0) => MACMUX2sel_D, |
|
288 | D(0) => MACMUX2sel_D, | |
| 262 | Q(0) => MACMUX2sel_D_D |
|
289 | Q(0) => MACMUX2sel_D_D | |
| 263 | ); |
|
290 | ); | |
| 264 |
|
291 | |||
| 265 | --============================================================== |
|
292 | --============================================================== | |
| 266 | --======================M A C M U X =========================== |
|
293 | --======================M A C M U X =========================== | |
| 267 | --============================================================== |
|
294 | --============================================================== | |
| 268 | MACMUX_inst : MAC_MUX |
|
295 | MACMUX_inst : MAC_MUX | |
| 269 | GENERIC MAP( |
|
296 | GENERIC MAP( | |
| 270 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
297 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
| 271 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
298 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
| 272 |
|
299 | |||
| 273 | ) |
|
300 | ) | |
| 274 | PORT MAP( |
|
301 | PORT MAP( | |
| 275 | sel => MACMUXsel_D, |
|
302 | sel => MACMUXsel_D, | |
| 276 | INA1 => ADDERout, |
|
303 | INA1 => ADDERout, | |
| 277 | INA2 => OP2_2C_D_Resz, |
|
304 | INA2 => OP2_2C_D_Resz, | |
| 278 | INB1 => MULTout, |
|
305 | INB1 => MULTout, | |
| 279 | INB2 => OP1_2C_D_Resz, |
|
306 | INB2 => OP1_2C_D_Resz, | |
| 280 | OUTA => ADDERinA, |
|
307 | OUTA => ADDERinA, | |
| 281 | OUTB => ADDERinB |
|
308 | OUTB => ADDERinB | |
| 282 | ); |
|
309 | ); | |
| 283 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); |
|
310 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); | |
| 284 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); |
|
311 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); | |
| 285 | --============================================================== |
|
312 | --============================================================== | |
| 286 |
|
313 | |||
| 287 |
|
314 | |||
| 288 | --============================================================== |
|
315 | --============================================================== | |
| 289 | --======================M A C M U X2 ========================== |
|
316 | --======================M A C M U X2 ========================== | |
| 290 | --============================================================== |
|
317 | --============================================================== | |
| 291 | MAC_MUX2_inst : MAC_MUX2 |
|
318 | MAC_MUX2_inst : MAC_MUX2 | |
| 292 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) |
|
319 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) | |
| 293 | PORT MAP( |
|
320 | PORT MAP( | |
| 294 | sel => MACMUX2sel_D_D, |
|
321 | sel => MACMUX2sel_D_D, | |
| 295 | RES2 => MULTout_D, |
|
322 | RES2 => MULTout_D, | |
| 296 | RES1 => ADDERout, |
|
323 | RES1 => ADDERout, | |
| 297 | RES => RES |
|
324 | RES => RES | |
| 298 | ); |
|
325 | ); | |
| 299 | --============================================================== |
|
326 | --============================================================== | |
| 300 |
|
327 | |||
| 301 | END ar_MAC; |
|
328 | END ar_MAC; | |
| @@ -1,10 +1,4 | |||||
| 1 | lpp_memory.vhd |
|
1 | lpp_memory.vhd | |
| 2 | lpp_FIFO.vhd |
|
2 | lpp_FIFO.vhd | |
| 3 | FillFifo.vhd |
|
|||
| 4 | Bridge.vhd |
|
|||
| 5 | APB_FIFO.vhd |
|
|||
| 6 | Bridge.vhd |
|
|||
| 7 | SSRAM_plugin.vhd |
|
|||
| 8 | lppFIFOx5.vhd |
|
|||
| 9 | lppFIFOxN.vhd |
|
3 | lppFIFOxN.vhd | |
| 10 |
|
4 | |||
| @@ -1,224 +1,225 | |||||
| 1 | LIBRARY IEEE; |
|
1 | LIBRARY IEEE; | |
| 2 | USE IEEE.std_logic_1164.ALL; |
|
2 | USE IEEE.std_logic_1164.ALL; | |
| 3 |
|
3 | |||
| 4 | LIBRARY lpp; |
|
4 | LIBRARY lpp; | |
| 5 | USE lpp.general_purpose.ALL; |
|
5 | USE lpp.general_purpose.ALL; | |
| 6 |
|
6 | |||
| 7 | ENTITY MS_calculation IS |
|
7 | ENTITY MS_calculation IS | |
| 8 | PORT ( |
|
8 | PORT ( | |
| 9 | clk : IN STD_LOGIC; |
|
9 | clk : IN STD_LOGIC; | |
| 10 | rstn : IN STD_LOGIC; |
|
10 | rstn : IN STD_LOGIC; | |
| 11 | -- IN |
|
11 | -- IN | |
| 12 | fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
12 | fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
| 13 | fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
13 | fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 14 | fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
14 | fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 15 | -- OUT |
|
15 | -- OUT | |
| 16 | fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); |
|
16 | fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); | |
| 17 | fifo_out_wen : OUT STD_LOGIC; |
|
17 | fifo_out_wen : OUT STD_LOGIC; | |
| 18 | fifo_out_full : IN STD_LOGIC; |
|
18 | fifo_out_full : IN STD_LOGIC; | |
| 19 | -- |
|
19 | -- | |
| 20 | correlation_start : IN STD_LOGIC; |
|
20 | correlation_start : IN STD_LOGIC; | |
| 21 | correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation |
|
21 | correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation | |
| 22 |
|
22 | |||
| 23 | correlation_begin : OUT STD_LOGIC; |
|
23 | correlation_begin : OUT STD_LOGIC; | |
| 24 | correlation_done : OUT STD_LOGIC |
|
24 | correlation_done : OUT STD_LOGIC | |
| 25 | ); |
|
25 | ); | |
| 26 | END MS_calculation; |
|
26 | END MS_calculation; | |
| 27 |
|
27 | |||
| 28 | ARCHITECTURE beh OF MS_calculation IS |
|
28 | ARCHITECTURE beh OF MS_calculation IS | |
| 29 |
|
29 | |||
| 30 | TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a); |
|
30 | TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a); | |
| 31 | SIGNAL state : fsm_calculation_MS; |
|
31 | SIGNAL state : fsm_calculation_MS; | |
| 32 |
|
32 | |||
| 33 | SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
33 | SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 34 | SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
34 | SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 35 | SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
35 | SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 36 |
|
36 | |||
| 37 | SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 38 |
|
38 | |||
| 39 |
|
39 | |||
| 40 | CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; |
|
40 | CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; | |
| 41 | CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010"; |
|
41 | CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010"; | |
| 42 | CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; |
|
42 | CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; | |
| 43 | CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; |
|
43 | CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; | |
| 44 |
|
44 | |||
| 45 |
|
45 | |||
| 46 |
|
46 | |||
| 47 | SIGNAL select_op1 : STD_LOGIC; |
|
47 | SIGNAL select_op1 : STD_LOGIC; | |
| 48 | SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; |
|
48 | SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; | |
| 49 |
|
49 | |||
| 50 | CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; |
|
50 | CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; | |
| 51 | CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; |
|
51 | CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; | |
| 52 | CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; |
|
52 | CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; | |
| 53 | CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; |
|
53 | CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; | |
| 54 |
|
54 | |||
| 55 | SIGNAL res_wen : STD_LOGIC; |
|
55 | SIGNAL res_wen : STD_LOGIC; | |
| 56 | SIGNAL res_wen_reg1 : STD_LOGIC; |
|
56 | SIGNAL res_wen_reg1 : STD_LOGIC; | |
| 57 |
|
|
57 | SIGNAL res_wen_reg2 : STD_LOGIC; | |
| 58 | --SIGNAL res_wen_reg3 : STD_LOGIC; |
|
58 | --SIGNAL res_wen_reg3 : STD_LOGIC; | |
| 59 |
|
59 | |||
| 60 | BEGIN |
|
60 | BEGIN | |
| 61 |
|
61 | |||
| 62 |
|
62 | |||
| 63 |
|
63 | |||
| 64 | PROCESS (clk, rstn) |
|
64 | PROCESS (clk, rstn) | |
| 65 | BEGIN |
|
65 | BEGIN | |
| 66 | IF rstn = '0' THEN |
|
66 | IF rstn = '0' THEN | |
| 67 |
|
67 | |||
| 68 | correlation_begin <= '0'; |
|
68 | correlation_begin <= '0'; | |
| 69 | correlation_done <= '0'; |
|
69 | correlation_done <= '0'; | |
| 70 | state <= IDLE; |
|
70 | state <= IDLE; | |
| 71 | fifo_in_ren <= "11"; |
|
71 | fifo_in_ren <= "11"; | |
| 72 | ALU_CTRL <= ALU_CTRL_NOP; |
|
72 | ALU_CTRL <= ALU_CTRL_NOP; | |
| 73 | select_op1 <= select_R0(0); |
|
73 | select_op1 <= select_R0(0); | |
| 74 | select_op2 <= select_R0; |
|
74 | select_op2 <= select_R0; | |
| 75 | res_wen <= '1'; |
|
75 | res_wen <= '1'; | |
| 76 |
|
76 | |||
| 77 | ELSIF clk'EVENT AND clk = '1' THEN |
|
77 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
|
78 | ALU_CTRL <= ALU_CTRL_NOP; | |||
| 78 | correlation_begin <= '0'; |
|
79 | correlation_begin <= '0'; | |
| 79 | fifo_in_ren <= "11"; |
|
80 | fifo_in_ren <= "11"; | |
| 80 | res_wen <= '1'; |
|
81 | res_wen <= '1'; | |
| 81 | correlation_done <= '0'; |
|
82 | correlation_done <= '0'; | |
| 82 | CASE state IS |
|
83 | CASE state IS | |
| 83 | WHEN IDLE => |
|
84 | WHEN IDLE => | |
| 84 | IF correlation_start = '1' THEN |
|
85 | IF correlation_start = '1' THEN | |
| 85 | IF correlation_auto = '1' THEN |
|
86 | IF correlation_auto = '1' THEN | |
| 86 | IF fifo_out_full = '1' THEN |
|
87 | IF fifo_out_full = '1' THEN | |
| 87 | state <= WFa; |
|
88 | state <= WFa; | |
| 88 | ELSE |
|
89 | ELSE | |
| 89 | correlation_begin <= '1'; |
|
90 | correlation_begin <= '1'; | |
| 90 | state <= S1a; |
|
91 | state <= S1a; | |
| 91 | fifo_in_ren <= "10"; |
|
92 | fifo_in_ren <= "10"; | |
| 92 | END IF; |
|
93 | END IF; | |
| 93 | ELSE |
|
94 | ELSE | |
| 94 | IF fifo_out_full = '1' THEN |
|
95 | IF fifo_out_full = '1' THEN | |
| 95 | state <= WF; |
|
96 | state <= WF; | |
| 96 | ELSE |
|
97 | ELSE | |
| 97 | correlation_begin <= '1'; |
|
98 | correlation_begin <= '1'; | |
| 98 | state <= S1; |
|
99 | state <= S1; | |
| 99 | fifo_in_ren <= "00"; |
|
100 | fifo_in_ren <= "00"; | |
| 100 | END IF; |
|
101 | END IF; | |
| 101 | END IF; |
|
102 | END IF; | |
| 102 | END IF; |
|
103 | END IF; | |
| 103 |
|
104 | |||
| 104 | --------------------------------------------------------------------- |
|
105 | --------------------------------------------------------------------- | |
| 105 | -- INTER CORRELATION |
|
106 | -- INTER CORRELATION | |
| 106 | --------------------------------------------------------------------- |
|
107 | --------------------------------------------------------------------- | |
| 107 | WHEN WF => |
|
108 | WHEN WF => | |
| 108 | IF fifo_out_full = '0' THEN |
|
109 | IF fifo_out_full = '0' THEN | |
| 109 | correlation_begin <= '1'; |
|
110 | correlation_begin <= '1'; | |
| 110 | state <= S1; |
|
111 | state <= S1; | |
| 111 | fifo_in_ren <= "00"; |
|
112 | fifo_in_ren <= "00"; | |
| 112 | END IF; |
|
113 | END IF; | |
| 113 | WHEN S1 => |
|
114 | WHEN S1 => | |
| 114 | ALU_CTRL <= ALU_CTRL_MULT; |
|
115 | ALU_CTRL <= ALU_CTRL_MULT; | |
| 115 | select_op1 <= select_R0(0); |
|
116 | select_op1 <= select_R0(0); | |
| 116 | select_op2 <= select_R1; |
|
117 | select_op2 <= select_R1; | |
| 117 | state <= S2; |
|
118 | state <= S2; | |
| 118 | WHEN S2 => |
|
119 | WHEN S2 => | |
| 119 | ALU_CTRL <= ALU_CTRL_MAC; |
|
120 | ALU_CTRL <= ALU_CTRL_MAC; | |
| 120 | select_op1 <= select_I0(0); |
|
121 | select_op1 <= select_I0(0); | |
| 121 | select_op2 <= select_I1; |
|
122 | select_op2 <= select_I1; | |
| 122 | res_wen <= '0'; |
|
123 | res_wen <= '0'; | |
| 123 | state <= S3; |
|
124 | state <= S3; | |
| 124 | WHEN S3 => |
|
125 | WHEN S3 => | |
| 125 | ALU_CTRL <= ALU_CTRL_MULT; |
|
126 | ALU_CTRL <= ALU_CTRL_MULT; | |
| 126 | select_op1 <= select_I0(0); |
|
127 | select_op1 <= select_I0(0); | |
| 127 | select_op2 <= select_R1; |
|
128 | select_op2 <= select_R1; | |
| 128 | state <= S4; |
|
129 | state <= S4; | |
| 129 | WHEN S4 => |
|
130 | WHEN S4 => | |
| 130 | ALU_CTRL <= ALU_CTRL_MACn; |
|
131 | ALU_CTRL <= ALU_CTRL_MACn; | |
| 131 | select_op1 <= select_R0(0); |
|
132 | select_op1 <= select_R0(0); | |
| 132 | select_op2 <= select_I1; |
|
133 | select_op2 <= select_I1; | |
| 133 | res_wen <= '0'; |
|
134 | res_wen <= '0'; | |
| 134 | IF fifo_in_empty = "00" THEN |
|
135 | IF fifo_in_empty = "00" THEN | |
| 135 | state <= S1; |
|
136 | state <= S1; | |
| 136 | fifo_in_ren <= "00"; |
|
137 | fifo_in_ren <= "00"; | |
| 137 | ELSE |
|
138 | ELSE | |
| 138 | correlation_done <= '1'; |
|
139 | correlation_done <= '1'; | |
| 139 | state <= IDLE; |
|
140 | state <= IDLE; | |
| 140 | END IF; |
|
141 | END IF; | |
| 141 |
|
142 | |||
| 142 |
|
143 | |||
| 143 |
|
144 | |||
| 144 | --------------------------------------------------------------------- |
|
145 | --------------------------------------------------------------------- | |
| 145 | -- AUTO CORRELATION |
|
146 | -- AUTO CORRELATION | |
| 146 | --------------------------------------------------------------------- |
|
147 | --------------------------------------------------------------------- | |
| 147 | WHEN WFa => |
|
148 | WHEN WFa => | |
| 148 | IF fifo_out_full = '0' THEN |
|
149 | IF fifo_out_full = '0' THEN | |
| 149 | correlation_begin <= '1'; |
|
150 | correlation_begin <= '1'; | |
| 150 | state <= S1a; |
|
151 | state <= S1a; | |
| 151 | fifo_in_ren <= "10"; |
|
152 | fifo_in_ren <= "10"; | |
| 152 | END IF; |
|
153 | END IF; | |
| 153 | WHEN S1a => |
|
154 | WHEN S1a => | |
| 154 | ALU_CTRL <= ALU_CTRL_MULT; |
|
155 | ALU_CTRL <= ALU_CTRL_MULT; | |
| 155 | select_op1 <= select_R0(0); |
|
156 | select_op1 <= select_R0(0); | |
| 156 | select_op2 <= select_R0; |
|
157 | select_op2 <= select_R0; | |
| 157 | state <= S2a; |
|
158 | state <= S2a; | |
| 158 | WHEN S2a => |
|
159 | WHEN S2a => | |
| 159 | ALU_CTRL <= ALU_CTRL_MAC; |
|
160 | ALU_CTRL <= ALU_CTRL_MAC; | |
| 160 | select_op1 <= select_I0(0); |
|
161 | select_op1 <= select_I0(0); | |
| 161 | select_op2 <= select_I0; |
|
162 | select_op2 <= select_I0; | |
| 162 | res_wen <= '0'; |
|
163 | res_wen <= '0'; | |
| 163 | IF fifo_in_empty(0) = '0' THEN |
|
164 | IF fifo_in_empty(0) = '0' THEN | |
| 164 | state <= S1a; |
|
165 | state <= S1a; | |
| 165 | fifo_in_ren <= "10"; |
|
166 | fifo_in_ren <= "10"; | |
| 166 | ELSE |
|
167 | ELSE | |
| 167 | correlation_done <= '1'; |
|
168 | correlation_done <= '1'; | |
| 168 | state <= IDLE; |
|
169 | state <= IDLE; | |
| 169 | END IF; |
|
170 | END IF; | |
| 170 |
|
171 | |||
| 171 |
|
172 | |||
| 172 | WHEN OTHERS => NULL; |
|
173 | WHEN OTHERS => NULL; | |
| 173 | END CASE; |
|
174 | END CASE; | |
| 174 |
|
175 | |||
| 175 | END IF; |
|
176 | END IF; | |
| 176 | END PROCESS; |
|
177 | END PROCESS; | |
| 177 |
|
178 | |||
| 178 | OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE |
|
179 | OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE | |
| 179 | fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE |
|
180 | fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE | |
| 180 |
|
181 | |||
| 181 | OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE |
|
182 | OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE | |
| 182 | fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE |
|
183 | fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE | |
| 183 | fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE |
|
184 | fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE | |
| 184 | fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE |
|
185 | fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE | |
| 185 |
|
186 | |||
| 186 | ALU_MS : ALU |
|
187 | ALU_MS : ALU | |
| 187 | GENERIC MAP ( |
|
188 | GENERIC MAP ( | |
| 188 | Arith_en => 1, |
|
189 | Arith_en => 1, | |
| 189 | Logic_en => 0, |
|
190 | Logic_en => 0, | |
| 190 | Input_SZ_1 => 16, |
|
191 | Input_SZ_1 => 16, | |
| 191 | Input_SZ_2 => 16, |
|
192 | Input_SZ_2 => 16, | |
| 192 | COMP_EN => 1) |
|
193 | COMP_EN => 0) -- 0> Enable and 1> Disable | |
| 193 | PORT MAP ( |
|
194 | PORT MAP ( | |
| 194 | clk => clk, |
|
195 | clk => clk, | |
| 195 | reset => rstn, |
|
196 | reset => rstn, | |
| 196 |
|
197 | |||
| 197 | ctrl => ALU_CTRL(2 DOWNTO 0), |
|
198 | ctrl => ALU_CTRL(2 DOWNTO 0), | |
| 198 | comp => ALU_CTRL(4 DOWNTO 3), |
|
199 | comp => ALU_CTRL(4 DOWNTO 3), | |
| 199 |
|
200 | |||
| 200 | OP1 => OP1, |
|
201 | OP1 => OP1, | |
| 201 | OP2 => OP2, |
|
202 | OP2 => OP2, | |
| 202 |
|
203 | |||
| 203 | RES => RES); |
|
204 | RES => RES); | |
| 204 |
|
205 | |||
| 205 | fifo_out_data <= RES; |
|
206 | fifo_out_data <= RES; | |
| 206 |
|
207 | |||
| 207 |
|
208 | |||
| 208 | PROCESS (clk, rstn) |
|
209 | PROCESS (clk, rstn) | |
| 209 | BEGIN |
|
210 | BEGIN | |
| 210 | IF rstn = '0' THEN |
|
211 | IF rstn = '0' THEN | |
| 211 | res_wen_reg1 <= '1'; |
|
212 | res_wen_reg1 <= '1'; | |
| 212 |
|
|
213 | res_wen_reg2 <= '1'; | |
| 213 | --res_wen_reg3 <= '1'; |
|
214 | --res_wen_reg3 <= '1'; | |
| 214 | fifo_out_wen <= '1'; |
|
215 | fifo_out_wen <= '1'; | |
| 215 | ELSIF clk'event AND clk = '1' THEN |
|
216 | ELSIF clk'event AND clk = '1' THEN | |
| 216 | res_wen_reg1 <= res_wen; |
|
217 | res_wen_reg1 <= res_wen; | |
| 217 |
|
|
218 | res_wen_reg2 <= res_wen_reg1; | |
| 218 | --res_wen_reg3 <= res_wen_reg2; |
|
219 | --res_wen_reg3 <= res_wen_reg2; | |
| 219 |
fifo_out_wen <= res_wen_reg |
|
220 | fifo_out_wen <= res_wen_reg2; | |
| 220 | END IF; |
|
221 | END IF; | |
| 221 | END PROCESS; |
|
222 | END PROCESS; | |
| 222 |
|
223 | |||
| 223 |
|
224 | |||
| 224 | END beh; |
|
225 | END beh; | |
| @@ -1,36 +1,36 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 |
|
3 | |||
| 4 | ENTITY spectral_matrix_time_managment IS |
|
4 | ENTITY spectral_matrix_time_managment IS | |
| 5 |
|
5 | |||
| 6 | PORT ( |
|
6 | PORT ( | |
| 7 | clk : IN STD_LOGIC; |
|
7 | clk : IN STD_LOGIC; | |
| 8 | rstn : IN STD_LOGIC; |
|
8 | rstn : IN STD_LOGIC; | |
| 9 |
|
9 | |||
| 10 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
10 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 11 | update_1 : IN STD_LOGIC; |
|
11 | update_1 : IN STD_LOGIC; | |
| 12 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
12 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
| 13 | ); |
|
13 | ); | |
| 14 |
|
14 | |||
| 15 | END spectral_matrix_time_managment; |
|
15 | END spectral_matrix_time_managment; | |
| 16 |
|
16 | |||
| 17 | ARCHITECTURE beh OF spectral_matrix_time_managment IS |
|
17 | ARCHITECTURE beh OF spectral_matrix_time_managment IS | |
| 18 |
|
18 | |||
| 19 | SIGNAL time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
19 | SIGNAL time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 20 |
|
20 | |||
| 21 | BEGIN -- beh |
|
21 | BEGIN -- beh | |
| 22 |
|
22 | |||
| 23 | PROCESS (clk, rstn) |
|
23 | PROCESS (clk, rstn) | |
| 24 | BEGIN |
|
24 | BEGIN | |
| 25 | IF rstn = '0' THEN |
|
25 | IF rstn = '0' THEN | |
| 26 | time_reg <= (OTHERS => '0'); |
|
26 | time_reg <= (OTHERS => '0'); | |
| 27 | ELSIF clk'event AND clk = '1' THEN |
|
27 | ELSIF clk'event AND clk = '1' THEN | |
| 28 | IF update_1 = '1' THEN |
|
28 | IF update_1 = '1' THEN | |
| 29 | time_reg <= time_in; |
|
29 | time_reg <= time_in; | |
| 30 | END IF; |
|
30 | END IF; | |
| 31 | END IF; |
|
31 | END IF; | |
| 32 | END PROCESS; |
|
32 | END PROCESS; | |
| 33 |
|
33 | |||
| 34 |
time_out <= time_ |
|
34 | time_out <= time_reg; | |
| 35 |
|
35 | |||
| 36 | END beh; |
|
36 | END beh; | |
| @@ -1,764 +1,762 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
| 4 |
|
4 | |||
| 5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
| 6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
| 7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
| 8 | USE lpp.FILTERcfg.ALL; |
|
8 | USE lpp.FILTERcfg.ALL; | |
| 9 | USE lpp.lpp_memory.ALL; |
|
9 | USE lpp.lpp_memory.ALL; | |
| 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
| 11 | USE lpp.lpp_dma_pkg.ALL; |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
| 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
| 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
| 14 | USE lpp.general_purpose.ALL; |
|
14 | USE lpp.general_purpose.ALL; | |
| 15 |
|
15 | |||
| 16 | LIBRARY techmap; |
|
16 | LIBRARY techmap; | |
| 17 | USE techmap.gencomp.ALL; |
|
17 | USE techmap.gencomp.ALL; | |
| 18 |
|
18 | |||
| 19 | LIBRARY grlib; |
|
19 | LIBRARY grlib; | |
| 20 | USE grlib.amba.ALL; |
|
20 | USE grlib.amba.ALL; | |
| 21 | USE grlib.stdlib.ALL; |
|
21 | USE grlib.stdlib.ALL; | |
| 22 | USE grlib.devices.ALL; |
|
22 | USE grlib.devices.ALL; | |
| 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
| 24 |
|
24 | |||
| 25 | ENTITY lpp_lfr IS |
|
25 | ENTITY lpp_lfr IS | |
| 26 | GENERIC ( |
|
26 | GENERIC ( | |
| 27 | Mem_use : INTEGER := use_RAM; |
|
27 | Mem_use : INTEGER := use_RAM; | |
| 28 | nb_data_by_buffer_size : INTEGER := 11; |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
| 29 | nb_word_by_buffer_size : INTEGER := 11; |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
| 30 | nb_snapshot_param_size : INTEGER := 11; |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
| 31 | delta_vector_size : INTEGER := 20; |
|
31 | delta_vector_size : INTEGER := 20; | |
| 32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
| 33 |
|
33 | |||
| 34 | pindex : INTEGER := 4; |
|
34 | pindex : INTEGER := 4; | |
| 35 | paddr : INTEGER := 4; |
|
35 | paddr : INTEGER := 4; | |
| 36 | pmask : INTEGER := 16#fff#; |
|
36 | pmask : INTEGER := 16#fff#; | |
| 37 | pirq_ms : INTEGER := 0; |
|
37 | pirq_ms : INTEGER := 0; | |
| 38 | pirq_wfp : INTEGER := 1; |
|
38 | pirq_wfp : INTEGER := 1; | |
| 39 |
|
39 | |||
| 40 | hindex : INTEGER := 2; |
|
40 | hindex : INTEGER := 2; | |
| 41 |
|
41 | |||
| 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
| 43 |
|
43 | |||
| 44 | ); |
|
44 | ); | |
| 45 | PORT ( |
|
45 | PORT ( | |
| 46 | clk : IN STD_LOGIC; |
|
46 | clk : IN STD_LOGIC; | |
| 47 | rstn : IN STD_LOGIC; |
|
47 | rstn : IN STD_LOGIC; | |
| 48 | -- SAMPLE |
|
48 | -- SAMPLE | |
| 49 | sample_B : IN Samples(2 DOWNTO 0); |
|
49 | sample_B : IN Samples(2 DOWNTO 0); | |
| 50 | sample_E : IN Samples(4 DOWNTO 0); |
|
50 | sample_E : IN Samples(4 DOWNTO 0); | |
| 51 | sample_val : IN STD_LOGIC; |
|
51 | sample_val : IN STD_LOGIC; | |
| 52 | -- APB |
|
52 | -- APB | |
| 53 | apbi : IN apb_slv_in_type; |
|
53 | apbi : IN apb_slv_in_type; | |
| 54 | apbo : OUT apb_slv_out_type; |
|
54 | apbo : OUT apb_slv_out_type; | |
| 55 | -- AHB |
|
55 | -- AHB | |
| 56 | ahbi : IN AHB_Mst_In_Type; |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
| 57 | ahbo : OUT AHB_Mst_Out_Type; |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
| 58 | -- TIME |
|
58 | -- TIME | |
| 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
| 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
| 61 | -- |
|
61 | -- | |
| 62 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
| 63 | -- |
|
63 | -- | |
| 64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
| 65 |
|
65 | |||
| 66 | --debug |
|
66 | --debug | |
| 67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
| 69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
70 | --debug_f1_data_valid : OUT STD_LOGIC; | |
| 71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f2_data_valid : OUT STD_LOGIC; | |
| 73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
| 74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
74 | --debug_f3_data_valid : OUT STD_LOGIC; | |
| 75 |
|
75 | |||
| 76 | ---- debug FIFO_IN |
|
76 | ---- debug FIFO_IN | |
| 77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
| 79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
| 81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
| 83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
| 85 |
|
85 | |||
| 86 | ----debug FIFO OUT |
|
86 | ----debug FIFO OUT | |
| 87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
| 89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
| 91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
| 93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
| 95 |
|
95 | |||
| 96 | ----debug DMA IN |
|
96 | ----debug DMA IN | |
| 97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
| 99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
| 101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
| 103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
| 105 | ); |
|
105 | ); | |
| 106 | END lpp_lfr; |
|
106 | END lpp_lfr; | |
| 107 |
|
107 | |||
| 108 | ARCHITECTURE beh OF lpp_lfr IS |
|
108 | ARCHITECTURE beh OF lpp_lfr IS | |
| 109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); | |
| 110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
| 111 | -- |
|
111 | -- | |
| 112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
| 113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
| 114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
| 115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
| 116 | -- |
|
116 | -- | |
| 117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 120 | -- |
|
120 | -- | |
| 121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
121 | SIGNAL sample_f0_val : STD_LOGIC; | |
| 122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
122 | SIGNAL sample_f1_val : STD_LOGIC; | |
| 123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
123 | SIGNAL sample_f2_val : STD_LOGIC; | |
| 124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
124 | SIGNAL sample_f3_val : STD_LOGIC; | |
| 125 | -- |
|
125 | -- | |
| 126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 130 | -- |
|
130 | -- | |
| 131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 134 |
|
134 | |||
| 135 | -- SM |
|
135 | -- SM | |
| 136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
| 137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
| 138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
| 139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
| 140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
| 141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
| 142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
| 144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
| 145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
| 146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
| 147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
| 148 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
148 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
| 149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
| 150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
| 151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 155 |
|
155 | |||
| 156 | -- WFP |
|
156 | -- WFP | |
| 157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
| 164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 166 |
|
166 | |||
| 167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
| 168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
| 169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
| 170 | SIGNAL enable_f0 : STD_LOGIC; |
|
170 | SIGNAL enable_f0 : STD_LOGIC; | |
| 171 | SIGNAL enable_f1 : STD_LOGIC; |
|
171 | SIGNAL enable_f1 : STD_LOGIC; | |
| 172 | SIGNAL enable_f2 : STD_LOGIC; |
|
172 | SIGNAL enable_f2 : STD_LOGIC; | |
| 173 | SIGNAL enable_f3 : STD_LOGIC; |
|
173 | SIGNAL enable_f3 : STD_LOGIC; | |
| 174 | SIGNAL burst_f0 : STD_LOGIC; |
|
174 | SIGNAL burst_f0 : STD_LOGIC; | |
| 175 | SIGNAL burst_f1 : STD_LOGIC; |
|
175 | SIGNAL burst_f1 : STD_LOGIC; | |
| 176 | SIGNAL burst_f2 : STD_LOGIC; |
|
176 | SIGNAL burst_f2 : STD_LOGIC; | |
| 177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 181 |
|
181 | |||
| 182 | SIGNAL run : STD_LOGIC; |
|
182 | SIGNAL run : STD_LOGIC; | |
| 183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
| 184 |
|
184 | |||
| 185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
| 188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
| 189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
| 190 | --f1 |
|
190 | --f1 | |
| 191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
| 194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
| 195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
| 196 | --f2 |
|
196 | --f2 | |
| 197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
| 200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
| 201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
| 202 | --f3 |
|
202 | --f3 | |
| 203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
| 206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
| 207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
| 208 |
|
208 | |||
| 209 | ----------------------------------------------------------------------------- |
|
209 | ----------------------------------------------------------------------------- | |
| 210 | -- |
|
210 | -- | |
| 211 | ----------------------------------------------------------------------------- |
|
211 | ----------------------------------------------------------------------------- | |
| 212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
| 214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
| 215 | --f1 |
|
215 | --f1 | |
| 216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
| 218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
| 219 | --f2 |
|
219 | --f2 | |
| 220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
| 222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
| 223 | --f3 |
|
223 | --f3 | |
| 224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
| 226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
| 227 |
|
227 | |||
| 228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
| 229 | -- DMA RR |
|
229 | -- DMA RR | |
| 230 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
| 231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
231 | SIGNAL dma_sel_valid : STD_LOGIC; | |
| 232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 236 |
|
236 | |||
| 237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 239 |
|
239 | |||
| 240 | ----------------------------------------------------------------------------- |
|
240 | ----------------------------------------------------------------------------- | |
| 241 | -- DMA_REG |
|
241 | -- DMA_REG | |
| 242 | ----------------------------------------------------------------------------- |
|
242 | ----------------------------------------------------------------------------- | |
| 243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
243 | SIGNAL ongoing_reg : STD_LOGIC; | |
| 244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
245 | SIGNAL dma_send_reg : STD_LOGIC; | |
| 246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
| 247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 249 |
|
249 | |||
| 250 |
|
250 | |||
| 251 | ----------------------------------------------------------------------------- |
|
251 | ----------------------------------------------------------------------------- | |
| 252 | -- DMA |
|
252 | -- DMA | |
| 253 | ----------------------------------------------------------------------------- |
|
253 | ----------------------------------------------------------------------------- | |
| 254 | SIGNAL dma_send : STD_LOGIC; |
|
254 | SIGNAL dma_send : STD_LOGIC; | |
| 255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
| 256 | SIGNAL dma_done : STD_LOGIC; |
|
256 | SIGNAL dma_done : STD_LOGIC; | |
| 257 | SIGNAL dma_ren : STD_LOGIC; |
|
257 | SIGNAL dma_ren : STD_LOGIC; | |
| 258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 261 |
|
261 | |||
| 262 | ----------------------------------------------------------------------------- |
|
262 | ----------------------------------------------------------------------------- | |
| 263 | -- DEBUG |
|
263 | -- DEBUG | |
| 264 | ----------------------------------------------------------------------------- |
|
264 | ----------------------------------------------------------------------------- | |
| 265 | -- |
|
265 | -- | |
| 266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 270 |
|
270 | |||
| 271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 279 |
|
279 | |||
| 280 | ----------------------------------------------------------------------------- |
|
280 | ----------------------------------------------------------------------------- | |
| 281 | -- MS |
|
281 | -- MS | |
| 282 | ----------------------------------------------------------------------------- |
|
282 | ----------------------------------------------------------------------------- | |
| 283 |
|
283 | |||
| 284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 286 | SIGNAL data_ms_valid : STD_LOGIC; |
|
286 | SIGNAL data_ms_valid : STD_LOGIC; | |
| 287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
| 288 | SIGNAL data_ms_ren : STD_LOGIC; |
|
288 | SIGNAL data_ms_ren : STD_LOGIC; | |
| 289 | SIGNAL data_ms_done : STD_LOGIC; |
|
289 | SIGNAL data_ms_done : STD_LOGIC; | |
| 290 |
|
290 | |||
| 291 | SIGNAL run_ms : STD_LOGIC; |
|
291 | SIGNAL run_ms : STD_LOGIC; | |
| 292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
| 293 |
|
293 | |||
| 294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 298 |
|
298 | |||
| 299 |
|
299 | |||
| 300 | BEGIN |
|
300 | BEGIN | |
| 301 |
|
301 | |||
| 302 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
302 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
| 303 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
303 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
| 304 |
|
304 | |||
| 305 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
305 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
| 306 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
306 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
| 307 | --END GENERATE all_channel; |
|
307 | --END GENERATE all_channel; | |
| 308 |
|
308 | |||
| 309 | ----------------------------------------------------------------------------- |
|
309 | ----------------------------------------------------------------------------- | |
| 310 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
310 | lpp_lfr_filter_1 : lpp_lfr_filter | |
| 311 | GENERIC MAP ( |
|
311 | GENERIC MAP ( | |
| 312 | Mem_use => Mem_use) |
|
312 | Mem_use => Mem_use) | |
| 313 | PORT MAP ( |
|
313 | PORT MAP ( | |
| 314 | sample => sample_s, |
|
314 | sample => sample_s, | |
| 315 | sample_val => sample_val, |
|
315 | sample_val => sample_val, | |
| 316 | clk => clk, |
|
316 | clk => clk, | |
| 317 | rstn => rstn, |
|
317 | rstn => rstn, | |
| 318 | data_shaping_SP0 => data_shaping_SP0, |
|
318 | data_shaping_SP0 => data_shaping_SP0, | |
| 319 | data_shaping_SP1 => data_shaping_SP1, |
|
319 | data_shaping_SP1 => data_shaping_SP1, | |
| 320 | data_shaping_R0 => data_shaping_R0, |
|
320 | data_shaping_R0 => data_shaping_R0, | |
| 321 | data_shaping_R1 => data_shaping_R1, |
|
321 | data_shaping_R1 => data_shaping_R1, | |
| 322 | sample_f0_val => sample_f0_val, |
|
322 | sample_f0_val => sample_f0_val, | |
| 323 | sample_f1_val => sample_f1_val, |
|
323 | sample_f1_val => sample_f1_val, | |
| 324 | sample_f2_val => sample_f2_val, |
|
324 | sample_f2_val => sample_f2_val, | |
| 325 | sample_f3_val => sample_f3_val, |
|
325 | sample_f3_val => sample_f3_val, | |
| 326 | sample_f0_wdata => sample_f0_data, |
|
326 | sample_f0_wdata => sample_f0_data, | |
| 327 | sample_f1_wdata => sample_f1_data, |
|
327 | sample_f1_wdata => sample_f1_data, | |
| 328 | sample_f2_wdata => sample_f2_data, |
|
328 | sample_f2_wdata => sample_f2_data, | |
| 329 | sample_f3_wdata => sample_f3_data); |
|
329 | sample_f3_wdata => sample_f3_data); | |
| 330 |
|
330 | |||
| 331 | ----------------------------------------------------------------------------- |
|
331 | ----------------------------------------------------------------------------- | |
| 332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
| 333 | GENERIC MAP ( |
|
333 | GENERIC MAP ( | |
| 334 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
334 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
| 335 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
335 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
| 336 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
336 | nb_snapshot_param_size => nb_snapshot_param_size, | |
| 337 | delta_vector_size => delta_vector_size, |
|
337 | delta_vector_size => delta_vector_size, | |
| 338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
| 339 | pindex => pindex, |
|
339 | pindex => pindex, | |
| 340 | paddr => paddr, |
|
340 | paddr => paddr, | |
| 341 | pmask => pmask, |
|
341 | pmask => pmask, | |
| 342 | pirq_ms => pirq_ms, |
|
342 | pirq_ms => pirq_ms, | |
| 343 | pirq_wfp => pirq_wfp, |
|
343 | pirq_wfp => pirq_wfp, | |
| 344 | top_lfr_version => top_lfr_version) |
|
344 | top_lfr_version => top_lfr_version) | |
| 345 | PORT MAP ( |
|
345 | PORT MAP ( | |
| 346 | HCLK => clk, |
|
346 | HCLK => clk, | |
| 347 | HRESETn => rstn, |
|
347 | HRESETn => rstn, | |
| 348 | apbi => apbi, |
|
348 | apbi => apbi, | |
| 349 | apbo => apbo, |
|
349 | apbo => apbo, | |
| 350 |
|
350 | |||
| 351 | run_ms => run_ms, |
|
351 | run_ms => run_ms, | |
| 352 |
|
352 | |||
| 353 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
353 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
| 354 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
354 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
| 355 | ready_matrix_f1 => ready_matrix_f1, |
|
355 | ready_matrix_f1 => ready_matrix_f1, | |
| 356 | ready_matrix_f2 => ready_matrix_f2, |
|
356 | ready_matrix_f2 => ready_matrix_f2, | |
| 357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
| 358 | error_bad_component_error => error_bad_component_error, |
|
358 | error_bad_component_error => error_bad_component_error, | |
| 359 | debug_reg => debug_reg, |
|
359 | debug_reg => debug_reg, | |
| 360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
| 361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
| 362 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
362 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
| 363 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
363 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
| 364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
| 365 | status_error_bad_component_error => status_error_bad_component_error, |
|
365 | status_error_bad_component_error => status_error_bad_component_error, | |
| 366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
| 367 | config_active_interruption_onError => config_active_interruption_onError, |
|
367 | config_active_interruption_onError => config_active_interruption_onError, | |
| 368 |
|
368 | |||
| 369 | matrix_time_f0_0 => matrix_time_f0_0, |
|
369 | matrix_time_f0_0 => matrix_time_f0_0, | |
| 370 | matrix_time_f0_1 => matrix_time_f0_1, |
|
370 | matrix_time_f0_1 => matrix_time_f0_1, | |
| 371 | matrix_time_f1 => matrix_time_f1, |
|
371 | matrix_time_f1 => matrix_time_f1, | |
| 372 | matrix_time_f2 => matrix_time_f2, |
|
372 | matrix_time_f2 => matrix_time_f2, | |
| 373 |
|
373 | |||
| 374 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
374 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
| 375 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
375 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
| 376 | addr_matrix_f1 => addr_matrix_f1, |
|
376 | addr_matrix_f1 => addr_matrix_f1, | |
| 377 | addr_matrix_f2 => addr_matrix_f2, |
|
377 | addr_matrix_f2 => addr_matrix_f2, | |
| 378 | status_full => status_full, |
|
378 | status_full => status_full, | |
| 379 | status_full_ack => status_full_ack, |
|
379 | status_full_ack => status_full_ack, | |
| 380 | status_full_err => status_full_err, |
|
380 | status_full_err => status_full_err, | |
| 381 | status_new_err => status_new_err, |
|
381 | status_new_err => status_new_err, | |
| 382 | data_shaping_BW => data_shaping_BW, |
|
382 | data_shaping_BW => data_shaping_BW, | |
| 383 | data_shaping_SP0 => data_shaping_SP0, |
|
383 | data_shaping_SP0 => data_shaping_SP0, | |
| 384 | data_shaping_SP1 => data_shaping_SP1, |
|
384 | data_shaping_SP1 => data_shaping_SP1, | |
| 385 | data_shaping_R0 => data_shaping_R0, |
|
385 | data_shaping_R0 => data_shaping_R0, | |
| 386 | data_shaping_R1 => data_shaping_R1, |
|
386 | data_shaping_R1 => data_shaping_R1, | |
| 387 | delta_snapshot => delta_snapshot, |
|
387 | delta_snapshot => delta_snapshot, | |
| 388 | delta_f0 => delta_f0, |
|
388 | delta_f0 => delta_f0, | |
| 389 | delta_f0_2 => delta_f0_2, |
|
389 | delta_f0_2 => delta_f0_2, | |
| 390 | delta_f1 => delta_f1, |
|
390 | delta_f1 => delta_f1, | |
| 391 | delta_f2 => delta_f2, |
|
391 | delta_f2 => delta_f2, | |
| 392 | nb_data_by_buffer => nb_data_by_buffer, |
|
392 | nb_data_by_buffer => nb_data_by_buffer, | |
| 393 | nb_word_by_buffer => nb_word_by_buffer, |
|
393 | nb_word_by_buffer => nb_word_by_buffer, | |
| 394 | nb_snapshot_param => nb_snapshot_param, |
|
394 | nb_snapshot_param => nb_snapshot_param, | |
| 395 | enable_f0 => enable_f0, |
|
395 | enable_f0 => enable_f0, | |
| 396 | enable_f1 => enable_f1, |
|
396 | enable_f1 => enable_f1, | |
| 397 | enable_f2 => enable_f2, |
|
397 | enable_f2 => enable_f2, | |
| 398 | enable_f3 => enable_f3, |
|
398 | enable_f3 => enable_f3, | |
| 399 | burst_f0 => burst_f0, |
|
399 | burst_f0 => burst_f0, | |
| 400 | burst_f1 => burst_f1, |
|
400 | burst_f1 => burst_f1, | |
| 401 | burst_f2 => burst_f2, |
|
401 | burst_f2 => burst_f2, | |
| 402 | run => run, |
|
402 | run => run, | |
| 403 | addr_data_f0 => addr_data_f0, |
|
403 | addr_data_f0 => addr_data_f0, | |
| 404 | addr_data_f1 => addr_data_f1, |
|
404 | addr_data_f1 => addr_data_f1, | |
| 405 | addr_data_f2 => addr_data_f2, |
|
405 | addr_data_f2 => addr_data_f2, | |
| 406 | addr_data_f3 => addr_data_f3, |
|
406 | addr_data_f3 => addr_data_f3, | |
| 407 | start_date => start_date, |
|
407 | start_date => start_date, | |
| 408 | --------------------------------------------------------------------------- |
|
408 | --------------------------------------------------------------------------- | |
| 409 | debug_reg0 => debug_reg0, |
|
409 | debug_reg0 => debug_reg0, | |
| 410 | debug_reg1 => debug_reg1, |
|
410 | debug_reg1 => debug_reg1, | |
| 411 | debug_reg2 => debug_reg2, |
|
411 | debug_reg2 => debug_reg2, | |
| 412 | debug_reg3 => debug_reg3, |
|
412 | debug_reg3 => debug_reg3, | |
| 413 | debug_reg4 => debug_reg4, |
|
413 | debug_reg4 => debug_reg4, | |
| 414 | debug_reg5 => debug_reg5, |
|
414 | debug_reg5 => debug_reg5, | |
| 415 | debug_reg6 => debug_reg6, |
|
415 | debug_reg6 => debug_reg6, | |
| 416 | debug_reg7 => debug_reg7); |
|
416 | debug_reg7 => debug_reg7); | |
| 417 |
|
417 | |||
| 418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
| 419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
| 420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
| 421 | ----------------------------------------------------------------------------- |
|
421 | ----------------------------------------------------------------------------- | |
| 422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
| 423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
| 424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
| 425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
| 426 |
|
426 | |||
| 427 |
|
427 | |||
| 428 | ----------------------------------------------------------------------------- |
|
428 | ----------------------------------------------------------------------------- | |
| 429 | lpp_waveform_1 : lpp_waveform |
|
429 | lpp_waveform_1 : lpp_waveform | |
| 430 | GENERIC MAP ( |
|
430 | GENERIC MAP ( | |
| 431 | tech => inferred, |
|
431 | tech => inferred, | |
| 432 | data_size => 6*16, |
|
432 | data_size => 6*16, | |
| 433 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
433 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
| 434 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
434 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
| 435 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
435 | nb_snapshot_param_size => nb_snapshot_param_size, | |
| 436 | delta_vector_size => delta_vector_size, |
|
436 | delta_vector_size => delta_vector_size, | |
| 437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
| 438 | ) |
|
438 | ) | |
| 439 | PORT MAP ( |
|
439 | PORT MAP ( | |
| 440 | clk => clk, |
|
440 | clk => clk, | |
| 441 | rstn => rstn, |
|
441 | rstn => rstn, | |
| 442 |
|
442 | |||
| 443 | reg_run => run, |
|
443 | reg_run => run, | |
| 444 | reg_start_date => start_date, |
|
444 | reg_start_date => start_date, | |
| 445 | reg_delta_snapshot => delta_snapshot, |
|
445 | reg_delta_snapshot => delta_snapshot, | |
| 446 | reg_delta_f0 => delta_f0, |
|
446 | reg_delta_f0 => delta_f0, | |
| 447 | reg_delta_f0_2 => delta_f0_2, |
|
447 | reg_delta_f0_2 => delta_f0_2, | |
| 448 | reg_delta_f1 => delta_f1, |
|
448 | reg_delta_f1 => delta_f1, | |
| 449 | reg_delta_f2 => delta_f2, |
|
449 | reg_delta_f2 => delta_f2, | |
| 450 |
|
450 | |||
| 451 | enable_f0 => enable_f0, |
|
451 | enable_f0 => enable_f0, | |
| 452 | enable_f1 => enable_f1, |
|
452 | enable_f1 => enable_f1, | |
| 453 | enable_f2 => enable_f2, |
|
453 | enable_f2 => enable_f2, | |
| 454 | enable_f3 => enable_f3, |
|
454 | enable_f3 => enable_f3, | |
| 455 | burst_f0 => burst_f0, |
|
455 | burst_f0 => burst_f0, | |
| 456 | burst_f1 => burst_f1, |
|
456 | burst_f1 => burst_f1, | |
| 457 | burst_f2 => burst_f2, |
|
457 | burst_f2 => burst_f2, | |
| 458 |
|
458 | |||
| 459 | nb_data_by_buffer => nb_data_by_buffer, |
|
459 | nb_data_by_buffer => nb_data_by_buffer, | |
| 460 | nb_word_by_buffer => nb_word_by_buffer, |
|
460 | nb_word_by_buffer => nb_word_by_buffer, | |
| 461 | nb_snapshot_param => nb_snapshot_param, |
|
461 | nb_snapshot_param => nb_snapshot_param, | |
| 462 | status_full => status_full, |
|
462 | status_full => status_full, | |
| 463 | status_full_ack => status_full_ack, |
|
463 | status_full_ack => status_full_ack, | |
| 464 | status_full_err => status_full_err, |
|
464 | status_full_err => status_full_err, | |
| 465 | status_new_err => status_new_err, |
|
465 | status_new_err => status_new_err, | |
| 466 |
|
466 | |||
| 467 | coarse_time => coarse_time, |
|
467 | coarse_time => coarse_time, | |
| 468 | fine_time => fine_time, |
|
468 | fine_time => fine_time, | |
| 469 |
|
469 | |||
| 470 | --f0 |
|
470 | --f0 | |
| 471 | addr_data_f0 => addr_data_f0, |
|
471 | addr_data_f0 => addr_data_f0, | |
| 472 | data_f0_in_valid => sample_f0_val, |
|
472 | data_f0_in_valid => sample_f0_val, | |
| 473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
| 474 | --f1 |
|
474 | --f1 | |
| 475 | addr_data_f1 => addr_data_f1, |
|
475 | addr_data_f1 => addr_data_f1, | |
| 476 | data_f1_in_valid => sample_f1_val, |
|
476 | data_f1_in_valid => sample_f1_val, | |
| 477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
| 478 | --f2 |
|
478 | --f2 | |
| 479 | addr_data_f2 => addr_data_f2, |
|
479 | addr_data_f2 => addr_data_f2, | |
| 480 | data_f2_in_valid => sample_f2_val, |
|
480 | data_f2_in_valid => sample_f2_val, | |
| 481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
| 482 | --f3 |
|
482 | --f3 | |
| 483 | addr_data_f3 => addr_data_f3, |
|
483 | addr_data_f3 => addr_data_f3, | |
| 484 | data_f3_in_valid => sample_f3_val, |
|
484 | data_f3_in_valid => sample_f3_val, | |
| 485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
| 486 | -- OUTPUT -- DMA interface |
|
486 | -- OUTPUT -- DMA interface | |
| 487 | --f0 |
|
487 | --f0 | |
| 488 | data_f0_addr_out => data_f0_addr_out_s, |
|
488 | data_f0_addr_out => data_f0_addr_out_s, | |
| 489 | data_f0_data_out => data_f0_data_out, |
|
489 | data_f0_data_out => data_f0_data_out, | |
| 490 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
490 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
| 491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
| 492 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
492 | data_f0_data_out_ren => data_f0_data_out_ren, | |
| 493 | --f1 |
|
493 | --f1 | |
| 494 | data_f1_addr_out => data_f1_addr_out_s, |
|
494 | data_f1_addr_out => data_f1_addr_out_s, | |
| 495 | data_f1_data_out => data_f1_data_out, |
|
495 | data_f1_data_out => data_f1_data_out, | |
| 496 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
496 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
| 497 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
497 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
| 498 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
498 | data_f1_data_out_ren => data_f1_data_out_ren, | |
| 499 | --f2 |
|
499 | --f2 | |
| 500 | data_f2_addr_out => data_f2_addr_out_s, |
|
500 | data_f2_addr_out => data_f2_addr_out_s, | |
| 501 | data_f2_data_out => data_f2_data_out, |
|
501 | data_f2_data_out => data_f2_data_out, | |
| 502 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
502 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
| 503 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
503 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
| 504 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
504 | data_f2_data_out_ren => data_f2_data_out_ren, | |
| 505 | --f3 |
|
505 | --f3 | |
| 506 | data_f3_addr_out => data_f3_addr_out_s, |
|
506 | data_f3_addr_out => data_f3_addr_out_s, | |
| 507 | data_f3_data_out => data_f3_data_out, |
|
507 | data_f3_data_out => data_f3_data_out, | |
| 508 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
508 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
| 509 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
509 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
| 510 | data_f3_data_out_ren => data_f3_data_out_ren , |
|
510 | data_f3_data_out_ren => data_f3_data_out_ren , | |
| 511 |
|
511 | |||
| 512 | ------------------------------------------------------------------------- |
|
512 | ------------------------------------------------------------------------- | |
| 513 | observation_reg => OPEN |
|
513 | observation_reg => OPEN | |
| 514 |
|
514 | |||
| 515 | ); |
|
515 | ); | |
| 516 |
|
516 | |||
| 517 |
|
517 | |||
| 518 | ----------------------------------------------------------------------------- |
|
518 | ----------------------------------------------------------------------------- | |
| 519 | -- TEMP |
|
519 | -- TEMP | |
| 520 | ----------------------------------------------------------------------------- |
|
520 | ----------------------------------------------------------------------------- | |
| 521 |
|
521 | |||
| 522 | PROCESS (clk, rstn) |
|
522 | PROCESS (clk, rstn) | |
| 523 | BEGIN -- PROCESS |
|
523 | BEGIN -- PROCESS | |
| 524 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
524 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 525 | data_f0_data_out_valid <= '0'; |
|
525 | data_f0_data_out_valid <= '0'; | |
| 526 | data_f0_data_out_valid_burst <= '0'; |
|
526 | data_f0_data_out_valid_burst <= '0'; | |
| 527 | data_f1_data_out_valid <= '0'; |
|
527 | data_f1_data_out_valid <= '0'; | |
| 528 | data_f1_data_out_valid_burst <= '0'; |
|
528 | data_f1_data_out_valid_burst <= '0'; | |
| 529 | data_f2_data_out_valid <= '0'; |
|
529 | data_f2_data_out_valid <= '0'; | |
| 530 | data_f2_data_out_valid_burst <= '0'; |
|
530 | data_f2_data_out_valid_burst <= '0'; | |
| 531 | data_f3_data_out_valid <= '0'; |
|
531 | data_f3_data_out_valid <= '0'; | |
| 532 | data_f3_data_out_valid_burst <= '0'; |
|
532 | data_f3_data_out_valid_burst <= '0'; | |
| 533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
| 535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
| 536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
| 537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
| 538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
| 539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
| 540 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
540 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
| 541 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
541 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
| 542 | END IF; |
|
542 | END IF; | |
| 543 | END PROCESS; |
|
543 | END PROCESS; | |
| 544 |
|
544 | |||
| 545 | data_f0_addr_out <= data_f0_addr_out_s; |
|
545 | data_f0_addr_out <= data_f0_addr_out_s; | |
| 546 | data_f1_addr_out <= data_f1_addr_out_s; |
|
546 | data_f1_addr_out <= data_f1_addr_out_s; | |
| 547 | data_f2_addr_out <= data_f2_addr_out_s; |
|
547 | data_f2_addr_out <= data_f2_addr_out_s; | |
| 548 | data_f3_addr_out <= data_f3_addr_out_s; |
|
548 | data_f3_addr_out <= data_f3_addr_out_s; | |
| 549 |
|
549 | |||
| 550 | ----------------------------------------------------------------------------- |
|
550 | ----------------------------------------------------------------------------- | |
| 551 | -- RoundRobin Selection For DMA |
|
551 | -- RoundRobin Selection For DMA | |
| 552 | ----------------------------------------------------------------------------- |
|
552 | ----------------------------------------------------------------------------- | |
| 553 |
|
553 | |||
| 554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
| 555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
| 556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
| 557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
| 558 |
|
558 | |||
| 559 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
559 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
| 560 | PORT MAP ( |
|
560 | PORT MAP ( | |
| 561 | clk => clk, |
|
561 | clk => clk, | |
| 562 | rstn => rstn, |
|
562 | rstn => rstn, | |
| 563 | in_valid => dma_rr_valid, |
|
563 | in_valid => dma_rr_valid, | |
| 564 | out_grant => dma_rr_grant_s); |
|
564 | out_grant => dma_rr_grant_s); | |
| 565 |
|
565 | |||
| 566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
| 567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
| 568 | dma_rr_valid_ms(2) <= '0'; |
|
568 | dma_rr_valid_ms(2) <= '0'; | |
| 569 | dma_rr_valid_ms(3) <= '0'; |
|
569 | dma_rr_valid_ms(3) <= '0'; | |
| 570 |
|
570 | |||
| 571 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
571 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
| 572 | PORT MAP ( |
|
572 | PORT MAP ( | |
| 573 | clk => clk, |
|
573 | clk => clk, | |
| 574 | rstn => rstn, |
|
574 | rstn => rstn, | |
| 575 | in_valid => dma_rr_valid_ms, |
|
575 | in_valid => dma_rr_valid_ms, | |
| 576 | out_grant => dma_rr_grant_ms); |
|
576 | out_grant => dma_rr_grant_ms); | |
| 577 |
|
577 | |||
| 578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
| 579 |
|
579 | |||
| 580 |
|
580 | |||
| 581 | ----------------------------------------------------------------------------- |
|
581 | ----------------------------------------------------------------------------- | |
| 582 | -- in : dma_rr_grant |
|
582 | -- in : dma_rr_grant | |
| 583 | -- send |
|
583 | -- send | |
| 584 | -- out : dma_sel |
|
584 | -- out : dma_sel | |
| 585 | -- dma_valid_burst |
|
585 | -- dma_valid_burst | |
| 586 | -- dma_sel_valid |
|
586 | -- dma_sel_valid | |
| 587 | ----------------------------------------------------------------------------- |
|
587 | ----------------------------------------------------------------------------- | |
| 588 | PROCESS (clk, rstn) |
|
588 | PROCESS (clk, rstn) | |
| 589 | BEGIN -- PROCESS |
|
589 | BEGIN -- PROCESS | |
| 590 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
590 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 591 | dma_sel <= (OTHERS => '0'); |
|
591 | dma_sel <= (OTHERS => '0'); | |
| 592 | dma_send <= '0'; |
|
592 | dma_send <= '0'; | |
| 593 | dma_valid_burst <= '0'; |
|
593 | dma_valid_burst <= '0'; | |
| 594 | data_ms_done <= '0'; |
|
594 | data_ms_done <= '0'; | |
| 595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 596 | IF run = '1' THEN |
|
596 | IF run = '1' THEN | |
| 597 | data_ms_done <= '0'; |
|
597 | data_ms_done <= '0'; | |
| 598 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
598 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
| 599 | dma_sel <= dma_rr_grant; |
|
599 | dma_sel <= dma_rr_grant; | |
| 600 | IF dma_rr_grant(0) = '1' THEN |
|
600 | IF dma_rr_grant(0) = '1' THEN | |
| 601 | dma_send <= '1'; |
|
601 | dma_send <= '1'; | |
| 602 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
602 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
| 603 | dma_sel_valid <= data_f0_data_out_valid; |
|
603 | dma_sel_valid <= data_f0_data_out_valid; | |
| 604 | ELSIF dma_rr_grant(1) = '1' THEN |
|
604 | ELSIF dma_rr_grant(1) = '1' THEN | |
| 605 | dma_send <= '1'; |
|
605 | dma_send <= '1'; | |
| 606 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
606 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
| 607 | dma_sel_valid <= data_f1_data_out_valid; |
|
607 | dma_sel_valid <= data_f1_data_out_valid; | |
| 608 | ELSIF dma_rr_grant(2) = '1' THEN |
|
608 | ELSIF dma_rr_grant(2) = '1' THEN | |
| 609 | dma_send <= '1'; |
|
609 | dma_send <= '1'; | |
| 610 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
610 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
| 611 | dma_sel_valid <= data_f2_data_out_valid; |
|
611 | dma_sel_valid <= data_f2_data_out_valid; | |
| 612 | ELSIF dma_rr_grant(3) = '1' THEN |
|
612 | ELSIF dma_rr_grant(3) = '1' THEN | |
| 613 | dma_send <= '1'; |
|
613 | dma_send <= '1'; | |
| 614 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
614 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
| 615 | dma_sel_valid <= data_f3_data_out_valid; |
|
615 | dma_sel_valid <= data_f3_data_out_valid; | |
| 616 | ELSIF dma_rr_grant(4) = '1' THEN |
|
616 | ELSIF dma_rr_grant(4) = '1' THEN | |
| 617 | dma_send <= '1'; |
|
617 | dma_send <= '1'; | |
| 618 | dma_valid_burst <= data_ms_valid_burst; |
|
618 | dma_valid_burst <= data_ms_valid_burst; | |
| 619 | dma_sel_valid <= data_ms_valid; |
|
619 | dma_sel_valid <= data_ms_valid; | |
| 620 | END IF; |
|
620 | END IF; | |
| 621 |
|
621 | |||
| 622 | IF dma_sel(4) = '1' THEN |
|
622 | IF dma_sel(4) = '1' THEN | |
| 623 | data_ms_done <= '1'; |
|
623 | data_ms_done <= '1'; | |
| 624 | END IF; |
|
624 | END IF; | |
| 625 | ELSE |
|
625 | ELSE | |
| 626 | dma_sel <= dma_sel; |
|
626 | dma_sel <= dma_sel; | |
| 627 | dma_send <= '0'; |
|
627 | dma_send <= '0'; | |
| 628 | END IF; |
|
628 | END IF; | |
| 629 | ELSE |
|
629 | ELSE | |
| 630 | data_ms_done <= '0'; |
|
630 | data_ms_done <= '0'; | |
| 631 | dma_sel <= (OTHERS => '0'); |
|
631 | dma_sel <= (OTHERS => '0'); | |
| 632 | dma_send <= '0'; |
|
632 | dma_send <= '0'; | |
| 633 | dma_valid_burst <= '0'; |
|
633 | dma_valid_burst <= '0'; | |
| 634 | END IF; |
|
634 | END IF; | |
| 635 | END IF; |
|
635 | END IF; | |
| 636 | END PROCESS; |
|
636 | END PROCESS; | |
| 637 |
|
637 | |||
| 638 |
|
638 | |||
| 639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
| 640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
| 641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
| 642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
| 643 | data_ms_addr; |
|
643 | data_ms_addr; | |
| 644 |
|
644 | |||
| 645 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
645 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
| 646 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
646 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
| 647 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
647 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
| 648 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
648 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
| 649 | data_ms_data; |
|
649 | data_ms_data; | |
| 650 |
|
650 | |||
| 651 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
651 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
| 652 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
652 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
| 653 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
653 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
| 654 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
654 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
| 655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |
| 656 |
|
656 | |||
| 657 | dma_data_2 <= dma_data; |
|
657 | dma_data_2 <= dma_data; | |
| 658 |
|
658 | |||
| 659 |
|
659 | |||
| 660 |
|
660 | |||
| 661 |
|
661 | |||
| 662 |
|
662 | |||
| 663 | ----------------------------------------------------------------------------- |
|
663 | ----------------------------------------------------------------------------- | |
| 664 | -- DEBUG -- DMA IN |
|
664 | -- DEBUG -- DMA IN | |
| 665 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
665 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
| 666 | --debug_f0_data_dma_in <= dma_data; |
|
666 | --debug_f0_data_dma_in <= dma_data; | |
| 667 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
667 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
| 668 | --debug_f1_data_dma_in <= dma_data; |
|
668 | --debug_f1_data_dma_in <= dma_data; | |
| 669 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
669 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
| 670 | --debug_f2_data_dma_in <= dma_data; |
|
670 | --debug_f2_data_dma_in <= dma_data; | |
| 671 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
671 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
| 672 | --debug_f3_data_dma_in <= dma_data; |
|
672 | --debug_f3_data_dma_in <= dma_data; | |
| 673 | ----------------------------------------------------------------------------- |
|
673 | ----------------------------------------------------------------------------- | |
| 674 |
|
674 | |||
| 675 | ----------------------------------------------------------------------------- |
|
675 | ----------------------------------------------------------------------------- | |
| 676 | -- DMA |
|
676 | -- DMA | |
| 677 | ----------------------------------------------------------------------------- |
|
677 | ----------------------------------------------------------------------------- | |
| 678 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
678 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
| 679 | GENERIC MAP ( |
|
679 | GENERIC MAP ( | |
| 680 | tech => inferred, |
|
680 | tech => inferred, | |
| 681 | hindex => hindex) |
|
681 | hindex => hindex) | |
| 682 | PORT MAP ( |
|
682 | PORT MAP ( | |
| 683 | HCLK => clk, |
|
683 | HCLK => clk, | |
| 684 | HRESETn => rstn, |
|
684 | HRESETn => rstn, | |
| 685 | run => run, |
|
685 | run => run, | |
| 686 | AHB_Master_In => ahbi, |
|
686 | AHB_Master_In => ahbi, | |
| 687 | AHB_Master_Out => ahbo, |
|
687 | AHB_Master_Out => ahbo, | |
| 688 |
|
688 | |||
| 689 | send => dma_send, |
|
689 | send => dma_send, | |
| 690 | valid_burst => dma_valid_burst, |
|
690 | valid_burst => dma_valid_burst, | |
| 691 | done => dma_done, |
|
691 | done => dma_done, | |
| 692 | ren => dma_ren, |
|
692 | ren => dma_ren, | |
| 693 | address => dma_address, |
|
693 | address => dma_address, | |
| 694 | data => dma_data_2); |
|
694 | data => dma_data_2); | |
| 695 |
|
695 | |||
| 696 | ----------------------------------------------------------------------------- |
|
696 | ----------------------------------------------------------------------------- | |
| 697 | -- Matrix Spectral |
|
697 | -- Matrix Spectral | |
| 698 | ----------------------------------------------------------------------------- |
|
698 | ----------------------------------------------------------------------------- | |
| 699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
| 700 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
700 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
| 701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
| 702 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
702 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
| 703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
| 704 | NOT(sample_f3_val) & NOT(sample_f3_val); |
|
704 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
| 705 |
|
705 | |||
| 706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
| 707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
| 708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
| 709 |
|
709 | |||
| 710 | ------------------------------------------------------------------------------- |
|
710 | ------------------------------------------------------------------------------- | |
| 711 |
|
711 | |||
| 712 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
712 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
| 713 |
|
713 | |||
| 714 | ----------------------------------------------------------------------------- |
|
714 | ----------------------------------------------------------------------------- | |
| 715 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
715 | lpp_lfr_ms_1 : lpp_lfr_ms | |
| 716 | GENERIC MAP ( |
|
716 | GENERIC MAP ( | |
| 717 | Mem_use => Mem_use) |
|
717 | Mem_use => Mem_use) | |
| 718 | PORT MAP ( |
|
718 | PORT MAP ( | |
| 719 | clk => clk, |
|
719 | clk => clk, | |
| 720 | rstn => ms_softandhard_rstn, --rstn, |
|
720 | rstn => ms_softandhard_rstn, --rstn, | |
| 721 |
|
721 | |||
| 722 | coarse_time => coarse_time, |
|
722 | coarse_time => coarse_time, | |
| 723 | fine_time => fine_time, |
|
723 | fine_time => fine_time, | |
| 724 |
|
724 | |||
| 725 | sample_f0_wen => sample_f0_wen, |
|
725 | sample_f0_wen => sample_f0_wen, | |
| 726 | sample_f0_wdata => sample_f0_wdata, |
|
726 | sample_f0_wdata => sample_f0_wdata, | |
| 727 | sample_f1_wen => sample_f1_wen, |
|
727 | sample_f1_wen => sample_f1_wen, | |
| 728 | sample_f1_wdata => sample_f1_wdata, |
|
728 | sample_f1_wdata => sample_f1_wdata, | |
| 729 |
sample_f |
|
729 | sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data | |
| 730 |
sample_f |
|
730 | sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data | |
| 731 |
|
731 | |||
| 732 | dma_addr => data_ms_addr, -- |
|
732 | dma_addr => data_ms_addr, -- | |
| 733 | dma_data => data_ms_data, -- |
|
733 | dma_data => data_ms_data, -- | |
| 734 | dma_valid => data_ms_valid, -- |
|
734 | dma_valid => data_ms_valid, -- | |
| 735 | dma_valid_burst => data_ms_valid_burst, -- |
|
735 | dma_valid_burst => data_ms_valid_burst, -- | |
| 736 | dma_ren => data_ms_ren, -- |
|
736 | dma_ren => data_ms_ren, -- | |
| 737 | dma_done => data_ms_done, -- |
|
737 | dma_done => data_ms_done, -- | |
| 738 |
|
738 | |||
| 739 |
ready_matrix_f0 |
|
739 | ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename | |
| 740 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
|||
| 741 | ready_matrix_f1 => ready_matrix_f1, |
|
740 | ready_matrix_f1 => ready_matrix_f1, | |
| 742 | ready_matrix_f2 => ready_matrix_f2, |
|
741 | ready_matrix_f2 => ready_matrix_f2, | |
| 743 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
742 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
| 744 | error_bad_component_error => error_bad_component_error, |
|
743 | error_bad_component_error => error_bad_component_error, | |
| 745 | debug_reg => observation_reg, --debug_reg, |
|
744 | error_buffer_full => OPEN, -- TODO | |
| 746 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
745 | error_input_fifo_write => OPEN, -- TODO | |
| 747 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
746 | debug_reg => observation_reg, | |
|
|
747 | status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename | |||
| 748 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
748 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
| 749 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
749 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
| 750 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
750 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
| 751 | status_error_bad_component_error => status_error_bad_component_error, |
|
751 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
| 752 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
752 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
| 753 | config_active_interruption_onError => config_active_interruption_onError, |
|
753 | config_active_interruption_onError => config_active_interruption_onError, | |
| 754 |
addr_matrix_f0 |
|
754 | addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename | |
| 755 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
|||
| 756 | addr_matrix_f1 => addr_matrix_f1, |
|
755 | addr_matrix_f1 => addr_matrix_f1, | |
| 757 | addr_matrix_f2 => addr_matrix_f2, |
|
756 | addr_matrix_f2 => addr_matrix_f2, | |
| 758 |
|
757 | |||
| 759 |
matrix_time_f0 |
|
758 | matrix_time_f0 => matrix_time_f0_0,-- TODO rename | |
| 760 | matrix_time_f0_1 => matrix_time_f0_1, |
|
|||
| 761 | matrix_time_f1 => matrix_time_f1, |
|
759 | matrix_time_f1 => matrix_time_f1, | |
| 762 | matrix_time_f2 => matrix_time_f2); |
|
760 | matrix_time_f2 => matrix_time_f2); | |
| 763 |
|
761 | |||
| 764 | END beh; |
|
762 | END beh; | |
| @@ -1,1078 +1,1067 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 |
|
3 | |||
| 4 |
|
4 | |||
| 5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
| 6 | USE lpp.lpp_memory.ALL; |
|
6 | USE lpp.lpp_memory.ALL; | |
| 7 | USE lpp.iir_filter.ALL; |
|
7 | USE lpp.iir_filter.ALL; | |
| 8 | USE lpp.spectral_matrix_package.ALL; |
|
8 | USE lpp.spectral_matrix_package.ALL; | |
| 9 | USE lpp.lpp_dma_pkg.ALL; |
|
9 | USE lpp.lpp_dma_pkg.ALL; | |
| 10 | USE lpp.lpp_Header.ALL; |
|
10 | USE lpp.lpp_Header.ALL; | |
| 11 | USE lpp.lpp_matrix.ALL; |
|
11 | USE lpp.lpp_matrix.ALL; | |
| 12 | USE lpp.lpp_matrix.ALL; |
|
12 | USE lpp.lpp_matrix.ALL; | |
| 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
| 14 | USE lpp.lpp_fft.ALL; |
|
14 | USE lpp.lpp_fft.ALL; | |
| 15 | USE lpp.fft_components.ALL; |
|
15 | USE lpp.fft_components.ALL; | |
| 16 |
|
16 | |||
| 17 | ENTITY lpp_lfr_ms IS |
|
17 | ENTITY lpp_lfr_ms IS | |
| 18 | GENERIC ( |
|
18 | GENERIC ( | |
| 19 | Mem_use : INTEGER := use_RAM |
|
19 | Mem_use : INTEGER := use_RAM | |
| 20 | ); |
|
20 | ); | |
| 21 | PORT ( |
|
21 | PORT ( | |
| 22 | clk : IN STD_LOGIC; |
|
22 | clk : IN STD_LOGIC; | |
| 23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
| 24 |
|
24 | |||
| 25 | --------------------------------------------------------------------------- |
|
25 | --------------------------------------------------------------------------- | |
| 26 | -- DATA INPUT |
|
26 | -- DATA INPUT | |
| 27 | --------------------------------------------------------------------------- |
|
27 | --------------------------------------------------------------------------- | |
| 28 | -- TIME |
|
28 | -- TIME | |
| 29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
| 30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
| 31 | -- |
|
31 | -- | |
| 32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 34 | -- |
|
34 | -- | |
| 35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 37 | -- |
|
37 | -- | |
| 38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 40 |
|
40 | |||
| 41 | --------------------------------------------------------------------------- |
|
41 | --------------------------------------------------------------------------- | |
| 42 | -- DMA |
|
42 | -- DMA | |
| 43 | --------------------------------------------------------------------------- |
|
43 | --------------------------------------------------------------------------- | |
| 44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 46 | dma_valid : OUT STD_LOGIC; |
|
46 | dma_valid : OUT STD_LOGIC; | |
| 47 | dma_valid_burst : OUT STD_LOGIC; |
|
47 | dma_valid_burst : OUT STD_LOGIC; | |
| 48 | dma_ren : IN STD_LOGIC; |
|
48 | dma_ren : IN STD_LOGIC; | |
| 49 | dma_done : IN STD_LOGIC; |
|
49 | dma_done : IN STD_LOGIC; | |
| 50 |
|
50 | |||
| 51 | -- Reg out |
|
51 | -- Reg out | |
| 52 | ready_matrix_f0 : OUT STD_LOGIC; |
|
52 | ready_matrix_f0 : OUT STD_LOGIC; | |
| 53 | -- ready_matrix_f0 : OUT STD_LOGIC; |
|
53 | -- ready_matrix_f0 : OUT STD_LOGIC; | |
| 54 | ready_matrix_f1 : OUT STD_LOGIC; |
|
54 | ready_matrix_f1 : OUT STD_LOGIC; | |
| 55 | ready_matrix_f2 : OUT STD_LOGIC; |
|
55 | ready_matrix_f2 : OUT STD_LOGIC; | |
| 56 | --error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
56 | --error_anticipating_empty_fifo : OUT STD_LOGIC; | |
| 57 | error_bad_component_error : OUT STD_LOGIC; |
|
57 | error_bad_component_error : OUT STD_LOGIC; | |
| 58 | error_buffer_full : OUT STD_LOGIC; |
|
58 | error_buffer_full : OUT STD_LOGIC; | |
| 59 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
59 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
| 60 |
|
60 | |||
| 61 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
61 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 62 |
|
62 | |||
| 63 | -- Reg In |
|
63 | -- Reg In | |
| 64 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
64 | status_ready_matrix_f0 : IN STD_LOGIC; | |
| 65 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
65 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
| 66 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
66 | status_ready_matrix_f1 : IN STD_LOGIC; | |
| 67 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
67 | status_ready_matrix_f2 : IN STD_LOGIC; | |
| 68 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
68 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
| 69 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
69 | -- status_error_bad_component_error : IN STD_LOGIC; | |
| 70 | -- status_error_buffer_full : IN STD_LOGIC; |
|
70 | -- status_error_buffer_full : IN STD_LOGIC; | |
| 71 |
|
71 | |||
| 72 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
72 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
| 73 | config_active_interruption_onError : IN STD_LOGIC; |
|
73 | config_active_interruption_onError : IN STD_LOGIC; | |
| 74 | -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 78 |
|
78 | |||
| 79 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
79 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 80 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
80 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 81 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
81 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 82 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
82 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
| 83 |
|
83 | |||
| 84 | ); |
|
84 | ); | |
| 85 | END; |
|
85 | END; | |
| 86 |
|
86 | |||
| 87 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
87 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
| 88 |
|
88 | |||
| 89 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
89 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 90 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
90 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 91 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 92 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 93 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
93 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 94 |
|
94 | |||
| 95 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
95 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 96 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
96 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 97 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 98 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
98 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 99 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 100 |
|
100 | |||
| 101 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
101 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 102 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
102 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 103 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
103 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 104 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
104 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 105 |
|
105 | |||
| 106 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
106 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 107 |
|
107 | |||
| 108 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
108 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 109 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 110 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
110 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 111 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
111 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 112 |
|
112 | |||
| 113 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
113 | SIGNAL error_wen_f0 : STD_LOGIC; | |
| 114 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
114 | SIGNAL error_wen_f1 : STD_LOGIC; | |
| 115 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
115 | SIGNAL error_wen_f2 : STD_LOGIC; | |
| 116 |
|
116 | |||
| 117 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
117 | SIGNAL one_sample_f1_full : STD_LOGIC; | |
| 118 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
118 | SIGNAL one_sample_f1_wen : STD_LOGIC; | |
| 119 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
119 | SIGNAL one_sample_f2_full : STD_LOGIC; | |
| 120 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
120 | SIGNAL one_sample_f2_wen : STD_LOGIC; | |
| 121 |
|
121 | |||
| 122 | ----------------------------------------------------------------------------- |
|
122 | ----------------------------------------------------------------------------- | |
| 123 | -- FSM / SWITCH SELECT CHANNEL |
|
123 | -- FSM / SWITCH SELECT CHANNEL | |
| 124 | ----------------------------------------------------------------------------- |
|
124 | ----------------------------------------------------------------------------- | |
| 125 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
125 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); | |
| 126 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
126 | SIGNAL state_fsm_select_channel : fsm_select_channel; | |
| 127 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
127 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
| 128 |
|
128 | |||
| 129 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 130 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
130 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 131 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
131 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 132 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
132 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 133 |
|
133 | |||
| 134 | ----------------------------------------------------------------------------- |
|
134 | ----------------------------------------------------------------------------- | |
| 135 | -- FSM LOAD FFT |
|
135 | -- FSM LOAD FFT | |
| 136 | ----------------------------------------------------------------------------- |
|
136 | ----------------------------------------------------------------------------- | |
| 137 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
137 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
| 138 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
138 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; | |
| 139 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
139 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
| 140 |
|
140 | |||
| 141 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
141 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 142 | SIGNAL sample_load : STD_LOGIC; |
|
142 | SIGNAL sample_load : STD_LOGIC; | |
| 143 | SIGNAL sample_valid : STD_LOGIC; |
|
143 | SIGNAL sample_valid : STD_LOGIC; | |
| 144 | SIGNAL sample_valid_r : STD_LOGIC; |
|
144 | SIGNAL sample_valid_r : STD_LOGIC; | |
| 145 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
145 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 146 |
|
146 | |||
| 147 |
|
147 | |||
| 148 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
| 149 | -- FFT |
|
149 | -- FFT | |
| 150 | ----------------------------------------------------------------------------- |
|
150 | ----------------------------------------------------------------------------- | |
| 151 | SIGNAL fft_read : STD_LOGIC; |
|
151 | SIGNAL fft_read : STD_LOGIC; | |
| 152 | SIGNAL fft_pong : STD_LOGIC; |
|
152 | SIGNAL fft_pong : STD_LOGIC; | |
| 153 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
153 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 154 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
154 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 155 | SIGNAL fft_data_valid : STD_LOGIC; |
|
155 | SIGNAL fft_data_valid : STD_LOGIC; | |
| 156 | SIGNAL fft_ready : STD_LOGIC; |
|
156 | SIGNAL fft_ready : STD_LOGIC; | |
| 157 | ----------------------------------------------------------------------------- |
|
157 | ----------------------------------------------------------------------------- | |
| 158 | SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
158 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 159 | ----------------------------------------------------------------------------- |
|
159 | ----------------------------------------------------------------------------- | |
| 160 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
160 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
| 161 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
161 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
| 162 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
162 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 163 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
163 | SIGNAL current_fifo_empty : STD_LOGIC; | |
| 164 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
164 | SIGNAL current_fifo_locked : STD_LOGIC; | |
| 165 | SIGNAL current_fifo_full : STD_LOGIC; |
|
165 | SIGNAL current_fifo_full : STD_LOGIC; | |
| 166 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
166 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 167 |
|
167 | |||
| 168 | ----------------------------------------------------------------------------- |
|
168 | ----------------------------------------------------------------------------- | |
| 169 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
169 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 170 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
170 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 171 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 172 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
172 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 173 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
173 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
| 174 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
174 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
| 175 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
175 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 176 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
176 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 177 | ----------------------------------------------------------------------------- |
|
177 | ----------------------------------------------------------------------------- | |
| 178 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
178 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
| 179 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
179 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 180 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
180 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 181 |
|
181 | |||
| 182 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
182 | SIGNAL SM_correlation_start : STD_LOGIC; | |
| 183 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
183 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
| 184 | SIGNAL SM_correlation_done : STD_LOGIC; |
|
184 | SIGNAL SM_correlation_done : STD_LOGIC; | |
| 185 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
185 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; | |
| 186 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
186 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; | |
|
|
187 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; | |||
| 187 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
188 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
| 188 |
|
189 | |||
| 189 |
|
|
190 | -- SIGNAL temp_ongoing : STD_LOGIC; | |
| 190 | SIGNAL temp_auto : STD_LOGIC; |
|
191 | -- SIGNAL temp_auto : STD_LOGIC; | |
| 191 |
|
192 | |||
| 192 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; |
|
193 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
| 193 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
194 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 194 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; |
|
195 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
| 195 |
|
196 | |||
| 196 | SIGNAL current_matrix_write : STD_LOGIC; |
|
197 | SIGNAL current_matrix_write : STD_LOGIC; | |
| 197 | SIGNAL current_matrix_wait_empty : STD_LOGIC; |
|
198 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
| 198 |
|
199 | |||
| 199 | --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
200 | --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 200 |
|
201 | |||
| 201 | ----------------------------------------------------------------------------- |
|
202 | ----------------------------------------------------------------------------- | |
| 202 | SIGNAL fifo_0_ready : STD_LOGIC; |
|
203 | SIGNAL fifo_0_ready : STD_LOGIC; | |
| 203 | SIGNAL fifo_1_ready : STD_LOGIC; |
|
204 | SIGNAL fifo_1_ready : STD_LOGIC; | |
| 204 | SIGNAL fifo_ongoing : STD_LOGIC; |
|
205 | SIGNAL fifo_ongoing : STD_LOGIC; | |
| 205 |
|
206 | |||
| 206 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
207 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
| 207 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
208 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
| 208 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
209 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 209 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
210 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
| 210 |
|
211 | |||
| 211 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
| 212 | SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
213 | -- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 213 | SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
214 | --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 214 | SIGNAL HEAD_SM_Wen : STD_LOGIC; |
|
215 | --SIGNAL HEAD_SM_Wen : STD_LOGIC; | |
| 215 | SIGNAL HEAD_Valid : STD_LOGIC; |
|
216 | --SIGNAL HEAD_Valid : STD_LOGIC; | |
| 216 | SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
217 | --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 217 | SIGNAL HEAD_Empty : STD_LOGIC; |
|
218 | --SIGNAL HEAD_Empty : STD_LOGIC; | |
| 218 | SIGNAL HEAD_Read : STD_LOGIC; |
|
219 | --SIGNAL HEAD_Read : STD_LOGIC; | |
| 219 | ----------------------------------------------------------------------------- |
|
220 | ----------------------------------------------------------------------------- | |
| 220 | SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
221 | -- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 221 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
222 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 222 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
223 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 223 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
224 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
| 224 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
225 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
| 225 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
226 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 226 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
227 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 227 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
| 228 | SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
229 | --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 229 | SIGNAL DMA_Header_Val : STD_LOGIC; |
|
230 | --SIGNAL DMA_Header_Val : STD_LOGIC; | |
| 230 | SIGNAL DMA_Header_Ack : STD_LOGIC; |
|
231 | --SIGNAL DMA_Header_Ack : STD_LOGIC; | |
| 231 |
|
232 | |||
| 232 | ----------------------------------------------------------------------------- |
|
233 | ----------------------------------------------------------------------------- | |
| 233 | -- TIME REG & INFOs |
|
234 | -- TIME REG & INFOs | |
| 234 | ----------------------------------------------------------------------------- |
|
235 | ----------------------------------------------------------------------------- | |
| 235 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
236 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 236 |
|
237 | |||
| 237 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
238 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 238 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
239 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 239 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
240 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 240 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
241 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 241 |
|
242 | |||
| 242 | SIGNAL time_update_f0_A : STD_LOGIC; |
|
243 | SIGNAL time_update_f0_A : STD_LOGIC; | |
| 243 | SIGNAL time_update_f0_B : STD_LOGIC; |
|
244 | SIGNAL time_update_f0_B : STD_LOGIC; | |
| 244 | SIGNAL time_update_f1 : STD_LOGIC; |
|
245 | SIGNAL time_update_f1 : STD_LOGIC; | |
| 245 | SIGNAL time_update_f2 : STD_LOGIC; |
|
246 | SIGNAL time_update_f2 : STD_LOGIC; | |
| 246 | -- |
|
247 | -- | |
| 247 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
248 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
| 248 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
249 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
| 249 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
250 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
| 250 |
|
251 | |||
| 251 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
252 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
| 252 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
253 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
| 253 | SIGNAL status_component_fifo_0_new : STD_LOGIC; |
|
254 | -- SIGNAL status_component_fifo_0_new : STD_LOGIC; | |
| 254 | SIGNAL status_component_fifo_1_new : STD_LOGIC; |
|
255 | -- SIGNAL status_component_fifo_1_new : STD_LOGIC; | |
| 255 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
256 | SIGNAL status_component_fifo_0_end : STD_LOGIC; | |
| 256 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
257 | SIGNAL status_component_fifo_1_end : STD_LOGIC; | |
| 257 |
|
258 | |||
| 258 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
259 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 259 | ----------------------------------------------------------------------------- |
|
260 | ----------------------------------------------------------------------------- | |
| 260 |
|
261 | |||
| 261 | BEGIN |
|
262 | BEGIN | |
| 262 |
|
263 | |||
| 263 |
|
264 | |||
| 264 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
|
265 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
| 265 |
|
266 | |||
| 266 |
|
267 | |||
| 267 | switch_f0_inst : spectral_matrix_switch_f0 |
|
268 | switch_f0_inst : spectral_matrix_switch_f0 | |
| 268 | PORT MAP ( |
|
269 | PORT MAP ( | |
| 269 | clk => clk, |
|
270 | clk => clk, | |
| 270 | rstn => rstn, |
|
271 | rstn => rstn, | |
| 271 |
|
272 | |||
| 272 | sample_wen => sample_f0_wen, |
|
273 | sample_wen => sample_f0_wen, | |
| 273 |
|
274 | |||
| 274 | fifo_A_empty => sample_f0_A_empty, |
|
275 | fifo_A_empty => sample_f0_A_empty, | |
| 275 | fifo_A_full => sample_f0_A_full, |
|
276 | fifo_A_full => sample_f0_A_full, | |
| 276 | fifo_A_wen => sample_f0_A_wen, |
|
277 | fifo_A_wen => sample_f0_A_wen, | |
| 277 |
|
278 | |||
| 278 | fifo_B_empty => sample_f0_B_empty, |
|
279 | fifo_B_empty => sample_f0_B_empty, | |
| 279 | fifo_B_full => sample_f0_B_full, |
|
280 | fifo_B_full => sample_f0_B_full, | |
| 280 | fifo_B_wen => sample_f0_B_wen, |
|
281 | fifo_B_wen => sample_f0_B_wen, | |
| 281 |
|
282 | |||
| 282 | error_wen => error_wen_f0); -- TODO |
|
283 | error_wen => error_wen_f0); -- TODO | |
| 283 |
|
284 | |||
| 284 | ----------------------------------------------------------------------------- |
|
285 | ----------------------------------------------------------------------------- | |
| 285 | -- FIFO IN |
|
286 | -- FIFO IN | |
| 286 | ----------------------------------------------------------------------------- |
|
287 | ----------------------------------------------------------------------------- | |
| 287 | lppFIFOxN_f0_a : lppFIFOxN |
|
288 | lppFIFOxN_f0_a : lppFIFOxN | |
| 288 | GENERIC MAP ( |
|
289 | GENERIC MAP ( | |
| 289 | tech => 0, |
|
290 | tech => 0, | |
| 290 | Mem_use => Mem_use, |
|
291 | Mem_use => Mem_use, | |
| 291 | Data_sz => 16, |
|
292 | Data_sz => 16, | |
| 292 | Addr_sz => 8, |
|
293 | Addr_sz => 8, | |
| 293 | FifoCnt => 5) |
|
294 | FifoCnt => 5) | |
| 294 | PORT MAP ( |
|
295 | PORT MAP ( | |
| 295 | clk => clk, |
|
296 | clk => clk, | |
| 296 | rstn => rstn, |
|
297 | rstn => rstn, | |
| 297 |
|
298 | |||
| 298 | ReUse => (OTHERS => '0'), |
|
299 | ReUse => (OTHERS => '0'), | |
| 299 |
|
300 | |||
| 300 | wen => sample_f0_A_wen, |
|
301 | wen => sample_f0_A_wen, | |
| 301 | wdata => sample_f0_wdata, |
|
302 | wdata => sample_f0_wdata, | |
| 302 |
|
303 | |||
| 303 | ren => sample_f0_A_ren, |
|
304 | ren => sample_f0_A_ren, | |
| 304 | rdata => sample_f0_A_rdata, |
|
305 | rdata => sample_f0_A_rdata, | |
| 305 |
|
306 | |||
| 306 | empty => sample_f0_A_empty, |
|
307 | empty => sample_f0_A_empty, | |
| 307 | full => sample_f0_A_full, |
|
308 | full => sample_f0_A_full, | |
| 308 | almost_full => OPEN); |
|
309 | almost_full => OPEN); | |
| 309 |
|
310 | |||
| 310 | lppFIFOxN_f0_b : lppFIFOxN |
|
311 | lppFIFOxN_f0_b : lppFIFOxN | |
| 311 | GENERIC MAP ( |
|
312 | GENERIC MAP ( | |
| 312 | tech => 0, |
|
313 | tech => 0, | |
| 313 | Mem_use => Mem_use, |
|
314 | Mem_use => Mem_use, | |
| 314 | Data_sz => 16, |
|
315 | Data_sz => 16, | |
| 315 | Addr_sz => 8, |
|
316 | Addr_sz => 8, | |
| 316 | FifoCnt => 5) |
|
317 | FifoCnt => 5) | |
| 317 | PORT MAP ( |
|
318 | PORT MAP ( | |
| 318 | clk => clk, |
|
319 | clk => clk, | |
| 319 | rstn => rstn, |
|
320 | rstn => rstn, | |
| 320 |
|
321 | |||
| 321 | ReUse => (OTHERS => '0'), |
|
322 | ReUse => (OTHERS => '0'), | |
| 322 |
|
323 | |||
| 323 | wen => sample_f0_B_wen, |
|
324 | wen => sample_f0_B_wen, | |
| 324 | wdata => sample_f0_wdata, |
|
325 | wdata => sample_f0_wdata, | |
| 325 | ren => sample_f0_B_ren, |
|
326 | ren => sample_f0_B_ren, | |
| 326 | rdata => sample_f0_B_rdata, |
|
327 | rdata => sample_f0_B_rdata, | |
| 327 | empty => sample_f0_B_empty, |
|
328 | empty => sample_f0_B_empty, | |
| 328 | full => sample_f0_B_full, |
|
329 | full => sample_f0_B_full, | |
| 329 | almost_full => OPEN); |
|
330 | almost_full => OPEN); | |
| 330 |
|
331 | |||
| 331 | lppFIFOxN_f1 : lppFIFOxN |
|
332 | lppFIFOxN_f1 : lppFIFOxN | |
| 332 | GENERIC MAP ( |
|
333 | GENERIC MAP ( | |
| 333 | tech => 0, |
|
334 | tech => 0, | |
| 334 | Mem_use => Mem_use, |
|
335 | Mem_use => Mem_use, | |
| 335 | Data_sz => 16, |
|
336 | Data_sz => 16, | |
| 336 | Addr_sz => 8, |
|
337 | Addr_sz => 8, | |
| 337 | FifoCnt => 5) |
|
338 | FifoCnt => 5) | |
| 338 | PORT MAP ( |
|
339 | PORT MAP ( | |
| 339 | clk => clk, |
|
340 | clk => clk, | |
| 340 | rstn => rstn, |
|
341 | rstn => rstn, | |
| 341 |
|
342 | |||
| 342 | ReUse => (OTHERS => '0'), |
|
343 | ReUse => (OTHERS => '0'), | |
| 343 |
|
344 | |||
| 344 | wen => sample_f1_wen, |
|
345 | wen => sample_f1_wen, | |
| 345 | wdata => sample_f1_wdata, |
|
346 | wdata => sample_f1_wdata, | |
| 346 | ren => sample_f1_ren, |
|
347 | ren => sample_f1_ren, | |
| 347 | rdata => sample_f1_rdata, |
|
348 | rdata => sample_f1_rdata, | |
| 348 | empty => sample_f1_empty, |
|
349 | empty => sample_f1_empty, | |
| 349 | full => sample_f1_full, |
|
350 | full => sample_f1_full, | |
| 350 | almost_full => sample_f1_almost_full); |
|
351 | almost_full => sample_f1_almost_full); | |
| 351 |
|
352 | |||
| 352 |
|
353 | |||
| 353 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
354 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; | |
| 354 |
|
355 | |||
| 355 | PROCESS (clk, rstn) |
|
356 | PROCESS (clk, rstn) | |
| 356 | BEGIN -- PROCESS |
|
357 | BEGIN -- PROCESS | |
| 357 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
358 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 358 | one_sample_f1_full <= '0'; |
|
359 | one_sample_f1_full <= '0'; | |
| 359 | error_wen_f1 <= '0'; |
|
360 | error_wen_f1 <= '0'; | |
| 360 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
361 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 361 | IF sample_f1_full = "00000" THEN |
|
362 | IF sample_f1_full = "00000" THEN | |
| 362 | one_sample_f1_full <= '0'; |
|
363 | one_sample_f1_full <= '0'; | |
| 363 | ELSE |
|
364 | ELSE | |
| 364 | one_sample_f1_full <= '1'; |
|
365 | one_sample_f1_full <= '1'; | |
| 365 | END IF; |
|
366 | END IF; | |
| 366 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
367 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; | |
| 367 | END IF; |
|
368 | END IF; | |
| 368 | END PROCESS; |
|
369 | END PROCESS; | |
| 369 |
|
370 | |||
| 370 |
|
371 | |||
| 371 | lppFIFOxN_f2 : lppFIFOxN |
|
372 | lppFIFOxN_f2 : lppFIFOxN | |
| 372 | GENERIC MAP ( |
|
373 | GENERIC MAP ( | |
| 373 | tech => 0, |
|
374 | tech => 0, | |
| 374 | Mem_use => Mem_use, |
|
375 | Mem_use => Mem_use, | |
| 375 | Data_sz => 16, |
|
376 | Data_sz => 16, | |
| 376 | Addr_sz => 8, |
|
377 | Addr_sz => 8, | |
| 377 | FifoCnt => 5) |
|
378 | FifoCnt => 5) | |
| 378 | PORT MAP ( |
|
379 | PORT MAP ( | |
| 379 | clk => clk, |
|
380 | clk => clk, | |
| 380 | rstn => rstn, |
|
381 | rstn => rstn, | |
| 381 |
|
382 | |||
| 382 | ReUse => (OTHERS => '0'), |
|
383 | ReUse => (OTHERS => '0'), | |
| 383 |
|
384 | |||
| 384 | wen => sample_f2_wen, |
|
385 | wen => sample_f2_wen, | |
| 385 | wdata => sample_f2_wdata, |
|
386 | wdata => sample_f2_wdata, | |
| 386 | ren => sample_f2_ren, |
|
387 | ren => sample_f2_ren, | |
| 387 | rdata => sample_f2_rdata, |
|
388 | rdata => sample_f2_rdata, | |
| 388 | empty => sample_f2_empty, |
|
389 | empty => sample_f2_empty, | |
| 389 | full => sample_f2_full, |
|
390 | full => sample_f2_full, | |
| 390 | almost_full => OPEN); |
|
391 | almost_full => OPEN); | |
| 391 |
|
392 | |||
| 392 |
|
393 | |||
| 393 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
394 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; | |
| 394 |
|
395 | |||
| 395 | PROCESS (clk, rstn) |
|
396 | PROCESS (clk, rstn) | |
| 396 | BEGIN -- PROCESS |
|
397 | BEGIN -- PROCESS | |
| 397 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
398 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 398 | one_sample_f2_full <= '0'; |
|
399 | one_sample_f2_full <= '0'; | |
| 399 | error_wen_f2 <= '0'; |
|
400 | error_wen_f2 <= '0'; | |
| 400 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
401 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
| 401 | IF sample_f2_full = "00000" THEN |
|
402 | IF sample_f2_full = "00000" THEN | |
| 402 | one_sample_f2_full <= '0'; |
|
403 | one_sample_f2_full <= '0'; | |
| 403 | ELSE |
|
404 | ELSE | |
| 404 | one_sample_f2_full <= '1'; |
|
405 | one_sample_f2_full <= '1'; | |
| 405 | END IF; |
|
406 | END IF; | |
| 406 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
407 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; | |
| 407 | END IF; |
|
408 | END IF; | |
| 408 | END PROCESS; |
|
409 | END PROCESS; | |
| 409 |
|
410 | |||
| 410 | ----------------------------------------------------------------------------- |
|
411 | ----------------------------------------------------------------------------- | |
| 411 | -- FSM SELECT CHANNEL |
|
412 | -- FSM SELECT CHANNEL | |
| 412 | ----------------------------------------------------------------------------- |
|
413 | ----------------------------------------------------------------------------- | |
| 413 | PROCESS (clk, rstn) |
|
414 | PROCESS (clk, rstn) | |
| 414 | BEGIN |
|
415 | BEGIN | |
| 415 | IF rstn = '0' THEN |
|
416 | IF rstn = '0' THEN | |
| 416 | state_fsm_select_channel <= IDLE; |
|
417 | state_fsm_select_channel <= IDLE; | |
| 417 | ELSIF clk'EVENT AND clk = '1' THEN |
|
418 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 418 | CASE state_fsm_select_channel IS |
|
419 | CASE state_fsm_select_channel IS | |
| 419 | WHEN IDLE => |
|
420 | WHEN IDLE => | |
| 420 | IF sample_f1_full = "11111" THEN |
|
421 | IF sample_f1_full = "11111" THEN | |
| 421 | state_fsm_select_channel <= SWITCH_F1; |
|
422 | state_fsm_select_channel <= SWITCH_F1; | |
| 422 | ELSIF sample_f1_almost_full = "00000" THEN |
|
423 | ELSIF sample_f1_almost_full = "00000" THEN | |
| 423 | IF sample_f0_A_full = "11111" THEN |
|
424 | IF sample_f0_A_full = "11111" THEN | |
| 424 | state_fsm_select_channel <= SWITCH_F0_A; |
|
425 | state_fsm_select_channel <= SWITCH_F0_A; | |
| 425 | ELSIF sample_f0_B_full = "11111" THEN |
|
426 | ELSIF sample_f0_B_full = "11111" THEN | |
| 426 | state_fsm_select_channel <= SWITCH_F0_B; |
|
427 | state_fsm_select_channel <= SWITCH_F0_B; | |
| 427 | ELSIF sample_f2_full = "11111" THEN |
|
428 | ELSIF sample_f2_full = "11111" THEN | |
| 428 | state_fsm_select_channel <= SWITCH_F2; |
|
429 | state_fsm_select_channel <= SWITCH_F2; | |
| 429 | END IF; |
|
430 | END IF; | |
| 430 | END IF; |
|
431 | END IF; | |
| 431 |
|
432 | |||
| 432 | WHEN SWITCH_F0_A => |
|
433 | WHEN SWITCH_F0_A => | |
| 433 | IF sample_f0_A_empty = "11111" THEN |
|
434 | IF sample_f0_A_empty = "11111" THEN | |
| 434 | state_fsm_select_channel <= IDLE; |
|
435 | state_fsm_select_channel <= IDLE; | |
| 435 | END IF; |
|
436 | END IF; | |
| 436 | WHEN SWITCH_F0_B => |
|
437 | WHEN SWITCH_F0_B => | |
| 437 | IF sample_f0_B_empty = "11111" THEN |
|
438 | IF sample_f0_B_empty = "11111" THEN | |
| 438 | state_fsm_select_channel <= IDLE; |
|
439 | state_fsm_select_channel <= IDLE; | |
| 439 | END IF; |
|
440 | END IF; | |
| 440 | WHEN SWITCH_F1 => |
|
441 | WHEN SWITCH_F1 => | |
| 441 | IF sample_f1_empty = "11111" THEN |
|
442 | IF sample_f1_empty = "11111" THEN | |
| 442 | state_fsm_select_channel <= IDLE; |
|
443 | state_fsm_select_channel <= IDLE; | |
| 443 | END IF; |
|
444 | END IF; | |
| 444 | WHEN SWITCH_F2 => |
|
445 | WHEN SWITCH_F2 => | |
| 445 | IF sample_f2_empty = "11111" THEN |
|
446 | IF sample_f2_empty = "11111" THEN | |
| 446 | state_fsm_select_channel <= IDLE; |
|
447 | state_fsm_select_channel <= IDLE; | |
| 447 | END IF; |
|
448 | END IF; | |
| 448 | WHEN OTHERS => NULL; |
|
449 | WHEN OTHERS => NULL; | |
| 449 | END CASE; |
|
450 | END CASE; | |
| 450 |
|
451 | |||
| 451 | END IF; |
|
452 | END IF; | |
| 452 | END PROCESS; |
|
453 | END PROCESS; | |
| 453 |
|
454 | |||
| 454 | PROCESS (clk, rstn) |
|
455 | PROCESS (clk, rstn) | |
| 455 | BEGIN |
|
456 | BEGIN | |
| 456 | IF rstn = '0' THEN |
|
457 | IF rstn = '0' THEN | |
| 457 | pre_state_fsm_select_channel <= IDLE; |
|
458 | pre_state_fsm_select_channel <= IDLE; | |
| 458 | ELSIF clk'EVENT AND clk = '1' THEN |
|
459 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 459 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
460 | pre_state_fsm_select_channel <= state_fsm_select_channel; | |
| 460 | END IF; |
|
461 | END IF; | |
| 461 | END PROCESS; |
|
462 | END PROCESS; | |
| 462 |
|
463 | |||
| 463 |
|
464 | |||
| 464 | ----------------------------------------------------------------------------- |
|
465 | ----------------------------------------------------------------------------- | |
| 465 | -- SWITCH SELECT CHANNEL |
|
466 | -- SWITCH SELECT CHANNEL | |
| 466 | ----------------------------------------------------------------------------- |
|
467 | ----------------------------------------------------------------------------- | |
| 467 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
468 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
| 468 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
469 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
| 469 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
470 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
| 470 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
471 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
| 471 | (OTHERS => '1'); |
|
472 | (OTHERS => '1'); | |
| 472 |
|
473 | |||
| 473 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
474 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
| 474 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
475 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
| 475 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
476 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
| 476 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
477 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
| 477 | (OTHERS => '0'); |
|
478 | (OTHERS => '0'); | |
| 478 |
|
479 | |||
| 479 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
480 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
| 480 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
481 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
| 481 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
482 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
| 482 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
483 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
| 483 |
|
484 | |||
| 484 |
|
485 | |||
| 485 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
486 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); | |
| 486 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
487 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); | |
| 487 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
488 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); | |
| 488 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
489 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); | |
| 489 |
|
490 | |||
| 490 |
|
491 | |||
| 491 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
492 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
| 492 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
493 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
| 493 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
494 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
| 494 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
495 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
| 495 |
|
496 | |||
| 496 | ----------------------------------------------------------------------------- |
|
497 | ----------------------------------------------------------------------------- | |
| 497 | -- FSM LOAD FFT |
|
498 | -- FSM LOAD FFT | |
| 498 | ----------------------------------------------------------------------------- |
|
499 | ----------------------------------------------------------------------------- | |
| 499 |
|
500 | |||
| 500 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); |
|
501 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); | |
| 501 |
|
502 | |||
| 502 | PROCESS (clk, rstn) |
|
503 | PROCESS (clk, rstn) | |
| 503 | BEGIN |
|
504 | BEGIN | |
| 504 | IF rstn = '0' THEN |
|
505 | IF rstn = '0' THEN | |
| 505 | sample_ren_s <= (OTHERS => '1'); |
|
506 | sample_ren_s <= (OTHERS => '1'); | |
| 506 | state_fsm_load_FFT <= IDLE; |
|
507 | state_fsm_load_FFT <= IDLE; | |
| 507 | status_MS_input <= (OTHERS => '0'); |
|
508 | status_MS_input <= (OTHERS => '0'); | |
| 508 | --next_state_fsm_load_FFT <= IDLE; |
|
509 | --next_state_fsm_load_FFT <= IDLE; | |
| 509 | --sample_valid <= '0'; |
|
510 | --sample_valid <= '0'; | |
| 510 | ELSIF clk'EVENT AND clk = '1' THEN |
|
511 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 511 | CASE state_fsm_load_FFT IS |
|
512 | CASE state_fsm_load_FFT IS | |
| 512 | WHEN IDLE => |
|
513 | WHEN IDLE => | |
| 513 | --sample_valid <= '0'; |
|
514 | --sample_valid <= '0'; | |
| 514 | sample_ren_s <= (OTHERS => '1'); |
|
515 | sample_ren_s <= (OTHERS => '1'); | |
| 515 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
516 | IF sample_full = "11111" AND sample_load = '1' THEN | |
| 516 | state_fsm_load_FFT <= FIFO_1; |
|
517 | state_fsm_load_FFT <= FIFO_1; | |
| 517 | status_MS_input <= status_channel; |
|
518 | status_MS_input <= status_channel; | |
| 518 | END IF; |
|
519 | END IF; | |
| 519 |
|
520 | |||
| 520 | WHEN FIFO_1 => |
|
521 | WHEN FIFO_1 => | |
| 521 | sample_ren_s <= "1111" & NOT(sample_load); |
|
522 | sample_ren_s <= "1111" & NOT(sample_load); | |
| 522 | IF sample_empty(0) = '1' THEN |
|
523 | IF sample_empty(0) = '1' THEN | |
| 523 | sample_ren_s <= (OTHERS => '1'); |
|
524 | sample_ren_s <= (OTHERS => '1'); | |
| 524 | state_fsm_load_FFT <= FIFO_2; |
|
525 | state_fsm_load_FFT <= FIFO_2; | |
| 525 | END IF; |
|
526 | END IF; | |
| 526 |
|
527 | |||
| 527 | WHEN FIFO_2 => |
|
528 | WHEN FIFO_2 => | |
| 528 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
529 | sample_ren_s <= "111" & NOT(sample_load) & '1'; | |
| 529 | IF sample_empty(1) = '1' THEN |
|
530 | IF sample_empty(1) = '1' THEN | |
| 530 | sample_ren_s <= (OTHERS => '1'); |
|
531 | sample_ren_s <= (OTHERS => '1'); | |
| 531 | state_fsm_load_FFT <= FIFO_3; |
|
532 | state_fsm_load_FFT <= FIFO_3; | |
| 532 | END IF; |
|
533 | END IF; | |
| 533 |
|
534 | |||
| 534 | WHEN FIFO_3 => |
|
535 | WHEN FIFO_3 => | |
| 535 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
536 | sample_ren_s <= "11" & NOT(sample_load) & "11"; | |
| 536 | IF sample_empty(2) = '1' THEN |
|
537 | IF sample_empty(2) = '1' THEN | |
| 537 | sample_ren_s <= (OTHERS => '1'); |
|
538 | sample_ren_s <= (OTHERS => '1'); | |
| 538 | state_fsm_load_FFT <= FIFO_4; |
|
539 | state_fsm_load_FFT <= FIFO_4; | |
| 539 | END IF; |
|
540 | END IF; | |
| 540 |
|
541 | |||
| 541 | WHEN FIFO_4 => |
|
542 | WHEN FIFO_4 => | |
| 542 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
543 | sample_ren_s <= '1' & NOT(sample_load) & "111"; | |
| 543 | IF sample_empty(3) = '1' THEN |
|
544 | IF sample_empty(3) = '1' THEN | |
| 544 | sample_ren_s <= (OTHERS => '1'); |
|
545 | sample_ren_s <= (OTHERS => '1'); | |
| 545 | state_fsm_load_FFT <= FIFO_5; |
|
546 | state_fsm_load_FFT <= FIFO_5; | |
| 546 | END IF; |
|
547 | END IF; | |
| 547 |
|
548 | |||
| 548 | WHEN FIFO_5 => |
|
549 | WHEN FIFO_5 => | |
| 549 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
550 | sample_ren_s <= NOT(sample_load) & "1111"; | |
| 550 | IF sample_empty(4) = '1' THEN |
|
551 | IF sample_empty(4) = '1' THEN | |
| 551 | sample_ren_s <= (OTHERS => '1'); |
|
552 | sample_ren_s <= (OTHERS => '1'); | |
| 552 | state_fsm_load_FFT <= IDLE; |
|
553 | state_fsm_load_FFT <= IDLE; | |
| 553 | END IF; |
|
554 | END IF; | |
| 554 | WHEN OTHERS => NULL; |
|
555 | WHEN OTHERS => NULL; | |
| 555 | END CASE; |
|
556 | END CASE; | |
| 556 | END IF; |
|
557 | END IF; | |
| 557 | END PROCESS; |
|
558 | END PROCESS; | |
| 558 |
|
559 | |||
| 559 | PROCESS (clk, rstn) |
|
560 | PROCESS (clk, rstn) | |
| 560 | BEGIN |
|
561 | BEGIN | |
| 561 | IF rstn = '0' THEN |
|
562 | IF rstn = '0' THEN | |
| 562 | sample_valid_r <= '0'; |
|
563 | sample_valid_r <= '0'; | |
| 563 | next_state_fsm_load_FFT <= IDLE; |
|
564 | next_state_fsm_load_FFT <= IDLE; | |
| 564 | ELSIF clk'EVENT AND clk = '1' THEN |
|
565 | ELSIF clk'EVENT AND clk = '1' THEN | |
| 565 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
566 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
| 566 | IF sample_ren_s = "11111" THEN |
|
567 | IF sample_ren_s = "11111" THEN | |
| 567 | sample_valid_r <= '0'; |
|
568 | sample_valid_r <= '0'; | |
| 568 | ELSE |
|
569 | ELSE | |
| 569 | sample_valid_r <= '1'; |
|
570 | sample_valid_r <= '1'; | |
| 570 | END IF; |
|
571 | END IF; | |
| 571 | END IF; |
|
572 | END IF; | |
| 572 | END PROCESS; |
|
573 | END PROCESS; | |
| 573 |
|
574 | |||
| 574 | sample_valid <= sample_valid_r AND sample_load; |
|
575 | sample_valid <= sample_valid_r AND sample_load; | |
| 575 |
|
576 | |||
| 576 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
577 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
| 577 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
578 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
| 578 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
579 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
| 579 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
580 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
| 580 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
581 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
| 581 |
|
582 | |||
| 582 | ----------------------------------------------------------------------------- |
|
583 | ----------------------------------------------------------------------------- | |
| 583 | -- FFT |
|
584 | -- FFT | |
| 584 | ----------------------------------------------------------------------------- |
|
585 | ----------------------------------------------------------------------------- | |
| 585 | CoreFFT_1 : CoreFFT |
|
586 | lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT | |
| 586 | GENERIC MAP ( |
|
|||
| 587 | LOGPTS => gLOGPTS, |
|
|||
| 588 | LOGLOGPTS => gLOGLOGPTS, |
|
|||
| 589 | WSIZE => gWSIZE, |
|
|||
| 590 | TWIDTH => gTWIDTH, |
|
|||
| 591 | DWIDTH => gDWIDTH, |
|
|||
| 592 | TDWIDTH => gTDWIDTH, |
|
|||
| 593 | RND_MODE => gRND_MODE, |
|
|||
| 594 | SCALE_MODE => gSCALE_MODE, |
|
|||
| 595 | PTS => gPTS, |
|
|||
| 596 | HALFPTS => gHALFPTS, |
|
|||
| 597 | inBuf_RWDLY => gInBuf_RWDLY) |
|
|||
| 598 | PORT MAP ( |
|
587 | PORT MAP ( | |
| 599 | clk => clk, |
|
588 | clk => clk, | |
| 600 | ifiStart => '1', |
|
589 | rstn => rstn, | |
| 601 | ifiNreset => rstn, |
|
590 | sample_valid => sample_valid, | |
| 602 |
|
591 | fft_read => fft_read, | ||
| 603 | ifiD_valid => sample_valid, -- IN |
|
592 | sample_data => sample_data, | |
| 604 | ifiRead_y => fft_read, |
|
593 | sample_load => sample_load, | |
| 605 | ifiD_im => (OTHERS => '0'), -- IN |
|
594 | fft_pong => fft_pong, | |
| 606 | ifiD_re => sample_data, -- IN |
|
595 | fft_data_im => fft_data_im, | |
| 607 | ifoLoad => sample_load, -- IN |
|
596 | fft_data_re => fft_data_re, | |
| 608 |
|
597 | fft_data_valid => fft_data_valid, | ||
| 609 | ifoPong => fft_pong, |
|
598 | fft_ready => fft_ready); | |
| 610 | ifoY_im => fft_data_im, |
|
|||
| 611 | ifoY_re => fft_data_re, |
|
|||
| 612 | ifoY_valid => fft_data_valid, |
|
|||
| 613 | ifoY_rdy => fft_ready); |
|
|||
| 614 |
|
599 | |||
| 615 | ----------------------------------------------------------------------------- |
|
600 | ----------------------------------------------------------------------------- | |
| 616 | -- in fft_data_im & fft_data_re |
|
601 | -- in fft_data_im & fft_data_re | |
| 617 | -- in fft_data_valid |
|
602 | -- in fft_data_valid | |
| 618 | -- in fft_ready |
|
603 | -- in fft_ready | |
| 619 | -- out fft_read |
|
604 | -- out fft_read | |
| 620 | PROCESS (clk, rstn) |
|
605 | PROCESS (clk, rstn) | |
| 621 | BEGIN |
|
606 | BEGIN | |
| 622 | IF rstn = '0' THEN |
|
607 | IF rstn = '0' THEN | |
| 623 | state_fsm_load_MS_memory <= IDLE; |
|
608 | state_fsm_load_MS_memory <= IDLE; | |
| 624 | current_fifo_load <= "00001"; |
|
609 | current_fifo_load <= "00001"; | |
| 625 | ELSIF clk'event AND clk = '1' THEN |
|
610 | ELSIF clk'event AND clk = '1' THEN | |
| 626 | CASE state_fsm_load_MS_memory IS |
|
611 | CASE state_fsm_load_MS_memory IS | |
| 627 | WHEN IDLE => |
|
612 | WHEN IDLE => | |
| 628 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
613 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
| 629 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
614 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
| 630 | END IF; |
|
615 | END IF; | |
| 631 | WHEN LOAD_FIFO => |
|
616 | WHEN LOAD_FIFO => | |
| 632 | IF current_fifo_full = '1' THEN |
|
617 | IF current_fifo_full = '1' THEN | |
| 633 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
618 | state_fsm_load_MS_memory <= TRASH_FFT; | |
| 634 | END IF; |
|
619 | END IF; | |
| 635 | WHEN TRASH_FFT => |
|
620 | WHEN TRASH_FFT => | |
| 636 | IF fft_ready = '0' THEN |
|
621 | IF fft_ready = '0' THEN | |
| 637 | state_fsm_load_MS_memory <= IDLE; |
|
622 | state_fsm_load_MS_memory <= IDLE; | |
| 638 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
623 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
| 639 | END IF; |
|
624 | END IF; | |
| 640 | WHEN OTHERS => NULL; |
|
625 | WHEN OTHERS => NULL; | |
| 641 | END CASE; |
|
626 | END CASE; | |
| 642 |
|
627 | |||
| 643 | END IF; |
|
628 | END IF; | |
| 644 | END PROCESS; |
|
629 | END PROCESS; | |
| 645 |
|
630 | |||
| 646 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
631 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
| 647 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
632 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
| 648 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
633 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
| 649 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
634 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
| 650 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
635 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
| 651 |
|
636 | |||
| 652 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
637 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
| 653 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
638 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
| 654 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
639 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
| 655 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
640 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
| 656 | MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
641 | MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
| 657 |
|
642 | |||
| 658 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
643 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
| 659 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
644 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
| 660 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
645 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
| 661 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
646 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
| 662 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
647 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
| 663 |
|
648 | |||
| 664 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
649 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
| 665 |
|
650 | |||
| 666 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE |
|
651 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE | |
| 667 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
652 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
| 668 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
653 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
| 669 | AND current_fifo_load(I) = '1' |
|
654 | AND current_fifo_load(I) = '1' | |
| 670 | ELSE '1'; |
|
655 | ELSE '1'; | |
| 671 | END GENERATE all_fifo; |
|
656 | END GENERATE all_fifo; | |
| 672 |
|
657 | |||
| 673 | PROCESS (clk, rstn) |
|
658 | PROCESS (clk, rstn) | |
| 674 | BEGIN |
|
659 | BEGIN | |
| 675 | IF rstn = '0' THEN |
|
660 | IF rstn = '0' THEN | |
| 676 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
661 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
| 677 | ELSIF clk'event AND clk = '1' THEN |
|
662 | ELSIF clk'event AND clk = '1' THEN | |
| 678 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
663 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
| 679 | END IF; |
|
664 | END IF; | |
| 680 | END PROCESS; |
|
665 | END PROCESS; | |
| 681 |
|
666 | |||
| 682 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
667 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
| 683 | (fft_data_im & fft_data_re) & |
|
668 | (fft_data_im & fft_data_re) & | |
| 684 | (fft_data_im & fft_data_re) & |
|
669 | (fft_data_im & fft_data_re) & | |
| 685 | (fft_data_im & fft_data_re) & |
|
670 | (fft_data_im & fft_data_re) & | |
| 686 | (fft_data_im & fft_data_re); |
|
671 | (fft_data_im & fft_data_re); | |
| 687 |
|
672 | |||
| 688 |
|
673 | |||
| 689 | -- out SM_MEM_IN_wData |
|
674 | -- out SM_MEM_IN_wData | |
| 690 | -- out SM_MEM_IN_wen |
|
675 | -- out SM_MEM_IN_wen | |
| 691 | -- out SM_MEM_IN_Full |
|
676 | -- out SM_MEM_IN_Full | |
| 692 |
|
677 | |||
| 693 | -- out SM_MEM_IN_locked |
|
678 | -- out SM_MEM_IN_locked | |
| 694 | ----------------------------------------------------------------------------- |
|
679 | ----------------------------------------------------------------------------- | |
| 695 | ----------------------------------------------------------------------------- |
|
680 | ----------------------------------------------------------------------------- | |
| 696 | ----------------------------------------------------------------------------- |
|
681 | ----------------------------------------------------------------------------- | |
| 697 | ----------------------------------------------------------------------------- |
|
682 | ----------------------------------------------------------------------------- | |
| 698 | --Linker_FFT_1 : Linker_FFT |
|
683 | --Linker_FFT_1 : Linker_FFT | |
| 699 | -- GENERIC MAP ( |
|
684 | -- GENERIC MAP ( | |
| 700 | -- Data_sz => 16, |
|
685 | -- Data_sz => 16, | |
| 701 | -- NbData => 256) |
|
686 | -- NbData => 256) | |
| 702 | -- PORT MAP ( |
|
687 | -- PORT MAP ( | |
| 703 | -- clk => clk, |
|
688 | -- clk => clk, | |
| 704 | -- rstn => rstn, |
|
689 | -- rstn => rstn, | |
| 705 |
|
690 | |||
| 706 | -- Ready => fft_ready, |
|
691 | -- Ready => fft_ready, | |
| 707 | -- Valid => fft_data_valid, |
|
692 | -- Valid => fft_data_valid, | |
| 708 |
|
693 | |||
| 709 | -- Full => MEM_IN_SM_Full, |
|
694 | -- Full => MEM_IN_SM_Full, | |
| 710 |
|
695 | |||
| 711 | -- Data_re => fft_data_re, |
|
696 | -- Data_re => fft_data_re, | |
| 712 | -- Data_im => fft_data_im, |
|
697 | -- Data_im => fft_data_im, | |
| 713 | -- Read => fft_read, |
|
698 | -- Read => fft_read, | |
| 714 |
|
699 | |||
| 715 | -- Write => MEM_IN_SM_wen, |
|
700 | -- Write => MEM_IN_SM_wen, | |
| 716 | -- ReUse => fft_linker_ReUse, |
|
701 | -- ReUse => fft_linker_ReUse, | |
| 717 | -- DATA => MEM_IN_SM_wData); |
|
702 | -- DATA => MEM_IN_SM_wData); | |
| 718 |
|
703 | |||
| 719 | ----------------------------------------------------------------------------- |
|
704 | ----------------------------------------------------------------------------- | |
| 720 | Mem_In_SpectralMatrix : lppFIFOxN |
|
705 | Mem_In_SpectralMatrix : lppFIFOxN | |
| 721 | GENERIC MAP ( |
|
706 | GENERIC MAP ( | |
| 722 | tech => 0, |
|
707 | tech => 0, | |
| 723 | Mem_use => Mem_use, |
|
708 | Mem_use => Mem_use, | |
| 724 | Data_sz => 32, --16, |
|
709 | Data_sz => 32, --16, | |
| 725 | Addr_sz => 7, --8 |
|
710 | Addr_sz => 7, --8 | |
| 726 | FifoCnt => 5) |
|
711 | FifoCnt => 5) | |
| 727 | PORT MAP ( |
|
712 | PORT MAP ( | |
| 728 | clk => clk, |
|
713 | clk => clk, | |
| 729 | rstn => rstn, |
|
714 | rstn => rstn, | |
| 730 |
|
715 | |||
| 731 | ReUse => MEM_IN_SM_ReUse, |
|
716 | ReUse => MEM_IN_SM_ReUse, | |
| 732 |
|
717 | |||
| 733 | wen => MEM_IN_SM_wen, |
|
718 | wen => MEM_IN_SM_wen, | |
| 734 | wdata => MEM_IN_SM_wData, |
|
719 | wdata => MEM_IN_SM_wData, | |
| 735 |
|
720 | |||
| 736 | ren => MEM_IN_SM_ren, |
|
721 | ren => MEM_IN_SM_ren, | |
| 737 | rdata => MEM_IN_SM_rData, |
|
722 | rdata => MEM_IN_SM_rData, | |
| 738 | full => MEM_IN_SM_Full, |
|
723 | full => MEM_IN_SM_Full, | |
| 739 |
empty => MEM_IN_SM_Empty |
|
724 | empty => MEM_IN_SM_Empty, | |
|
|
725 | almost_full => OPEN); | |||
| 740 |
|
726 | |||
| 741 |
|
727 | |||
| 742 | --all_lock: FOR I IN 4 DOWNTO 0 GENERATE |
|
728 | --all_lock: FOR I IN 4 DOWNTO 0 GENERATE | |
| 743 | -- PROCESS (clk, rstn) |
|
729 | -- PROCESS (clk, rstn) | |
| 744 | -- BEGIN |
|
730 | -- BEGIN | |
| 745 | -- IF rstn = '0' THEN |
|
731 | -- IF rstn = '0' THEN | |
| 746 | -- MEM_IN_SM_locked(I) <= '0'; |
|
732 | -- MEM_IN_SM_locked(I) <= '0'; | |
| 747 | -- ELSIF clk'event AND clk = '1' THEN |
|
733 | -- ELSIF clk'event AND clk = '1' THEN | |
| 748 | -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO |
|
734 | -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO | |
| 749 | -- END IF; |
|
735 | -- END IF; | |
| 750 | -- END PROCESS; |
|
736 | -- END PROCESS; | |
| 751 | --END GENERATE all_lock; |
|
737 | --END GENERATE all_lock; | |
| 752 |
|
738 | |||
| 753 | ----------------------------------------------------------------------------- |
|
739 | ----------------------------------------------------------------------------- | |
| 754 | MS_control_1: MS_control |
|
740 | MS_control_1: MS_control | |
| 755 | PORT MAP ( |
|
741 | PORT MAP ( | |
| 756 | clk => clk, |
|
742 | clk => clk, | |
| 757 | rstn => rstn, |
|
743 | rstn => rstn, | |
| 758 |
|
744 | |||
| 759 | current_status_ms => status_MS_input, |
|
745 | current_status_ms => status_MS_input, | |
| 760 |
|
746 | |||
| 761 | fifo_in_lock => MEM_IN_SM_locked, |
|
747 | fifo_in_lock => MEM_IN_SM_locked, | |
| 762 | fifo_in_data => MEM_IN_SM_rdata, |
|
748 | fifo_in_data => MEM_IN_SM_rdata, | |
| 763 | fifo_in_full => MEM_IN_SM_Full, |
|
749 | fifo_in_full => MEM_IN_SM_Full, | |
| 764 | fifo_in_empty => MEM_IN_SM_Empty, |
|
750 | fifo_in_empty => MEM_IN_SM_Empty, | |
| 765 | fifo_in_ren => MEM_IN_SM_ren, |
|
751 | fifo_in_ren => MEM_IN_SM_ren, | |
| 766 | fifo_in_reuse => MEM_IN_SM_ReUse, |
|
752 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
| 767 |
|
753 | |||
| 768 | fifo_out_data => SM_in_data, |
|
754 | fifo_out_data => SM_in_data, | |
| 769 | fifo_out_ren => SM_in_ren, |
|
755 | fifo_out_ren => SM_in_ren, | |
| 770 | fifo_out_empty => SM_in_empty, |
|
756 | fifo_out_empty => SM_in_empty, | |
| 771 |
|
757 | |||
| 772 | current_status_component => status_component, |
|
758 | current_status_component => status_component, | |
| 773 |
|
759 | |||
| 774 | correlation_start => SM_correlation_start, |
|
760 | correlation_start => SM_correlation_start, | |
| 775 | correlation_auto => SM_correlation_auto, |
|
761 | correlation_auto => SM_correlation_auto, | |
| 776 | correlation_done => SM_correlation_done); |
|
762 | correlation_done => SM_correlation_done); | |
| 777 |
|
763 | |||
| 778 |
|
764 | |||
| 779 | MS_calculation_1: MS_calculation |
|
765 | MS_calculation_1: MS_calculation | |
| 780 | PORT MAP ( |
|
766 | PORT MAP ( | |
| 781 | clk => clk, |
|
767 | clk => clk, | |
| 782 | rstn => rstn, |
|
768 | rstn => rstn, | |
| 783 |
|
769 | |||
| 784 | fifo_in_data => SM_in_data, |
|
770 | fifo_in_data => SM_in_data, | |
| 785 | fifo_in_ren => SM_in_ren, |
|
771 | fifo_in_ren => SM_in_ren, | |
| 786 | fifo_in_empty => SM_in_empty, |
|
772 | fifo_in_empty => SM_in_empty, | |
| 787 |
|
773 | |||
| 788 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO |
|
774 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
| 789 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO |
|
775 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
| 790 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO |
|
776 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
| 791 |
|
777 | |||
| 792 | correlation_start => SM_correlation_start, |
|
778 | correlation_start => SM_correlation_start, | |
| 793 | correlation_auto => SM_correlation_auto, |
|
779 | correlation_auto => SM_correlation_auto, | |
| 794 | correlation_begin => SM_correlation_begin, |
|
780 | correlation_begin => SM_correlation_begin, | |
| 795 | correlation_done => SM_correlation_done); |
|
781 | correlation_done => SM_correlation_done); | |
| 796 |
|
782 | |||
| 797 | ----------------------------------------------------------------------------- |
|
783 | ----------------------------------------------------------------------------- | |
| 798 | PROCESS (clk, rstn) |
|
784 | PROCESS (clk, rstn) | |
| 799 | BEGIN -- PROCESS |
|
785 | BEGIN -- PROCESS | |
| 800 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
786 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
| 801 | current_matrix_write <= '0'; |
|
787 | current_matrix_write <= '0'; | |
| 802 | current_matrix_wait_empty <= '1'; |
|
788 | current_matrix_wait_empty <= '1'; | |
| 803 | status_component_fifo_0 <= (OTHERS => '0'); |
|
789 | status_component_fifo_0 <= (OTHERS => '0'); | |
| 804 | status_component_fifo_1 <= (OTHERS => '0'); |
|
790 | status_component_fifo_1 <= (OTHERS => '0'); | |
| 805 |
|
|
791 | -- status_component_fifo_0_new <= '0'; | |
| 806 |
|
|
792 | -- status_component_fifo_1_new <= '0'; | |
| 807 | status_component_fifo_0_end <= '0'; |
|
793 | status_component_fifo_0_end <= '0'; | |
| 808 | status_component_fifo_1_end <= '0'; |
|
794 | status_component_fifo_1_end <= '0'; | |
| 809 | SM_correlation_done_reg1 <= '0'; |
|
795 | SM_correlation_done_reg1 <= '0'; | |
| 810 | SM_correlation_done_reg2 <= '0'; |
|
796 | SM_correlation_done_reg2 <= '0'; | |
|
|
797 | SM_correlation_done_reg3 <= '0'; | |||
| 811 |
|
798 | |||
| 812 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
799 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
| 813 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
800 | SM_correlation_done_reg1 <= SM_correlation_done; | |
| 814 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
801 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
|
|
802 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |||
| 815 |
|
803 | |||
| 816 |
|
|
804 | -- status_component_fifo_0_new <= '0'; | |
| 817 | status_component_fifo_1_new <= '0'; |
|
805 | -- status_component_fifo_1_new <= '0'; | |
| 818 | status_component_fifo_0_end <= '0'; |
|
806 | status_component_fifo_0_end <= '0'; | |
| 819 | status_component_fifo_1_end <= '0'; |
|
807 | status_component_fifo_1_end <= '0'; | |
| 820 |
|
808 | |||
| 821 |
|
809 | |||
| 822 |
|
810 | |||
| 823 | IF SM_correlation_begin = '1' THEN |
|
811 | IF SM_correlation_begin = '1' THEN | |
| 824 | IF current_matrix_write = '0' THEN |
|
812 | IF current_matrix_write = '0' THEN | |
| 825 | status_component_fifo_0_new <= '1'; |
|
813 | -- status_component_fifo_0_new <= '1'; | |
| 826 | status_component_fifo_0 <= status_component; |
|
814 | status_component_fifo_0 <= status_component; | |
| 827 | ELSE |
|
815 | ELSE | |
| 828 | status_component_fifo_1_new <= '1'; |
|
816 | -- status_component_fifo_1_new <= '1'; | |
| 829 | status_component_fifo_1 <= status_component; |
|
817 | status_component_fifo_1 <= status_component; | |
| 830 | END IF; |
|
818 | END IF; | |
| 831 | END IF; |
|
819 | END IF; | |
| 832 |
|
820 | |||
| 833 |
IF SM_correlation_done_reg |
|
821 | IF SM_correlation_done_reg3 = '1' THEN | |
| 834 | IF current_matrix_write = '0' THEN |
|
822 | IF current_matrix_write = '0' THEN | |
| 835 | status_component_fifo_0_end <= '1'; |
|
823 | status_component_fifo_0_end <= '1'; | |
| 836 | ELSE |
|
824 | ELSE | |
| 837 | status_component_fifo_1_end <= '1'; |
|
825 | status_component_fifo_1_end <= '1'; | |
| 838 | END IF; |
|
826 | END IF; | |
| 839 | current_matrix_wait_empty <= '1'; |
|
827 | current_matrix_wait_empty <= '1'; | |
| 840 | current_matrix_write <= NOT current_matrix_write; |
|
828 | current_matrix_write <= NOT current_matrix_write; | |
| 841 | END IF; |
|
829 | END IF; | |
| 842 |
|
830 | |||
| 843 | IF current_matrix_wait_empty <= '1' THEN |
|
831 | IF current_matrix_wait_empty <= '1' THEN | |
| 844 | IF current_matrix_write = '0' THEN |
|
832 | IF current_matrix_write = '0' THEN | |
| 845 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
833 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); | |
| 846 | ELSE |
|
834 | ELSE | |
| 847 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
835 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); | |
| 848 | END IF; |
|
836 | END IF; | |
| 849 | END IF; |
|
837 | END IF; | |
| 850 |
|
838 | |||
| 851 | END IF; |
|
839 | END IF; | |
| 852 | END PROCESS; |
|
840 | END PROCESS; | |
| 853 |
|
841 | |||
| 854 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE |
|
842 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
| 855 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
843 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
| 856 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
844 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
|
|
845 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |||
| 857 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
846 | '1' WHEN current_matrix_wait_empty = '1' ELSE | |
| 858 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
847 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
| 859 | MEM_OUT_SM_Full(1); |
|
848 | MEM_OUT_SM_Full(1); | |
| 860 |
|
849 | |||
| 861 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
850 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; | |
| 862 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
851 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; | |
| 863 |
|
852 | |||
| 864 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; |
|
853 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
| 865 | ----------------------------------------------------------------------------- |
|
854 | ----------------------------------------------------------------------------- | |
| 866 |
|
855 | |||
| 867 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
856 | Mem_Out_SpectralMatrix : lppFIFOxN | |
| 868 | GENERIC MAP ( |
|
857 | GENERIC MAP ( | |
| 869 | tech => 0, |
|
858 | tech => 0, | |
| 870 | Mem_use => Mem_use, |
|
859 | Mem_use => Mem_use, | |
| 871 | Data_sz => 32, |
|
860 | Data_sz => 32, | |
| 872 | Addr_sz => 8, |
|
861 | Addr_sz => 8, | |
| 873 | FifoCnt => 2) |
|
862 | FifoCnt => 2) | |
| 874 | PORT MAP ( |
|
863 | PORT MAP ( | |
| 875 | clk => clk, |
|
864 | clk => clk, | |
| 876 | rstn => rstn, |
|
865 | rstn => rstn, | |
| 877 |
|
866 | |||
| 878 | ReUse => (OTHERS => '0'), |
|
867 | ReUse => (OTHERS => '0'), | |
| 879 |
|
868 | |||
| 880 | wen => MEM_OUT_SM_Write, |
|
869 | wen => MEM_OUT_SM_Write, | |
| 881 | wdata => MEM_OUT_SM_Data_in, |
|
870 | wdata => MEM_OUT_SM_Data_in, | |
| 882 |
|
871 | |||
| 883 | ren => MEM_OUT_SM_Read, |
|
872 | ren => MEM_OUT_SM_Read, | |
| 884 | rdata => MEM_OUT_SM_Data_out, |
|
873 | rdata => MEM_OUT_SM_Data_out, | |
| 885 |
|
874 | |||
| 886 | full => MEM_OUT_SM_Full, |
|
875 | full => MEM_OUT_SM_Full, | |
| 887 | empty => MEM_OUT_SM_Empty, |
|
876 | empty => MEM_OUT_SM_Empty, | |
| 888 | almost_full => OPEN); |
|
877 | almost_full => OPEN); | |
| 889 |
|
878 | |||
| 890 | ----------------------------------------------------------------------------- |
|
879 | ----------------------------------------------------------------------------- | |
| 891 | -- MEM_OUT_SM_Read <= "00"; |
|
880 | -- MEM_OUT_SM_Read <= "00"; | |
| 892 | PROCESS (clk, rstn) |
|
881 | PROCESS (clk, rstn) | |
| 893 | BEGIN |
|
882 | BEGIN | |
| 894 | IF rstn = '0' THEN |
|
883 | IF rstn = '0' THEN | |
| 895 | fifo_0_ready <= '0'; |
|
884 | fifo_0_ready <= '0'; | |
| 896 | fifo_1_ready <= '0'; |
|
885 | fifo_1_ready <= '0'; | |
| 897 | fifo_ongoing <= '0'; |
|
886 | fifo_ongoing <= '0'; | |
| 898 | ELSIF clk'event AND clk = '1' THEN |
|
887 | ELSIF clk'event AND clk = '1' THEN | |
| 899 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
888 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN | |
| 900 | fifo_ongoing <= '1'; |
|
889 | fifo_ongoing <= '1'; | |
| 901 | fifo_0_ready <= '0'; |
|
890 | fifo_0_ready <= '0'; | |
| 902 | ELSIF status_component_fifo_0_end = '1' THEN |
|
891 | ELSIF status_component_fifo_0_end = '1' THEN | |
| 903 | fifo_0_ready <= '1'; |
|
892 | fifo_0_ready <= '1'; | |
| 904 | END IF; |
|
893 | END IF; | |
| 905 |
|
894 | |||
| 906 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
895 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN | |
| 907 | fifo_ongoing <= '0'; |
|
896 | fifo_ongoing <= '0'; | |
| 908 | fifo_1_ready <= '0'; |
|
897 | fifo_1_ready <= '0'; | |
| 909 | ELSIF status_component_fifo_1_end = '1' THEN |
|
898 | ELSIF status_component_fifo_1_end = '1' THEN | |
| 910 | fifo_1_ready <= '1'; |
|
899 | fifo_1_ready <= '1'; | |
| 911 | END IF; |
|
900 | END IF; | |
| 912 |
|
901 | |||
| 913 | END IF; |
|
902 | END IF; | |
| 914 | END PROCESS; |
|
903 | END PROCESS; | |
| 915 |
|
904 | |||
| 916 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
905 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE | |
| 917 | '1' WHEN fifo_0_ready = '0' ELSE |
|
906 | '1' WHEN fifo_0_ready = '0' ELSE | |
| 918 | FSM_DMA_fifo_ren; |
|
907 | FSM_DMA_fifo_ren; | |
| 919 |
|
908 | |||
| 920 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
909 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE | |
| 921 | '1' WHEN fifo_1_ready = '0' ELSE |
|
910 | '1' WHEN fifo_1_ready = '0' ELSE | |
| 922 | FSM_DMA_fifo_ren; |
|
911 | FSM_DMA_fifo_ren; | |
| 923 |
|
912 | |||
| 924 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
913 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
| 925 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
914 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
| 926 | '1'; |
|
915 | '1'; | |
| 927 |
|
916 | |||
| 928 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE |
|
917 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
| 929 | status_component_fifo_1; |
|
918 | status_component_fifo_1; | |
| 930 |
|
919 | |||
| 931 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE |
|
920 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
| 932 | MEM_OUT_SM_Data_out(63 DOWNTO 32); |
|
921 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
| 933 |
|
922 | |||
| 934 | ----------------------------------------------------------------------------- |
|
923 | ----------------------------------------------------------------------------- | |
| 935 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
924 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
| 936 | PORT MAP ( |
|
925 | PORT MAP ( | |
| 937 | HCLK => clk, |
|
926 | HCLK => clk, | |
| 938 | HRESETn => rstn, |
|
927 | HRESETn => rstn, | |
| 939 |
|
928 | |||
| 940 | fifo_matrix_type => FSM_DMA_fifo_status( 5 DOWNTO 4), |
|
929 | fifo_matrix_type => FSM_DMA_fifo_status( 5 DOWNTO 4), | |
| 941 | fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0), |
|
930 | fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0), | |
| 942 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
931 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
| 943 | fifo_data => FSM_DMA_fifo_data, |
|
932 | fifo_data => FSM_DMA_fifo_data, | |
| 944 | fifo_empty => FSM_DMA_fifo_empty, |
|
933 | fifo_empty => FSM_DMA_fifo_empty, | |
| 945 | fifo_ren => FSM_DMA_fifo_ren, |
|
934 | fifo_ren => FSM_DMA_fifo_ren, | |
| 946 |
|
935 | |||
| 947 | ---- FIFO IN |
|
936 | ---- FIFO IN | |
| 948 | --data_time => dma_time, |
|
937 | --data_time => dma_time, | |
| 949 |
|
938 | |||
| 950 | --fifo_data => HEAD_Data, |
|
939 | --fifo_data => HEAD_Data, | |
| 951 | --fifo_empty => HEAD_Empty, |
|
940 | --fifo_empty => HEAD_Empty, | |
| 952 | --fifo_ren => HEAD_Read, |
|
941 | --fifo_ren => HEAD_Read, | |
| 953 |
|
942 | |||
| 954 | --header => DMA_Header, |
|
943 | --header => DMA_Header, | |
| 955 | --header_val => DMA_Header_Val, |
|
944 | --header_val => DMA_Header_Val, | |
| 956 | --header_ack => DMA_Header_Ack, |
|
945 | --header_ack => DMA_Header_Ack, | |
| 957 |
|
946 | |||
| 958 | dma_addr => dma_addr, |
|
947 | dma_addr => dma_addr, | |
| 959 | dma_data => dma_data, |
|
948 | dma_data => dma_data, | |
| 960 | dma_valid => dma_valid, |
|
949 | dma_valid => dma_valid, | |
| 961 | dma_valid_burst => dma_valid_burst, |
|
950 | dma_valid_burst => dma_valid_burst, | |
| 962 | dma_ren => dma_ren, |
|
951 | dma_ren => dma_ren, | |
| 963 | dma_done => dma_done, |
|
952 | dma_done => dma_done, | |
| 964 |
|
953 | |||
| 965 | ready_matrix_f0 => ready_matrix_f0, |
|
954 | ready_matrix_f0 => ready_matrix_f0, | |
| 966 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
955 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
| 967 | ready_matrix_f1 => ready_matrix_f1, |
|
956 | ready_matrix_f1 => ready_matrix_f1, | |
| 968 | ready_matrix_f2 => ready_matrix_f2, |
|
957 | ready_matrix_f2 => ready_matrix_f2, | |
| 969 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
958 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
| 970 | error_bad_component_error => error_bad_component_error, |
|
959 | error_bad_component_error => error_bad_component_error, | |
| 971 | error_buffer_full => error_buffer_full, |
|
960 | error_buffer_full => error_buffer_full, | |
| 972 | debug_reg => debug_reg, |
|
961 | debug_reg => debug_reg, | |
| 973 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
962 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
| 974 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
963 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
| 975 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
964 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
| 976 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
965 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
| 977 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
966 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
| 978 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
967 | -- status_error_bad_component_error => status_error_bad_component_error, | |
| 979 | -- status_error_buffer_full => status_error_buffer_full, |
|
968 | -- status_error_buffer_full => status_error_buffer_full, | |
| 980 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
969 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
| 981 | config_active_interruption_onError => config_active_interruption_onError, |
|
970 | config_active_interruption_onError => config_active_interruption_onError, | |
| 982 | addr_matrix_f0 => addr_matrix_f0, |
|
971 | addr_matrix_f0 => addr_matrix_f0, | |
| 983 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
972 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
| 984 | addr_matrix_f1 => addr_matrix_f1, |
|
973 | addr_matrix_f1 => addr_matrix_f1, | |
| 985 | addr_matrix_f2 => addr_matrix_f2, |
|
974 | addr_matrix_f2 => addr_matrix_f2, | |
| 986 |
|
975 | |||
| 987 | matrix_time_f0 => matrix_time_f0, |
|
976 | matrix_time_f0 => matrix_time_f0, | |
| 988 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
977 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
| 989 | matrix_time_f1 => matrix_time_f1, |
|
978 | matrix_time_f1 => matrix_time_f1, | |
| 990 | matrix_time_f2 => matrix_time_f2 |
|
979 | matrix_time_f2 => matrix_time_f2 | |
| 991 | ); |
|
980 | ); | |
| 992 | ----------------------------------------------------------------------------- |
|
981 | ----------------------------------------------------------------------------- | |
| 993 |
|
982 | |||
| 994 |
|
983 | |||
| 995 |
|
984 | |||
| 996 |
|
985 | |||
| 997 |
|
986 | |||
| 998 |
|
987 | |||
| 999 |
|
988 | |||
| 1000 |
|
989 | |||
| 1001 |
|
990 | |||
| 1002 |
|
991 | |||
| 1003 |
|
992 | |||
| 1004 | ----------------------------------------------------------------------------- |
|
993 | ----------------------------------------------------------------------------- | |
| 1005 | ----------------------------------------------------------------------------- |
|
994 | ----------------------------------------------------------------------------- | |
| 1006 | ----------------------------------------------------------------------------- |
|
995 | ----------------------------------------------------------------------------- | |
| 1007 | ----------------------------------------------------------------------------- |
|
996 | ----------------------------------------------------------------------------- | |
| 1008 | ----------------------------------------------------------------------------- |
|
997 | ----------------------------------------------------------------------------- | |
| 1009 | ----------------------------------------------------------------------------- |
|
998 | ----------------------------------------------------------------------------- | |
| 1010 |
|
999 | |||
| 1011 |
|
1000 | |||
| 1012 |
|
1001 | |||
| 1013 |
|
1002 | |||
| 1014 |
|
1003 | |||
| 1015 |
|
1004 | |||
| 1016 | ----------------------------------------------------------------------------- |
|
1005 | ----------------------------------------------------------------------------- | |
| 1017 | -- TIME MANAGMENT |
|
1006 | -- TIME MANAGMENT | |
| 1018 | ----------------------------------------------------------------------------- |
|
1007 | ----------------------------------------------------------------------------- | |
| 1019 | all_time <= coarse_time & fine_time; |
|
1008 | all_time <= coarse_time & fine_time; | |
| 1020 | -- |
|
1009 | -- | |
| 1021 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE |
|
1010 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE | |
| 1022 | '1' WHEN sample_f0_A_empty = "11111" ELSE |
|
1011 | '1' WHEN sample_f0_A_empty = "11111" ELSE | |
| 1023 | '0'; |
|
1012 | '0'; | |
| 1024 |
|
1013 | |||
| 1025 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
1014 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
| 1026 | PORT MAP ( |
|
1015 | PORT MAP ( | |
| 1027 | clk => clk, |
|
1016 | clk => clk, | |
| 1028 | rstn => rstn, |
|
1017 | rstn => rstn, | |
| 1029 | time_in => all_time, |
|
1018 | time_in => all_time, | |
| 1030 | update_1 => time_update_f0_A, |
|
1019 | update_1 => time_update_f0_A, | |
| 1031 | time_out => time_reg_f0_A); |
|
1020 | time_out => time_reg_f0_A); | |
| 1032 |
|
1021 | |||
| 1033 | -- |
|
1022 | -- | |
| 1034 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE |
|
1023 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE | |
| 1035 | '1' WHEN sample_f0_B_empty = "11111" ELSE |
|
1024 | '1' WHEN sample_f0_B_empty = "11111" ELSE | |
| 1036 | '0'; |
|
1025 | '0'; | |
| 1037 |
|
1026 | |||
| 1038 | s_m_t_m_f0_B : spectral_matrix_time_managment |
|
1027 | s_m_t_m_f0_B : spectral_matrix_time_managment | |
| 1039 | PORT MAP ( |
|
1028 | PORT MAP ( | |
| 1040 | clk => clk, |
|
1029 | clk => clk, | |
| 1041 | rstn => rstn, |
|
1030 | rstn => rstn, | |
| 1042 | time_in => all_time, |
|
1031 | time_in => all_time, | |
| 1043 | update_1 => time_update_f0_B, |
|
1032 | update_1 => time_update_f0_B, | |
| 1044 | time_out => time_reg_f0_B); |
|
1033 | time_out => time_reg_f0_B); | |
| 1045 |
|
1034 | |||
| 1046 | -- |
|
1035 | -- | |
| 1047 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE |
|
1036 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE | |
| 1048 | '1' WHEN sample_f1_empty = "11111" ELSE |
|
1037 | '1' WHEN sample_f1_empty = "11111" ELSE | |
| 1049 | '0'; |
|
1038 | '0'; | |
| 1050 |
|
1039 | |||
| 1051 | s_m_t_m_f1 : spectral_matrix_time_managment |
|
1040 | s_m_t_m_f1 : spectral_matrix_time_managment | |
| 1052 | PORT MAP ( |
|
1041 | PORT MAP ( | |
| 1053 | clk => clk, |
|
1042 | clk => clk, | |
| 1054 | rstn => rstn, |
|
1043 | rstn => rstn, | |
| 1055 | time_in => all_time, |
|
1044 | time_in => all_time, | |
| 1056 | update_1 => time_update_f1, |
|
1045 | update_1 => time_update_f1, | |
| 1057 | time_out => time_reg_f1); |
|
1046 | time_out => time_reg_f1); | |
| 1058 |
|
1047 | |||
| 1059 | -- |
|
1048 | -- | |
| 1060 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE |
|
1049 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE | |
| 1061 | '1' WHEN sample_f2_empty = "11111" ELSE |
|
1050 | '1' WHEN sample_f2_empty = "11111" ELSE | |
| 1062 | '0'; |
|
1051 | '0'; | |
| 1063 |
|
1052 | |||
| 1064 | s_m_t_m_f2 : spectral_matrix_time_managment |
|
1053 | s_m_t_m_f2 : spectral_matrix_time_managment | |
| 1065 | PORT MAP ( |
|
1054 | PORT MAP ( | |
| 1066 | clk => clk, |
|
1055 | clk => clk, | |
| 1067 | rstn => rstn, |
|
1056 | rstn => rstn, | |
| 1068 | time_in => all_time, |
|
1057 | time_in => all_time, | |
| 1069 | update_1 => time_update_f2, |
|
1058 | update_1 => time_update_f2, | |
| 1070 | time_out => time_reg_f2); |
|
1059 | time_out => time_reg_f2); | |
| 1071 |
|
1060 | |||
| 1072 | ----------------------------------------------------------------------------- |
|
1061 | ----------------------------------------------------------------------------- | |
| 1073 | dma_time <= (OTHERS => '0'); -- TODO |
|
1062 | dma_time <= (OTHERS => '0'); -- TODO | |
| 1074 | ----------------------------------------------------------------------------- |
|
1063 | ----------------------------------------------------------------------------- | |
| 1075 |
|
1064 | |||
| 1076 |
|
1065 | |||
| 1077 |
|
1066 | |||
| 1078 | END Behavioral; |
|
1067 | END Behavioral; | |
| @@ -1,293 +1,296 | |||||
| 1 |
|
1 | |||
| 2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
| 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
| 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
| 5 | -- |
|
5 | -- | |
| 6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
| 7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
| 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
| 9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
| 10 | -- |
|
10 | -- | |
| 11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
| 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
| 15 | -- |
|
15 | -- | |
| 16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
| 17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
| 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
| 20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
| 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
| 22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
| 23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
| 24 | LIBRARY ieee; |
|
24 | LIBRARY ieee; | |
| 25 | USE ieee.std_logic_1164.ALL; |
|
25 | USE ieee.std_logic_1164.ALL; | |
| 26 | USE ieee.numeric_std.ALL; |
|
26 | USE ieee.numeric_std.ALL; | |
| 27 | LIBRARY grlib; |
|
27 | LIBRARY grlib; | |
| 28 | USE grlib.amba.ALL; |
|
28 | USE grlib.amba.ALL; | |
| 29 | USE grlib.stdlib.ALL; |
|
29 | USE grlib.stdlib.ALL; | |
| 30 | USE grlib.devices.ALL; |
|
30 | USE grlib.devices.ALL; | |
| 31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
31 | USE GRLIB.DMA2AHB_Package.ALL; | |
| 32 | LIBRARY lpp; |
|
32 | LIBRARY lpp; | |
| 33 | USE lpp.lpp_amba.ALL; |
|
33 | USE lpp.lpp_amba.ALL; | |
| 34 | USE lpp.apb_devices_list.ALL; |
|
34 | USE lpp.apb_devices_list.ALL; | |
| 35 | USE lpp.lpp_memory.ALL; |
|
35 | USE lpp.lpp_memory.ALL; | |
| 36 | USE lpp.lpp_dma_pkg.ALL; |
|
36 | USE lpp.lpp_dma_pkg.ALL; | |
| 37 | LIBRARY techmap; |
|
37 | LIBRARY techmap; | |
| 38 | USE techmap.gencomp.ALL; |
|
38 | USE techmap.gencomp.ALL; | |
| 39 |
|
39 | |||
| 40 |
|
40 | |||
| 41 | ENTITY lpp_lfr_ms_fsmdma IS |
|
41 | ENTITY lpp_lfr_ms_fsmdma IS | |
| 42 | PORT ( |
|
42 | PORT ( | |
| 43 | -- AMBA AHB system signals |
|
43 | -- AMBA AHB system signals | |
| 44 | HCLK : IN STD_ULOGIC; |
|
44 | HCLK : IN STD_ULOGIC; | |
| 45 | HRESETn : IN STD_ULOGIC; |
|
45 | HRESETn : IN STD_ULOGIC; | |
| 46 |
|
46 | |||
| 47 | --------------------------------------------------------------------------- |
|
47 | --------------------------------------------------------------------------- | |
| 48 | -- FIFO - IN |
|
48 | -- FIFO - IN | |
| 49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 53 | fifo_empty : IN STD_LOGIC; |
|
53 | fifo_empty : IN STD_LOGIC; | |
| 54 | fifo_ren : OUT STD_LOGIC; |
|
54 | fifo_ren : OUT STD_LOGIC; | |
| 55 |
|
55 | |||
| 56 | --------------------------------------------------------------------------- |
|
56 | --------------------------------------------------------------------------- | |
| 57 | -- DMA - OUT |
|
57 | -- DMA - OUT | |
| 58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 60 | dma_valid : OUT STD_LOGIC; |
|
60 | dma_valid : OUT STD_LOGIC; | |
| 61 | dma_valid_burst : OUT STD_LOGIC; |
|
61 | dma_valid_burst : OUT STD_LOGIC; | |
| 62 | dma_ren : IN STD_LOGIC; |
|
62 | dma_ren : IN STD_LOGIC; | |
| 63 | dma_done : IN STD_LOGIC; |
|
63 | dma_done : IN STD_LOGIC; | |
| 64 |
|
64 | |||
| 65 | --------------------------------------------------------------------------- |
|
65 | --------------------------------------------------------------------------- | |
| 66 | -- Reg out |
|
66 | -- Reg out | |
| 67 | ready_matrix_f0 : OUT STD_LOGIC; |
|
67 | ready_matrix_f0 : OUT STD_LOGIC; | |
| 68 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
68 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
| 69 | ready_matrix_f1 : OUT STD_LOGIC; |
|
69 | ready_matrix_f1 : OUT STD_LOGIC; | |
| 70 | ready_matrix_f2 : OUT STD_LOGIC; |
|
70 | ready_matrix_f2 : OUT STD_LOGIC; | |
| 71 | --error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
71 | --error_anticipating_empty_fifo : OUT STD_LOGIC; | |
| 72 | error_bad_component_error : OUT STD_LOGIC; |
|
72 | error_bad_component_error : OUT STD_LOGIC; | |
| 73 | error_buffer_full : OUT STD_LOGIC; |
|
73 | error_buffer_full : OUT STD_LOGIC; | |
| 74 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 75 |
|
75 | |||
| 76 | -- Reg In |
|
76 | -- Reg In | |
| 77 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
77 | status_ready_matrix_f0 : IN STD_LOGIC; | |
| 78 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
78 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
| 79 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
79 | status_ready_matrix_f1 : IN STD_LOGIC; | |
| 80 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
80 | status_ready_matrix_f2 : IN STD_LOGIC; | |
| 81 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
81 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
| 82 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
82 | -- status_error_bad_component_error : IN STD_LOGIC; | |
| 83 | -- status_error_buffer_full : IN STD_LOGIC; |
|
83 | -- status_error_buffer_full : IN STD_LOGIC; | |
| 84 |
|
84 | |||
| 85 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
85 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
| 86 | config_active_interruption_onError : IN STD_LOGIC; |
|
86 | config_active_interruption_onError : IN STD_LOGIC; | |
| 87 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 88 | --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 89 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 90 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 91 |
|
91 | |||
| 92 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
92 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 93 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
93 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 94 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
94 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 95 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
95 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
| 96 |
|
96 | |||
| 97 | ); |
|
97 | ); | |
| 98 | END; |
|
98 | END; | |
| 99 |
|
99 | |||
| 100 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
100 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS | |
| 101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
| 102 | TYPE state_DMAWriteBurst IS (IDLE, |
|
102 | TYPE state_DMAWriteBurst IS (IDLE, | |
| 103 | CHECK_COMPONENT_TYPE, |
|
103 | CHECK_COMPONENT_TYPE, | |
| 104 | WRITE_COARSE_TIME, |
|
104 | WRITE_COARSE_TIME, | |
| 105 | WRITE_FINE_TIME, |
|
105 | WRITE_FINE_TIME, | |
| 106 | TRASH_FIFO, |
|
106 | TRASH_FIFO, | |
| 107 | SEND_DATA, |
|
107 | SEND_DATA, | |
| 108 | WAIT_DATA_ACK |
|
108 | WAIT_DATA_ACK | |
| 109 | ); |
|
109 | ); | |
| 110 | SIGNAL state : state_DMAWriteBurst; |
|
110 | SIGNAL state : state_DMAWriteBurst; | |
| 111 |
|
111 | |||
| 112 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
112 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 113 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
113 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 114 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
114 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 115 | SIGNAL header_check_ok : STD_LOGIC; |
|
115 | SIGNAL header_check_ok : STD_LOGIC; | |
| 116 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 117 | SIGNAL send_matrix : STD_LOGIC; |
|
117 | -- SIGNAL send_matrix : STD_LOGIC; | |
| 118 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
| 120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
| 121 |
|
121 | |||
| 122 | SIGNAL component_send : STD_LOGIC; |
|
122 | SIGNAL component_send : STD_LOGIC; | |
| 123 | SIGNAL component_send_ok : STD_LOGIC; |
|
123 | SIGNAL component_send_ok : STD_LOGIC; | |
| 124 | -- SIGNAL component_send_ko : STD_LOGIC; |
|
124 | -- SIGNAL component_send_ko : STD_LOGIC; | |
| 125 | ----------------------------------------------------------------------------- |
|
125 | ----------------------------------------------------------------------------- | |
| 126 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
126 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
| 127 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
127 | -- SIGNAL component_fifo_ren : STD_LOGIC; | |
| 128 |
|
128 | |||
| 129 | ----------------------------------------------------------------------------- |
|
129 | ----------------------------------------------------------------------------- | |
| 130 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 131 | ----------------------------------------------------------------------------- |
|
131 | ----------------------------------------------------------------------------- | |
| 132 | SIGNAL log_empty_fifo : STD_LOGIC; |
|
132 | SIGNAL log_empty_fifo : STD_LOGIC; | |
| 133 | ----------------------------------------------------------------------------- |
|
133 | ----------------------------------------------------------------------------- | |
| 134 | SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
134 | --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 135 | SIGNAL header_reg_val : STD_LOGIC; |
|
135 | --SIGNAL header_reg_val : STD_LOGIC; | |
| 136 | SIGNAL header_reg_ack : STD_LOGIC; |
|
136 | --SIGNAL header_reg_ack : STD_LOGIC; | |
| 137 | SIGNAL header_error : STD_LOGIC; |
|
137 | -- SIGNAL header_error : STD_LOGIC; | |
| 138 |
|
138 | |||
| 139 | SIGNAL matrix_buffer_ready : STD_LOGIC; |
|
139 | SIGNAL matrix_buffer_ready : STD_LOGIC; | |
| 140 | BEGIN |
|
140 | BEGIN | |
| 141 |
|
141 | |||
| 142 | debug_reg <= debug_reg_s; |
|
142 | debug_reg <= debug_reg_s; | |
| 143 |
|
143 | |||
| 144 |
|
144 | |||
| 145 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE |
|
145 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE | |
| 146 | --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
146 | --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
| 147 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE |
|
147 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE | |
| 148 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE |
|
148 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE | |
| 149 | '0'; |
|
149 | '0'; | |
| 150 |
|
150 | |||
| 151 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
151 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
| 152 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE |
|
152 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE | |
| 153 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
153 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
| 154 | '0'; |
|
154 | '0'; | |
| 155 |
|
155 | |||
| 156 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE |
|
156 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE | |
| 157 | --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
157 | --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
| 158 | addr_matrix_f1 WHEN matrix_type = "01" ELSE |
|
158 | addr_matrix_f1 WHEN matrix_type = "01" ELSE | |
| 159 | addr_matrix_f2 WHEN matrix_type = "10" ELSE |
|
159 | addr_matrix_f2 WHEN matrix_type = "10" ELSE | |
| 160 | (OTHERS => '0'); |
|
160 | (OTHERS => '0'); | |
| 161 |
|
161 | |||
|
|
162 | debug_reg_s(31 DOWNTO 3) <= (OTHERS => '0'); | |||
| 162 | ----------------------------------------------------------------------------- |
|
163 | ----------------------------------------------------------------------------- | |
| 163 | -- DMA control |
|
164 | -- DMA control | |
| 164 | ----------------------------------------------------------------------------- |
|
165 | ----------------------------------------------------------------------------- | |
| 165 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
166 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
| 166 | BEGIN |
|
167 | BEGIN | |
| 167 | IF HRESETn = '0' THEN |
|
168 | IF HRESETn = '0' THEN | |
| 168 | matrix_type <= (OTHERS => '0'); |
|
169 | matrix_type <= (OTHERS => '0'); | |
| 169 | component_type <= (OTHERS => '0'); |
|
170 | component_type <= (OTHERS => '0'); | |
| 170 | state <= IDLE; |
|
171 | state <= IDLE; | |
| 171 | ready_matrix_f0 <= '0'; |
|
172 | ready_matrix_f0 <= '0'; | |
| 172 | -- ready_matrix_f0_1 <= '0'; |
|
173 | -- ready_matrix_f0_1 <= '0'; | |
| 173 | ready_matrix_f1 <= '0'; |
|
174 | ready_matrix_f1 <= '0'; | |
| 174 | ready_matrix_f2 <= '0'; |
|
175 | ready_matrix_f2 <= '0'; | |
| 175 | -- error_anticipating_empty_fifo <= '0'; |
|
176 | -- error_anticipating_empty_fifo <= '0'; | |
| 176 | error_bad_component_error <= '0'; |
|
177 | error_bad_component_error <= '0'; | |
| 177 | error_buffer_full <= '0'; -- TODO |
|
178 | error_buffer_full <= '0'; -- TODO | |
| 178 | component_type_pre <= "0000"; |
|
179 | component_type_pre <= "0000"; | |
| 179 | fifo_ren_trash <= '1'; |
|
180 | fifo_ren_trash <= '1'; | |
| 180 | component_send <= '0'; |
|
181 | component_send <= '0'; | |
| 181 | address <= (OTHERS => '0'); |
|
182 | address <= (OTHERS => '0'); | |
| 182 |
|
183 | |||
| 183 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); |
|
184 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); | |
| 184 | debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); |
|
|||
| 185 |
|
185 | |||
| 186 | log_empty_fifo <= '0'; |
|
186 | log_empty_fifo <= '0'; | |
| 187 |
|
187 | |||
|
|
188 | matrix_time_f0 <= (OTHERS => '0'); | |||
|
|
189 | matrix_time_f1 <= (OTHERS => '0'); | |||
|
|
190 | matrix_time_f2 <= (OTHERS => '0'); | |||
|
|
191 | ||||
| 188 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
192 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
| 189 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); |
|
|||
| 190 |
|
|
193 | ||
| 191 |
|
|
194 | ready_matrix_f0 <= '0'; | |
| 192 | -- ready_matrix_f0_1 <= '0'; |
|
195 | -- ready_matrix_f0_1 <= '0'; | |
| 193 | ready_matrix_f1 <= '0'; |
|
196 | ready_matrix_f1 <= '0'; | |
| 194 | ready_matrix_f2 <= '0'; |
|
197 | ready_matrix_f2 <= '0'; | |
| 195 | error_bad_component_error <= '0'; |
|
198 | error_bad_component_error <= '0'; | |
| 196 | error_buffer_full <= '0'; |
|
199 | error_buffer_full <= '0'; | |
| 197 |
|
200 | |||
| 198 | CASE state IS |
|
201 | CASE state IS | |
| 199 | WHEN IDLE => |
|
202 | WHEN IDLE => | |
| 200 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
203 | debug_reg_s(2 DOWNTO 0) <= "000"; | |
| 201 | IF fifo_empty = '0' THEN |
|
204 | IF fifo_empty = '0' THEN | |
| 202 | state <= CHECK_COMPONENT_TYPE; |
|
205 | state <= CHECK_COMPONENT_TYPE; | |
| 203 | matrix_type <= fifo_matrix_type; |
|
206 | matrix_type <= fifo_matrix_type; | |
| 204 | component_type <= fifo_matrix_component; |
|
207 | component_type <= fifo_matrix_component; | |
| 205 | component_type_pre <= component_type; |
|
208 | component_type_pre <= component_type; | |
| 206 | END IF; |
|
209 | END IF; | |
| 207 |
|
210 | |||
| 208 | log_empty_fifo <= '0'; |
|
211 | log_empty_fifo <= '0'; | |
| 209 |
|
212 | |||
| 210 | WHEN CHECK_COMPONENT_TYPE => |
|
213 | WHEN CHECK_COMPONENT_TYPE => | |
| 211 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
214 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
| 212 |
|
215 | |||
| 213 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN |
|
216 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN | |
| 214 | IF component_type = "0000" THEN |
|
217 | IF component_type = "0000" THEN | |
| 215 | address <= address_matrix; |
|
218 | address <= address_matrix; | |
| 216 | CASE matrix_type IS |
|
219 | CASE matrix_type IS | |
| 217 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; |
|
220 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; | |
| 218 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; |
|
221 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; | |
| 219 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; |
|
222 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; | |
| 220 | WHEN OTHERS => NULL; |
|
223 | WHEN OTHERS => NULL; | |
| 221 | END CASE; |
|
224 | END CASE; | |
| 222 | component_send <= '1'; |
|
225 | component_send <= '1'; | |
| 223 | END IF; |
|
226 | END IF; | |
| 224 | state <= SEND_DATA; |
|
227 | state <= SEND_DATA; | |
| 225 | -- |
|
228 | -- | |
| 226 | ELSE |
|
229 | ELSE | |
| 227 | error_bad_component_error <= NOT header_check_ok; |
|
230 | error_bad_component_error <= NOT header_check_ok; | |
| 228 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO |
|
231 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO | |
| 229 | component_type_pre <= "0000"; |
|
232 | component_type_pre <= "0000"; | |
| 230 | state <= TRASH_FIFO; |
|
233 | state <= TRASH_FIFO; | |
| 231 | END IF; |
|
234 | END IF; | |
| 232 |
|
235 | |||
| 233 | WHEN TRASH_FIFO => |
|
236 | WHEN TRASH_FIFO => | |
| 234 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
237 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
| 235 |
|
238 | |||
| 236 | error_bad_component_error <= '0'; |
|
239 | error_bad_component_error <= '0'; | |
| 237 | -- error_anticipating_empty_fifo <= '0'; |
|
240 | -- error_anticipating_empty_fifo <= '0'; | |
| 238 | IF fifo_empty = '1' THEN |
|
241 | IF fifo_empty = '1' THEN | |
| 239 | state <= IDLE; |
|
242 | state <= IDLE; | |
| 240 | fifo_ren_trash <= '1'; |
|
243 | fifo_ren_trash <= '1'; | |
| 241 | ELSE |
|
244 | ELSE | |
| 242 | fifo_ren_trash <= '0'; |
|
245 | fifo_ren_trash <= '0'; | |
| 243 | END IF; |
|
246 | END IF; | |
| 244 |
|
247 | |||
| 245 | WHEN SEND_DATA => |
|
248 | WHEN SEND_DATA => | |
| 246 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
249 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
| 247 |
|
250 | |||
| 248 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
251 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
| 249 | state <= IDLE; |
|
252 | state <= IDLE; | |
| 250 | IF component_type = "1110" THEN |
|
253 | IF component_type = "1110" THEN | |
| 251 | CASE matrix_type IS |
|
254 | CASE matrix_type IS | |
| 252 | WHEN "00" => ready_matrix_f0 <= '1'; |
|
255 | WHEN "00" => ready_matrix_f0 <= '1'; | |
| 253 | WHEN "01" => ready_matrix_f1 <= '1'; |
|
256 | WHEN "01" => ready_matrix_f1 <= '1'; | |
| 254 | WHEN "10" => ready_matrix_f2 <= '1'; |
|
257 | WHEN "10" => ready_matrix_f2 <= '1'; | |
| 255 | WHEN OTHERS => NULL; |
|
258 | WHEN OTHERS => NULL; | |
| 256 | END CASE; |
|
259 | END CASE; | |
| 257 | END IF; |
|
260 | END IF; | |
| 258 | ELSE |
|
261 | ELSE | |
| 259 | component_send <= '1'; |
|
262 | component_send <= '1'; | |
| 260 | address <= address; |
|
263 | address <= address; | |
| 261 | state <= WAIT_DATA_ACK; |
|
264 | state <= WAIT_DATA_ACK; | |
| 262 | END IF; |
|
265 | END IF; | |
| 263 |
|
266 | |||
| 264 | WHEN WAIT_DATA_ACK => |
|
267 | WHEN WAIT_DATA_ACK => | |
| 265 | log_empty_fifo <= fifo_empty OR log_empty_fifo; |
|
268 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |
| 266 |
|
269 | |||
| 267 | debug_reg_s(2 DOWNTO 0) <= "110"; |
|
270 | debug_reg_s(2 DOWNTO 0) <= "110"; | |
| 268 |
|
271 | |||
| 269 | component_send <= '0'; |
|
272 | component_send <= '0'; | |
| 270 | IF component_send_ok = '1' THEN |
|
273 | IF component_send_ok = '1' THEN | |
| 271 | address <= address + 64; |
|
274 | address <= address + 64; | |
| 272 | state <= SEND_DATA; |
|
275 | state <= SEND_DATA; | |
| 273 | -- ELSIF component_send_ko = '1' THEN |
|
276 | -- ELSIF component_send_ko = '1' THEN | |
| 274 | -- error_anticipating_empty_fifo <= '0'; |
|
277 | -- error_anticipating_empty_fifo <= '0'; | |
| 275 | -- state <= TRASH_FIFO; |
|
278 | -- state <= TRASH_FIFO; | |
| 276 | END IF; |
|
279 | END IF; | |
| 277 |
|
280 | |||
| 278 | WHEN OTHERS => NULL; |
|
281 | WHEN OTHERS => NULL; | |
| 279 | END CASE; |
|
282 | END CASE; | |
| 280 |
|
283 | |||
| 281 | END IF; |
|
284 | END IF; | |
| 282 | END PROCESS DMAWriteFSM_p; |
|
285 | END PROCESS DMAWriteFSM_p; | |
| 283 |
|
286 | |||
| 284 | dma_valid_burst <= component_send; |
|
287 | dma_valid_burst <= component_send; | |
| 285 | dma_valid <= '0'; |
|
288 | dma_valid <= '0'; | |
| 286 | dma_data <= fifo_data; |
|
289 | dma_data <= fifo_data; | |
| 287 | dma_addr <= address; |
|
290 | dma_addr <= address; | |
| 288 | fifo_ren <= dma_ren AND fifo_ren_trash; |
|
291 | fifo_ren <= dma_ren AND fifo_ren_trash; | |
| 289 |
|
292 | |||
| 290 | component_send_ok <= dma_done; |
|
293 | component_send_ok <= dma_done; | |
| 291 | -- component_send_ko <= '0'; |
|
294 | -- component_send_ko <= '0'; | |
| 292 |
|
295 | |||
| 293 | END Behavioral; |
|
296 | END Behavioral; | |
| @@ -1,334 +1,401 | |||||
| 1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
| 2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
| 3 |
|
3 | |||
| 4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
| 5 | USE grlib.amba.ALL; |
|
5 | USE grlib.amba.ALL; | |
| 6 |
|
6 | |||
| 7 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
| 8 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
| 9 | USE lpp.iir_filter.ALL; |
|
9 | USE lpp.iir_filter.ALL; | |
| 10 | USE lpp.FILTERcfg.ALL; |
|
10 | USE lpp.FILTERcfg.ALL; | |
| 11 | USE lpp.lpp_memory.ALL; |
|
11 | USE lpp.lpp_memory.ALL; | |
| 12 | LIBRARY techmap; |
|
12 | LIBRARY techmap; | |
| 13 | USE techmap.gencomp.ALL; |
|
13 | USE techmap.gencomp.ALL; | |
| 14 |
|
14 | |||
| 15 | PACKAGE lpp_lfr_pkg IS |
|
15 | PACKAGE lpp_lfr_pkg IS | |
|
|
16 | ----------------------------------------------------------------------------- | |||
|
|
17 | -- TEMP | |||
|
|
18 | ----------------------------------------------------------------------------- | |||
|
|
19 | COMPONENT lpp_lfr_ms_test | |||
|
|
20 | GENERIC ( | |||
|
|
21 | Mem_use : INTEGER); | |||
|
|
22 | PORT ( | |||
|
|
23 | clk : IN STD_LOGIC; | |||
|
|
24 | rstn : IN STD_LOGIC; | |||
| 16 |
|
25 | |||
|
|
26 | -- TIME | |||
|
|
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |||
|
|
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |||
|
|
29 | -- | |||
|
|
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
|
32 | -- | |||
|
|
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
|
35 | -- | |||
|
|
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
|
38 | ||||
|
|
39 | ||||
|
|
40 | ||||
|
|
41 | --------------------------------------------------------------------------- | |||
|
|
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
|
|
43 | ||||
|
|
44 | -- | |||
|
|
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
|
49 | ||||
|
|
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |||
|
|
51 | ||||
|
|
52 | -- IN | |||
|
|
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
|
54 | ||||
|
|
55 | ----------------------------------------------------------------------------- | |||
|
|
56 | ||||
|
|
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |||
|
|
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |||
|
|
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
|
61 | ||||
|
|
62 | SM_correlation_start : OUT STD_LOGIC; | |||
|
|
63 | SM_correlation_auto : OUT STD_LOGIC; | |||
|
|
64 | SM_correlation_done : IN STD_LOGIC | |||
|
|
65 | ); | |||
|
|
66 | END COMPONENT; | |||
|
|
67 | ||||
|
|
68 | ||||
|
|
69 | ----------------------------------------------------------------------------- | |||
| 17 | COMPONENT lpp_lfr_ms |
|
70 | COMPONENT lpp_lfr_ms | |
| 18 | GENERIC ( |
|
71 | GENERIC ( | |
| 19 | Mem_use : INTEGER |
|
72 | Mem_use : INTEGER | |
| 20 | ); |
|
73 | ); | |
| 21 | PORT ( |
|
74 | PORT ( | |
| 22 | clk : IN STD_LOGIC; |
|
75 | clk : IN STD_LOGIC; | |
| 23 | rstn : IN STD_LOGIC; |
|
76 | rstn : IN STD_LOGIC; | |
| 24 |
|
77 | |||
| 25 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
| 26 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
| 27 |
|
80 | |||
| 28 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 29 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 30 |
|
83 | |||
| 31 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 32 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 33 |
|
86 | |||
| 34 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
| 35 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
| 36 |
|
89 | |||
| 37 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 38 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 39 | dma_valid : OUT STD_LOGIC; |
|
92 | dma_valid : OUT STD_LOGIC; | |
| 40 | dma_valid_burst : OUT STD_LOGIC; |
|
93 | dma_valid_burst : OUT STD_LOGIC; | |
| 41 | dma_ren : IN STD_LOGIC; |
|
94 | dma_ren : IN STD_LOGIC; | |
| 42 | dma_done : IN STD_LOGIC; |
|
95 | dma_done : IN STD_LOGIC; | |
| 43 |
|
96 | |||
| 44 | ready_matrix_f0 : OUT STD_LOGIC; |
|
97 | ready_matrix_f0 : OUT STD_LOGIC; | |
| 45 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
| 46 | ready_matrix_f1 : OUT STD_LOGIC; |
|
99 | ready_matrix_f1 : OUT STD_LOGIC; | |
| 47 | ready_matrix_f2 : OUT STD_LOGIC; |
|
100 | ready_matrix_f2 : OUT STD_LOGIC; | |
| 48 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
| 49 | error_bad_component_error : OUT STD_LOGIC; |
|
102 | error_bad_component_error : OUT STD_LOGIC; | |
| 50 | error_buffer_full : OUT STD_LOGIC; |
|
103 | error_buffer_full : OUT STD_LOGIC; | |
| 51 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
| 52 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 53 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
106 | status_ready_matrix_f0 : IN STD_LOGIC; | |
| 54 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
| 55 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
108 | status_ready_matrix_f1 : IN STD_LOGIC; | |
| 56 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
109 | status_ready_matrix_f2 : IN STD_LOGIC; | |
| 57 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
| 58 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
111 | -- status_error_bad_component_error : IN STD_LOGIC; | |
| 59 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
| 60 | config_active_interruption_onError : IN STD_LOGIC; |
|
113 | config_active_interruption_onError : IN STD_LOGIC; | |
| 61 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 62 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 63 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 64 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 65 |
|
118 | |||
| 66 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 67 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 68 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 69 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
| 70 | END COMPONENT; |
|
123 | END COMPONENT; | |
| 71 |
|
124 | |||
| 72 | COMPONENT lpp_lfr_ms_fsmdma |
|
125 | COMPONENT lpp_lfr_ms_fsmdma | |
| 73 | PORT ( |
|
126 | PORT ( | |
| 74 | HCLK : IN STD_ULOGIC; |
|
127 | HCLK : IN STD_ULOGIC; | |
| 75 | HRESETn : IN STD_ULOGIC; |
|
128 | HRESETn : IN STD_ULOGIC; | |
| 76 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
| 77 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 78 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 79 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 80 | fifo_empty : IN STD_LOGIC; |
|
133 | fifo_empty : IN STD_LOGIC; | |
| 81 | fifo_ren : OUT STD_LOGIC; |
|
134 | fifo_ren : OUT STD_LOGIC; | |
| 82 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 83 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 84 | --fifo_empty : IN STD_LOGIC; |
|
137 | --fifo_empty : IN STD_LOGIC; | |
| 85 | --fifo_ren : OUT STD_LOGIC; |
|
138 | --fifo_ren : OUT STD_LOGIC; | |
| 86 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 87 | --header_val : IN STD_LOGIC; |
|
140 | --header_val : IN STD_LOGIC; | |
| 88 | --header_ack : OUT STD_LOGIC; |
|
141 | --header_ack : OUT STD_LOGIC; | |
| 89 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 90 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 91 | dma_valid : OUT STD_LOGIC; |
|
144 | dma_valid : OUT STD_LOGIC; | |
| 92 | dma_valid_burst : OUT STD_LOGIC; |
|
145 | dma_valid_burst : OUT STD_LOGIC; | |
| 93 | dma_ren : IN STD_LOGIC; |
|
146 | dma_ren : IN STD_LOGIC; | |
| 94 | dma_done : IN STD_LOGIC; |
|
147 | dma_done : IN STD_LOGIC; | |
| 95 | ready_matrix_f0 : OUT STD_LOGIC; |
|
148 | ready_matrix_f0 : OUT STD_LOGIC; | |
| 96 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
| 97 | ready_matrix_f1 : OUT STD_LOGIC; |
|
150 | ready_matrix_f1 : OUT STD_LOGIC; | |
| 98 | ready_matrix_f2 : OUT STD_LOGIC; |
|
151 | ready_matrix_f2 : OUT STD_LOGIC; | |
| 99 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; | |
| 100 | error_bad_component_error : OUT STD_LOGIC; |
|
153 | error_bad_component_error : OUT STD_LOGIC; | |
| 101 | error_buffer_full : OUT STD_LOGIC; |
|
154 | error_buffer_full : OUT STD_LOGIC; | |
| 102 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 103 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
156 | status_ready_matrix_f0 : IN STD_LOGIC; | |
| 104 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
| 105 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
158 | status_ready_matrix_f1 : IN STD_LOGIC; | |
| 106 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
159 | status_ready_matrix_f2 : IN STD_LOGIC; | |
| 107 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
| 108 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
161 | -- status_error_bad_component_error : IN STD_LOGIC; | |
| 109 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
| 110 | config_active_interruption_onError : IN STD_LOGIC; |
|
163 | config_active_interruption_onError : IN STD_LOGIC; | |
| 111 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 112 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 113 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 114 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 115 |
|
168 | |||
| 116 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 117 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 118 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 119 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
| 120 | ); |
|
173 | ); | |
| 121 | END COMPONENT; |
|
174 | END COMPONENT; | |
| 122 |
|
175 | |||
|
|
176 | COMPONENT lpp_lfr_ms_FFT | |||
|
|
177 | PORT ( | |||
|
|
178 | clk : IN STD_LOGIC; | |||
|
|
179 | rstn : IN STD_LOGIC; | |||
|
|
180 | sample_valid : IN STD_LOGIC; | |||
|
|
181 | fft_read : IN STD_LOGIC; | |||
|
|
182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
183 | sample_load : OUT STD_LOGIC; | |||
|
|
184 | fft_pong : OUT STD_LOGIC; | |||
|
|
185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
|
187 | fft_data_valid : OUT STD_LOGIC; | |||
|
|
188 | fft_ready : OUT STD_LOGIC); | |||
|
|
189 | END COMPONENT; | |||
| 123 |
|
190 | |||
| 124 | COMPONENT lpp_lfr_filter |
|
191 | COMPONENT lpp_lfr_filter | |
| 125 | GENERIC ( |
|
192 | GENERIC ( | |
| 126 | Mem_use : INTEGER); |
|
193 | Mem_use : INTEGER); | |
| 127 | PORT ( |
|
194 | PORT ( | |
| 128 | sample : IN Samples(7 DOWNTO 0); |
|
195 | sample : IN Samples(7 DOWNTO 0); | |
| 129 | sample_val : IN STD_LOGIC; |
|
196 | sample_val : IN STD_LOGIC; | |
| 130 | clk : IN STD_LOGIC; |
|
197 | clk : IN STD_LOGIC; | |
| 131 | rstn : IN STD_LOGIC; |
|
198 | rstn : IN STD_LOGIC; | |
| 132 | data_shaping_SP0 : IN STD_LOGIC; |
|
199 | data_shaping_SP0 : IN STD_LOGIC; | |
| 133 | data_shaping_SP1 : IN STD_LOGIC; |
|
200 | data_shaping_SP1 : IN STD_LOGIC; | |
| 134 | data_shaping_R0 : IN STD_LOGIC; |
|
201 | data_shaping_R0 : IN STD_LOGIC; | |
| 135 | data_shaping_R1 : IN STD_LOGIC; |
|
202 | data_shaping_R1 : IN STD_LOGIC; | |
| 136 | sample_f0_val : OUT STD_LOGIC; |
|
203 | sample_f0_val : OUT STD_LOGIC; | |
| 137 | sample_f1_val : OUT STD_LOGIC; |
|
204 | sample_f1_val : OUT STD_LOGIC; | |
| 138 | sample_f2_val : OUT STD_LOGIC; |
|
205 | sample_f2_val : OUT STD_LOGIC; | |
| 139 | sample_f3_val : OUT STD_LOGIC; |
|
206 | sample_f3_val : OUT STD_LOGIC; | |
| 140 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 141 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 142 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
| 143 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |
| 144 | END COMPONENT; |
|
211 | END COMPONENT; | |
| 145 |
|
212 | |||
| 146 | COMPONENT lpp_lfr |
|
213 | COMPONENT lpp_lfr | |
| 147 | GENERIC ( |
|
214 | GENERIC ( | |
| 148 | Mem_use : INTEGER; |
|
215 | Mem_use : INTEGER; | |
| 149 | nb_data_by_buffer_size : INTEGER; |
|
216 | nb_data_by_buffer_size : INTEGER; | |
| 150 | nb_word_by_buffer_size : INTEGER; |
|
217 | nb_word_by_buffer_size : INTEGER; | |
| 151 | nb_snapshot_param_size : INTEGER; |
|
218 | nb_snapshot_param_size : INTEGER; | |
| 152 | delta_vector_size : INTEGER; |
|
219 | delta_vector_size : INTEGER; | |
| 153 | delta_vector_size_f0_2 : INTEGER; |
|
220 | delta_vector_size_f0_2 : INTEGER; | |
| 154 | pindex : INTEGER; |
|
221 | pindex : INTEGER; | |
| 155 | paddr : INTEGER; |
|
222 | paddr : INTEGER; | |
| 156 | pmask : INTEGER; |
|
223 | pmask : INTEGER; | |
| 157 | pirq_ms : INTEGER; |
|
224 | pirq_ms : INTEGER; | |
| 158 | pirq_wfp : INTEGER; |
|
225 | pirq_wfp : INTEGER; | |
| 159 | hindex : INTEGER; |
|
226 | hindex : INTEGER; | |
| 160 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) | |
| 161 | ); |
|
228 | ); | |
| 162 | PORT ( |
|
229 | PORT ( | |
| 163 | clk : IN STD_LOGIC; |
|
230 | clk : IN STD_LOGIC; | |
| 164 | rstn : IN STD_LOGIC; |
|
231 | rstn : IN STD_LOGIC; | |
| 165 | sample_B : IN Samples(2 DOWNTO 0); |
|
232 | sample_B : IN Samples(2 DOWNTO 0); | |
| 166 | sample_E : IN Samples(4 DOWNTO 0); |
|
233 | sample_E : IN Samples(4 DOWNTO 0); | |
| 167 | sample_val : IN STD_LOGIC; |
|
234 | sample_val : IN STD_LOGIC; | |
| 168 | apbi : IN apb_slv_in_type; |
|
235 | apbi : IN apb_slv_in_type; | |
| 169 | apbo : OUT apb_slv_out_type; |
|
236 | apbo : OUT apb_slv_out_type; | |
| 170 | ahbi : IN AHB_Mst_In_Type; |
|
237 | ahbi : IN AHB_Mst_In_Type; | |
| 171 | ahbo : OUT AHB_Mst_Out_Type; |
|
238 | ahbo : OUT AHB_Mst_Out_Type; | |
| 172 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 173 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 174 | data_shaping_BW : OUT STD_LOGIC; |
|
241 | data_shaping_BW : OUT STD_LOGIC; | |
| 175 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
| 176 | ); |
|
243 | ); | |
| 177 | END COMPONENT; |
|
244 | END COMPONENT; | |
| 178 |
|
245 | |||
| 179 | ----------------------------------------------------------------------------- |
|
246 | ----------------------------------------------------------------------------- | |
| 180 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) | |
| 181 | ----------------------------------------------------------------------------- |
|
248 | ----------------------------------------------------------------------------- | |
| 182 | COMPONENT lpp_lfr_WFP_nMS |
|
249 | COMPONENT lpp_lfr_WFP_nMS | |
| 183 | GENERIC ( |
|
250 | GENERIC ( | |
| 184 | Mem_use : INTEGER; |
|
251 | Mem_use : INTEGER; | |
| 185 | nb_data_by_buffer_size : INTEGER; |
|
252 | nb_data_by_buffer_size : INTEGER; | |
| 186 | nb_word_by_buffer_size : INTEGER; |
|
253 | nb_word_by_buffer_size : INTEGER; | |
| 187 | nb_snapshot_param_size : INTEGER; |
|
254 | nb_snapshot_param_size : INTEGER; | |
| 188 | delta_vector_size : INTEGER; |
|
255 | delta_vector_size : INTEGER; | |
| 189 | delta_vector_size_f0_2 : INTEGER; |
|
256 | delta_vector_size_f0_2 : INTEGER; | |
| 190 | pindex : INTEGER; |
|
257 | pindex : INTEGER; | |
| 191 | paddr : INTEGER; |
|
258 | paddr : INTEGER; | |
| 192 | pmask : INTEGER; |
|
259 | pmask : INTEGER; | |
| 193 | pirq_ms : INTEGER; |
|
260 | pirq_ms : INTEGER; | |
| 194 | pirq_wfp : INTEGER; |
|
261 | pirq_wfp : INTEGER; | |
| 195 | hindex : INTEGER; |
|
262 | hindex : INTEGER; | |
| 196 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
| 197 | PORT ( |
|
264 | PORT ( | |
| 198 | clk : IN STD_LOGIC; |
|
265 | clk : IN STD_LOGIC; | |
| 199 | rstn : IN STD_LOGIC; |
|
266 | rstn : IN STD_LOGIC; | |
| 200 | sample_B : IN Samples(2 DOWNTO 0); |
|
267 | sample_B : IN Samples(2 DOWNTO 0); | |
| 201 | sample_E : IN Samples(4 DOWNTO 0); |
|
268 | sample_E : IN Samples(4 DOWNTO 0); | |
| 202 | sample_val : IN STD_LOGIC; |
|
269 | sample_val : IN STD_LOGIC; | |
| 203 | apbi : IN apb_slv_in_type; |
|
270 | apbi : IN apb_slv_in_type; | |
| 204 | apbo : OUT apb_slv_out_type; |
|
271 | apbo : OUT apb_slv_out_type; | |
| 205 | ahbi : IN AHB_Mst_In_Type; |
|
272 | ahbi : IN AHB_Mst_In_Type; | |
| 206 | ahbo : OUT AHB_Mst_Out_Type; |
|
273 | ahbo : OUT AHB_Mst_Out_Type; | |
| 207 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 208 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
| 209 | data_shaping_BW : OUT STD_LOGIC; |
|
276 | data_shaping_BW : OUT STD_LOGIC; | |
| 210 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
| 211 | END COMPONENT; |
|
278 | END COMPONENT; | |
| 212 | ----------------------------------------------------------------------------- |
|
279 | ----------------------------------------------------------------------------- | |
| 213 |
|
280 | |||
| 214 |
|
281 | |||
| 215 | COMPONENT lpp_lfr_apbreg |
|
282 | COMPONENT lpp_lfr_apbreg | |
| 216 | GENERIC ( |
|
283 | GENERIC ( | |
| 217 | nb_data_by_buffer_size : INTEGER; |
|
284 | nb_data_by_buffer_size : INTEGER; | |
| 218 | nb_word_by_buffer_size : INTEGER; |
|
285 | nb_word_by_buffer_size : INTEGER; | |
| 219 | nb_snapshot_param_size : INTEGER; |
|
286 | nb_snapshot_param_size : INTEGER; | |
| 220 | delta_vector_size : INTEGER; |
|
287 | delta_vector_size : INTEGER; | |
| 221 | delta_vector_size_f0_2 : INTEGER; |
|
288 | delta_vector_size_f0_2 : INTEGER; | |
| 222 | pindex : INTEGER; |
|
289 | pindex : INTEGER; | |
| 223 | paddr : INTEGER; |
|
290 | paddr : INTEGER; | |
| 224 | pmask : INTEGER; |
|
291 | pmask : INTEGER; | |
| 225 | pirq_ms : INTEGER; |
|
292 | pirq_ms : INTEGER; | |
| 226 | pirq_wfp : INTEGER; |
|
293 | pirq_wfp : INTEGER; | |
| 227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
294 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); | |
| 228 | PORT ( |
|
295 | PORT ( | |
| 229 | HCLK : IN STD_ULOGIC; |
|
296 | HCLK : IN STD_ULOGIC; | |
| 230 | HRESETn : IN STD_ULOGIC; |
|
297 | HRESETn : IN STD_ULOGIC; | |
| 231 | apbi : IN apb_slv_in_type; |
|
298 | apbi : IN apb_slv_in_type; | |
| 232 | apbo : OUT apb_slv_out_type; |
|
299 | apbo : OUT apb_slv_out_type; | |
| 233 | run_ms : OUT STD_LOGIC; |
|
300 | run_ms : OUT STD_LOGIC; | |
| 234 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
301 | ready_matrix_f0_0 : IN STD_LOGIC; | |
| 235 | ready_matrix_f0_1 : IN STD_LOGIC; |
|
302 | ready_matrix_f0_1 : IN STD_LOGIC; | |
| 236 | ready_matrix_f1 : IN STD_LOGIC; |
|
303 | ready_matrix_f1 : IN STD_LOGIC; | |
| 237 | ready_matrix_f2 : IN STD_LOGIC; |
|
304 | ready_matrix_f2 : IN STD_LOGIC; | |
| 238 | error_anticipating_empty_fifo : IN STD_LOGIC; |
|
305 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
| 239 | error_bad_component_error : IN STD_LOGIC; |
|
306 | error_bad_component_error : IN STD_LOGIC; | |
| 240 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
307 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 241 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
308 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |
| 242 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
|
309 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
| 243 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
310 | status_ready_matrix_f1 : OUT STD_LOGIC; | |
| 244 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
311 | status_ready_matrix_f2 : OUT STD_LOGIC; | |
| 245 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
312 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
| 246 | status_error_bad_component_error : OUT STD_LOGIC; |
|
313 | status_error_bad_component_error : OUT STD_LOGIC; | |
| 247 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
314 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |
| 248 | config_active_interruption_onError : OUT STD_LOGIC; |
|
315 | config_active_interruption_onError : OUT STD_LOGIC; | |
| 249 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
316 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 250 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
317 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 251 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
318 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 252 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
319 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 253 |
|
320 | |||
| 254 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
321 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 255 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
322 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 256 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
323 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 257 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
324 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 258 |
|
325 | |||
| 259 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
326 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 260 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
327 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 261 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
328 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 262 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
329 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
| 263 | data_shaping_BW : OUT STD_LOGIC; |
|
330 | data_shaping_BW : OUT STD_LOGIC; | |
| 264 | data_shaping_SP0 : OUT STD_LOGIC; |
|
331 | data_shaping_SP0 : OUT STD_LOGIC; | |
| 265 | data_shaping_SP1 : OUT STD_LOGIC; |
|
332 | data_shaping_SP1 : OUT STD_LOGIC; | |
| 266 | data_shaping_R0 : OUT STD_LOGIC; |
|
333 | data_shaping_R0 : OUT STD_LOGIC; | |
| 267 | data_shaping_R1 : OUT STD_LOGIC; |
|
334 | data_shaping_R1 : OUT STD_LOGIC; | |
| 268 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
335 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 269 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
336 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 270 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
337 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
| 271 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
338 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 272 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
339 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
| 273 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
340 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
| 274 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
341 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
| 275 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
342 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
| 276 | enable_f0 : OUT STD_LOGIC; |
|
343 | enable_f0 : OUT STD_LOGIC; | |
| 277 | enable_f1 : OUT STD_LOGIC; |
|
344 | enable_f1 : OUT STD_LOGIC; | |
| 278 | enable_f2 : OUT STD_LOGIC; |
|
345 | enable_f2 : OUT STD_LOGIC; | |
| 279 | enable_f3 : OUT STD_LOGIC; |
|
346 | enable_f3 : OUT STD_LOGIC; | |
| 280 | burst_f0 : OUT STD_LOGIC; |
|
347 | burst_f0 : OUT STD_LOGIC; | |
| 281 | burst_f1 : OUT STD_LOGIC; |
|
348 | burst_f1 : OUT STD_LOGIC; | |
| 282 | burst_f2 : OUT STD_LOGIC; |
|
349 | burst_f2 : OUT STD_LOGIC; | |
| 283 | run : OUT STD_LOGIC; |
|
350 | run : OUT STD_LOGIC; | |
| 284 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
351 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 285 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
352 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 286 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
353 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 287 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
354 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 288 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
355 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
| 289 | --------------------------------------------------------------------------- |
|
356 | --------------------------------------------------------------------------- | |
| 290 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
357 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 291 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
358 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 292 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
359 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 293 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
360 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 294 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
361 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 295 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
362 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 296 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
363 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
| 297 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
364 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
| 298 | END COMPONENT; |
|
365 | END COMPONENT; | |
| 299 |
|
366 | |||
| 300 | COMPONENT lpp_top_ms |
|
367 | COMPONENT lpp_top_ms | |
| 301 | GENERIC ( |
|
368 | GENERIC ( | |
| 302 | Mem_use : INTEGER; |
|
369 | Mem_use : INTEGER; | |
| 303 | nb_burst_available_size : INTEGER; |
|
370 | nb_burst_available_size : INTEGER; | |
| 304 | nb_snapshot_param_size : INTEGER; |
|
371 | nb_snapshot_param_size : INTEGER; | |
| 305 | delta_snapshot_size : INTEGER; |
|
372 | delta_snapshot_size : INTEGER; | |
| 306 | delta_f2_f0_size : INTEGER; |
|
373 | delta_f2_f0_size : INTEGER; | |
| 307 | delta_f2_f1_size : INTEGER; |
|
374 | delta_f2_f1_size : INTEGER; | |
| 308 | pindex : INTEGER; |
|
375 | pindex : INTEGER; | |
| 309 | paddr : INTEGER; |
|
376 | paddr : INTEGER; | |
| 310 | pmask : INTEGER; |
|
377 | pmask : INTEGER; | |
| 311 | pirq_ms : INTEGER; |
|
378 | pirq_ms : INTEGER; | |
| 312 | pirq_wfp : INTEGER; |
|
379 | pirq_wfp : INTEGER; | |
| 313 | hindex_wfp : INTEGER; |
|
380 | hindex_wfp : INTEGER; | |
| 314 | hindex_ms : INTEGER); |
|
381 | hindex_ms : INTEGER); | |
| 315 | PORT ( |
|
382 | PORT ( | |
| 316 | clk : IN STD_LOGIC; |
|
383 | clk : IN STD_LOGIC; | |
| 317 | rstn : IN STD_LOGIC; |
|
384 | rstn : IN STD_LOGIC; | |
| 318 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
385 | sample_B : IN Samples14v(2 DOWNTO 0); | |
| 319 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
386 | sample_E : IN Samples14v(4 DOWNTO 0); | |
| 320 | sample_val : IN STD_LOGIC; |
|
387 | sample_val : IN STD_LOGIC; | |
| 321 | apbi : IN apb_slv_in_type; |
|
388 | apbi : IN apb_slv_in_type; | |
| 322 | apbo : OUT apb_slv_out_type; |
|
389 | apbo : OUT apb_slv_out_type; | |
| 323 | ahbi_ms : IN AHB_Mst_In_Type; |
|
390 | ahbi_ms : IN AHB_Mst_In_Type; | |
| 324 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
391 | ahbo_ms : OUT AHB_Mst_Out_Type; | |
| 325 | data_shaping_BW : OUT STD_LOGIC; |
|
392 | data_shaping_BW : OUT STD_LOGIC; | |
| 326 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
393 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 327 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
394 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 328 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
395 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
| 329 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
396 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) | |
| 330 |
|
397 | |||
| 331 | ); |
|
398 | ); | |
| 332 | END COMPONENT; |
|
399 | END COMPONENT; | |
| 333 |
|
400 | |||
| 334 | END lpp_lfr_pkg; |
|
401 | END lpp_lfr_pkg; | |
| @@ -1,8 +1,10 | |||||
| 1 | lpp_top_lfr_pkg.vhd |
|
1 | lpp_top_lfr_pkg.vhd | |
| 2 | lpp_lfr_pkg.vhd |
|
2 | lpp_lfr_pkg.vhd | |
| 3 | lpp_lfr_filter.vhd |
|
3 | lpp_lfr_filter.vhd | |
| 4 | lpp_lfr_apbreg.vhd |
|
4 | lpp_lfr_apbreg.vhd | |
| 5 | lpp_lfr_ms_fsmdma.vhd |
|
5 | lpp_lfr_ms_fsmdma.vhd | |
|
|
6 | lpp_lfr_ms_FFT.vhd | |||
| 6 | lpp_lfr_ms.vhd |
|
7 | lpp_lfr_ms.vhd | |
|
|
8 | lpp_lfr_ms_test_synt.vhd | |||
| 7 | lpp_lfr_WFP_nMS.vhd |
|
9 | lpp_lfr_WFP_nMS.vhd | |
| 8 | lpp_lfr.vhd |
|
10 | lpp_lfr.vhd | |
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