# HG changeset patch # User pellion # Date 2014-05-22 13:30:03 # Node ID 5a38901d72d50f3b3cca647cc2bbea6b56681263 # Parent 453f650415b67d61ba099eedb44761fe5fde2314 MS + WFP : synthese ok ALU with comp is now OK. diff --git a/designs/Validation_LFR_SpectralMatrix/Makefile b/designs/Validation_LFR_SpectralMatrix/Makefile --- a/designs/Validation_LFR_SpectralMatrix/Makefile +++ b/designs/Validation_LFR_SpectralMatrix/Makefile @@ -397,6 +397,7 @@ vcom_lpp: $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd @echo "vcom lpp done" # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd diff --git a/designs/Validation_LFR_SpectralMatrix/wave.do b/designs/Validation_LFR_SpectralMatrix/wave.do --- a/designs/Validation_LFR_SpectralMatrix/wave.do +++ b/designs/Validation_LFR_SpectralMatrix/wave.do @@ -13,7 +13,6 @@ add wave -noupdate -group FIFO_f0_A /tb/ add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect -add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/more_16data add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full @@ -26,7 +25,6 @@ add wave -noupdate -expand -group FIFO_f add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren -add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/more_16data add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray @@ -37,28 +35,15 @@ add wave -noupdate -expand -group FIFO_f add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft -add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload -add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im -add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re -add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid -add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset -add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2 -add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y -add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong -add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy -add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid -add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im -add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re -add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray add wave -noupdate /tb/lpp_lfr_ms_1/status_channel -add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray -add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full @@ -98,10 +83,8 @@ add wave -noupdate -expand -group FIF0_0 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end -add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_new add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end -add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_new add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing @@ -115,12 +98,8 @@ add wave -noupdate -expand -group DMA_OU add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst -add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_0 -add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_1 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2 -add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_0 -add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_1 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state @@ -130,8 +109,36 @@ add wave -noupdate -radix unsigned /tb/l add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo +add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error +add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full +add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write +add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1 +add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2 +add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res +add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp +add wave -noupdate -expand -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty +add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full +add wave -noupdate -expand -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full +add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(200) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(201) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(202) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(203) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(204) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(205) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(206) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(207) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(208) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(209) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(210) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(211) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(212) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(213) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(214) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(215) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(216) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(217) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(218) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(219) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(220) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(221) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(222) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(223) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(224) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(225) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(226) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(227) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(228) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(229) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(230) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(231) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(232) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(233) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(234) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(235) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(236) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(237) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(238) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(239) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(240) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(241) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(242) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(243) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(244) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(245) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(246) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(247) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(248) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(249) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(250) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(251) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(252) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(253) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(254) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(255) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray +add wave -noupdate -expand -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult +add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1 +add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2 +add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res +add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add +add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr +add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load +add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1 +add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2 +add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44837900611 ps} 0} {{Cursor 3} {10445420000 ps} 0} {{Cursor 4} {61378464308 ps} 0} {{Cursor 5} {99992359332 ps} 0} +WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {10435060000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {99992359332 ps} 0} configure wave -namecolwidth 469 configure wave -valuecolwidth 112 configure wave -justifyvalue left @@ -146,6 +153,6 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ps update -WaveRestoreZoom {10380584292 ps} {10668763932 ps} +WaveRestoreZoom {10434939916 ps} {10435778196 ps} bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd --- a/lib/lpp/general_purpose/MAC.vhd +++ b/lib/lpp/general_purpose/MAC.vhd @@ -53,6 +53,10 @@ END MAC; ARCHITECTURE ar_MAC OF MAC IS + + SIGNAL clr_MAC_s : STD_LOGIC; + SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL add, mult : STD_LOGIC; SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); @@ -77,8 +81,8 @@ ARCHITECTURE ar_MAC OF MAC IS SIGNAL MACMUX2sel_D : STD_LOGIC; SIGNAL MACMUX2sel_D_D : STD_LOGIC; SIGNAL clr_MAC_D : STD_LOGIC; - SIGNAL clr_MAC_D_D : STD_LOGIC; - SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); +-- SIGNAL clr_MAC_D_D : STD_LOGIC; +-- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL load_mult_result : STD_LOGIC; SIGNAL load_mult_result_D : STD_LOGIC; @@ -93,7 +97,7 @@ BEGIN --============================================================== MAC_CONTROLER1 : MAC_CONTROLER PORT MAP( - ctrl => MAC_MUL_ADD, + ctrl => MAC_MUL_ADD_s, MULT => mult, ADD => add, LOAD_ADDER => load_mult_result, @@ -163,7 +167,7 @@ BEGIN PORT MAP( clk => clk, reset => reset, - clr => clr_MAC, + clr => '0',--clr_MAC, TwoComp => Comp_2C(0), OP => OP1, RES => OP1_2C @@ -176,16 +180,39 @@ BEGIN PORT MAP( clk => clk, reset => reset, - clr => clr_MAC, + clr => '0',--clr_MAC, TwoComp => Comp_2C(1), OP => OP2, RES => OP2_2C ); + + + clr_MACREG_comp : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC, + Q(0) => clr_MAC_s + ); + + MAC_MUL_ADD_REG : MAC_REG + GENERIC MAP(size => 2) + PORT MAP( + reset => reset, + clk => clk, + D => MAC_MUL_ADD, + Q => MAC_MUL_ADD_s + ); + END GENERATE gen_comp; no_gen_comp : IF COMP_EN = 1 GENERATE OP2_2C <= OP2; OP1_2C <= OP1; + + clr_MAC_s <= clr_MAC; + MAC_MUL_ADD_s <= MAC_MUL_ADD; END GENERATE no_gen_comp; --============================================================== @@ -194,7 +221,7 @@ BEGIN PORT MAP( reset => reset, clk => clk, - D(0) => clr_MAC, + D(0) => clr_MAC_s, Q(0) => clr_MAC_D ); diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt --- a/lib/lpp/lpp_memory/vhdlsyn.txt +++ b/lib/lpp/lpp_memory/vhdlsyn.txt @@ -1,10 +1,4 @@ lpp_memory.vhd lpp_FIFO.vhd -FillFifo.vhd -Bridge.vhd -APB_FIFO.vhd -Bridge.vhd -SSRAM_plugin.vhd -lppFIFOx5.vhd lppFIFOxN.vhd diff --git a/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd b/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd --- a/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd +++ b/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd @@ -54,7 +54,7 @@ ARCHITECTURE beh OF MS_calculation IS SIGNAL res_wen : STD_LOGIC; SIGNAL res_wen_reg1 : STD_LOGIC; --- SIGNAL res_wen_reg2 : STD_LOGIC; + SIGNAL res_wen_reg2 : STD_LOGIC; --SIGNAL res_wen_reg3 : STD_LOGIC; BEGIN @@ -75,6 +75,7 @@ BEGIN res_wen <= '1'; ELSIF clk'EVENT AND clk = '1' THEN + ALU_CTRL <= ALU_CTRL_NOP; correlation_begin <= '0'; fifo_in_ren <= "11"; res_wen <= '1'; @@ -189,7 +190,7 @@ BEGIN Logic_en => 0, Input_SZ_1 => 16, Input_SZ_2 => 16, - COMP_EN => 1) + COMP_EN => 0) -- 0> Enable and 1> Disable PORT MAP ( clk => clk, reset => rstn, @@ -209,14 +210,14 @@ BEGIN BEGIN IF rstn = '0' THEN res_wen_reg1 <= '1'; - --res_wen_reg2 <= '1'; + res_wen_reg2 <= '1'; --res_wen_reg3 <= '1'; fifo_out_wen <= '1'; ELSIF clk'event AND clk = '1' THEN res_wen_reg1 <= res_wen; - --res_wen_reg2 <= res_wen_reg1; + res_wen_reg2 <= res_wen_reg1; --res_wen_reg3 <= res_wen_reg2; - fifo_out_wen <= res_wen_reg1; + fifo_out_wen <= res_wen_reg2; END IF; END PROCESS; diff --git a/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd b/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd --- a/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd +++ b/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd @@ -31,6 +31,6 @@ BEGIN -- beh END IF; END PROCESS; - time_out <= time_in; + time_out <= time_reg; END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -726,8 +726,8 @@ BEGIN sample_f0_wdata => sample_f0_wdata, sample_f1_wen => sample_f1_wen, sample_f1_wdata => sample_f1_wdata, - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata, + sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data + sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data dma_addr => data_ms_addr, -- dma_data => data_ms_data, -- @@ -736,28 +736,26 @@ BEGIN dma_ren => data_ms_ren, -- dma_done => data_ms_done, -- - ready_matrix_f0_0 => ready_matrix_f0_0, - ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename ready_matrix_f1 => ready_matrix_f1, ready_matrix_f2 => ready_matrix_f2, - error_anticipating_empty_fifo => error_anticipating_empty_fifo, + --error_anticipating_empty_fifo => error_anticipating_empty_fifo, error_bad_component_error => error_bad_component_error, - debug_reg => observation_reg, --debug_reg, - status_ready_matrix_f0_0 => status_ready_matrix_f0_0, - status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + error_buffer_full => OPEN, -- TODO + error_input_fifo_write => OPEN, -- TODO + debug_reg => observation_reg, + status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename status_ready_matrix_f1 => status_ready_matrix_f1, status_ready_matrix_f2 => status_ready_matrix_f2, - status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, - status_error_bad_component_error => status_error_bad_component_error, +-- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO +-- status_error_bad_component_error => status_error_bad_component_error,-- TODO config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, config_active_interruption_onError => config_active_interruption_onError, - addr_matrix_f0_0 => addr_matrix_f0_0, - addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename addr_matrix_f1 => addr_matrix_f1, addr_matrix_f2 => addr_matrix_f2, - matrix_time_f0_0 => matrix_time_f0_0, - matrix_time_f0_1 => matrix_time_f0_1, + matrix_time_f0 => matrix_time_f0_0,-- TODO rename matrix_time_f1 => matrix_time_f1, matrix_time_f2 => matrix_time_f2); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -155,7 +155,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL fft_data_valid : STD_LOGIC; SIGNAL fft_ready : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); +-- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); ----------------------------------------------------------------------------- TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; @@ -184,10 +184,11 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL SM_correlation_done : STD_LOGIC; SIGNAL SM_correlation_done_reg1 : STD_LOGIC; SIGNAL SM_correlation_done_reg2 : STD_LOGIC; + SIGNAL SM_correlation_done_reg3 : STD_LOGIC; SIGNAL SM_correlation_begin : STD_LOGIC; - SIGNAL temp_ongoing : STD_LOGIC; - SIGNAL temp_auto : STD_LOGIC; +-- SIGNAL temp_ongoing : STD_LOGIC; +-- SIGNAL temp_auto : STD_LOGIC; SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -209,15 +210,15 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); ----------------------------------------------------------------------------- - SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL HEAD_SM_Wen : STD_LOGIC; - SIGNAL HEAD_Valid : STD_LOGIC; - SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL HEAD_Empty : STD_LOGIC; - SIGNAL HEAD_Read : STD_LOGIC; +-- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); + --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); + --SIGNAL HEAD_SM_Wen : STD_LOGIC; + --SIGNAL HEAD_Valid : STD_LOGIC; + --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); + --SIGNAL HEAD_Empty : STD_LOGIC; + --SIGNAL HEAD_Read : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); +-- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); @@ -225,9 +226,9 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); ----------------------------------------------------------------------------- - SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL DMA_Header_Val : STD_LOGIC; - SIGNAL DMA_Header_Ack : STD_LOGIC; + --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); + --SIGNAL DMA_Header_Val : STD_LOGIC; + --SIGNAL DMA_Header_Ack : STD_LOGIC; ----------------------------------------------------------------------------- -- TIME REG & INFOs @@ -250,8 +251,8 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); - SIGNAL status_component_fifo_0_new : STD_LOGIC; - SIGNAL status_component_fifo_1_new : STD_LOGIC; +-- SIGNAL status_component_fifo_0_new : STD_LOGIC; +-- SIGNAL status_component_fifo_1_new : STD_LOGIC; SIGNAL status_component_fifo_0_end : STD_LOGIC; SIGNAL status_component_fifo_1_end : STD_LOGIC; @@ -582,35 +583,19 @@ BEGIN ----------------------------------------------------------------------------- -- FFT ----------------------------------------------------------------------------- - CoreFFT_1 : CoreFFT - GENERIC MAP ( - LOGPTS => gLOGPTS, - LOGLOGPTS => gLOGLOGPTS, - WSIZE => gWSIZE, - TWIDTH => gTWIDTH, - DWIDTH => gDWIDTH, - TDWIDTH => gTDWIDTH, - RND_MODE => gRND_MODE, - SCALE_MODE => gSCALE_MODE, - PTS => gPTS, - HALFPTS => gHALFPTS, - inBuf_RWDLY => gInBuf_RWDLY) + lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT PORT MAP ( - clk => clk, - ifiStart => '1', - ifiNreset => rstn, - - ifiD_valid => sample_valid, -- IN - ifiRead_y => fft_read, - ifiD_im => (OTHERS => '0'), -- IN - ifiD_re => sample_data, -- IN - ifoLoad => sample_load, -- IN - - ifoPong => fft_pong, - ifoY_im => fft_data_im, - ifoY_re => fft_data_re, - ifoY_valid => fft_data_valid, - ifoY_rdy => fft_ready); + clk => clk, + rstn => rstn, + sample_valid => sample_valid, + fft_read => fft_read, + sample_data => sample_data, + sample_load => sample_load, + fft_pong => fft_pong, + fft_data_im => fft_data_im, + fft_data_re => fft_data_re, + fft_data_valid => fft_data_valid, + fft_ready => fft_ready); ----------------------------------------------------------------------------- -- in fft_data_im & fft_data_re @@ -736,7 +721,8 @@ BEGIN ren => MEM_IN_SM_ren, rdata => MEM_IN_SM_rData, full => MEM_IN_SM_Full, - empty => MEM_IN_SM_Empty); + empty => MEM_IN_SM_Empty, + almost_full => OPEN); --all_lock: FOR I IN 4 DOWNTO 0 GENERATE @@ -802,19 +788,21 @@ BEGIN current_matrix_wait_empty <= '1'; status_component_fifo_0 <= (OTHERS => '0'); status_component_fifo_1 <= (OTHERS => '0'); - status_component_fifo_0_new <= '0'; - status_component_fifo_1_new <= '0'; +-- status_component_fifo_0_new <= '0'; +-- status_component_fifo_1_new <= '0'; status_component_fifo_0_end <= '0'; status_component_fifo_1_end <= '0'; SM_correlation_done_reg1 <= '0'; SM_correlation_done_reg2 <= '0'; + SM_correlation_done_reg3 <= '0'; ELSIF clk'event AND clk = '1' THEN -- rising clock edge SM_correlation_done_reg1 <= SM_correlation_done; SM_correlation_done_reg2 <= SM_correlation_done_reg1; + SM_correlation_done_reg3 <= SM_correlation_done_reg2; - status_component_fifo_0_new <= '0'; - status_component_fifo_1_new <= '0'; +-- status_component_fifo_0_new <= '0'; +-- status_component_fifo_1_new <= '0'; status_component_fifo_0_end <= '0'; status_component_fifo_1_end <= '0'; @@ -822,15 +810,15 @@ BEGIN IF SM_correlation_begin = '1' THEN IF current_matrix_write = '0' THEN - status_component_fifo_0_new <= '1'; +-- status_component_fifo_0_new <= '1'; status_component_fifo_0 <= status_component; ELSE - status_component_fifo_1_new <= '1'; +-- status_component_fifo_1_new <= '1'; status_component_fifo_1 <= status_component; END IF; END IF; - IF SM_correlation_done_reg2 = '1' THEN + IF SM_correlation_done_reg3 = '1' THEN IF current_matrix_write = '0' THEN status_component_fifo_0_end <= '1'; ELSE @@ -854,6 +842,7 @@ BEGIN MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE '1' WHEN SM_correlation_done_reg1 = '1' ELSE '1' WHEN SM_correlation_done_reg2 = '1' ELSE + '1' WHEN SM_correlation_done_reg3 = '1' ELSE '1' WHEN current_matrix_wait_empty = '1' ELSE MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE MEM_OUT_SM_Full(1); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -114,7 +114,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms_fs SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL header_check_ok : STD_LOGIC; SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL send_matrix : STD_LOGIC; +-- SIGNAL send_matrix : STD_LOGIC; SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- @@ -124,17 +124,17 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms_fs -- SIGNAL component_send_ko : STD_LOGIC; ----------------------------------------------------------------------------- SIGNAL fifo_ren_trash : STD_LOGIC; - SIGNAL component_fifo_ren : STD_LOGIC; +-- SIGNAL component_fifo_ren : STD_LOGIC; ----------------------------------------------------------------------------- SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); ----------------------------------------------------------------------------- SIGNAL log_empty_fifo : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL header_reg_val : STD_LOGIC; - SIGNAL header_reg_ack : STD_LOGIC; - SIGNAL header_error : STD_LOGIC; + --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + --SIGNAL header_reg_val : STD_LOGIC; + --SIGNAL header_reg_ack : STD_LOGIC; +-- SIGNAL header_error : STD_LOGIC; SIGNAL matrix_buffer_ready : STD_LOGIC; BEGIN @@ -159,6 +159,7 @@ BEGIN addr_matrix_f2 WHEN matrix_type = "10" ELSE (OTHERS => '0'); + debug_reg_s(31 DOWNTO 3) <= (OTHERS => '0'); ----------------------------------------------------------------------------- -- DMA control ----------------------------------------------------------------------------- @@ -181,12 +182,14 @@ BEGIN address <= (OTHERS => '0'); debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); - debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); log_empty_fifo <= '0'; + matrix_time_f0 <= (OTHERS => '0'); + matrix_time_f1 <= (OTHERS => '0'); + matrix_time_f2 <= (OTHERS => '0'); + ELSIF HCLK'EVENT AND HCLK = '1' THEN - debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); ready_matrix_f0 <= '0'; -- ready_matrix_f0_1 <= '0'; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -13,7 +13,60 @@ LIBRARY techmap; USE techmap.gencomp.ALL; PACKAGE lpp_lfr_pkg IS + ----------------------------------------------------------------------------- + -- TEMP + ----------------------------------------------------------------------------- + COMPONENT lpp_lfr_ms_test + GENERIC ( + Mem_use : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + -- TIME + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo + -- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + + --------------------------------------------------------------------------- + error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + + -- + --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); + + -- IN + MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + + status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); + SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); + SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + + SM_correlation_start : OUT STD_LOGIC; + SM_correlation_auto : OUT STD_LOGIC; + SM_correlation_done : IN STD_LOGIC + ); + END COMPONENT; + + + ----------------------------------------------------------------------------- COMPONENT lpp_lfr_ms GENERIC ( Mem_use : INTEGER @@ -119,7 +172,21 @@ PACKAGE lpp_lfr_pkg IS matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) ); END COMPONENT; - + + COMPONENT lpp_lfr_ms_FFT + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_valid : IN STD_LOGIC; + fft_read : IN STD_LOGIC; + sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_load : OUT STD_LOGIC; + fft_pong : OUT STD_LOGIC; + fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fft_data_valid : OUT STD_LOGIC; + fft_ready : OUT STD_LOGIC); + END COMPONENT; COMPONENT lpp_lfr_filter GENERIC ( diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -3,6 +3,8 @@ lpp_lfr_pkg.vhd lpp_lfr_filter.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_fsmdma.vhd +lpp_lfr_ms_FFT.vhd lpp_lfr_ms.vhd +lpp_lfr_ms_test_synt.vhd lpp_lfr_WFP_nMS.vhd lpp_lfr.vhd