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1 | 1 | VHDLIB=../.. |
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2 | 2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
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3 | 3 | |
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4 | 4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
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5 | 5 | TOP=TB |
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6 | 6 | |
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7 | 7 | CMD_VLIB=vlib |
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8 | 8 | CMD_VMAP=vmap |
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9 | 9 | CMD_VCOM=@vcom -quiet -93 -work |
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10 | 10 | |
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11 | 11 | ################## project specific targets ########################## |
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12 | 12 | |
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13 | 13 | all: |
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14 | 14 | @echo "make vsim" |
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15 | 15 | @echo "make libs" |
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16 | 16 | @echo "make clean" |
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17 | 17 | @echo "make vcom_grlib vcom_lpp vcom_tb" |
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18 | 18 | |
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19 | 19 | run: |
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20 | 20 | @vsim work.TB -do run.do |
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21 | 21 | # @vsim work.TB |
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22 | 22 | # @vsim lpp.lpp_lfr_ms |
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23 | 23 | |
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24 | 24 | vsim: libs vcom run |
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25 | 25 | |
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26 | 26 | libs: |
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27 | 27 | @$(CMD_VLIB) modelsim |
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28 | 28 | @$(CMD_VMAP) modelsim modelsim |
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29 | 29 | @$(CMD_VLIB) modelsim/techmap |
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30 | 30 | @$(CMD_VMAP) techmap modelsim/techmap |
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31 | 31 | @$(CMD_VLIB) modelsim/grlib |
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32 | 32 | @$(CMD_VMAP) grlib modelsim/grlib |
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33 | 33 | @$(CMD_VLIB) modelsim/gaisler |
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34 | 34 | @$(CMD_VMAP) gaisler modelsim/gaisler |
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35 | 35 | @$(CMD_VLIB) modelsim/work |
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36 | 36 | @$(CMD_VMAP) work modelsim/work |
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37 | 37 | @$(CMD_VLIB) modelsim/lpp |
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38 | 38 | @$(CMD_VMAP) lpp modelsim/lpp |
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39 | 39 | @echo "libs done" |
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40 | 40 | |
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41 | 41 | |
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42 | 42 | clean: |
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43 | 43 | @rm -Rf modelsim |
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44 | 44 | @rm -Rf modelsim.ini |
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45 | 45 | @rm -Rf *~ |
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46 | 46 | @rm -Rf transcript |
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47 | 47 | @rm -Rf wlft* |
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48 | 48 | @rm -Rf *.wlf |
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49 | 49 | @rm -Rf vish_stacktrace.vstf |
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50 | 50 | @rm -Rf libs.do |
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51 | 51 | |
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52 | 52 | vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb |
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53 | 53 | |
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54 | 54 | |
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55 | 55 | vcom_tb: |
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56 | 56 | ## $(CMD_VCOM) lpp lpp_memory.vhd |
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57 | 57 | ## $(CMD_VCOM) lpp lppFIFOxN.vhd |
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58 | 58 | ## $(CMD_VCOM) lpp lpp_FIFO.vhd |
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59 | 59 | ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
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60 | 60 | $(CMD_VCOM) work TB.vhd |
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61 | 61 | @echo "vcom done" |
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62 | 62 | |
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63 | 63 | vcom_grlib: |
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64 | 64 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd |
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65 | 65 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd |
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66 | 66 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd |
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67 | 67 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd |
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68 | 68 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd |
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69 | 69 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd |
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70 | 70 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd |
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71 | 71 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd |
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72 | 72 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd |
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73 | 73 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd |
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74 | 74 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd |
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75 | 75 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd |
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76 | 76 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd |
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77 | 77 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd |
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78 | 78 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd |
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79 | 79 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd |
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80 | 80 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd |
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81 | 81 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd |
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82 | 82 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd |
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83 | 83 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd |
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84 | 84 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd |
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85 | 85 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd |
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86 | 86 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd |
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87 | 87 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd |
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88 | 88 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd |
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89 | 89 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd |
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90 | 90 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd |
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91 | 91 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd |
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92 | 92 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd |
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93 | 93 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd |
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94 | 94 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd |
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95 | 95 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd |
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96 | 96 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd |
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97 | 97 | $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd |
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98 | 98 | @echo "vcom grlib done" |
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99 | 99 | |
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100 | 100 | vcom_gaisler: |
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101 | 101 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd |
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102 | 102 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd |
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103 | 103 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd |
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104 | 104 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd |
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105 | 105 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd |
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106 | 106 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd |
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107 | 107 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd |
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108 | 108 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd |
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109 | 109 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd |
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110 | 110 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd |
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111 | 111 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd |
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112 | 112 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd |
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113 | 113 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd |
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114 | 114 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd |
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115 | 115 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd |
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116 | 116 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd |
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117 | 117 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd |
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118 | 118 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd |
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119 | 119 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd |
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120 | 120 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd |
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121 | 121 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd |
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122 | 122 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd |
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123 | 123 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd |
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124 | 124 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd |
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125 | 125 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd |
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126 | 126 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd |
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127 | 127 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd |
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128 | 128 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd |
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129 | 129 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd |
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130 | 130 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd |
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131 | 131 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd |
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132 | 132 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd |
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133 | 133 | # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd |
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134 | 134 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd |
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135 | 135 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd |
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136 | 136 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd |
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137 | 137 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd |
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138 | 138 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd |
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139 | 139 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd |
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140 | 140 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd |
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141 | 141 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd |
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142 | 142 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd |
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143 | 143 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd |
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144 | 144 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd |
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145 | 145 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd |
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146 | 146 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd |
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147 | 147 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd |
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148 | 148 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd |
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149 | 149 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd |
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150 | 150 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd |
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151 | 151 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd |
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152 | 152 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd |
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153 | 153 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd |
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154 | 154 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd |
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155 | 155 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd |
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156 | 156 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd |
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157 | 157 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd |
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158 | 158 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd |
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159 | 159 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd |
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160 | 160 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd |
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161 | 161 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd |
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162 | 162 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd |
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163 | 163 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd |
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164 | 164 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd |
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165 | 165 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd |
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166 | 166 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd |
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167 | 167 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd |
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168 | 168 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd |
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169 | 169 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd |
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170 | 170 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd |
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171 | 171 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd |
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172 | 172 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd |
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173 | 173 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd |
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174 | 174 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd |
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175 | 175 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd |
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176 | 176 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd |
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177 | 177 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd |
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178 | 178 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd |
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179 | 179 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd |
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180 | 180 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd |
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181 | 181 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd |
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182 | 182 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd |
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183 | 183 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd |
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184 | 184 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd |
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185 | 185 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd |
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186 | 186 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd |
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187 | 187 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd |
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188 | 188 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd |
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189 | 189 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd |
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190 | 190 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd |
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191 | 191 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd |
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192 | 192 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd |
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193 | 193 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd |
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194 | 194 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd |
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195 | 195 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd |
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196 | 196 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd |
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197 | 197 | ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd |
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198 | 198 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd |
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199 | 199 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd |
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200 | 200 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd |
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201 | 201 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd |
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202 | 202 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd |
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203 | 203 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd |
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204 | 204 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd |
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205 | 205 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd |
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206 | 206 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd |
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207 | 207 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd |
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208 | 208 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd |
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209 | 209 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd |
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210 | 210 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd |
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211 | 211 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd |
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212 | 212 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd |
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213 | 213 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd |
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214 | 214 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd |
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215 | 215 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd |
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216 | 216 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd |
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217 | 217 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd |
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218 | 218 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd |
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219 | 219 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd |
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220 | 220 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd |
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221 | 221 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd |
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222 | 222 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd |
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223 | 223 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd |
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224 | 224 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd |
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225 | 225 | $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd |
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226 | 226 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd |
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227 | 227 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd |
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228 | 228 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd |
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229 | 229 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd |
|
|
230 | 230 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd |
|
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231 | 231 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd |
|
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232 | 232 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd |
|
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233 | 233 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd |
|
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234 | 234 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd |
|
|
235 | 235 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd |
|
|
236 | 236 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd |
|
|
237 | 237 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd |
|
|
238 | 238 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd |
|
|
239 | 239 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd |
|
|
240 | 240 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd |
|
|
241 | 241 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd |
|
|
242 | 242 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd |
|
|
243 | 243 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd |
|
|
244 | 244 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd |
|
|
245 | 245 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd |
|
|
246 | 246 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd |
|
|
247 | 247 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd |
|
|
248 | 248 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd |
|
|
249 | 249 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd |
|
|
250 | 250 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd |
|
|
251 | 251 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd |
|
|
252 | 252 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd |
|
|
253 | 253 | # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd |
|
|
254 | 254 | @echo "vcom gaisler done" |
|
|
255 | 255 | |
|
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256 | 256 | vcom_techmap: |
|
|
257 | 257 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd |
|
|
258 | 258 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd |
|
|
259 | 259 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd |
|
|
260 | 260 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd |
|
|
261 | 261 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd |
|
|
262 | 262 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd |
|
|
263 | 263 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd |
|
|
264 | 264 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd |
|
|
265 | 265 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd |
|
|
266 | 266 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd |
|
|
267 | 267 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd |
|
|
268 | 268 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd |
|
|
269 | 269 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd |
|
|
270 | 270 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd |
|
|
271 | 271 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd |
|
|
272 | 272 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd |
|
|
273 | 273 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd |
|
|
274 | 274 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd |
|
|
275 | 275 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd |
|
|
276 | 276 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd |
|
|
277 | 277 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd |
|
|
278 | 278 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd |
|
|
279 | 279 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd |
|
|
280 | 280 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd |
|
|
281 | 281 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd |
|
|
282 | 282 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd |
|
|
283 | 283 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd |
|
|
284 | 284 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd |
|
|
285 | 285 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd |
|
|
286 | 286 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd |
|
|
287 | 287 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd |
|
|
288 | 288 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd |
|
|
289 | 289 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd |
|
|
290 | 290 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd |
|
|
291 | 291 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd |
|
|
292 | 292 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd |
|
|
293 | 293 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd |
|
|
294 | 294 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd |
|
|
295 | 295 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd |
|
|
296 | 296 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd |
|
|
297 | 297 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd |
|
|
298 | 298 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd |
|
|
299 | 299 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd |
|
|
300 | 300 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd |
|
|
301 | 301 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd |
|
|
302 | 302 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd |
|
|
303 | 303 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd |
|
|
304 | 304 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd |
|
|
305 | 305 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd |
|
|
306 | 306 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd |
|
|
307 | 307 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd |
|
|
308 | 308 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd |
|
|
309 | 309 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd |
|
|
310 | 310 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd |
|
|
311 | 311 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd |
|
|
312 | 312 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd |
|
|
313 | 313 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd |
|
|
314 | 314 | $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd |
|
|
315 | 315 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd |
|
|
316 | 316 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd |
|
|
317 | 317 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd |
|
|
318 | 318 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd |
|
|
319 | 319 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd |
|
|
320 | 320 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd |
|
|
321 | 321 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd |
|
|
322 | 322 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd |
|
|
323 | 323 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd |
|
|
324 | 324 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd |
|
|
325 | 325 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd |
|
|
326 | 326 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd |
|
|
327 | 327 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd |
|
|
328 | 328 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd |
|
|
329 | 329 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd |
|
|
330 | 330 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd |
|
|
331 | 331 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd |
|
|
332 | 332 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd |
|
|
333 | 333 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd |
|
|
334 | 334 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd |
|
|
335 | 335 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd |
|
|
336 | 336 | # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd |
|
|
337 | 337 | @echo "vcom techmap done" |
|
|
338 | 338 | |
|
|
339 | 339 | vcom_lpp: |
|
|
340 | 340 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
|
341 | 341 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
|
342 | 342 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
|
|
343 | 343 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
|
|
344 | 344 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
|
|
345 | 345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
|
|
346 | 346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
|
347 | 347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
|
348 | 348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
|
349 | 349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
|
350 | 350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
|
351 | 351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
|
352 | 352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
|
353 | 353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
|
354 | 354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
|
355 | 355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
|
356 | 356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
|
357 | 357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
|
358 | 358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
|
359 | 359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
|
360 | 360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
|
361 | 361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
|
362 | 362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
|
363 | 363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
|
364 | 364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
|
365 | 365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
|
366 | 366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
|
367 | 367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
|
368 | 368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
|
369 | 369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
|
370 | 370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
|
|
371 | 371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
|
372 | 372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd |
|
|
373 | 373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
|
374 | 374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
|
375 | 375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd |
|
|
376 | 376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
|
377 | 377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd |
|
|
378 | 378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd |
|
|
379 | 379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd |
|
|
380 | 380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd |
|
|
381 | 381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd |
|
|
382 | 382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd |
|
|
383 | 383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd |
|
|
384 | 384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd |
|
|
385 | 385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd |
|
|
386 | 386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd |
|
|
387 | 387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd |
|
|
388 | 388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd |
|
|
389 | 389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd |
|
|
390 | 390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd |
|
|
391 | 391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
|
|
392 | 392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd |
|
|
393 | 393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
|
|
394 | 394 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
|
|
395 | 395 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd |
|
|
396 | 396 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd |
|
|
397 | 397 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
|
398 | 398 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd |
|
|
399 | 399 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
|
400 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |
|
|
400 | 401 | @echo "vcom lpp done" |
|
|
401 | 402 | |
|
|
402 | 403 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
|
|
403 | 404 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd |
|
|
404 | 405 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd |
|
|
405 | 406 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd |
|
|
406 | 407 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd |
|
|
407 | 408 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd |
|
|
408 | 409 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd |
|
|
409 | 410 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd |
|
|
410 | 411 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd |
|
|
411 | 412 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd |
|
|
412 | 413 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd |
|
|
413 | 414 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd |
|
|
414 | 415 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd |
|
|
415 | 416 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd |
|
|
416 | 417 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd |
|
|
417 | 418 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd |
|
|
418 | 419 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd |
|
|
419 | 420 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd |
|
|
420 | 421 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd |
|
|
421 | 422 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd |
|
|
422 | 423 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd |
|
|
423 | 424 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd |
|
|
424 | 425 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
|
|
425 | 426 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
|
426 | 427 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
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427 | 428 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd |
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428 | 429 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
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429 | 430 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
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430 | 431 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
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431 | 432 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd |
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432 | 433 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd |
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433 | 434 | # @echo "vcom lpp done" |
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434 | 435 | |
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435 | 436 | #include Makefile_vcom_lpp |
| @@ -1,151 +1,158 | |||
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1 | 1 | onerror {resume} |
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2 | 2 | quietly WaveActivateNextPane {} 0 |
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3 | 3 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen |
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4 | 4 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata |
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5 | 5 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen |
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6 | 6 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata |
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7 | 7 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen |
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8 | 8 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata |
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9 | 9 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen |
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10 | 10 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full |
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11 | 11 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full |
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12 | 12 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty |
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13 | 13 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren |
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14 | 14 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect |
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15 | 15 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect |
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16 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/more_16data | |
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17 | 16 | add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
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18 | 17 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen |
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19 | 18 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full |
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20 | 19 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full |
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21 | 20 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty |
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22 | 21 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren |
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23 | 22 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen |
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24 | 23 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk |
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25 | 24 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full |
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26 | 25 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full |
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27 | 26 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty |
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28 | 27 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren |
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29 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/more_16data | |
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30 | 28 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull |
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31 | 29 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s |
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32 | 30 | add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
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33 | 31 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen |
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34 | 32 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full |
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35 | 33 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full |
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36 | 34 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty |
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37 | 35 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren |
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38 | 36 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel |
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39 | 37 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft |
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40 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload | |
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41 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im | |
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42 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re | |
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43 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid | |
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44 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset | |
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45 | add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart | |
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46 | 38 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0 |
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47 | 39 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1 |
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48 | 40 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2 |
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49 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y | |
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50 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong | |
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51 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy | |
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52 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid | |
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53 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im | |
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54 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re | |
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55 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray | |
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56 | 41 | add wave -noupdate /tb/lpp_lfr_ms_1/status_channel |
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57 |
add wave -noupdate |
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58 |
add wave -noupdate |
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59 |
add wave -noupdate |
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60 |
add wave -noupdate |
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61 |
add wave -noupdate |
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42 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
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43 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
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44 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray | |
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45 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray | |
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46 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray | |
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62 | 47 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load |
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63 | 48 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory |
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64 | 49 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full |
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65 | 50 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty |
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66 | 51 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full |
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67 | 52 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata |
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68 | 53 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen |
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69 | 54 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked |
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70 | 55 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata |
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71 | 56 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren |
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72 | 57 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto |
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73 | 58 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done |
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74 | 59 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start |
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75 | 60 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data |
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76 | 61 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty |
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77 | 62 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren |
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78 | 63 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data |
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79 | 64 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full |
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80 | 65 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen |
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81 | 66 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1 |
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82 | 67 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2 |
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83 | 68 | add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res |
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84 | 69 | add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state |
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85 | 70 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty |
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86 | 71 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full |
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87 | 72 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata |
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88 | 73 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen |
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89 | 74 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect |
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90 | 75 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s |
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91 | 76 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect |
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92 | 77 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s |
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93 | 78 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray |
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94 | 79 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect |
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95 | 80 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s |
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96 | 81 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect |
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97 | 82 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s |
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98 | 83 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
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99 | 84 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 |
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100 | 85 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end |
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101 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_new | |
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102 | 86 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 |
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103 | 87 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end |
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104 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_new | |
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105 | 88 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready |
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106 | 89 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready |
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107 | 90 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing |
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108 | 91 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data |
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109 | 92 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty |
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110 | 93 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren |
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111 | 94 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status |
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112 | 95 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr |
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113 | 96 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data |
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114 | 97 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done |
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115 | 98 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren |
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116 | 99 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid |
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117 | 100 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst |
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118 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_0 | |
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119 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_1 | |
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120 | 101 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1 |
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121 | 102 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2 |
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122 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_0 | |
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123 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_1 | |
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124 | 103 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1 |
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125 | 104 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2 |
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126 | 105 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state |
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127 | 106 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type |
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128 | 107 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre |
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129 | 108 | add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type |
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130 | 109 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok |
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131 | 110 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty |
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132 | 111 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo |
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112 | add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error | |
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113 | add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full | |
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114 | add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write | |
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115 | add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1 | |
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116 | add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2 | |
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117 | add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res | |
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118 | add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp | |
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119 | add wave -noupdate -expand -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl | |
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120 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse | |
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121 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen | |
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122 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata | |
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123 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren | |
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124 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata | |
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125 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty | |
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126 | add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full | |
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127 | add wave -noupdate -expand -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full | |
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128 | add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(128) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(129) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(130) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(131) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(132) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(133) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(134) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(135) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(136) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(137) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(138) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(139) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(140) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(141) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(142) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(143) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(144) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(145) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(146) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(147) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(148) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(149) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(150) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(151) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(152) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(153) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(154) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(155) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(156) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(157) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(158) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(159) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(160) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(161) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(162) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(163) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(164) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(165) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(166) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(167) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(168) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(169) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(170) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(171) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(172) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(173) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(174) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(175) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(176) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(177) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(178) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(179) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(180) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(181) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(182) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(183) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(184) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(185) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(186) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(187) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(188) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(189) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(190) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(191) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(192) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(193) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(194) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(195) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(196) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(197) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(198) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(199) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(200) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(201) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(202) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(203) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(204) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(205) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(206) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(207) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(208) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(209) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(210) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(211) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(212) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(213) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(214) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(215) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(216) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(217) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(218) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(219) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(220) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(221) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(222) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(223) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(224) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(225) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(226) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(227) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(228) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(229) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(230) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(231) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(232) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(233) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(234) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(235) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(236) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(237) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(238) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(239) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(240) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(241) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(242) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(243) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(244) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(245) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(246) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(247) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(248) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(249) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(250) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(251) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(252) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(253) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(254) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(255) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
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129 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
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130 | add wave -noupdate -expand -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult | |
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131 | add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1 | |
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132 | add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2 | |
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133 | add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res | |
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134 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add | |
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135 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr | |
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136 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load | |
|
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137 | add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1 | |
|
|
138 | add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2 | |
|
|
139 | add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res | |
|
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133 | 140 | TreeUpdate [SetDefaultTree] |
|
|
134 |
WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44 |
|
|
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141 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {10435060000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {99992359332 ps} 0} | |
|
|
135 | 142 | configure wave -namecolwidth 469 |
|
|
136 | 143 | configure wave -valuecolwidth 112 |
|
|
137 | 144 | configure wave -justifyvalue left |
|
|
138 | 145 | configure wave -signalnamewidth 0 |
|
|
139 | 146 | configure wave -snapdistance 10 |
|
|
140 | 147 | configure wave -datasetprefix 0 |
|
|
141 | 148 | configure wave -rowmargin 4 |
|
|
142 | 149 | configure wave -childrowmargin 2 |
|
|
143 | 150 | configure wave -gridoffset 0 |
|
|
144 | 151 | configure wave -gridperiod 1 |
|
|
145 | 152 | configure wave -griddelta 40 |
|
|
146 | 153 | configure wave -timeline 0 |
|
|
147 | 154 | configure wave -timelineunits ps |
|
|
148 | 155 | update |
|
|
149 |
WaveRestoreZoom {10 |
|
|
|
156 | WaveRestoreZoom {10434939916 ps} {10435778196 ps} | |
|
|
150 | 157 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
|
|
151 | 158 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
| @@ -1,301 +1,328 | |||
|
|
1 | 1 | ------------------------------------------------------------------------------ |
|
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
4 | 4 | -- |
|
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
8 | 8 | -- (at your option) any later version. |
|
|
9 | 9 | -- |
|
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
13 | 13 | -- GNU General Public License for more details. |
|
|
14 | 14 | -- |
|
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
18 | 18 | ------------------------------------------------------------------------------- |
|
|
19 | 19 | -- Author : Alexis Jeandet |
|
|
20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
|
21 | 21 | ---------------------------------------------------------------------------- |
|
|
22 | 22 | LIBRARY IEEE; |
|
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
|
25 | 25 | LIBRARY lpp; |
|
|
26 | 26 | USE lpp.general_purpose.ALL; |
|
|
27 | 27 | --TODO |
|
|
28 | 28 | --terminer le testbensh puis changer le resize dans les instanciations |
|
|
29 | 29 | --par un resize sur un vecteur en combi |
|
|
30 | 30 | |
|
|
31 | 31 | |
|
|
32 | 32 | ENTITY MAC IS |
|
|
33 | 33 | GENERIC( |
|
|
34 | 34 | Input_SZ_A : INTEGER := 8; |
|
|
35 | 35 | Input_SZ_B : INTEGER := 8; |
|
|
36 | 36 | COMP_EN : INTEGER := 0 -- 1 => No Comp |
|
|
37 | 37 | |
|
|
38 | 38 | ); |
|
|
39 | 39 | PORT( |
|
|
40 | 40 | clk : IN STD_LOGIC; |
|
|
41 | 41 | reset : IN STD_LOGIC; |
|
|
42 | 42 | clr_MAC : IN STD_LOGIC; |
|
|
43 | 43 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
44 | 44 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
45 | 45 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
46 | 46 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
47 | 47 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
|
48 | 48 | ); |
|
|
49 | 49 | END MAC; |
|
|
50 | 50 | |
|
|
51 | 51 | |
|
|
52 | 52 | |
|
|
53 | 53 | |
|
|
54 | 54 | ARCHITECTURE ar_MAC OF MAC IS |
|
|
55 | 55 | |
|
|
56 | ||
|
|
57 | SIGNAL clr_MAC_s : STD_LOGIC; | |
|
|
58 | SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
59 | ||
|
|
56 | 60 | SIGNAL add, mult : STD_LOGIC; |
|
|
57 | 61 | SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
58 | 62 | |
|
|
59 | 63 | SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
60 | 64 | SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
61 | 65 | SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
62 | 66 | |
|
|
63 | 67 | SIGNAL MACMUXsel : STD_LOGIC; |
|
|
64 | 68 | SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
65 | 69 | SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
66 | 70 | |
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|
67 | 71 | SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
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68 | 72 | SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
69 | 73 | |
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70 | 74 | SIGNAL MACMUX2sel : STD_LOGIC; |
|
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71 | 75 | |
|
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72 | 76 | SIGNAL add_D : STD_LOGIC; |
|
|
73 | 77 | SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
|
74 | 78 | SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
|
75 | 79 | SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); |
|
|
76 | 80 | SIGNAL MACMUXsel_D : STD_LOGIC; |
|
|
77 | 81 | SIGNAL MACMUX2sel_D : STD_LOGIC; |
|
|
78 | 82 | SIGNAL MACMUX2sel_D_D : STD_LOGIC; |
|
|
79 | 83 | SIGNAL clr_MAC_D : STD_LOGIC; |
|
|
80 | SIGNAL clr_MAC_D_D : STD_LOGIC; | |
|
|
81 | SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
84 | -- SIGNAL clr_MAC_D_D : STD_LOGIC; | |
|
|
85 | -- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
82 | 86 | |
|
|
83 | 87 | SIGNAL load_mult_result : STD_LOGIC; |
|
|
84 | 88 | SIGNAL load_mult_result_D : STD_LOGIC; |
|
|
85 | 89 | |
|
|
86 | 90 | BEGIN |
|
|
87 | 91 | |
|
|
88 | 92 | |
|
|
89 | 93 | |
|
|
90 | 94 | |
|
|
91 | 95 | --============================================================== |
|
|
92 | 96 | --=============M A C C O N T R O L E R========================= |
|
|
93 | 97 | --============================================================== |
|
|
94 | 98 | MAC_CONTROLER1 : MAC_CONTROLER |
|
|
95 | 99 | PORT MAP( |
|
|
96 | ctrl => MAC_MUL_ADD, | |
|
|
100 | ctrl => MAC_MUL_ADD_s, | |
|
|
97 | 101 | MULT => mult, |
|
|
98 | 102 | ADD => add, |
|
|
99 | 103 | LOAD_ADDER => load_mult_result, |
|
|
100 | 104 | MACMUX_sel => MACMUXsel, |
|
|
101 | 105 | MACMUX2_sel => MACMUX2sel |
|
|
102 | 106 | |
|
|
103 | 107 | ); |
|
|
104 | 108 | --============================================================== |
|
|
105 | 109 | |
|
|
106 | 110 | |
|
|
107 | 111 | |
|
|
108 | 112 | |
|
|
109 | 113 | --============================================================== |
|
|
110 | 114 | --=============M U L T I P L I E R============================== |
|
|
111 | 115 | --============================================================== |
|
|
112 | 116 | Multiplieri_nst : Multiplier |
|
|
113 | 117 | GENERIC MAP( |
|
|
114 | 118 | Input_SZ_A => Input_SZ_A, |
|
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115 | 119 | Input_SZ_B => Input_SZ_B |
|
|
116 | 120 | ) |
|
|
117 | 121 | PORT MAP( |
|
|
118 | 122 | clk => clk, |
|
|
119 | 123 | reset => reset, |
|
|
120 | 124 | mult => mult, |
|
|
121 | 125 | OP1 => OP1_2C, |
|
|
122 | 126 | OP2 => OP2_2C, |
|
|
123 | 127 | RES => MULTout |
|
|
124 | 128 | ); |
|
|
125 | 129 | --============================================================== |
|
|
126 | 130 | |
|
|
127 | 131 | PROCESS (clk, reset) |
|
|
128 | 132 | BEGIN -- PROCESS |
|
|
129 | 133 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
|
130 | 134 | load_mult_result_D <= '0'; |
|
|
131 | 135 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|
132 | 136 | load_mult_result_D <= load_mult_result; |
|
|
133 | 137 | END IF; |
|
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134 | 138 | END PROCESS; |
|
|
135 | 139 | |
|
|
136 | 140 | --============================================================== |
|
|
137 | 141 | --======================A D D E R ============================== |
|
|
138 | 142 | --============================================================== |
|
|
139 | 143 | adder_inst : Adder |
|
|
140 | 144 | GENERIC MAP( |
|
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141 | 145 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
|
142 | 146 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
|
143 | 147 | ) |
|
|
144 | 148 | PORT MAP( |
|
|
145 | 149 | clk => clk, |
|
|
146 | 150 | reset => reset, |
|
|
147 | 151 | clr => clr_MAC_D, |
|
|
148 | 152 | load => load_mult_result_D, |
|
|
149 | 153 | add => add_D, |
|
|
150 | 154 | OP1 => ADDERinA, |
|
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151 | 155 | OP2 => ADDERinB, |
|
|
152 | 156 | RES => ADDERout |
|
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153 | 157 | ); |
|
|
154 | 158 | |
|
|
155 | 159 | --============================================================== |
|
|
156 | 160 | --===================TWO COMPLEMENTERS========================== |
|
|
157 | 161 | --============================================================== |
|
|
158 | 162 | gen_comp : IF COMP_EN = 0 GENERATE |
|
|
159 | 163 | TWO_COMPLEMENTER1 : TwoComplementer |
|
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160 | 164 | GENERIC MAP( |
|
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161 | 165 | Input_SZ => Input_SZ_A |
|
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162 | 166 | ) |
|
|
163 | 167 | PORT MAP( |
|
|
164 | 168 | clk => clk, |
|
|
165 | 169 | reset => reset, |
|
|
166 |
clr => |
|
|
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170 | clr => '0',--clr_MAC, | |
|
|
167 | 171 | TwoComp => Comp_2C(0), |
|
|
168 | 172 | OP => OP1, |
|
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169 | 173 | RES => OP1_2C |
|
|
170 | 174 | ); |
|
|
171 | 175 | |
|
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172 | 176 | TWO_COMPLEMENTER2 : TwoComplementer |
|
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173 | 177 | GENERIC MAP( |
|
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174 | 178 | Input_SZ => Input_SZ_B |
|
|
175 | 179 | ) |
|
|
176 | 180 | PORT MAP( |
|
|
177 | 181 | clk => clk, |
|
|
178 | 182 | reset => reset, |
|
|
179 |
clr => |
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|
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183 | clr => '0',--clr_MAC, | |
|
|
180 | 184 | TwoComp => Comp_2C(1), |
|
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181 | 185 | OP => OP2, |
|
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182 | 186 | RES => OP2_2C |
|
|
183 | 187 | ); |
|
|
188 | ||
|
|
189 | ||
|
|
190 | clr_MACREG_comp : MAC_REG | |
|
|
191 | GENERIC MAP(size => 1) | |
|
|
192 | PORT MAP( | |
|
|
193 | reset => reset, | |
|
|
194 | clk => clk, | |
|
|
195 | D(0) => clr_MAC, | |
|
|
196 | Q(0) => clr_MAC_s | |
|
|
197 | ); | |
|
|
198 | ||
|
|
199 | MAC_MUL_ADD_REG : MAC_REG | |
|
|
200 | GENERIC MAP(size => 2) | |
|
|
201 | PORT MAP( | |
|
|
202 | reset => reset, | |
|
|
203 | clk => clk, | |
|
|
204 | D => MAC_MUL_ADD, | |
|
|
205 | Q => MAC_MUL_ADD_s | |
|
|
206 | ); | |
|
|
207 | ||
|
|
184 | 208 |
|
|
|
185 | 209 | |
|
|
186 | 210 | no_gen_comp : IF COMP_EN = 1 GENERATE |
|
|
187 | 211 | OP2_2C <= OP2; |
|
|
188 | 212 | OP1_2C <= OP1; |
|
|
213 | ||
|
|
214 | clr_MAC_s <= clr_MAC; | |
|
|
215 | MAC_MUL_ADD_s <= MAC_MUL_ADD; | |
|
|
189 | 216 | END GENERATE no_gen_comp; |
|
|
190 | 217 | --============================================================== |
|
|
191 | 218 | |
|
|
192 | 219 | clr_MACREG1 : MAC_REG |
|
|
193 | 220 | GENERIC MAP(size => 1) |
|
|
194 | 221 | PORT MAP( |
|
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195 | 222 | reset => reset, |
|
|
196 | 223 | clk => clk, |
|
|
197 | D(0) => clr_MAC, | |
|
|
224 | D(0) => clr_MAC_s, | |
|
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198 | 225 | Q(0) => clr_MAC_D |
|
|
199 | 226 | ); |
|
|
200 | 227 | |
|
|
201 | 228 | addREG : MAC_REG |
|
|
202 | 229 | GENERIC MAP(size => 1) |
|
|
203 | 230 | PORT MAP( |
|
|
204 | 231 | reset => reset, |
|
|
205 | 232 | clk => clk, |
|
|
206 | 233 | D(0) => add, |
|
|
207 | 234 | Q(0) => add_D |
|
|
208 | 235 | ); |
|
|
209 | 236 | |
|
|
210 | 237 | OP1REG : MAC_REG |
|
|
211 | 238 | GENERIC MAP(size => Input_SZ_A) |
|
|
212 | 239 | PORT MAP( |
|
|
213 | 240 | reset => reset, |
|
|
214 | 241 | clk => clk, |
|
|
215 | 242 | D => OP1_2C, |
|
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216 | 243 | Q => OP1_2C_D |
|
|
217 | 244 | ); |
|
|
218 | 245 | |
|
|
219 | 246 | |
|
|
220 | 247 | OP2REG : MAC_REG |
|
|
221 | 248 | GENERIC MAP(size => Input_SZ_B) |
|
|
222 | 249 | PORT MAP( |
|
|
223 | 250 | reset => reset, |
|
|
224 | 251 | clk => clk, |
|
|
225 | 252 | D => OP2_2C, |
|
|
226 | 253 | Q => OP2_2C_D |
|
|
227 | 254 | ); |
|
|
228 | 255 | |
|
|
229 | 256 | MULToutREG : MAC_REG |
|
|
230 | 257 | GENERIC MAP(size => Input_SZ_A+Input_SZ_B) |
|
|
231 | 258 | PORT MAP( |
|
|
232 | 259 | reset => reset, |
|
|
233 | 260 | clk => clk, |
|
|
234 | 261 | D => MULTout, |
|
|
235 | 262 | Q => MULTout_D |
|
|
236 | 263 | ); |
|
|
237 | 264 | |
|
|
238 | 265 | MACMUXselREG : MAC_REG |
|
|
239 | 266 | GENERIC MAP(size => 1) |
|
|
240 | 267 | PORT MAP( |
|
|
241 | 268 | reset => reset, |
|
|
242 | 269 | clk => clk, |
|
|
243 | 270 | D(0) => MACMUXsel, |
|
|
244 | 271 | Q(0) => MACMUXsel_D |
|
|
245 | 272 | ); |
|
|
246 | 273 | |
|
|
247 | 274 | MACMUX2selREG : MAC_REG |
|
|
248 | 275 | GENERIC MAP(size => 1) |
|
|
249 | 276 | PORT MAP( |
|
|
250 | 277 | reset => reset, |
|
|
251 | 278 | clk => clk, |
|
|
252 | 279 | D(0) => MACMUX2sel, |
|
|
253 | 280 | Q(0) => MACMUX2sel_D |
|
|
254 | 281 | ); |
|
|
255 | 282 | |
|
|
256 | 283 | MACMUX2selREG2 : MAC_REG |
|
|
257 | 284 | GENERIC MAP(size => 1) |
|
|
258 | 285 | PORT MAP( |
|
|
259 | 286 | reset => reset, |
|
|
260 | 287 | clk => clk, |
|
|
261 | 288 | D(0) => MACMUX2sel_D, |
|
|
262 | 289 | Q(0) => MACMUX2sel_D_D |
|
|
263 | 290 | ); |
|
|
264 | 291 | |
|
|
265 | 292 | --============================================================== |
|
|
266 | 293 | --======================M A C M U X =========================== |
|
|
267 | 294 | --============================================================== |
|
|
268 | 295 | MACMUX_inst : MAC_MUX |
|
|
269 | 296 | GENERIC MAP( |
|
|
270 | 297 | Input_SZ_A => Input_SZ_A+Input_SZ_B, |
|
|
271 | 298 | Input_SZ_B => Input_SZ_A+Input_SZ_B |
|
|
272 | 299 | |
|
|
273 | 300 | ) |
|
|
274 | 301 | PORT MAP( |
|
|
275 | 302 | sel => MACMUXsel_D, |
|
|
276 | 303 | INA1 => ADDERout, |
|
|
277 | 304 | INA2 => OP2_2C_D_Resz, |
|
|
278 | 305 | INB1 => MULTout, |
|
|
279 | 306 | INB2 => OP1_2C_D_Resz, |
|
|
280 | 307 | OUTA => ADDERinA, |
|
|
281 | 308 | OUTB => ADDERinB |
|
|
282 | 309 | ); |
|
|
283 | 310 | OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); |
|
|
284 | 311 | OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); |
|
|
285 | 312 | --============================================================== |
|
|
286 | 313 | |
|
|
287 | 314 | |
|
|
288 | 315 | --============================================================== |
|
|
289 | 316 | --======================M A C M U X2 ========================== |
|
|
290 | 317 | --============================================================== |
|
|
291 | 318 | MAC_MUX2_inst : MAC_MUX2 |
|
|
292 | 319 | GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) |
|
|
293 | 320 | PORT MAP( |
|
|
294 | 321 | sel => MACMUX2sel_D_D, |
|
|
295 | 322 | RES2 => MULTout_D, |
|
|
296 | 323 | RES1 => ADDERout, |
|
|
297 | 324 | RES => RES |
|
|
298 | 325 | ); |
|
|
299 | 326 | --============================================================== |
|
|
300 | 327 | |
|
|
301 | 328 | END ar_MAC; |
| @@ -1,10 +1,4 | |||
|
|
1 | 1 | lpp_memory.vhd |
|
|
2 | 2 | lpp_FIFO.vhd |
|
|
3 | FillFifo.vhd | |
|
|
4 | Bridge.vhd | |
|
|
5 | APB_FIFO.vhd | |
|
|
6 | Bridge.vhd | |
|
|
7 | SSRAM_plugin.vhd | |
|
|
8 | lppFIFOx5.vhd | |
|
|
9 | 3 | lppFIFOxN.vhd |
|
|
10 | 4 | |
| @@ -1,224 +1,225 | |||
|
|
1 | 1 | LIBRARY IEEE; |
|
|
2 | 2 | USE IEEE.std_logic_1164.ALL; |
|
|
3 | 3 | |
|
|
4 | 4 | LIBRARY lpp; |
|
|
5 | 5 | USE lpp.general_purpose.ALL; |
|
|
6 | 6 | |
|
|
7 | 7 | ENTITY MS_calculation IS |
|
|
8 | 8 | PORT ( |
|
|
9 | 9 | clk : IN STD_LOGIC; |
|
|
10 | 10 | rstn : IN STD_LOGIC; |
|
|
11 | 11 | -- IN |
|
|
12 | 12 | fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
|
13 | 13 | fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
14 | 14 | fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
15 | 15 | -- OUT |
|
|
16 | 16 | fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0); |
|
|
17 | 17 | fifo_out_wen : OUT STD_LOGIC; |
|
|
18 | 18 | fifo_out_full : IN STD_LOGIC; |
|
|
19 | 19 | -- |
|
|
20 | 20 | correlation_start : IN STD_LOGIC; |
|
|
21 | 21 | correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation |
|
|
22 | 22 | |
|
|
23 | 23 | correlation_begin : OUT STD_LOGIC; |
|
|
24 | 24 | correlation_done : OUT STD_LOGIC |
|
|
25 | 25 | ); |
|
|
26 | 26 | END MS_calculation; |
|
|
27 | 27 | |
|
|
28 | 28 | ARCHITECTURE beh OF MS_calculation IS |
|
|
29 | 29 | |
|
|
30 | 30 | TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a); |
|
|
31 | 31 | SIGNAL state : fsm_calculation_MS; |
|
|
32 | 32 | |
|
|
33 | 33 | SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
34 | 34 | SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
35 | 35 | SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
36 | 36 | |
|
|
37 | 37 | SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
38 | 38 | |
|
|
39 | 39 | |
|
|
40 | 40 | CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000"; |
|
|
41 | 41 | CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010"; |
|
|
42 | 42 | CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001"; |
|
|
43 | 43 | CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001"; |
|
|
44 | 44 | |
|
|
45 | 45 | |
|
|
46 | 46 | |
|
|
47 | 47 | SIGNAL select_op1 : STD_LOGIC; |
|
|
48 | 48 | SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ; |
|
|
49 | 49 | |
|
|
50 | 50 | CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; |
|
|
51 | 51 | CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; |
|
|
52 | 52 | CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; |
|
|
53 | 53 | CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; |
|
|
54 | 54 | |
|
|
55 | 55 | SIGNAL res_wen : STD_LOGIC; |
|
|
56 | 56 | SIGNAL res_wen_reg1 : STD_LOGIC; |
|
|
57 |
|
|
|
|
57 | SIGNAL res_wen_reg2 : STD_LOGIC; | |
|
|
58 | 58 | --SIGNAL res_wen_reg3 : STD_LOGIC; |
|
|
59 | 59 | |
|
|
60 | 60 | BEGIN |
|
|
61 | 61 | |
|
|
62 | 62 | |
|
|
63 | 63 | |
|
|
64 | 64 | PROCESS (clk, rstn) |
|
|
65 | 65 | BEGIN |
|
|
66 | 66 | IF rstn = '0' THEN |
|
|
67 | 67 | |
|
|
68 | 68 | correlation_begin <= '0'; |
|
|
69 | 69 | correlation_done <= '0'; |
|
|
70 | 70 | state <= IDLE; |
|
|
71 | 71 | fifo_in_ren <= "11"; |
|
|
72 | 72 | ALU_CTRL <= ALU_CTRL_NOP; |
|
|
73 | 73 | select_op1 <= select_R0(0); |
|
|
74 | 74 | select_op2 <= select_R0; |
|
|
75 | 75 | res_wen <= '1'; |
|
|
76 | 76 | |
|
|
77 | 77 | ELSIF clk'EVENT AND clk = '1' THEN |
|
|
78 | ALU_CTRL <= ALU_CTRL_NOP; | |
|
|
78 | 79 | correlation_begin <= '0'; |
|
|
79 | 80 | fifo_in_ren <= "11"; |
|
|
80 | 81 | res_wen <= '1'; |
|
|
81 | 82 | correlation_done <= '0'; |
|
|
82 | 83 | CASE state IS |
|
|
83 | 84 | WHEN IDLE => |
|
|
84 | 85 | IF correlation_start = '1' THEN |
|
|
85 | 86 | IF correlation_auto = '1' THEN |
|
|
86 | 87 | IF fifo_out_full = '1' THEN |
|
|
87 | 88 | state <= WFa; |
|
|
88 | 89 | ELSE |
|
|
89 | 90 | correlation_begin <= '1'; |
|
|
90 | 91 | state <= S1a; |
|
|
91 | 92 | fifo_in_ren <= "10"; |
|
|
92 | 93 | END IF; |
|
|
93 | 94 | ELSE |
|
|
94 | 95 | IF fifo_out_full = '1' THEN |
|
|
95 | 96 | state <= WF; |
|
|
96 | 97 | ELSE |
|
|
97 | 98 | correlation_begin <= '1'; |
|
|
98 | 99 | state <= S1; |
|
|
99 | 100 | fifo_in_ren <= "00"; |
|
|
100 | 101 | END IF; |
|
|
101 | 102 | END IF; |
|
|
102 | 103 | END IF; |
|
|
103 | 104 | |
|
|
104 | 105 | --------------------------------------------------------------------- |
|
|
105 | 106 | -- INTER CORRELATION |
|
|
106 | 107 | --------------------------------------------------------------------- |
|
|
107 | 108 | WHEN WF => |
|
|
108 | 109 | IF fifo_out_full = '0' THEN |
|
|
109 | 110 | correlation_begin <= '1'; |
|
|
110 | 111 | state <= S1; |
|
|
111 | 112 | fifo_in_ren <= "00"; |
|
|
112 | 113 | END IF; |
|
|
113 | 114 | WHEN S1 => |
|
|
114 | 115 | ALU_CTRL <= ALU_CTRL_MULT; |
|
|
115 | 116 | select_op1 <= select_R0(0); |
|
|
116 | 117 | select_op2 <= select_R1; |
|
|
117 | 118 | state <= S2; |
|
|
118 | 119 | WHEN S2 => |
|
|
119 | 120 | ALU_CTRL <= ALU_CTRL_MAC; |
|
|
120 | 121 | select_op1 <= select_I0(0); |
|
|
121 | 122 | select_op2 <= select_I1; |
|
|
122 | 123 | res_wen <= '0'; |
|
|
123 | 124 | state <= S3; |
|
|
124 | 125 | WHEN S3 => |
|
|
125 | 126 | ALU_CTRL <= ALU_CTRL_MULT; |
|
|
126 | 127 | select_op1 <= select_I0(0); |
|
|
127 | 128 | select_op2 <= select_R1; |
|
|
128 | 129 | state <= S4; |
|
|
129 | 130 | WHEN S4 => |
|
|
130 | 131 | ALU_CTRL <= ALU_CTRL_MACn; |
|
|
131 | 132 | select_op1 <= select_R0(0); |
|
|
132 | 133 | select_op2 <= select_I1; |
|
|
133 | 134 | res_wen <= '0'; |
|
|
134 | 135 | IF fifo_in_empty = "00" THEN |
|
|
135 | 136 | state <= S1; |
|
|
136 | 137 | fifo_in_ren <= "00"; |
|
|
137 | 138 | ELSE |
|
|
138 | 139 | correlation_done <= '1'; |
|
|
139 | 140 | state <= IDLE; |
|
|
140 | 141 | END IF; |
|
|
141 | 142 | |
|
|
142 | 143 | |
|
|
143 | 144 | |
|
|
144 | 145 | --------------------------------------------------------------------- |
|
|
145 | 146 | -- AUTO CORRELATION |
|
|
146 | 147 | --------------------------------------------------------------------- |
|
|
147 | 148 | WHEN WFa => |
|
|
148 | 149 | IF fifo_out_full = '0' THEN |
|
|
149 | 150 | correlation_begin <= '1'; |
|
|
150 | 151 | state <= S1a; |
|
|
151 | 152 | fifo_in_ren <= "10"; |
|
|
152 | 153 | END IF; |
|
|
153 | 154 | WHEN S1a => |
|
|
154 | 155 | ALU_CTRL <= ALU_CTRL_MULT; |
|
|
155 | 156 | select_op1 <= select_R0(0); |
|
|
156 | 157 | select_op2 <= select_R0; |
|
|
157 | 158 | state <= S2a; |
|
|
158 | 159 | WHEN S2a => |
|
|
159 | 160 | ALU_CTRL <= ALU_CTRL_MAC; |
|
|
160 | 161 | select_op1 <= select_I0(0); |
|
|
161 | 162 | select_op2 <= select_I0; |
|
|
162 | 163 | res_wen <= '0'; |
|
|
163 | 164 | IF fifo_in_empty(0) = '0' THEN |
|
|
164 | 165 | state <= S1a; |
|
|
165 | 166 | fifo_in_ren <= "10"; |
|
|
166 | 167 | ELSE |
|
|
167 | 168 | correlation_done <= '1'; |
|
|
168 | 169 | state <= IDLE; |
|
|
169 | 170 | END IF; |
|
|
170 | 171 | |
|
|
171 | 172 | |
|
|
172 | 173 | WHEN OTHERS => NULL; |
|
|
173 | 174 | END CASE; |
|
|
174 | 175 | |
|
|
175 | 176 | END IF; |
|
|
176 | 177 | END PROCESS; |
|
|
177 | 178 | |
|
|
178 | 179 | OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE |
|
|
179 | 180 | fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE |
|
|
180 | 181 | |
|
|
181 | 182 | OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE |
|
|
182 | 183 | fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE |
|
|
183 | 184 | fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE |
|
|
184 | 185 | fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE |
|
|
185 | 186 | |
|
|
186 | 187 | ALU_MS : ALU |
|
|
187 | 188 | GENERIC MAP ( |
|
|
188 | 189 | Arith_en => 1, |
|
|
189 | 190 | Logic_en => 0, |
|
|
190 | 191 | Input_SZ_1 => 16, |
|
|
191 | 192 | Input_SZ_2 => 16, |
|
|
192 | COMP_EN => 1) | |
|
|
193 | COMP_EN => 0) -- 0> Enable and 1> Disable | |
|
|
193 | 194 | PORT MAP ( |
|
|
194 | 195 | clk => clk, |
|
|
195 | 196 | reset => rstn, |
|
|
196 | 197 | |
|
|
197 | 198 | ctrl => ALU_CTRL(2 DOWNTO 0), |
|
|
198 | 199 | comp => ALU_CTRL(4 DOWNTO 3), |
|
|
199 | 200 | |
|
|
200 | 201 | OP1 => OP1, |
|
|
201 | 202 | OP2 => OP2, |
|
|
202 | 203 | |
|
|
203 | 204 | RES => RES); |
|
|
204 | 205 | |
|
|
205 | 206 | fifo_out_data <= RES; |
|
|
206 | 207 | |
|
|
207 | 208 | |
|
|
208 | 209 | PROCESS (clk, rstn) |
|
|
209 | 210 | BEGIN |
|
|
210 | 211 | IF rstn = '0' THEN |
|
|
211 | 212 | res_wen_reg1 <= '1'; |
|
|
212 |
|
|
|
|
213 | res_wen_reg2 <= '1'; | |
|
|
213 | 214 | --res_wen_reg3 <= '1'; |
|
|
214 | 215 | fifo_out_wen <= '1'; |
|
|
215 | 216 | ELSIF clk'event AND clk = '1' THEN |
|
|
216 | 217 | res_wen_reg1 <= res_wen; |
|
|
217 |
|
|
|
|
218 | res_wen_reg2 <= res_wen_reg1; | |
|
|
218 | 219 | --res_wen_reg3 <= res_wen_reg2; |
|
|
219 |
fifo_out_wen <= res_wen_reg |
|
|
|
220 | fifo_out_wen <= res_wen_reg2; | |
|
|
220 | 221 | END IF; |
|
|
221 | 222 | END PROCESS; |
|
|
222 | 223 | |
|
|
223 | 224 | |
|
|
224 | 225 | END beh; |
| @@ -1,36 +1,36 | |||
|
|
1 | 1 | LIBRARY ieee; |
|
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
|
3 | 3 | |
|
|
4 | 4 | ENTITY spectral_matrix_time_managment IS |
|
|
5 | 5 | |
|
|
6 | 6 | PORT ( |
|
|
7 | 7 | clk : IN STD_LOGIC; |
|
|
8 | 8 | rstn : IN STD_LOGIC; |
|
|
9 | 9 | |
|
|
10 | 10 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
11 | 11 | update_1 : IN STD_LOGIC; |
|
|
12 | 12 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
|
13 | 13 | ); |
|
|
14 | 14 | |
|
|
15 | 15 | END spectral_matrix_time_managment; |
|
|
16 | 16 | |
|
|
17 | 17 | ARCHITECTURE beh OF spectral_matrix_time_managment IS |
|
|
18 | 18 | |
|
|
19 | 19 | SIGNAL time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
20 | 20 | |
|
|
21 | 21 | BEGIN -- beh |
|
|
22 | 22 | |
|
|
23 | 23 | PROCESS (clk, rstn) |
|
|
24 | 24 | BEGIN |
|
|
25 | 25 | IF rstn = '0' THEN |
|
|
26 | 26 | time_reg <= (OTHERS => '0'); |
|
|
27 | 27 | ELSIF clk'event AND clk = '1' THEN |
|
|
28 | 28 | IF update_1 = '1' THEN |
|
|
29 | 29 | time_reg <= time_in; |
|
|
30 | 30 | END IF; |
|
|
31 | 31 | END IF; |
|
|
32 | 32 | END PROCESS; |
|
|
33 | 33 | |
|
|
34 |
time_out <= time_ |
|
|
|
34 | time_out <= time_reg; | |
|
|
35 | 35 | |
|
|
36 | 36 | END beh; |
| @@ -1,764 +1,762 | |||
|
|
1 | 1 | LIBRARY ieee; |
|
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
|
3 | 3 | USE ieee.numeric_std.ALL; |
|
|
4 | 4 | |
|
|
5 | 5 | LIBRARY lpp; |
|
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
|
8 | 8 | USE lpp.FILTERcfg.ALL; |
|
|
9 | 9 | USE lpp.lpp_memory.ALL; |
|
|
10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
|
11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
|
|
12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
|
14 | 14 | USE lpp.general_purpose.ALL; |
|
|
15 | 15 | |
|
|
16 | 16 | LIBRARY techmap; |
|
|
17 | 17 | USE techmap.gencomp.ALL; |
|
|
18 | 18 | |
|
|
19 | 19 | LIBRARY grlib; |
|
|
20 | 20 | USE grlib.amba.ALL; |
|
|
21 | 21 | USE grlib.stdlib.ALL; |
|
|
22 | 22 | USE grlib.devices.ALL; |
|
|
23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
|
|
24 | 24 | |
|
|
25 | 25 | ENTITY lpp_lfr IS |
|
|
26 | 26 | GENERIC ( |
|
|
27 | 27 | Mem_use : INTEGER := use_RAM; |
|
|
28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
|
|
29 | 29 | nb_word_by_buffer_size : INTEGER := 11; |
|
|
30 | 30 | nb_snapshot_param_size : INTEGER := 11; |
|
|
31 | 31 | delta_vector_size : INTEGER := 20; |
|
|
32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
|
|
33 | 33 | |
|
|
34 | 34 | pindex : INTEGER := 4; |
|
|
35 | 35 | paddr : INTEGER := 4; |
|
|
36 | 36 | pmask : INTEGER := 16#fff#; |
|
|
37 | 37 | pirq_ms : INTEGER := 0; |
|
|
38 | 38 | pirq_wfp : INTEGER := 1; |
|
|
39 | 39 | |
|
|
40 | 40 | hindex : INTEGER := 2; |
|
|
41 | 41 | |
|
|
42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
|
|
43 | 43 | |
|
|
44 | 44 | ); |
|
|
45 | 45 | PORT ( |
|
|
46 | 46 | clk : IN STD_LOGIC; |
|
|
47 | 47 | rstn : IN STD_LOGIC; |
|
|
48 | 48 | -- SAMPLE |
|
|
49 | 49 | sample_B : IN Samples(2 DOWNTO 0); |
|
|
50 | 50 | sample_E : IN Samples(4 DOWNTO 0); |
|
|
51 | 51 | sample_val : IN STD_LOGIC; |
|
|
52 | 52 | -- APB |
|
|
53 | 53 | apbi : IN apb_slv_in_type; |
|
|
54 | 54 | apbo : OUT apb_slv_out_type; |
|
|
55 | 55 | -- AHB |
|
|
56 | 56 | ahbi : IN AHB_Mst_In_Type; |
|
|
57 | 57 | ahbo : OUT AHB_Mst_Out_Type; |
|
|
58 | 58 | -- TIME |
|
|
59 | 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
|
60 | 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
|
61 | 61 | -- |
|
|
62 | 62 | data_shaping_BW : OUT STD_LOGIC; |
|
|
63 | 63 | -- |
|
|
64 | 64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
|
65 | 65 | |
|
|
66 | 66 | --debug |
|
|
67 | 67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|
68 | 68 | --debug_f0_data_valid : OUT STD_LOGIC; |
|
|
69 | 69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|
70 | 70 | --debug_f1_data_valid : OUT STD_LOGIC; |
|
|
71 | 71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|
72 | 72 | --debug_f2_data_valid : OUT STD_LOGIC; |
|
|
73 | 73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
|
74 | 74 | --debug_f3_data_valid : OUT STD_LOGIC; |
|
|
75 | 75 | |
|
|
76 | 76 | ---- debug FIFO_IN |
|
|
77 | 77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
78 | 78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
|
79 | 79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
80 | 80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
|
81 | 81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
82 | 82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
|
83 | 83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
84 | 84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
|
85 | 85 | |
|
|
86 | 86 | ----debug FIFO OUT |
|
|
87 | 87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
88 | 88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
|
89 | 89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
90 | 90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
|
91 | 91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
92 | 92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
|
93 | 93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
94 | 94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
|
95 | 95 | |
|
|
96 | 96 | ----debug DMA IN |
|
|
97 | 97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
98 | 98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
|
99 | 99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
100 | 100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
|
101 | 101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
102 | 102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
|
103 | 103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
104 | 104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
|
105 | 105 | ); |
|
|
106 | 106 | END lpp_lfr; |
|
|
107 | 107 | |
|
|
108 | 108 | ARCHITECTURE beh OF lpp_lfr IS |
|
|
109 | 109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
|
110 | 110 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
|
111 | 111 | -- |
|
|
112 | 112 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
|
113 | 113 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
|
114 | 114 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
|
115 | 115 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
|
116 | 116 | -- |
|
|
117 | 117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
118 | 118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
119 | 119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
120 | 120 | -- |
|
|
121 | 121 | SIGNAL sample_f0_val : STD_LOGIC; |
|
|
122 | 122 | SIGNAL sample_f1_val : STD_LOGIC; |
|
|
123 | 123 | SIGNAL sample_f2_val : STD_LOGIC; |
|
|
124 | 124 | SIGNAL sample_f3_val : STD_LOGIC; |
|
|
125 | 125 | -- |
|
|
126 | 126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
127 | 127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
128 | 128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
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129 | 129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
130 | 130 | -- |
|
|
131 | 131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
132 | 132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
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133 | 133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
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134 | 134 | |
|
|
135 | 135 | -- SM |
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136 | 136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
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137 | 137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
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138 | 138 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
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139 | 139 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
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140 | 140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
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141 | 141 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
|
142 | 142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
143 | 143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
|
144 | 144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
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145 | 145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
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146 | 146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
|
147 | 147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
|
148 | 148 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
|
149 | 149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
|
150 | 150 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
|
151 | 151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
152 | 152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
153 | 153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
154 | 154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
155 | 155 | |
|
|
156 | 156 | -- WFP |
|
|
157 | 157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
158 | 158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
159 | 159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
160 | 160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
161 | 161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
|
162 | 162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
|
163 | 163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
|
164 | 164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
|
165 | 165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
|
166 | 166 | |
|
|
167 | 167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
|
168 | 168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
|
169 | 169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
|
170 | 170 | SIGNAL enable_f0 : STD_LOGIC; |
|
|
171 | 171 | SIGNAL enable_f1 : STD_LOGIC; |
|
|
172 | 172 | SIGNAL enable_f2 : STD_LOGIC; |
|
|
173 | 173 | SIGNAL enable_f3 : STD_LOGIC; |
|
|
174 | 174 | SIGNAL burst_f0 : STD_LOGIC; |
|
|
175 | 175 | SIGNAL burst_f1 : STD_LOGIC; |
|
|
176 | 176 | SIGNAL burst_f2 : STD_LOGIC; |
|
|
177 | 177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
178 | 178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
179 | 179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
180 | 180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
181 | 181 | |
|
|
182 | 182 | SIGNAL run : STD_LOGIC; |
|
|
183 | 183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
|
184 | 184 | |
|
|
185 | 185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
186 | 186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
187 | 187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
|
|
188 | 188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
|
|
189 | 189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
|
|
190 | 190 | --f1 |
|
|
191 | 191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
192 | 192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
193 | 193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
|
|
194 | 194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
|
|
195 | 195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
|
|
196 | 196 | --f2 |
|
|
197 | 197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
198 | 198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
199 | 199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
|
|
200 | 200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
|
|
201 | 201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
|
|
202 | 202 | --f3 |
|
|
203 | 203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
204 | 204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
205 | 205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
|
|
206 | 206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
|
|
207 | 207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
|
|
208 | 208 | |
|
|
209 | 209 | ----------------------------------------------------------------------------- |
|
|
210 | 210 | -- |
|
|
211 | 211 | ----------------------------------------------------------------------------- |
|
|
212 | 212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
213 | 213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
|
|
214 | 214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
|
|
215 | 215 | --f1 |
|
|
216 | 216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
217 | 217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
|
|
218 | 218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
|
|
219 | 219 | --f2 |
|
|
220 | 220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
221 | 221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
|
|
222 | 222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
|
|
223 | 223 | --f3 |
|
|
224 | 224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
225 | 225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
|
|
226 | 226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
|
|
227 | 227 | |
|
|
228 | 228 | ----------------------------------------------------------------------------- |
|
|
229 | 229 | -- DMA RR |
|
|
230 | 230 | ----------------------------------------------------------------------------- |
|
|
231 | 231 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
|
232 | 232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
233 | 233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
234 | 234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
235 | 235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
236 | 236 | |
|
|
237 | 237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
238 | 238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
239 | 239 | |
|
|
240 | 240 | ----------------------------------------------------------------------------- |
|
|
241 | 241 | -- DMA_REG |
|
|
242 | 242 | ----------------------------------------------------------------------------- |
|
|
243 | 243 | SIGNAL ongoing_reg : STD_LOGIC; |
|
|
244 | 244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
245 | 245 | SIGNAL dma_send_reg : STD_LOGIC; |
|
|
246 | 246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
|
247 | 247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
248 | 248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
249 | 249 | |
|
|
250 | 250 | |
|
|
251 | 251 | ----------------------------------------------------------------------------- |
|
|
252 | 252 | -- DMA |
|
|
253 | 253 | ----------------------------------------------------------------------------- |
|
|
254 | 254 | SIGNAL dma_send : STD_LOGIC; |
|
|
255 | 255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
|
|
256 | 256 | SIGNAL dma_done : STD_LOGIC; |
|
|
257 | 257 | SIGNAL dma_ren : STD_LOGIC; |
|
|
258 | 258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
259 | 259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
260 | 260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
261 | 261 | |
|
|
262 | 262 | ----------------------------------------------------------------------------- |
|
|
263 | 263 | -- DEBUG |
|
|
264 | 264 | ----------------------------------------------------------------------------- |
|
|
265 | 265 | -- |
|
|
266 | 266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
267 | 267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
268 | 268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
269 | 269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
|
270 | 270 | |
|
|
271 | 271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
272 | 272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
273 | 273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
274 | 274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
275 | 275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
276 | 276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
277 | 277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
278 | 278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
279 | 279 | |
|
|
280 | 280 | ----------------------------------------------------------------------------- |
|
|
281 | 281 | -- MS |
|
|
282 | 282 | ----------------------------------------------------------------------------- |
|
|
283 | 283 | |
|
|
284 | 284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
285 | 285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
286 | 286 | SIGNAL data_ms_valid : STD_LOGIC; |
|
|
287 | 287 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
|
|
288 | 288 | SIGNAL data_ms_ren : STD_LOGIC; |
|
|
289 | 289 | SIGNAL data_ms_done : STD_LOGIC; |
|
|
290 | 290 | |
|
|
291 | 291 | SIGNAL run_ms : STD_LOGIC; |
|
|
292 | 292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
|
|
293 | 293 | |
|
|
294 | 294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
295 | 295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
296 | 296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
297 | 297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
298 | 298 | |
|
|
299 | 299 | |
|
|
300 | 300 | BEGIN |
|
|
301 | 301 | |
|
|
302 | 302 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
|
303 | 303 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
|
|
304 | 304 | |
|
|
305 | 305 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
|
|
306 | 306 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
|
307 | 307 | --END GENERATE all_channel; |
|
|
308 | 308 | |
|
|
309 | 309 | ----------------------------------------------------------------------------- |
|
|
310 | 310 | lpp_lfr_filter_1 : lpp_lfr_filter |
|
|
311 | 311 | GENERIC MAP ( |
|
|
312 | 312 | Mem_use => Mem_use) |
|
|
313 | 313 | PORT MAP ( |
|
|
314 | 314 | sample => sample_s, |
|
|
315 | 315 | sample_val => sample_val, |
|
|
316 | 316 | clk => clk, |
|
|
317 | 317 | rstn => rstn, |
|
|
318 | 318 | data_shaping_SP0 => data_shaping_SP0, |
|
|
319 | 319 | data_shaping_SP1 => data_shaping_SP1, |
|
|
320 | 320 | data_shaping_R0 => data_shaping_R0, |
|
|
321 | 321 | data_shaping_R1 => data_shaping_R1, |
|
|
322 | 322 | sample_f0_val => sample_f0_val, |
|
|
323 | 323 | sample_f1_val => sample_f1_val, |
|
|
324 | 324 | sample_f2_val => sample_f2_val, |
|
|
325 | 325 | sample_f3_val => sample_f3_val, |
|
|
326 | 326 | sample_f0_wdata => sample_f0_data, |
|
|
327 | 327 | sample_f1_wdata => sample_f1_data, |
|
|
328 | 328 | sample_f2_wdata => sample_f2_data, |
|
|
329 | 329 | sample_f3_wdata => sample_f3_data); |
|
|
330 | 330 | |
|
|
331 | 331 | ----------------------------------------------------------------------------- |
|
|
332 | 332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
|
333 | 333 | GENERIC MAP ( |
|
|
334 | 334 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
|
335 | 335 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
|
336 | 336 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
|
337 | 337 | delta_vector_size => delta_vector_size, |
|
|
338 | 338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
|
339 | 339 | pindex => pindex, |
|
|
340 | 340 | paddr => paddr, |
|
|
341 | 341 | pmask => pmask, |
|
|
342 | 342 | pirq_ms => pirq_ms, |
|
|
343 | 343 | pirq_wfp => pirq_wfp, |
|
|
344 | 344 | top_lfr_version => top_lfr_version) |
|
|
345 | 345 | PORT MAP ( |
|
|
346 | 346 | HCLK => clk, |
|
|
347 | 347 | HRESETn => rstn, |
|
|
348 | 348 | apbi => apbi, |
|
|
349 | 349 | apbo => apbo, |
|
|
350 | 350 | |
|
|
351 | 351 | run_ms => run_ms, |
|
|
352 | 352 | |
|
|
353 | 353 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
|
354 | 354 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
|
355 | 355 | ready_matrix_f1 => ready_matrix_f1, |
|
|
356 | 356 | ready_matrix_f2 => ready_matrix_f2, |
|
|
357 | 357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
|
358 | 358 | error_bad_component_error => error_bad_component_error, |
|
|
359 | 359 | debug_reg => debug_reg, |
|
|
360 | 360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
|
361 | 361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
|
362 | 362 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
|
363 | 363 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
|
364 | 364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
|
365 | 365 | status_error_bad_component_error => status_error_bad_component_error, |
|
|
366 | 366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
|
367 | 367 | config_active_interruption_onError => config_active_interruption_onError, |
|
|
368 | 368 | |
|
|
369 | 369 | matrix_time_f0_0 => matrix_time_f0_0, |
|
|
370 | 370 | matrix_time_f0_1 => matrix_time_f0_1, |
|
|
371 | 371 | matrix_time_f1 => matrix_time_f1, |
|
|
372 | 372 | matrix_time_f2 => matrix_time_f2, |
|
|
373 | 373 | |
|
|
374 | 374 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
|
375 | 375 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
|
376 | 376 | addr_matrix_f1 => addr_matrix_f1, |
|
|
377 | 377 | addr_matrix_f2 => addr_matrix_f2, |
|
|
378 | 378 | status_full => status_full, |
|
|
379 | 379 | status_full_ack => status_full_ack, |
|
|
380 | 380 | status_full_err => status_full_err, |
|
|
381 | 381 | status_new_err => status_new_err, |
|
|
382 | 382 | data_shaping_BW => data_shaping_BW, |
|
|
383 | 383 | data_shaping_SP0 => data_shaping_SP0, |
|
|
384 | 384 | data_shaping_SP1 => data_shaping_SP1, |
|
|
385 | 385 | data_shaping_R0 => data_shaping_R0, |
|
|
386 | 386 | data_shaping_R1 => data_shaping_R1, |
|
|
387 | 387 | delta_snapshot => delta_snapshot, |
|
|
388 | 388 | delta_f0 => delta_f0, |
|
|
389 | 389 | delta_f0_2 => delta_f0_2, |
|
|
390 | 390 | delta_f1 => delta_f1, |
|
|
391 | 391 | delta_f2 => delta_f2, |
|
|
392 | 392 | nb_data_by_buffer => nb_data_by_buffer, |
|
|
393 | 393 | nb_word_by_buffer => nb_word_by_buffer, |
|
|
394 | 394 | nb_snapshot_param => nb_snapshot_param, |
|
|
395 | 395 | enable_f0 => enable_f0, |
|
|
396 | 396 | enable_f1 => enable_f1, |
|
|
397 | 397 | enable_f2 => enable_f2, |
|
|
398 | 398 | enable_f3 => enable_f3, |
|
|
399 | 399 | burst_f0 => burst_f0, |
|
|
400 | 400 | burst_f1 => burst_f1, |
|
|
401 | 401 | burst_f2 => burst_f2, |
|
|
402 | 402 | run => run, |
|
|
403 | 403 | addr_data_f0 => addr_data_f0, |
|
|
404 | 404 | addr_data_f1 => addr_data_f1, |
|
|
405 | 405 | addr_data_f2 => addr_data_f2, |
|
|
406 | 406 | addr_data_f3 => addr_data_f3, |
|
|
407 | 407 | start_date => start_date, |
|
|
408 | 408 | --------------------------------------------------------------------------- |
|
|
409 | 409 | debug_reg0 => debug_reg0, |
|
|
410 | 410 | debug_reg1 => debug_reg1, |
|
|
411 | 411 | debug_reg2 => debug_reg2, |
|
|
412 | 412 | debug_reg3 => debug_reg3, |
|
|
413 | 413 | debug_reg4 => debug_reg4, |
|
|
414 | 414 | debug_reg5 => debug_reg5, |
|
|
415 | 415 | debug_reg6 => debug_reg6, |
|
|
416 | 416 | debug_reg7 => debug_reg7); |
|
|
417 | 417 | |
|
|
418 | 418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
|
419 | 419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
|
420 | 420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
|
421 | 421 | ----------------------------------------------------------------------------- |
|
|
422 | 422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
|
423 | 423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
|
424 | 424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
|
425 | 425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
|
426 | 426 | |
|
|
427 | 427 | |
|
|
428 | 428 | ----------------------------------------------------------------------------- |
|
|
429 | 429 | lpp_waveform_1 : lpp_waveform |
|
|
430 | 430 | GENERIC MAP ( |
|
|
431 | 431 | tech => inferred, |
|
|
432 | 432 | data_size => 6*16, |
|
|
433 | 433 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
|
434 | 434 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
|
435 | 435 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
|
436 | 436 | delta_vector_size => delta_vector_size, |
|
|
437 | 437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
|
438 | 438 | ) |
|
|
439 | 439 | PORT MAP ( |
|
|
440 | 440 | clk => clk, |
|
|
441 | 441 | rstn => rstn, |
|
|
442 | 442 | |
|
|
443 | 443 | reg_run => run, |
|
|
444 | 444 | reg_start_date => start_date, |
|
|
445 | 445 | reg_delta_snapshot => delta_snapshot, |
|
|
446 | 446 | reg_delta_f0 => delta_f0, |
|
|
447 | 447 | reg_delta_f0_2 => delta_f0_2, |
|
|
448 | 448 | reg_delta_f1 => delta_f1, |
|
|
449 | 449 | reg_delta_f2 => delta_f2, |
|
|
450 | 450 | |
|
|
451 | 451 | enable_f0 => enable_f0, |
|
|
452 | 452 | enable_f1 => enable_f1, |
|
|
453 | 453 | enable_f2 => enable_f2, |
|
|
454 | 454 | enable_f3 => enable_f3, |
|
|
455 | 455 | burst_f0 => burst_f0, |
|
|
456 | 456 | burst_f1 => burst_f1, |
|
|
457 | 457 | burst_f2 => burst_f2, |
|
|
458 | 458 | |
|
|
459 | 459 | nb_data_by_buffer => nb_data_by_buffer, |
|
|
460 | 460 | nb_word_by_buffer => nb_word_by_buffer, |
|
|
461 | 461 | nb_snapshot_param => nb_snapshot_param, |
|
|
462 | 462 | status_full => status_full, |
|
|
463 | 463 | status_full_ack => status_full_ack, |
|
|
464 | 464 | status_full_err => status_full_err, |
|
|
465 | 465 | status_new_err => status_new_err, |
|
|
466 | 466 | |
|
|
467 | 467 | coarse_time => coarse_time, |
|
|
468 | 468 | fine_time => fine_time, |
|
|
469 | 469 | |
|
|
470 | 470 | --f0 |
|
|
471 | 471 | addr_data_f0 => addr_data_f0, |
|
|
472 | 472 | data_f0_in_valid => sample_f0_val, |
|
|
473 | 473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
|
474 | 474 | --f1 |
|
|
475 | 475 | addr_data_f1 => addr_data_f1, |
|
|
476 | 476 | data_f1_in_valid => sample_f1_val, |
|
|
477 | 477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
|
478 | 478 | --f2 |
|
|
479 | 479 | addr_data_f2 => addr_data_f2, |
|
|
480 | 480 | data_f2_in_valid => sample_f2_val, |
|
|
481 | 481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
|
482 | 482 | --f3 |
|
|
483 | 483 | addr_data_f3 => addr_data_f3, |
|
|
484 | 484 | data_f3_in_valid => sample_f3_val, |
|
|
485 | 485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
|
486 | 486 | -- OUTPUT -- DMA interface |
|
|
487 | 487 | --f0 |
|
|
488 | 488 | data_f0_addr_out => data_f0_addr_out_s, |
|
|
489 | 489 | data_f0_data_out => data_f0_data_out, |
|
|
490 | 490 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
|
491 | 491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
|
492 | 492 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
|
493 | 493 | --f1 |
|
|
494 | 494 | data_f1_addr_out => data_f1_addr_out_s, |
|
|
495 | 495 | data_f1_data_out => data_f1_data_out, |
|
|
496 | 496 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
|
497 | 497 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
|
498 | 498 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
|
499 | 499 | --f2 |
|
|
500 | 500 | data_f2_addr_out => data_f2_addr_out_s, |
|
|
501 | 501 | data_f2_data_out => data_f2_data_out, |
|
|
502 | 502 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
|
503 | 503 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
|
504 | 504 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
|
505 | 505 | --f3 |
|
|
506 | 506 | data_f3_addr_out => data_f3_addr_out_s, |
|
|
507 | 507 | data_f3_data_out => data_f3_data_out, |
|
|
508 | 508 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
|
509 | 509 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
|
510 | 510 | data_f3_data_out_ren => data_f3_data_out_ren , |
|
|
511 | 511 | |
|
|
512 | 512 | ------------------------------------------------------------------------- |
|
|
513 | 513 | observation_reg => OPEN |
|
|
514 | 514 | |
|
|
515 | 515 | ); |
|
|
516 | 516 | |
|
|
517 | 517 | |
|
|
518 | 518 | ----------------------------------------------------------------------------- |
|
|
519 | 519 | -- TEMP |
|
|
520 | 520 | ----------------------------------------------------------------------------- |
|
|
521 | 521 | |
|
|
522 | 522 | PROCESS (clk, rstn) |
|
|
523 | 523 | BEGIN -- PROCESS |
|
|
524 | 524 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|
525 | 525 | data_f0_data_out_valid <= '0'; |
|
|
526 | 526 | data_f0_data_out_valid_burst <= '0'; |
|
|
527 | 527 | data_f1_data_out_valid <= '0'; |
|
|
528 | 528 | data_f1_data_out_valid_burst <= '0'; |
|
|
529 | 529 | data_f2_data_out_valid <= '0'; |
|
|
530 | 530 | data_f2_data_out_valid_burst <= '0'; |
|
|
531 | 531 | data_f3_data_out_valid <= '0'; |
|
|
532 | 532 | data_f3_data_out_valid_burst <= '0'; |
|
|
533 | 533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|
534 | 534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
|
535 | 535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
|
536 | 536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
|
537 | 537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
|
538 | 538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
|
539 | 539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
|
540 | 540 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
|
541 | 541 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
|
542 | 542 | END IF; |
|
|
543 | 543 | END PROCESS; |
|
|
544 | 544 | |
|
|
545 | 545 | data_f0_addr_out <= data_f0_addr_out_s; |
|
|
546 | 546 | data_f1_addr_out <= data_f1_addr_out_s; |
|
|
547 | 547 | data_f2_addr_out <= data_f2_addr_out_s; |
|
|
548 | 548 | data_f3_addr_out <= data_f3_addr_out_s; |
|
|
549 | 549 | |
|
|
550 | 550 | ----------------------------------------------------------------------------- |
|
|
551 | 551 | -- RoundRobin Selection For DMA |
|
|
552 | 552 | ----------------------------------------------------------------------------- |
|
|
553 | 553 | |
|
|
554 | 554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
|
555 | 555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
|
556 | 556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
|
557 | 557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
|
558 | 558 | |
|
|
559 | 559 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
|
560 | 560 | PORT MAP ( |
|
|
561 | 561 | clk => clk, |
|
|
562 | 562 | rstn => rstn, |
|
|
563 | 563 | in_valid => dma_rr_valid, |
|
|
564 | 564 | out_grant => dma_rr_grant_s); |
|
|
565 | 565 | |
|
|
566 | 566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
|
567 | 567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
|
568 | 568 | dma_rr_valid_ms(2) <= '0'; |
|
|
569 | 569 | dma_rr_valid_ms(3) <= '0'; |
|
|
570 | 570 | |
|
|
571 | 571 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
|
572 | 572 | PORT MAP ( |
|
|
573 | 573 | clk => clk, |
|
|
574 | 574 | rstn => rstn, |
|
|
575 | 575 | in_valid => dma_rr_valid_ms, |
|
|
576 | 576 | out_grant => dma_rr_grant_ms); |
|
|
577 | 577 | |
|
|
578 | 578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
|
579 | 579 | |
|
|
580 | 580 | |
|
|
581 | 581 | ----------------------------------------------------------------------------- |
|
|
582 | 582 | -- in : dma_rr_grant |
|
|
583 | 583 | -- send |
|
|
584 | 584 | -- out : dma_sel |
|
|
585 | 585 | -- dma_valid_burst |
|
|
586 | 586 | -- dma_sel_valid |
|
|
587 | 587 | ----------------------------------------------------------------------------- |
|
|
588 | 588 | PROCESS (clk, rstn) |
|
|
589 | 589 | BEGIN -- PROCESS |
|
|
590 | 590 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|
591 | 591 | dma_sel <= (OTHERS => '0'); |
|
|
592 | 592 | dma_send <= '0'; |
|
|
593 | 593 | dma_valid_burst <= '0'; |
|
|
594 | 594 | data_ms_done <= '0'; |
|
|
595 | 595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|
596 | 596 | IF run = '1' THEN |
|
|
597 | 597 | data_ms_done <= '0'; |
|
|
598 | 598 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
|
599 | 599 | dma_sel <= dma_rr_grant; |
|
|
600 | 600 | IF dma_rr_grant(0) = '1' THEN |
|
|
601 | 601 | dma_send <= '1'; |
|
|
602 | 602 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
|
603 | 603 | dma_sel_valid <= data_f0_data_out_valid; |
|
|
604 | 604 | ELSIF dma_rr_grant(1) = '1' THEN |
|
|
605 | 605 | dma_send <= '1'; |
|
|
606 | 606 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
|
607 | 607 | dma_sel_valid <= data_f1_data_out_valid; |
|
|
608 | 608 | ELSIF dma_rr_grant(2) = '1' THEN |
|
|
609 | 609 | dma_send <= '1'; |
|
|
610 | 610 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
|
611 | 611 | dma_sel_valid <= data_f2_data_out_valid; |
|
|
612 | 612 | ELSIF dma_rr_grant(3) = '1' THEN |
|
|
613 | 613 | dma_send <= '1'; |
|
|
614 | 614 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
|
615 | 615 | dma_sel_valid <= data_f3_data_out_valid; |
|
|
616 | 616 | ELSIF dma_rr_grant(4) = '1' THEN |
|
|
617 | 617 | dma_send <= '1'; |
|
|
618 | 618 | dma_valid_burst <= data_ms_valid_burst; |
|
|
619 | 619 | dma_sel_valid <= data_ms_valid; |
|
|
620 | 620 | END IF; |
|
|
621 | 621 | |
|
|
622 | 622 | IF dma_sel(4) = '1' THEN |
|
|
623 | 623 | data_ms_done <= '1'; |
|
|
624 | 624 | END IF; |
|
|
625 | 625 | ELSE |
|
|
626 | 626 | dma_sel <= dma_sel; |
|
|
627 | 627 | dma_send <= '0'; |
|
|
628 | 628 | END IF; |
|
|
629 | 629 | ELSE |
|
|
630 | 630 | data_ms_done <= '0'; |
|
|
631 | 631 | dma_sel <= (OTHERS => '0'); |
|
|
632 | 632 | dma_send <= '0'; |
|
|
633 | 633 | dma_valid_burst <= '0'; |
|
|
634 | 634 | END IF; |
|
|
635 | 635 | END IF; |
|
|
636 | 636 | END PROCESS; |
|
|
637 | 637 | |
|
|
638 | 638 | |
|
|
639 | 639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
|
640 | 640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
|
641 | 641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
|
642 | 642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
|
643 | 643 | data_ms_addr; |
|
|
644 | 644 | |
|
|
645 | 645 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
|
646 | 646 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
|
647 | 647 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
|
648 | 648 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
|
649 | 649 | data_ms_data; |
|
|
650 | 650 | |
|
|
651 | 651 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
|
652 | 652 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
|
653 | 653 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
|
654 | 654 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
|
655 | 655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
|
656 | 656 | |
|
|
657 | 657 | dma_data_2 <= dma_data; |
|
|
658 | 658 | |
|
|
659 | 659 | |
|
|
660 | 660 | |
|
|
661 | 661 | |
|
|
662 | 662 | |
|
|
663 | 663 | ----------------------------------------------------------------------------- |
|
|
664 | 664 | -- DEBUG -- DMA IN |
|
|
665 | 665 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
|
666 | 666 | --debug_f0_data_dma_in <= dma_data; |
|
|
667 | 667 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
|
668 | 668 | --debug_f1_data_dma_in <= dma_data; |
|
|
669 | 669 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
|
670 | 670 | --debug_f2_data_dma_in <= dma_data; |
|
|
671 | 671 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
|
672 | 672 | --debug_f3_data_dma_in <= dma_data; |
|
|
673 | 673 | ----------------------------------------------------------------------------- |
|
|
674 | 674 | |
|
|
675 | 675 | ----------------------------------------------------------------------------- |
|
|
676 | 676 | -- DMA |
|
|
677 | 677 | ----------------------------------------------------------------------------- |
|
|
678 | 678 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
|
679 | 679 | GENERIC MAP ( |
|
|
680 | 680 | tech => inferred, |
|
|
681 | 681 | hindex => hindex) |
|
|
682 | 682 | PORT MAP ( |
|
|
683 | 683 | HCLK => clk, |
|
|
684 | 684 | HRESETn => rstn, |
|
|
685 | 685 | run => run, |
|
|
686 | 686 | AHB_Master_In => ahbi, |
|
|
687 | 687 | AHB_Master_Out => ahbo, |
|
|
688 | 688 | |
|
|
689 | 689 | send => dma_send, |
|
|
690 | 690 | valid_burst => dma_valid_burst, |
|
|
691 | 691 | done => dma_done, |
|
|
692 | 692 | ren => dma_ren, |
|
|
693 | 693 | address => dma_address, |
|
|
694 | 694 | data => dma_data_2); |
|
|
695 | 695 | |
|
|
696 | 696 | ----------------------------------------------------------------------------- |
|
|
697 | 697 | -- Matrix Spectral |
|
|
698 | 698 | ----------------------------------------------------------------------------- |
|
|
699 | 699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
|
700 | 700 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
|
701 | 701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
|
702 | 702 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
|
703 | 703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
|
704 | 704 | NOT(sample_f3_val) & NOT(sample_f3_val); |
|
|
705 | 705 | |
|
|
706 | 706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
|
707 | 707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
|
708 | 708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
|
709 | 709 | |
|
|
710 | 710 | ------------------------------------------------------------------------------- |
|
|
711 | 711 | |
|
|
712 | 712 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
|
713 | 713 | |
|
|
714 | 714 | ----------------------------------------------------------------------------- |
|
|
715 | 715 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
|
716 | 716 | GENERIC MAP ( |
|
|
717 | 717 | Mem_use => Mem_use) |
|
|
718 | 718 | PORT MAP ( |
|
|
719 | 719 | clk => clk, |
|
|
720 | 720 | rstn => ms_softandhard_rstn, --rstn, |
|
|
721 | 721 | |
|
|
722 | 722 | coarse_time => coarse_time, |
|
|
723 | 723 | fine_time => fine_time, |
|
|
724 | 724 | |
|
|
725 | 725 | sample_f0_wen => sample_f0_wen, |
|
|
726 | 726 | sample_f0_wdata => sample_f0_wdata, |
|
|
727 | 727 | sample_f1_wen => sample_f1_wen, |
|
|
728 | 728 | sample_f1_wdata => sample_f1_wdata, |
|
|
729 |
sample_f |
|
|
|
730 |
sample_f |
|
|
|
729 | sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data | |
|
|
730 | sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data | |
|
|
731 | 731 | |
|
|
732 | 732 | dma_addr => data_ms_addr, -- |
|
|
733 | 733 | dma_data => data_ms_data, -- |
|
|
734 | 734 | dma_valid => data_ms_valid, -- |
|
|
735 | 735 | dma_valid_burst => data_ms_valid_burst, -- |
|
|
736 | 736 | dma_ren => data_ms_ren, -- |
|
|
737 | 737 | dma_done => data_ms_done, -- |
|
|
738 | 738 | |
|
|
739 |
ready_matrix_f0 |
|
|
|
740 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
|
739 | ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename | |
|
|
741 | 740 | ready_matrix_f1 => ready_matrix_f1, |
|
|
742 | 741 | ready_matrix_f2 => ready_matrix_f2, |
|
|
743 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
|
742 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
|
744 | 743 | error_bad_component_error => error_bad_component_error, |
|
|
745 | debug_reg => observation_reg, --debug_reg, | |
|
|
746 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
|
747 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
|
744 | error_buffer_full => OPEN, -- TODO | |
|
|
745 | error_input_fifo_write => OPEN, -- TODO | |
|
|
746 | debug_reg => observation_reg, | |
|
|
747 | status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename | |
|
|
748 | 748 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
|
749 | 749 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
|
750 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
|
751 | status_error_bad_component_error => status_error_bad_component_error, | |
|
|
750 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
|
|
751 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
|
|
752 | 752 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
|
753 | 753 | config_active_interruption_onError => config_active_interruption_onError, |
|
|
754 |
addr_matrix_f0 |
|
|
|
755 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
|
754 | addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename | |
|
|
756 | 755 | addr_matrix_f1 => addr_matrix_f1, |
|
|
757 | 756 | addr_matrix_f2 => addr_matrix_f2, |
|
|
758 | 757 | |
|
|
759 |
matrix_time_f0 |
|
|
|
760 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
|
758 | matrix_time_f0 => matrix_time_f0_0,-- TODO rename | |
|
|
761 | 759 | matrix_time_f1 => matrix_time_f1, |
|
|
762 | 760 | matrix_time_f2 => matrix_time_f2); |
|
|
763 | 761 | |
|
|
764 | 762 | END beh; |
| @@ -1,1078 +1,1067 | |||
|
|
1 | 1 | LIBRARY ieee; |
|
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
|
3 | 3 | |
|
|
4 | 4 | |
|
|
5 | 5 | LIBRARY lpp; |
|
|
6 | 6 | USE lpp.lpp_memory.ALL; |
|
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
|
8 | 8 | USE lpp.spectral_matrix_package.ALL; |
|
|
9 | 9 | USE lpp.lpp_dma_pkg.ALL; |
|
|
10 | 10 | USE lpp.lpp_Header.ALL; |
|
|
11 | 11 | USE lpp.lpp_matrix.ALL; |
|
|
12 | 12 | USE lpp.lpp_matrix.ALL; |
|
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
|
14 | 14 | USE lpp.lpp_fft.ALL; |
|
|
15 | 15 | USE lpp.fft_components.ALL; |
|
|
16 | 16 | |
|
|
17 | 17 | ENTITY lpp_lfr_ms IS |
|
|
18 | 18 | GENERIC ( |
|
|
19 | 19 | Mem_use : INTEGER := use_RAM |
|
|
20 | 20 | ); |
|
|
21 | 21 | PORT ( |
|
|
22 | 22 | clk : IN STD_LOGIC; |
|
|
23 | 23 | rstn : IN STD_LOGIC; |
|
|
24 | 24 | |
|
|
25 | 25 | --------------------------------------------------------------------------- |
|
|
26 | 26 | -- DATA INPUT |
|
|
27 | 27 | --------------------------------------------------------------------------- |
|
|
28 | 28 | -- TIME |
|
|
29 | 29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
|
30 | 30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
|
31 | 31 | -- |
|
|
32 | 32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
33 | 33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
34 | 34 | -- |
|
|
35 | 35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
36 | 36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
37 | 37 | -- |
|
|
38 | 38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
39 | 39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
40 | 40 | |
|
|
41 | 41 | --------------------------------------------------------------------------- |
|
|
42 | 42 | -- DMA |
|
|
43 | 43 | --------------------------------------------------------------------------- |
|
|
44 | 44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
45 | 45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
46 | 46 | dma_valid : OUT STD_LOGIC; |
|
|
47 | 47 | dma_valid_burst : OUT STD_LOGIC; |
|
|
48 | 48 | dma_ren : IN STD_LOGIC; |
|
|
49 | 49 | dma_done : IN STD_LOGIC; |
|
|
50 | 50 | |
|
|
51 | 51 | -- Reg out |
|
|
52 | 52 | ready_matrix_f0 : OUT STD_LOGIC; |
|
|
53 | 53 | -- ready_matrix_f0 : OUT STD_LOGIC; |
|
|
54 | 54 | ready_matrix_f1 : OUT STD_LOGIC; |
|
|
55 | 55 | ready_matrix_f2 : OUT STD_LOGIC; |
|
|
56 | 56 | --error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
|
57 | 57 | error_bad_component_error : OUT STD_LOGIC; |
|
|
58 | 58 | error_buffer_full : OUT STD_LOGIC; |
|
|
59 | 59 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
|
60 | 60 | |
|
|
61 | 61 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
62 | 62 | |
|
|
63 | 63 | -- Reg In |
|
|
64 | 64 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
|
65 | 65 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
|
66 | 66 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
|
67 | 67 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
|
68 | 68 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|
69 | 69 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
|
70 | 70 | -- status_error_buffer_full : IN STD_LOGIC; |
|
|
71 | 71 | |
|
|
72 | 72 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
|
73 | 73 | config_active_interruption_onError : IN STD_LOGIC; |
|
|
74 | 74 | -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
75 | 75 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
76 | 76 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
77 | 77 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
78 | 78 | |
|
|
79 | 79 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
80 | 80 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
81 | 81 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
82 | 82 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
|
83 | 83 | |
|
|
84 | 84 | ); |
|
|
85 | 85 | END; |
|
|
86 | 86 | |
|
|
87 | 87 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
|
88 | 88 | |
|
|
89 | 89 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
90 | 90 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
91 | 91 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
92 | 92 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
93 | 93 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
94 | 94 | |
|
|
95 | 95 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
96 | 96 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
97 | 97 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
98 | 98 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
99 | 99 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
100 | 100 | |
|
|
101 | 101 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
102 | 102 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
103 | 103 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
104 | 104 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
105 | 105 | |
|
|
106 | 106 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
107 | 107 | |
|
|
108 | 108 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
109 | 109 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
110 | 110 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
111 | 111 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
112 | 112 | |
|
|
113 | 113 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
|
114 | 114 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
|
115 | 115 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
|
116 | 116 | |
|
|
117 | 117 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
|
118 | 118 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
|
119 | 119 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
|
120 | 120 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
|
121 | 121 | |
|
|
122 | 122 | ----------------------------------------------------------------------------- |
|
|
123 | 123 | -- FSM / SWITCH SELECT CHANNEL |
|
|
124 | 124 | ----------------------------------------------------------------------------- |
|
|
125 | 125 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
|
126 | 126 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
|
127 | 127 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
|
128 | 128 | |
|
|
129 | 129 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
130 | 130 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
131 | 131 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
132 | 132 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
133 | 133 | |
|
|
134 | 134 | ----------------------------------------------------------------------------- |
|
|
135 | 135 | -- FSM LOAD FFT |
|
|
136 | 136 | ----------------------------------------------------------------------------- |
|
|
137 | 137 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
|
138 | 138 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
|
139 | 139 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
|
140 | 140 | |
|
|
141 | 141 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
142 | 142 | SIGNAL sample_load : STD_LOGIC; |
|
|
143 | 143 | SIGNAL sample_valid : STD_LOGIC; |
|
|
144 | 144 | SIGNAL sample_valid_r : STD_LOGIC; |
|
|
145 | 145 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
146 | 146 | |
|
|
147 | 147 | |
|
|
148 | 148 | ----------------------------------------------------------------------------- |
|
|
149 | 149 | -- FFT |
|
|
150 | 150 | ----------------------------------------------------------------------------- |
|
|
151 | 151 | SIGNAL fft_read : STD_LOGIC; |
|
|
152 | 152 | SIGNAL fft_pong : STD_LOGIC; |
|
|
153 | 153 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
154 | 154 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
|
155 | 155 | SIGNAL fft_data_valid : STD_LOGIC; |
|
|
156 | 156 | SIGNAL fft_ready : STD_LOGIC; |
|
|
157 | 157 | ----------------------------------------------------------------------------- |
|
|
158 | SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
158 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
159 | 159 | ----------------------------------------------------------------------------- |
|
|
160 | 160 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
|
161 | 161 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
|
162 | 162 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
163 | 163 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
|
164 | 164 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
|
165 | 165 | SIGNAL current_fifo_full : STD_LOGIC; |
|
|
166 | 166 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
167 | 167 | |
|
|
168 | 168 | ----------------------------------------------------------------------------- |
|
|
169 | 169 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
170 | 170 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
171 | 171 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
172 | 172 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
173 | 173 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
|
174 | 174 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
|
175 | 175 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
176 | 176 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
177 | 177 | ----------------------------------------------------------------------------- |
|
|
178 | 178 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
|
179 | 179 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
180 | 180 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
181 | 181 | |
|
|
182 | 182 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
|
183 | 183 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
|
184 | 184 | SIGNAL SM_correlation_done : STD_LOGIC; |
|
|
185 | 185 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
|
186 | 186 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
|
187 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; | |
|
|
187 | 188 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
|
188 | 189 | |
|
|
189 |
|
|
|
|
190 | SIGNAL temp_auto : STD_LOGIC; | |
|
|
190 | -- SIGNAL temp_ongoing : STD_LOGIC; | |
|
|
191 | -- SIGNAL temp_auto : STD_LOGIC; | |
|
|
191 | 192 | |
|
|
192 | 193 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; |
|
|
193 | 194 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
194 | 195 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; |
|
|
195 | 196 | |
|
|
196 | 197 | SIGNAL current_matrix_write : STD_LOGIC; |
|
|
197 | 198 | SIGNAL current_matrix_wait_empty : STD_LOGIC; |
|
|
198 | 199 | |
|
|
199 | 200 | --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
200 | 201 | |
|
|
201 | 202 | ----------------------------------------------------------------------------- |
|
|
202 | 203 | SIGNAL fifo_0_ready : STD_LOGIC; |
|
|
203 | 204 | SIGNAL fifo_1_ready : STD_LOGIC; |
|
|
204 | 205 | SIGNAL fifo_ongoing : STD_LOGIC; |
|
|
205 | 206 | |
|
|
206 | 207 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
|
207 | 208 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
|
208 | 209 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
209 | 210 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
|
210 | 211 | |
|
|
211 | 212 | ----------------------------------------------------------------------------- |
|
|
212 | SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
|
213 | SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
214 | SIGNAL HEAD_SM_Wen : STD_LOGIC; | |
|
|
215 | SIGNAL HEAD_Valid : STD_LOGIC; | |
|
|
216 | SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
217 | SIGNAL HEAD_Empty : STD_LOGIC; | |
|
|
218 | SIGNAL HEAD_Read : STD_LOGIC; | |
|
|
213 | -- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
|
214 | --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
215 | --SIGNAL HEAD_SM_Wen : STD_LOGIC; | |
|
|
216 | --SIGNAL HEAD_Valid : STD_LOGIC; | |
|
|
217 | --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
218 | --SIGNAL HEAD_Empty : STD_LOGIC; | |
|
|
219 | --SIGNAL HEAD_Read : STD_LOGIC; | |
|
|
219 | 220 | ----------------------------------------------------------------------------- |
|
|
220 | SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
221 | -- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
221 | 222 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
222 | 223 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
223 | 224 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
|
224 | 225 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
|
225 | 226 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
226 | 227 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
227 | 228 | ----------------------------------------------------------------------------- |
|
|
228 | SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
229 | SIGNAL DMA_Header_Val : STD_LOGIC; | |
|
|
230 | SIGNAL DMA_Header_Ack : STD_LOGIC; | |
|
|
229 | --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
230 | --SIGNAL DMA_Header_Val : STD_LOGIC; | |
|
|
231 | --SIGNAL DMA_Header_Ack : STD_LOGIC; | |
|
|
231 | 232 | |
|
|
232 | 233 | ----------------------------------------------------------------------------- |
|
|
233 | 234 | -- TIME REG & INFOs |
|
|
234 | 235 | ----------------------------------------------------------------------------- |
|
|
235 | 236 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
236 | 237 | |
|
|
237 | 238 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
238 | 239 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
239 | 240 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
240 | 241 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
241 | 242 | |
|
|
242 | 243 | SIGNAL time_update_f0_A : STD_LOGIC; |
|
|
243 | 244 | SIGNAL time_update_f0_B : STD_LOGIC; |
|
|
244 | 245 | SIGNAL time_update_f1 : STD_LOGIC; |
|
|
245 | 246 | SIGNAL time_update_f2 : STD_LOGIC; |
|
|
246 | 247 | -- |
|
|
247 | 248 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
|
248 | 249 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
|
249 | 250 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
|
250 | 251 | |
|
|
251 | 252 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
|
252 | 253 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
|
253 | SIGNAL status_component_fifo_0_new : STD_LOGIC; | |
|
|
254 | SIGNAL status_component_fifo_1_new : STD_LOGIC; | |
|
|
254 | -- SIGNAL status_component_fifo_0_new : STD_LOGIC; | |
|
|
255 | -- SIGNAL status_component_fifo_1_new : STD_LOGIC; | |
|
|
255 | 256 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
|
256 | 257 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
|
257 | 258 | |
|
|
258 | 259 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
259 | 260 | ----------------------------------------------------------------------------- |
|
|
260 | 261 | |
|
|
261 | 262 | BEGIN |
|
|
262 | 263 | |
|
|
263 | 264 | |
|
|
264 | 265 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
|
|
265 | 266 | |
|
|
266 | 267 | |
|
|
267 | 268 | switch_f0_inst : spectral_matrix_switch_f0 |
|
|
268 | 269 | PORT MAP ( |
|
|
269 | 270 | clk => clk, |
|
|
270 | 271 | rstn => rstn, |
|
|
271 | 272 | |
|
|
272 | 273 | sample_wen => sample_f0_wen, |
|
|
273 | 274 | |
|
|
274 | 275 | fifo_A_empty => sample_f0_A_empty, |
|
|
275 | 276 | fifo_A_full => sample_f0_A_full, |
|
|
276 | 277 | fifo_A_wen => sample_f0_A_wen, |
|
|
277 | 278 | |
|
|
278 | 279 | fifo_B_empty => sample_f0_B_empty, |
|
|
279 | 280 | fifo_B_full => sample_f0_B_full, |
|
|
280 | 281 | fifo_B_wen => sample_f0_B_wen, |
|
|
281 | 282 | |
|
|
282 | 283 | error_wen => error_wen_f0); -- TODO |
|
|
283 | 284 | |
|
|
284 | 285 | ----------------------------------------------------------------------------- |
|
|
285 | 286 | -- FIFO IN |
|
|
286 | 287 | ----------------------------------------------------------------------------- |
|
|
287 | 288 | lppFIFOxN_f0_a : lppFIFOxN |
|
|
288 | 289 | GENERIC MAP ( |
|
|
289 | 290 | tech => 0, |
|
|
290 | 291 | Mem_use => Mem_use, |
|
|
291 | 292 | Data_sz => 16, |
|
|
292 | 293 | Addr_sz => 8, |
|
|
293 | 294 | FifoCnt => 5) |
|
|
294 | 295 | PORT MAP ( |
|
|
295 | 296 | clk => clk, |
|
|
296 | 297 | rstn => rstn, |
|
|
297 | 298 | |
|
|
298 | 299 | ReUse => (OTHERS => '0'), |
|
|
299 | 300 | |
|
|
300 | 301 | wen => sample_f0_A_wen, |
|
|
301 | 302 | wdata => sample_f0_wdata, |
|
|
302 | 303 | |
|
|
303 | 304 | ren => sample_f0_A_ren, |
|
|
304 | 305 | rdata => sample_f0_A_rdata, |
|
|
305 | 306 | |
|
|
306 | 307 | empty => sample_f0_A_empty, |
|
|
307 | 308 | full => sample_f0_A_full, |
|
|
308 | 309 | almost_full => OPEN); |
|
|
309 | 310 | |
|
|
310 | 311 | lppFIFOxN_f0_b : lppFIFOxN |
|
|
311 | 312 | GENERIC MAP ( |
|
|
312 | 313 | tech => 0, |
|
|
313 | 314 | Mem_use => Mem_use, |
|
|
314 | 315 | Data_sz => 16, |
|
|
315 | 316 | Addr_sz => 8, |
|
|
316 | 317 | FifoCnt => 5) |
|
|
317 | 318 | PORT MAP ( |
|
|
318 | 319 | clk => clk, |
|
|
319 | 320 | rstn => rstn, |
|
|
320 | 321 | |
|
|
321 | 322 | ReUse => (OTHERS => '0'), |
|
|
322 | 323 | |
|
|
323 | 324 | wen => sample_f0_B_wen, |
|
|
324 | 325 | wdata => sample_f0_wdata, |
|
|
325 | 326 | ren => sample_f0_B_ren, |
|
|
326 | 327 | rdata => sample_f0_B_rdata, |
|
|
327 | 328 | empty => sample_f0_B_empty, |
|
|
328 | 329 | full => sample_f0_B_full, |
|
|
329 | 330 | almost_full => OPEN); |
|
|
330 | 331 | |
|
|
331 | 332 | lppFIFOxN_f1 : lppFIFOxN |
|
|
332 | 333 | GENERIC MAP ( |
|
|
333 | 334 | tech => 0, |
|
|
334 | 335 | Mem_use => Mem_use, |
|
|
335 | 336 | Data_sz => 16, |
|
|
336 | 337 | Addr_sz => 8, |
|
|
337 | 338 | FifoCnt => 5) |
|
|
338 | 339 | PORT MAP ( |
|
|
339 | 340 | clk => clk, |
|
|
340 | 341 | rstn => rstn, |
|
|
341 | 342 | |
|
|
342 | 343 | ReUse => (OTHERS => '0'), |
|
|
343 | 344 | |
|
|
344 | 345 | wen => sample_f1_wen, |
|
|
345 | 346 | wdata => sample_f1_wdata, |
|
|
346 | 347 | ren => sample_f1_ren, |
|
|
347 | 348 | rdata => sample_f1_rdata, |
|
|
348 | 349 | empty => sample_f1_empty, |
|
|
349 | 350 | full => sample_f1_full, |
|
|
350 | 351 | almost_full => sample_f1_almost_full); |
|
|
351 | 352 | |
|
|
352 | 353 | |
|
|
353 | 354 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
|
354 | 355 | |
|
|
355 | 356 | PROCESS (clk, rstn) |
|
|
356 | 357 | BEGIN -- PROCESS |
|
|
357 | 358 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|
358 | 359 | one_sample_f1_full <= '0'; |
|
|
359 | 360 | error_wen_f1 <= '0'; |
|
|
360 | 361 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|
361 | 362 | IF sample_f1_full = "00000" THEN |
|
|
362 | 363 | one_sample_f1_full <= '0'; |
|
|
363 | 364 | ELSE |
|
|
364 | 365 | one_sample_f1_full <= '1'; |
|
|
365 | 366 | END IF; |
|
|
366 | 367 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
|
367 | 368 | END IF; |
|
|
368 | 369 | END PROCESS; |
|
|
369 | 370 | |
|
|
370 | 371 | |
|
|
371 | 372 | lppFIFOxN_f2 : lppFIFOxN |
|
|
372 | 373 | GENERIC MAP ( |
|
|
373 | 374 | tech => 0, |
|
|
374 | 375 | Mem_use => Mem_use, |
|
|
375 | 376 | Data_sz => 16, |
|
|
376 | 377 | Addr_sz => 8, |
|
|
377 | 378 | FifoCnt => 5) |
|
|
378 | 379 | PORT MAP ( |
|
|
379 | 380 | clk => clk, |
|
|
380 | 381 | rstn => rstn, |
|
|
381 | 382 | |
|
|
382 | 383 | ReUse => (OTHERS => '0'), |
|
|
383 | 384 | |
|
|
384 | 385 | wen => sample_f2_wen, |
|
|
385 | 386 | wdata => sample_f2_wdata, |
|
|
386 | 387 | ren => sample_f2_ren, |
|
|
387 | 388 | rdata => sample_f2_rdata, |
|
|
388 | 389 | empty => sample_f2_empty, |
|
|
389 | 390 | full => sample_f2_full, |
|
|
390 | 391 | almost_full => OPEN); |
|
|
391 | 392 | |
|
|
392 | 393 | |
|
|
393 | 394 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
|
394 | 395 | |
|
|
395 | 396 | PROCESS (clk, rstn) |
|
|
396 | 397 | BEGIN -- PROCESS |
|
|
397 | 398 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|
398 | 399 | one_sample_f2_full <= '0'; |
|
|
399 | 400 | error_wen_f2 <= '0'; |
|
|
400 | 401 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
|
401 | 402 | IF sample_f2_full = "00000" THEN |
|
|
402 | 403 | one_sample_f2_full <= '0'; |
|
|
403 | 404 | ELSE |
|
|
404 | 405 | one_sample_f2_full <= '1'; |
|
|
405 | 406 | END IF; |
|
|
406 | 407 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
|
407 | 408 | END IF; |
|
|
408 | 409 | END PROCESS; |
|
|
409 | 410 | |
|
|
410 | 411 | ----------------------------------------------------------------------------- |
|
|
411 | 412 | -- FSM SELECT CHANNEL |
|
|
412 | 413 | ----------------------------------------------------------------------------- |
|
|
413 | 414 | PROCESS (clk, rstn) |
|
|
414 | 415 | BEGIN |
|
|
415 | 416 | IF rstn = '0' THEN |
|
|
416 | 417 | state_fsm_select_channel <= IDLE; |
|
|
417 | 418 | ELSIF clk'EVENT AND clk = '1' THEN |
|
|
418 | 419 | CASE state_fsm_select_channel IS |
|
|
419 | 420 | WHEN IDLE => |
|
|
420 | 421 | IF sample_f1_full = "11111" THEN |
|
|
421 | 422 | state_fsm_select_channel <= SWITCH_F1; |
|
|
422 | 423 | ELSIF sample_f1_almost_full = "00000" THEN |
|
|
423 | 424 | IF sample_f0_A_full = "11111" THEN |
|
|
424 | 425 | state_fsm_select_channel <= SWITCH_F0_A; |
|
|
425 | 426 | ELSIF sample_f0_B_full = "11111" THEN |
|
|
426 | 427 | state_fsm_select_channel <= SWITCH_F0_B; |
|
|
427 | 428 | ELSIF sample_f2_full = "11111" THEN |
|
|
428 | 429 | state_fsm_select_channel <= SWITCH_F2; |
|
|
429 | 430 | END IF; |
|
|
430 | 431 | END IF; |
|
|
431 | 432 | |
|
|
432 | 433 | WHEN SWITCH_F0_A => |
|
|
433 | 434 | IF sample_f0_A_empty = "11111" THEN |
|
|
434 | 435 | state_fsm_select_channel <= IDLE; |
|
|
435 | 436 | END IF; |
|
|
436 | 437 | WHEN SWITCH_F0_B => |
|
|
437 | 438 | IF sample_f0_B_empty = "11111" THEN |
|
|
438 | 439 | state_fsm_select_channel <= IDLE; |
|
|
439 | 440 | END IF; |
|
|
440 | 441 | WHEN SWITCH_F1 => |
|
|
441 | 442 | IF sample_f1_empty = "11111" THEN |
|
|
442 | 443 | state_fsm_select_channel <= IDLE; |
|
|
443 | 444 | END IF; |
|
|
444 | 445 | WHEN SWITCH_F2 => |
|
|
445 | 446 | IF sample_f2_empty = "11111" THEN |
|
|
446 | 447 | state_fsm_select_channel <= IDLE; |
|
|
447 | 448 | END IF; |
|
|
448 | 449 | WHEN OTHERS => NULL; |
|
|
449 | 450 | END CASE; |
|
|
450 | 451 | |
|
|
451 | 452 | END IF; |
|
|
452 | 453 | END PROCESS; |
|
|
453 | 454 | |
|
|
454 | 455 | PROCESS (clk, rstn) |
|
|
455 | 456 | BEGIN |
|
|
456 | 457 | IF rstn = '0' THEN |
|
|
457 | 458 | pre_state_fsm_select_channel <= IDLE; |
|
|
458 | 459 | ELSIF clk'EVENT AND clk = '1' THEN |
|
|
459 | 460 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
|
460 | 461 | END IF; |
|
|
461 | 462 | END PROCESS; |
|
|
462 | 463 | |
|
|
463 | 464 | |
|
|
464 | 465 | ----------------------------------------------------------------------------- |
|
|
465 | 466 | -- SWITCH SELECT CHANNEL |
|
|
466 | 467 | ----------------------------------------------------------------------------- |
|
|
467 | 468 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
|
468 | 469 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
|
469 | 470 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
|
470 | 471 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
|
471 | 472 | (OTHERS => '1'); |
|
|
472 | 473 | |
|
|
473 | 474 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
|
474 | 475 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
|
475 | 476 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
|
476 | 477 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
|
477 | 478 | (OTHERS => '0'); |
|
|
478 | 479 | |
|
|
479 | 480 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
|
480 | 481 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
|
481 | 482 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
|
482 | 483 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
|
483 | 484 | |
|
|
484 | 485 | |
|
|
485 | 486 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
|
486 | 487 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
|
487 | 488 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
|
488 | 489 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
|
489 | 490 | |
|
|
490 | 491 | |
|
|
491 | 492 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
|
492 | 493 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
|
493 | 494 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
|
494 | 495 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
|
495 | 496 | |
|
|
496 | 497 | ----------------------------------------------------------------------------- |
|
|
497 | 498 | -- FSM LOAD FFT |
|
|
498 | 499 | ----------------------------------------------------------------------------- |
|
|
499 | 500 | |
|
|
500 | 501 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); |
|
|
501 | 502 | |
|
|
502 | 503 | PROCESS (clk, rstn) |
|
|
503 | 504 | BEGIN |
|
|
504 | 505 | IF rstn = '0' THEN |
|
|
505 | 506 | sample_ren_s <= (OTHERS => '1'); |
|
|
506 | 507 | state_fsm_load_FFT <= IDLE; |
|
|
507 | 508 | status_MS_input <= (OTHERS => '0'); |
|
|
508 | 509 | --next_state_fsm_load_FFT <= IDLE; |
|
|
509 | 510 | --sample_valid <= '0'; |
|
|
510 | 511 | ELSIF clk'EVENT AND clk = '1' THEN |
|
|
511 | 512 | CASE state_fsm_load_FFT IS |
|
|
512 | 513 | WHEN IDLE => |
|
|
513 | 514 | --sample_valid <= '0'; |
|
|
514 | 515 | sample_ren_s <= (OTHERS => '1'); |
|
|
515 | 516 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
|
516 | 517 | state_fsm_load_FFT <= FIFO_1; |
|
|
517 | 518 | status_MS_input <= status_channel; |
|
|
518 | 519 | END IF; |
|
|
519 | 520 | |
|
|
520 | 521 | WHEN FIFO_1 => |
|
|
521 | 522 | sample_ren_s <= "1111" & NOT(sample_load); |
|
|
522 | 523 | IF sample_empty(0) = '1' THEN |
|
|
523 | 524 | sample_ren_s <= (OTHERS => '1'); |
|
|
524 | 525 | state_fsm_load_FFT <= FIFO_2; |
|
|
525 | 526 | END IF; |
|
|
526 | 527 | |
|
|
527 | 528 | WHEN FIFO_2 => |
|
|
528 | 529 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
|
529 | 530 | IF sample_empty(1) = '1' THEN |
|
|
530 | 531 | sample_ren_s <= (OTHERS => '1'); |
|
|
531 | 532 | state_fsm_load_FFT <= FIFO_3; |
|
|
532 | 533 | END IF; |
|
|
533 | 534 | |
|
|
534 | 535 | WHEN FIFO_3 => |
|
|
535 | 536 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
|
536 | 537 | IF sample_empty(2) = '1' THEN |
|
|
537 | 538 | sample_ren_s <= (OTHERS => '1'); |
|
|
538 | 539 | state_fsm_load_FFT <= FIFO_4; |
|
|
539 | 540 | END IF; |
|
|
540 | 541 | |
|
|
541 | 542 | WHEN FIFO_4 => |
|
|
542 | 543 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
|
543 | 544 | IF sample_empty(3) = '1' THEN |
|
|
544 | 545 | sample_ren_s <= (OTHERS => '1'); |
|
|
545 | 546 | state_fsm_load_FFT <= FIFO_5; |
|
|
546 | 547 | END IF; |
|
|
547 | 548 | |
|
|
548 | 549 | WHEN FIFO_5 => |
|
|
549 | 550 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
|
550 | 551 | IF sample_empty(4) = '1' THEN |
|
|
551 | 552 | sample_ren_s <= (OTHERS => '1'); |
|
|
552 | 553 | state_fsm_load_FFT <= IDLE; |
|
|
553 | 554 | END IF; |
|
|
554 | 555 | WHEN OTHERS => NULL; |
|
|
555 | 556 | END CASE; |
|
|
556 | 557 | END IF; |
|
|
557 | 558 | END PROCESS; |
|
|
558 | 559 | |
|
|
559 | 560 | PROCESS (clk, rstn) |
|
|
560 | 561 | BEGIN |
|
|
561 | 562 | IF rstn = '0' THEN |
|
|
562 | 563 | sample_valid_r <= '0'; |
|
|
563 | 564 | next_state_fsm_load_FFT <= IDLE; |
|
|
564 | 565 | ELSIF clk'EVENT AND clk = '1' THEN |
|
|
565 | 566 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
|
566 | 567 | IF sample_ren_s = "11111" THEN |
|
|
567 | 568 | sample_valid_r <= '0'; |
|
|
568 | 569 | ELSE |
|
|
569 | 570 | sample_valid_r <= '1'; |
|
|
570 | 571 | END IF; |
|
|
571 | 572 | END IF; |
|
|
572 | 573 | END PROCESS; |
|
|
573 | 574 | |
|
|
574 | 575 | sample_valid <= sample_valid_r AND sample_load; |
|
|
575 | 576 | |
|
|
576 | 577 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
|
577 | 578 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
|
578 | 579 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
|
579 | 580 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
|
580 | 581 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
|
581 | 582 | |
|
|
582 | 583 | ----------------------------------------------------------------------------- |
|
|
583 | 584 | -- FFT |
|
|
584 | 585 | ----------------------------------------------------------------------------- |
|
|
585 | CoreFFT_1 : CoreFFT | |
|
|
586 | GENERIC MAP ( | |
|
|
587 | LOGPTS => gLOGPTS, | |
|
|
588 | LOGLOGPTS => gLOGLOGPTS, | |
|
|
589 | WSIZE => gWSIZE, | |
|
|
590 | TWIDTH => gTWIDTH, | |
|
|
591 | DWIDTH => gDWIDTH, | |
|
|
592 | TDWIDTH => gTDWIDTH, | |
|
|
593 | RND_MODE => gRND_MODE, | |
|
|
594 | SCALE_MODE => gSCALE_MODE, | |
|
|
595 | PTS => gPTS, | |
|
|
596 | HALFPTS => gHALFPTS, | |
|
|
597 | inBuf_RWDLY => gInBuf_RWDLY) | |
|
|
586 | lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT | |
|
|
598 | 587 | PORT MAP ( |
|
|
599 | 588 | clk => clk, |
|
|
600 | ifiStart => '1', | |
|
|
601 | ifiNreset => rstn, | |
|
|
602 | ||
|
|
603 | ifiD_valid => sample_valid, -- IN | |
|
|
604 | ifiRead_y => fft_read, | |
|
|
605 | ifiD_im => (OTHERS => '0'), -- IN | |
|
|
606 | ifiD_re => sample_data, -- IN | |
|
|
607 | ifoLoad => sample_load, -- IN | |
|
|
608 | ||
|
|
609 | ifoPong => fft_pong, | |
|
|
610 | ifoY_im => fft_data_im, | |
|
|
611 | ifoY_re => fft_data_re, | |
|
|
612 | ifoY_valid => fft_data_valid, | |
|
|
613 | ifoY_rdy => fft_ready); | |
|
|
589 | rstn => rstn, | |
|
|
590 | sample_valid => sample_valid, | |
|
|
591 | fft_read => fft_read, | |
|
|
592 | sample_data => sample_data, | |
|
|
593 | sample_load => sample_load, | |
|
|
594 | fft_pong => fft_pong, | |
|
|
595 | fft_data_im => fft_data_im, | |
|
|
596 | fft_data_re => fft_data_re, | |
|
|
597 | fft_data_valid => fft_data_valid, | |
|
|
598 | fft_ready => fft_ready); | |
|
|
614 | 599 | |
|
|
615 | 600 | ----------------------------------------------------------------------------- |
|
|
616 | 601 | -- in fft_data_im & fft_data_re |
|
|
617 | 602 | -- in fft_data_valid |
|
|
618 | 603 | -- in fft_ready |
|
|
619 | 604 | -- out fft_read |
|
|
620 | 605 | PROCESS (clk, rstn) |
|
|
621 | 606 | BEGIN |
|
|
622 | 607 | IF rstn = '0' THEN |
|
|
623 | 608 | state_fsm_load_MS_memory <= IDLE; |
|
|
624 | 609 | current_fifo_load <= "00001"; |
|
|
625 | 610 | ELSIF clk'event AND clk = '1' THEN |
|
|
626 | 611 | CASE state_fsm_load_MS_memory IS |
|
|
627 | 612 | WHEN IDLE => |
|
|
628 | 613 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
|
629 | 614 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
|
630 | 615 | END IF; |
|
|
631 | 616 | WHEN LOAD_FIFO => |
|
|
632 | 617 | IF current_fifo_full = '1' THEN |
|
|
633 | 618 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
|
634 | 619 | END IF; |
|
|
635 | 620 | WHEN TRASH_FFT => |
|
|
636 | 621 | IF fft_ready = '0' THEN |
|
|
637 | 622 | state_fsm_load_MS_memory <= IDLE; |
|
|
638 | 623 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
|
639 | 624 | END IF; |
|
|
640 | 625 | WHEN OTHERS => NULL; |
|
|
641 | 626 | END CASE; |
|
|
642 | 627 | |
|
|
643 | 628 | END IF; |
|
|
644 | 629 | END PROCESS; |
|
|
645 | 630 | |
|
|
646 | 631 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
|
647 | 632 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
|
648 | 633 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
|
649 | 634 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
|
650 | 635 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
|
651 | 636 | |
|
|
652 | 637 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
|
653 | 638 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
|
654 | 639 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
|
655 | 640 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
|
656 | 641 | MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
|
657 | 642 | |
|
|
658 | 643 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
|
659 | 644 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
|
660 | 645 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
|
661 | 646 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
|
662 | 647 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE |
|
|
663 | 648 | |
|
|
664 | 649 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
|
665 | 650 | |
|
|
666 | 651 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE |
|
|
667 | 652 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
|
668 | 653 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
|
669 | 654 | AND current_fifo_load(I) = '1' |
|
|
670 | 655 | ELSE '1'; |
|
|
671 | 656 | END GENERATE all_fifo; |
|
|
672 | 657 | |
|
|
673 | 658 | PROCESS (clk, rstn) |
|
|
674 | 659 | BEGIN |
|
|
675 | 660 | IF rstn = '0' THEN |
|
|
676 | 661 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
|
677 | 662 | ELSIF clk'event AND clk = '1' THEN |
|
|
678 | 663 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
|
679 | 664 | END IF; |
|
|
680 | 665 | END PROCESS; |
|
|
681 | 666 | |
|
|
682 | 667 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
|
683 | 668 | (fft_data_im & fft_data_re) & |
|
|
684 | 669 | (fft_data_im & fft_data_re) & |
|
|
685 | 670 | (fft_data_im & fft_data_re) & |
|
|
686 | 671 | (fft_data_im & fft_data_re); |
|
|
687 | 672 | |
|
|
688 | 673 | |
|
|
689 | 674 | -- out SM_MEM_IN_wData |
|
|
690 | 675 | -- out SM_MEM_IN_wen |
|
|
691 | 676 | -- out SM_MEM_IN_Full |
|
|
692 | 677 | |
|
|
693 | 678 | -- out SM_MEM_IN_locked |
|
|
694 | 679 | ----------------------------------------------------------------------------- |
|
|
695 | 680 | ----------------------------------------------------------------------------- |
|
|
696 | 681 | ----------------------------------------------------------------------------- |
|
|
697 | 682 | ----------------------------------------------------------------------------- |
|
|
698 | 683 | --Linker_FFT_1 : Linker_FFT |
|
|
699 | 684 | -- GENERIC MAP ( |
|
|
700 | 685 | -- Data_sz => 16, |
|
|
701 | 686 | -- NbData => 256) |
|
|
702 | 687 | -- PORT MAP ( |
|
|
703 | 688 | -- clk => clk, |
|
|
704 | 689 | -- rstn => rstn, |
|
|
705 | 690 | |
|
|
706 | 691 | -- Ready => fft_ready, |
|
|
707 | 692 | -- Valid => fft_data_valid, |
|
|
708 | 693 | |
|
|
709 | 694 | -- Full => MEM_IN_SM_Full, |
|
|
710 | 695 | |
|
|
711 | 696 | -- Data_re => fft_data_re, |
|
|
712 | 697 | -- Data_im => fft_data_im, |
|
|
713 | 698 | -- Read => fft_read, |
|
|
714 | 699 | |
|
|
715 | 700 | -- Write => MEM_IN_SM_wen, |
|
|
716 | 701 | -- ReUse => fft_linker_ReUse, |
|
|
717 | 702 | -- DATA => MEM_IN_SM_wData); |
|
|
718 | 703 | |
|
|
719 | 704 | ----------------------------------------------------------------------------- |
|
|
720 | 705 | Mem_In_SpectralMatrix : lppFIFOxN |
|
|
721 | 706 | GENERIC MAP ( |
|
|
722 | 707 | tech => 0, |
|
|
723 | 708 | Mem_use => Mem_use, |
|
|
724 | 709 | Data_sz => 32, --16, |
|
|
725 | 710 | Addr_sz => 7, --8 |
|
|
726 | 711 | FifoCnt => 5) |
|
|
727 | 712 | PORT MAP ( |
|
|
728 | 713 | clk => clk, |
|
|
729 | 714 | rstn => rstn, |
|
|
730 | 715 | |
|
|
731 | 716 | ReUse => MEM_IN_SM_ReUse, |
|
|
732 | 717 | |
|
|
733 | 718 | wen => MEM_IN_SM_wen, |
|
|
734 | 719 | wdata => MEM_IN_SM_wData, |
|
|
735 | 720 | |
|
|
736 | 721 | ren => MEM_IN_SM_ren, |
|
|
737 | 722 | rdata => MEM_IN_SM_rData, |
|
|
738 | 723 | full => MEM_IN_SM_Full, |
|
|
739 |
empty => MEM_IN_SM_Empty |
|
|
|
724 | empty => MEM_IN_SM_Empty, | |
|
|
725 | almost_full => OPEN); | |
|
|
740 | 726 | |
|
|
741 | 727 | |
|
|
742 | 728 | --all_lock: FOR I IN 4 DOWNTO 0 GENERATE |
|
|
743 | 729 | -- PROCESS (clk, rstn) |
|
|
744 | 730 | -- BEGIN |
|
|
745 | 731 | -- IF rstn = '0' THEN |
|
|
746 | 732 | -- MEM_IN_SM_locked(I) <= '0'; |
|
|
747 | 733 | -- ELSIF clk'event AND clk = '1' THEN |
|
|
748 | 734 | -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO |
|
|
749 | 735 | -- END IF; |
|
|
750 | 736 | -- END PROCESS; |
|
|
751 | 737 | --END GENERATE all_lock; |
|
|
752 | 738 | |
|
|
753 | 739 | ----------------------------------------------------------------------------- |
|
|
754 | 740 | MS_control_1: MS_control |
|
|
755 | 741 | PORT MAP ( |
|
|
756 | 742 | clk => clk, |
|
|
757 | 743 | rstn => rstn, |
|
|
758 | 744 | |
|
|
759 | 745 | current_status_ms => status_MS_input, |
|
|
760 | 746 | |
|
|
761 | 747 | fifo_in_lock => MEM_IN_SM_locked, |
|
|
762 | 748 | fifo_in_data => MEM_IN_SM_rdata, |
|
|
763 | 749 | fifo_in_full => MEM_IN_SM_Full, |
|
|
764 | 750 | fifo_in_empty => MEM_IN_SM_Empty, |
|
|
765 | 751 | fifo_in_ren => MEM_IN_SM_ren, |
|
|
766 | 752 | fifo_in_reuse => MEM_IN_SM_ReUse, |
|
|
767 | 753 | |
|
|
768 | 754 | fifo_out_data => SM_in_data, |
|
|
769 | 755 | fifo_out_ren => SM_in_ren, |
|
|
770 | 756 | fifo_out_empty => SM_in_empty, |
|
|
771 | 757 | |
|
|
772 | 758 | current_status_component => status_component, |
|
|
773 | 759 | |
|
|
774 | 760 | correlation_start => SM_correlation_start, |
|
|
775 | 761 | correlation_auto => SM_correlation_auto, |
|
|
776 | 762 | correlation_done => SM_correlation_done); |
|
|
777 | 763 | |
|
|
778 | 764 | |
|
|
779 | 765 | MS_calculation_1: MS_calculation |
|
|
780 | 766 | PORT MAP ( |
|
|
781 | 767 | clk => clk, |
|
|
782 | 768 | rstn => rstn, |
|
|
783 | 769 | |
|
|
784 | 770 | fifo_in_data => SM_in_data, |
|
|
785 | 771 | fifo_in_ren => SM_in_ren, |
|
|
786 | 772 | fifo_in_empty => SM_in_empty, |
|
|
787 | 773 | |
|
|
788 | 774 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO |
|
|
789 | 775 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO |
|
|
790 | 776 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO |
|
|
791 | 777 | |
|
|
792 | 778 | correlation_start => SM_correlation_start, |
|
|
793 | 779 | correlation_auto => SM_correlation_auto, |
|
|
794 | 780 | correlation_begin => SM_correlation_begin, |
|
|
795 | 781 | correlation_done => SM_correlation_done); |
|
|
796 | 782 | |
|
|
797 | 783 | ----------------------------------------------------------------------------- |
|
|
798 | 784 | PROCESS (clk, rstn) |
|
|
799 | 785 | BEGIN -- PROCESS |
|
|
800 | 786 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
|
801 | 787 | current_matrix_write <= '0'; |
|
|
802 | 788 | current_matrix_wait_empty <= '1'; |
|
|
803 | 789 | status_component_fifo_0 <= (OTHERS => '0'); |
|
|
804 | 790 | status_component_fifo_1 <= (OTHERS => '0'); |
|
|
805 |
|
|
|
|
806 |
|
|
|
|
791 | -- status_component_fifo_0_new <= '0'; | |
|
|
792 | -- status_component_fifo_1_new <= '0'; | |
|
|
807 | 793 | status_component_fifo_0_end <= '0'; |
|
|
808 | 794 | status_component_fifo_1_end <= '0'; |
|
|
809 | 795 | SM_correlation_done_reg1 <= '0'; |
|
|
810 | 796 | SM_correlation_done_reg2 <= '0'; |
|
|
797 | SM_correlation_done_reg3 <= '0'; | |
|
|
811 | 798 | |
|
|
812 | 799 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
|
813 | 800 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
|
814 | 801 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
|
802 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
|
|
815 | 803 | |
|
|
816 |
|
|
|
|
817 | status_component_fifo_1_new <= '0'; | |
|
|
804 | -- status_component_fifo_0_new <= '0'; | |
|
|
805 | -- status_component_fifo_1_new <= '0'; | |
|
|
818 | 806 | status_component_fifo_0_end <= '0'; |
|
|
819 | 807 | status_component_fifo_1_end <= '0'; |
|
|
820 | 808 | |
|
|
821 | 809 | |
|
|
822 | 810 | |
|
|
823 | 811 | IF SM_correlation_begin = '1' THEN |
|
|
824 | 812 | IF current_matrix_write = '0' THEN |
|
|
825 | status_component_fifo_0_new <= '1'; | |
|
|
813 | -- status_component_fifo_0_new <= '1'; | |
|
|
826 | 814 | status_component_fifo_0 <= status_component; |
|
|
827 | 815 | ELSE |
|
|
828 | status_component_fifo_1_new <= '1'; | |
|
|
816 | -- status_component_fifo_1_new <= '1'; | |
|
|
829 | 817 | status_component_fifo_1 <= status_component; |
|
|
830 | 818 | END IF; |
|
|
831 | 819 | END IF; |
|
|
832 | 820 | |
|
|
833 |
IF SM_correlation_done_reg |
|
|
|
821 | IF SM_correlation_done_reg3 = '1' THEN | |
|
|
834 | 822 | IF current_matrix_write = '0' THEN |
|
|
835 | 823 | status_component_fifo_0_end <= '1'; |
|
|
836 | 824 | ELSE |
|
|
837 | 825 | status_component_fifo_1_end <= '1'; |
|
|
838 | 826 | END IF; |
|
|
839 | 827 | current_matrix_wait_empty <= '1'; |
|
|
840 | 828 | current_matrix_write <= NOT current_matrix_write; |
|
|
841 | 829 | END IF; |
|
|
842 | 830 | |
|
|
843 | 831 | IF current_matrix_wait_empty <= '1' THEN |
|
|
844 | 832 | IF current_matrix_write = '0' THEN |
|
|
845 | 833 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
|
846 | 834 | ELSE |
|
|
847 | 835 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
|
848 | 836 | END IF; |
|
|
849 | 837 | END IF; |
|
|
850 | 838 | |
|
|
851 | 839 | END IF; |
|
|
852 | 840 | END PROCESS; |
|
|
853 | 841 | |
|
|
854 | 842 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE |
|
|
855 | 843 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
|
856 | 844 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
|
845 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
|
|
857 | 846 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
|
858 | 847 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
|
859 | 848 | MEM_OUT_SM_Full(1); |
|
|
860 | 849 | |
|
|
861 | 850 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
|
862 | 851 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
|
863 | 852 | |
|
|
864 | 853 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; |
|
|
865 | 854 | ----------------------------------------------------------------------------- |
|
|
866 | 855 | |
|
|
867 | 856 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
|
868 | 857 | GENERIC MAP ( |
|
|
869 | 858 | tech => 0, |
|
|
870 | 859 | Mem_use => Mem_use, |
|
|
871 | 860 | Data_sz => 32, |
|
|
872 | 861 | Addr_sz => 8, |
|
|
873 | 862 | FifoCnt => 2) |
|
|
874 | 863 | PORT MAP ( |
|
|
875 | 864 | clk => clk, |
|
|
876 | 865 | rstn => rstn, |
|
|
877 | 866 | |
|
|
878 | 867 | ReUse => (OTHERS => '0'), |
|
|
879 | 868 | |
|
|
880 | 869 | wen => MEM_OUT_SM_Write, |
|
|
881 | 870 | wdata => MEM_OUT_SM_Data_in, |
|
|
882 | 871 | |
|
|
883 | 872 | ren => MEM_OUT_SM_Read, |
|
|
884 | 873 | rdata => MEM_OUT_SM_Data_out, |
|
|
885 | 874 | |
|
|
886 | 875 | full => MEM_OUT_SM_Full, |
|
|
887 | 876 | empty => MEM_OUT_SM_Empty, |
|
|
888 | 877 | almost_full => OPEN); |
|
|
889 | 878 | |
|
|
890 | 879 | ----------------------------------------------------------------------------- |
|
|
891 | 880 | -- MEM_OUT_SM_Read <= "00"; |
|
|
892 | 881 | PROCESS (clk, rstn) |
|
|
893 | 882 | BEGIN |
|
|
894 | 883 | IF rstn = '0' THEN |
|
|
895 | 884 | fifo_0_ready <= '0'; |
|
|
896 | 885 | fifo_1_ready <= '0'; |
|
|
897 | 886 | fifo_ongoing <= '0'; |
|
|
898 | 887 | ELSIF clk'event AND clk = '1' THEN |
|
|
899 | 888 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
|
900 | 889 | fifo_ongoing <= '1'; |
|
|
901 | 890 | fifo_0_ready <= '0'; |
|
|
902 | 891 | ELSIF status_component_fifo_0_end = '1' THEN |
|
|
903 | 892 | fifo_0_ready <= '1'; |
|
|
904 | 893 | END IF; |
|
|
905 | 894 | |
|
|
906 | 895 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
|
907 | 896 | fifo_ongoing <= '0'; |
|
|
908 | 897 | fifo_1_ready <= '0'; |
|
|
909 | 898 | ELSIF status_component_fifo_1_end = '1' THEN |
|
|
910 | 899 | fifo_1_ready <= '1'; |
|
|
911 | 900 | END IF; |
|
|
912 | 901 | |
|
|
913 | 902 | END IF; |
|
|
914 | 903 | END PROCESS; |
|
|
915 | 904 | |
|
|
916 | 905 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
|
917 | 906 | '1' WHEN fifo_0_ready = '0' ELSE |
|
|
918 | 907 | FSM_DMA_fifo_ren; |
|
|
919 | 908 | |
|
|
920 | 909 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
|
921 | 910 | '1' WHEN fifo_1_ready = '0' ELSE |
|
|
922 | 911 | FSM_DMA_fifo_ren; |
|
|
923 | 912 | |
|
|
924 | 913 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
|
925 | 914 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
|
926 | 915 | '1'; |
|
|
927 | 916 | |
|
|
928 | 917 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE |
|
|
929 | 918 | status_component_fifo_1; |
|
|
930 | 919 | |
|
|
931 | 920 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE |
|
|
932 | 921 | MEM_OUT_SM_Data_out(63 DOWNTO 32); |
|
|
933 | 922 | |
|
|
934 | 923 | ----------------------------------------------------------------------------- |
|
|
935 | 924 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
|
936 | 925 | PORT MAP ( |
|
|
937 | 926 | HCLK => clk, |
|
|
938 | 927 | HRESETn => rstn, |
|
|
939 | 928 | |
|
|
940 | 929 | fifo_matrix_type => FSM_DMA_fifo_status( 5 DOWNTO 4), |
|
|
941 | 930 | fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0), |
|
|
942 | 931 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
|
943 | 932 | fifo_data => FSM_DMA_fifo_data, |
|
|
944 | 933 | fifo_empty => FSM_DMA_fifo_empty, |
|
|
945 | 934 | fifo_ren => FSM_DMA_fifo_ren, |
|
|
946 | 935 | |
|
|
947 | 936 | ---- FIFO IN |
|
|
948 | 937 | --data_time => dma_time, |
|
|
949 | 938 | |
|
|
950 | 939 | --fifo_data => HEAD_Data, |
|
|
951 | 940 | --fifo_empty => HEAD_Empty, |
|
|
952 | 941 | --fifo_ren => HEAD_Read, |
|
|
953 | 942 | |
|
|
954 | 943 | --header => DMA_Header, |
|
|
955 | 944 | --header_val => DMA_Header_Val, |
|
|
956 | 945 | --header_ack => DMA_Header_Ack, |
|
|
957 | 946 | |
|
|
958 | 947 | dma_addr => dma_addr, |
|
|
959 | 948 | dma_data => dma_data, |
|
|
960 | 949 | dma_valid => dma_valid, |
|
|
961 | 950 | dma_valid_burst => dma_valid_burst, |
|
|
962 | 951 | dma_ren => dma_ren, |
|
|
963 | 952 | dma_done => dma_done, |
|
|
964 | 953 | |
|
|
965 | 954 | ready_matrix_f0 => ready_matrix_f0, |
|
|
966 | 955 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
|
967 | 956 | ready_matrix_f1 => ready_matrix_f1, |
|
|
968 | 957 | ready_matrix_f2 => ready_matrix_f2, |
|
|
969 | 958 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
|
970 | 959 | error_bad_component_error => error_bad_component_error, |
|
|
971 | 960 | error_buffer_full => error_buffer_full, |
|
|
972 | 961 | debug_reg => debug_reg, |
|
|
973 | 962 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
|
974 | 963 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
|
975 | 964 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
|
976 | 965 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
|
977 | 966 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
|
978 | 967 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
|
979 | 968 | -- status_error_buffer_full => status_error_buffer_full, |
|
|
980 | 969 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
|
981 | 970 | config_active_interruption_onError => config_active_interruption_onError, |
|
|
982 | 971 | addr_matrix_f0 => addr_matrix_f0, |
|
|
983 | 972 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
|
984 | 973 | addr_matrix_f1 => addr_matrix_f1, |
|
|
985 | 974 | addr_matrix_f2 => addr_matrix_f2, |
|
|
986 | 975 | |
|
|
987 | 976 | matrix_time_f0 => matrix_time_f0, |
|
|
988 | 977 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
|
989 | 978 | matrix_time_f1 => matrix_time_f1, |
|
|
990 | 979 | matrix_time_f2 => matrix_time_f2 |
|
|
991 | 980 | ); |
|
|
992 | 981 | ----------------------------------------------------------------------------- |
|
|
993 | 982 | |
|
|
994 | 983 | |
|
|
995 | 984 | |
|
|
996 | 985 | |
|
|
997 | 986 | |
|
|
998 | 987 | |
|
|
999 | 988 | |
|
|
1000 | 989 | |
|
|
1001 | 990 | |
|
|
1002 | 991 | |
|
|
1003 | 992 | |
|
|
1004 | 993 | ----------------------------------------------------------------------------- |
|
|
1005 | 994 | ----------------------------------------------------------------------------- |
|
|
1006 | 995 | ----------------------------------------------------------------------------- |
|
|
1007 | 996 | ----------------------------------------------------------------------------- |
|
|
1008 | 997 | ----------------------------------------------------------------------------- |
|
|
1009 | 998 | ----------------------------------------------------------------------------- |
|
|
1010 | 999 | |
|
|
1011 | 1000 | |
|
|
1012 | 1001 | |
|
|
1013 | 1002 | |
|
|
1014 | 1003 | |
|
|
1015 | 1004 | |
|
|
1016 | 1005 | ----------------------------------------------------------------------------- |
|
|
1017 | 1006 | -- TIME MANAGMENT |
|
|
1018 | 1007 | ----------------------------------------------------------------------------- |
|
|
1019 | 1008 | all_time <= coarse_time & fine_time; |
|
|
1020 | 1009 | -- |
|
|
1021 | 1010 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE |
|
|
1022 | 1011 | '1' WHEN sample_f0_A_empty = "11111" ELSE |
|
|
1023 | 1012 | '0'; |
|
|
1024 | 1013 | |
|
|
1025 | 1014 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
|
1026 | 1015 | PORT MAP ( |
|
|
1027 | 1016 | clk => clk, |
|
|
1028 | 1017 | rstn => rstn, |
|
|
1029 | 1018 | time_in => all_time, |
|
|
1030 | 1019 | update_1 => time_update_f0_A, |
|
|
1031 | 1020 | time_out => time_reg_f0_A); |
|
|
1032 | 1021 | |
|
|
1033 | 1022 | -- |
|
|
1034 | 1023 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE |
|
|
1035 | 1024 | '1' WHEN sample_f0_B_empty = "11111" ELSE |
|
|
1036 | 1025 | '0'; |
|
|
1037 | 1026 | |
|
|
1038 | 1027 | s_m_t_m_f0_B : spectral_matrix_time_managment |
|
|
1039 | 1028 | PORT MAP ( |
|
|
1040 | 1029 | clk => clk, |
|
|
1041 | 1030 | rstn => rstn, |
|
|
1042 | 1031 | time_in => all_time, |
|
|
1043 | 1032 | update_1 => time_update_f0_B, |
|
|
1044 | 1033 | time_out => time_reg_f0_B); |
|
|
1045 | 1034 | |
|
|
1046 | 1035 | -- |
|
|
1047 | 1036 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE |
|
|
1048 | 1037 | '1' WHEN sample_f1_empty = "11111" ELSE |
|
|
1049 | 1038 | '0'; |
|
|
1050 | 1039 | |
|
|
1051 | 1040 | s_m_t_m_f1 : spectral_matrix_time_managment |
|
|
1052 | 1041 | PORT MAP ( |
|
|
1053 | 1042 | clk => clk, |
|
|
1054 | 1043 | rstn => rstn, |
|
|
1055 | 1044 | time_in => all_time, |
|
|
1056 | 1045 | update_1 => time_update_f1, |
|
|
1057 | 1046 | time_out => time_reg_f1); |
|
|
1058 | 1047 | |
|
|
1059 | 1048 | -- |
|
|
1060 | 1049 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE |
|
|
1061 | 1050 | '1' WHEN sample_f2_empty = "11111" ELSE |
|
|
1062 | 1051 | '0'; |
|
|
1063 | 1052 | |
|
|
1064 | 1053 | s_m_t_m_f2 : spectral_matrix_time_managment |
|
|
1065 | 1054 | PORT MAP ( |
|
|
1066 | 1055 | clk => clk, |
|
|
1067 | 1056 | rstn => rstn, |
|
|
1068 | 1057 | time_in => all_time, |
|
|
1069 | 1058 | update_1 => time_update_f2, |
|
|
1070 | 1059 | time_out => time_reg_f2); |
|
|
1071 | 1060 | |
|
|
1072 | 1061 | ----------------------------------------------------------------------------- |
|
|
1073 | 1062 | dma_time <= (OTHERS => '0'); -- TODO |
|
|
1074 | 1063 | ----------------------------------------------------------------------------- |
|
|
1075 | 1064 | |
|
|
1076 | 1065 | |
|
|
1077 | 1066 | |
|
|
1078 | 1067 | END Behavioral; |
| @@ -1,293 +1,296 | |||
|
|
1 | 1 | |
|
|
2 | 2 | ------------------------------------------------------------------------------ |
|
|
3 | 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
|
4 | 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
|
5 | 5 | -- |
|
|
6 | 6 | -- This program is free software; you can redistribute it and/or modify |
|
|
7 | 7 | -- it under the terms of the GNU General Public License as published by |
|
|
8 | 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
|
9 | 9 | -- (at your option) any later version. |
|
|
10 | 10 | -- |
|
|
11 | 11 | -- This program is distributed in the hope that it will be useful, |
|
|
12 | 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
|
13 | 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
|
14 | 14 | -- GNU General Public License for more details. |
|
|
15 | 15 | -- |
|
|
16 | 16 | -- You should have received a copy of the GNU General Public License |
|
|
17 | 17 | -- along with this program; if not, write to the Free Software |
|
|
18 | 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
|
19 | 19 | ------------------------------------------------------------------------------- |
|
|
20 | 20 | -- Author : Jean-christophe Pellion |
|
|
21 | 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
|
22 | 22 | -- jean-christophe.pellion@easii-ic.com |
|
|
23 | 23 | ------------------------------------------------------------------------------- |
|
|
24 | 24 | LIBRARY ieee; |
|
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
|
26 | 26 | USE ieee.numeric_std.ALL; |
|
|
27 | 27 | LIBRARY grlib; |
|
|
28 | 28 | USE grlib.amba.ALL; |
|
|
29 | 29 | USE grlib.stdlib.ALL; |
|
|
30 | 30 | USE grlib.devices.ALL; |
|
|
31 | 31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
|
32 | 32 | LIBRARY lpp; |
|
|
33 | 33 | USE lpp.lpp_amba.ALL; |
|
|
34 | 34 | USE lpp.apb_devices_list.ALL; |
|
|
35 | 35 | USE lpp.lpp_memory.ALL; |
|
|
36 | 36 | USE lpp.lpp_dma_pkg.ALL; |
|
|
37 | 37 | LIBRARY techmap; |
|
|
38 | 38 | USE techmap.gencomp.ALL; |
|
|
39 | 39 | |
|
|
40 | 40 | |
|
|
41 | 41 | ENTITY lpp_lfr_ms_fsmdma IS |
|
|
42 | 42 | PORT ( |
|
|
43 | 43 | -- AMBA AHB system signals |
|
|
44 | 44 | HCLK : IN STD_ULOGIC; |
|
|
45 | 45 | HRESETn : IN STD_ULOGIC; |
|
|
46 | 46 | |
|
|
47 | 47 | --------------------------------------------------------------------------- |
|
|
48 | 48 | -- FIFO - IN |
|
|
49 | 49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
50 | 50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
51 | 51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
52 | 52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
53 | 53 | fifo_empty : IN STD_LOGIC; |
|
|
54 | 54 | fifo_ren : OUT STD_LOGIC; |
|
|
55 | 55 | |
|
|
56 | 56 | --------------------------------------------------------------------------- |
|
|
57 | 57 | -- DMA - OUT |
|
|
58 | 58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
59 | 59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
60 | 60 | dma_valid : OUT STD_LOGIC; |
|
|
61 | 61 | dma_valid_burst : OUT STD_LOGIC; |
|
|
62 | 62 | dma_ren : IN STD_LOGIC; |
|
|
63 | 63 | dma_done : IN STD_LOGIC; |
|
|
64 | 64 | |
|
|
65 | 65 | --------------------------------------------------------------------------- |
|
|
66 | 66 | -- Reg out |
|
|
67 | 67 | ready_matrix_f0 : OUT STD_LOGIC; |
|
|
68 | 68 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
|
69 | 69 | ready_matrix_f1 : OUT STD_LOGIC; |
|
|
70 | 70 | ready_matrix_f2 : OUT STD_LOGIC; |
|
|
71 | 71 | --error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
|
72 | 72 | error_bad_component_error : OUT STD_LOGIC; |
|
|
73 | 73 | error_buffer_full : OUT STD_LOGIC; |
|
|
74 | 74 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
75 | 75 | |
|
|
76 | 76 | -- Reg In |
|
|
77 | 77 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
|
78 | 78 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
|
79 | 79 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
|
80 | 80 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
|
81 | 81 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|
82 | 82 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
|
83 | 83 | -- status_error_buffer_full : IN STD_LOGIC; |
|
|
84 | 84 | |
|
|
85 | 85 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
|
86 | 86 | config_active_interruption_onError : IN STD_LOGIC; |
|
|
87 | 87 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
88 | 88 | --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
89 | 89 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
90 | 90 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
91 | 91 | |
|
|
92 | 92 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
93 | 93 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
94 | 94 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
95 | 95 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
|
96 | 96 | |
|
|
97 | 97 | ); |
|
|
98 | 98 | END; |
|
|
99 | 99 | |
|
|
100 | 100 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
|
101 | 101 | ----------------------------------------------------------------------------- |
|
|
102 | 102 | TYPE state_DMAWriteBurst IS (IDLE, |
|
|
103 | 103 | CHECK_COMPONENT_TYPE, |
|
|
104 | 104 | WRITE_COARSE_TIME, |
|
|
105 | 105 | WRITE_FINE_TIME, |
|
|
106 | 106 | TRASH_FIFO, |
|
|
107 | 107 | SEND_DATA, |
|
|
108 | 108 | WAIT_DATA_ACK |
|
|
109 | 109 | ); |
|
|
110 | 110 | SIGNAL state : state_DMAWriteBurst; |
|
|
111 | 111 | |
|
|
112 | 112 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
113 | 113 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
114 | 114 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
115 | 115 | SIGNAL header_check_ok : STD_LOGIC; |
|
|
116 | 116 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
117 | SIGNAL send_matrix : STD_LOGIC; | |
|
|
117 | -- SIGNAL send_matrix : STD_LOGIC; | |
|
|
118 | 118 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
119 | 119 | ----------------------------------------------------------------------------- |
|
|
120 | 120 | ----------------------------------------------------------------------------- |
|
|
121 | 121 | |
|
|
122 | 122 | SIGNAL component_send : STD_LOGIC; |
|
|
123 | 123 | SIGNAL component_send_ok : STD_LOGIC; |
|
|
124 | 124 | -- SIGNAL component_send_ko : STD_LOGIC; |
|
|
125 | 125 | ----------------------------------------------------------------------------- |
|
|
126 | 126 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
|
127 | SIGNAL component_fifo_ren : STD_LOGIC; | |
|
|
127 | -- SIGNAL component_fifo_ren : STD_LOGIC; | |
|
|
128 | 128 | |
|
|
129 | 129 | ----------------------------------------------------------------------------- |
|
|
130 | 130 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
131 | 131 | ----------------------------------------------------------------------------- |
|
|
132 | 132 | SIGNAL log_empty_fifo : STD_LOGIC; |
|
|
133 | 133 | ----------------------------------------------------------------------------- |
|
|
134 | SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
|
135 | SIGNAL header_reg_val : STD_LOGIC; | |
|
|
136 | SIGNAL header_reg_ack : STD_LOGIC; | |
|
|
137 | SIGNAL header_error : STD_LOGIC; | |
|
|
134 | --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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135 | --SIGNAL header_reg_val : STD_LOGIC; | |
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136 | --SIGNAL header_reg_ack : STD_LOGIC; | |
|
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137 | -- SIGNAL header_error : STD_LOGIC; | |
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138 | 138 | |
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139 | 139 | SIGNAL matrix_buffer_ready : STD_LOGIC; |
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|
140 | 140 | BEGIN |
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141 | 141 | |
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142 | 142 | debug_reg <= debug_reg_s; |
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143 | 143 | |
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144 | 144 | |
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145 | 145 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE |
|
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146 | 146 | --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
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147 | 147 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE |
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148 | 148 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE |
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149 | 149 | '0'; |
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150 | 150 | |
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151 | 151 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
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152 | 152 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE |
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153 | 153 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
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154 | 154 | '0'; |
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155 | 155 | |
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156 | 156 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE |
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157 | 157 | --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
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158 | 158 | addr_matrix_f1 WHEN matrix_type = "01" ELSE |
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159 | 159 | addr_matrix_f2 WHEN matrix_type = "10" ELSE |
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160 | 160 | (OTHERS => '0'); |
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161 | 161 | |
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162 | debug_reg_s(31 DOWNTO 3) <= (OTHERS => '0'); | |
|
|
162 | 163 | ----------------------------------------------------------------------------- |
|
|
163 | 164 | -- DMA control |
|
|
164 | 165 | ----------------------------------------------------------------------------- |
|
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165 | 166 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
|
166 | 167 | BEGIN |
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167 | 168 | IF HRESETn = '0' THEN |
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168 | 169 | matrix_type <= (OTHERS => '0'); |
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169 | 170 | component_type <= (OTHERS => '0'); |
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170 | 171 | state <= IDLE; |
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171 | 172 | ready_matrix_f0 <= '0'; |
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172 | 173 | -- ready_matrix_f0_1 <= '0'; |
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173 | 174 | ready_matrix_f1 <= '0'; |
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174 | 175 | ready_matrix_f2 <= '0'; |
|
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175 | 176 | -- error_anticipating_empty_fifo <= '0'; |
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176 | 177 | error_bad_component_error <= '0'; |
|
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177 | 178 | error_buffer_full <= '0'; -- TODO |
|
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178 | 179 | component_type_pre <= "0000"; |
|
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179 | 180 | fifo_ren_trash <= '1'; |
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180 | 181 | component_send <= '0'; |
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181 | 182 | address <= (OTHERS => '0'); |
|
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182 | 183 | |
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183 | 184 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); |
|
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184 | debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); | |
|
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185 | 185 | |
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186 | 186 | log_empty_fifo <= '0'; |
|
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187 | 187 | |
|
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188 | matrix_time_f0 <= (OTHERS => '0'); | |
|
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189 | matrix_time_f1 <= (OTHERS => '0'); | |
|
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190 | matrix_time_f2 <= (OTHERS => '0'); | |
|
|
191 | ||
|
|
188 | 192 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
|
189 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |
|
|
190 | 193 |
|
|
|
191 | 194 |
|
|
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192 | 195 | -- ready_matrix_f0_1 <= '0'; |
|
|
193 | 196 | ready_matrix_f1 <= '0'; |
|
|
194 | 197 | ready_matrix_f2 <= '0'; |
|
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195 | 198 | error_bad_component_error <= '0'; |
|
|
196 | 199 | error_buffer_full <= '0'; |
|
|
197 | 200 | |
|
|
198 | 201 | CASE state IS |
|
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199 | 202 | WHEN IDLE => |
|
|
200 | 203 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
|
201 | 204 | IF fifo_empty = '0' THEN |
|
|
202 | 205 | state <= CHECK_COMPONENT_TYPE; |
|
|
203 | 206 | matrix_type <= fifo_matrix_type; |
|
|
204 | 207 | component_type <= fifo_matrix_component; |
|
|
205 | 208 | component_type_pre <= component_type; |
|
|
206 | 209 | END IF; |
|
|
207 | 210 | |
|
|
208 | 211 | log_empty_fifo <= '0'; |
|
|
209 | 212 | |
|
|
210 | 213 | WHEN CHECK_COMPONENT_TYPE => |
|
|
211 | 214 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
|
212 | 215 | |
|
|
213 | 216 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN |
|
|
214 | 217 | IF component_type = "0000" THEN |
|
|
215 | 218 | address <= address_matrix; |
|
|
216 | 219 | CASE matrix_type IS |
|
|
217 | 220 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; |
|
|
218 | 221 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; |
|
|
219 | 222 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; |
|
|
220 | 223 | WHEN OTHERS => NULL; |
|
|
221 | 224 | END CASE; |
|
|
222 | 225 | component_send <= '1'; |
|
|
223 | 226 | END IF; |
|
|
224 | 227 | state <= SEND_DATA; |
|
|
225 | 228 | -- |
|
|
226 | 229 | ELSE |
|
|
227 | 230 | error_bad_component_error <= NOT header_check_ok; |
|
|
228 | 231 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO |
|
|
229 | 232 | component_type_pre <= "0000"; |
|
|
230 | 233 | state <= TRASH_FIFO; |
|
|
231 | 234 | END IF; |
|
|
232 | 235 | |
|
|
233 | 236 | WHEN TRASH_FIFO => |
|
|
234 | 237 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
|
235 | 238 | |
|
|
236 | 239 | error_bad_component_error <= '0'; |
|
|
237 | 240 | -- error_anticipating_empty_fifo <= '0'; |
|
|
238 | 241 | IF fifo_empty = '1' THEN |
|
|
239 | 242 | state <= IDLE; |
|
|
240 | 243 | fifo_ren_trash <= '1'; |
|
|
241 | 244 | ELSE |
|
|
242 | 245 | fifo_ren_trash <= '0'; |
|
|
243 | 246 | END IF; |
|
|
244 | 247 | |
|
|
245 | 248 | WHEN SEND_DATA => |
|
|
246 | 249 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
|
247 | 250 | |
|
|
248 | 251 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
|
249 | 252 | state <= IDLE; |
|
|
250 | 253 | IF component_type = "1110" THEN |
|
|
251 | 254 | CASE matrix_type IS |
|
|
252 | 255 | WHEN "00" => ready_matrix_f0 <= '1'; |
|
|
253 | 256 | WHEN "01" => ready_matrix_f1 <= '1'; |
|
|
254 | 257 | WHEN "10" => ready_matrix_f2 <= '1'; |
|
|
255 | 258 | WHEN OTHERS => NULL; |
|
|
256 | 259 | END CASE; |
|
|
257 | 260 | END IF; |
|
|
258 | 261 | ELSE |
|
|
259 | 262 | component_send <= '1'; |
|
|
260 | 263 | address <= address; |
|
|
261 | 264 | state <= WAIT_DATA_ACK; |
|
|
262 | 265 | END IF; |
|
|
263 | 266 | |
|
|
264 | 267 | WHEN WAIT_DATA_ACK => |
|
|
265 | 268 | log_empty_fifo <= fifo_empty OR log_empty_fifo; |
|
|
266 | 269 | |
|
|
267 | 270 | debug_reg_s(2 DOWNTO 0) <= "110"; |
|
|
268 | 271 | |
|
|
269 | 272 | component_send <= '0'; |
|
|
270 | 273 | IF component_send_ok = '1' THEN |
|
|
271 | 274 | address <= address + 64; |
|
|
272 | 275 | state <= SEND_DATA; |
|
|
273 | 276 | -- ELSIF component_send_ko = '1' THEN |
|
|
274 | 277 | -- error_anticipating_empty_fifo <= '0'; |
|
|
275 | 278 | -- state <= TRASH_FIFO; |
|
|
276 | 279 | END IF; |
|
|
277 | 280 | |
|
|
278 | 281 | WHEN OTHERS => NULL; |
|
|
279 | 282 | END CASE; |
|
|
280 | 283 | |
|
|
281 | 284 | END IF; |
|
|
282 | 285 | END PROCESS DMAWriteFSM_p; |
|
|
283 | 286 | |
|
|
284 | 287 | dma_valid_burst <= component_send; |
|
|
285 | 288 | dma_valid <= '0'; |
|
|
286 | 289 | dma_data <= fifo_data; |
|
|
287 | 290 | dma_addr <= address; |
|
|
288 | 291 | fifo_ren <= dma_ren AND fifo_ren_trash; |
|
|
289 | 292 | |
|
|
290 | 293 | component_send_ok <= dma_done; |
|
|
291 | 294 | -- component_send_ko <= '0'; |
|
|
292 | 295 | |
|
|
293 | 296 | END Behavioral; |
| @@ -1,334 +1,401 | |||
|
|
1 | 1 | LIBRARY ieee; |
|
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
|
3 | 3 | |
|
|
4 | 4 | LIBRARY grlib; |
|
|
5 | 5 | USE grlib.amba.ALL; |
|
|
6 | 6 | |
|
|
7 | 7 | LIBRARY lpp; |
|
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
|
12 | 12 | LIBRARY techmap; |
|
|
13 | 13 | USE techmap.gencomp.ALL; |
|
|
14 | 14 | |
|
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
|
16 | ----------------------------------------------------------------------------- | |
|
|
17 | -- TEMP | |
|
|
18 | ----------------------------------------------------------------------------- | |
|
|
19 | COMPONENT lpp_lfr_ms_test | |
|
|
20 | GENERIC ( | |
|
|
21 | Mem_use : INTEGER); | |
|
|
22 | PORT ( | |
|
|
23 | clk : IN STD_LOGIC; | |
|
|
24 | rstn : IN STD_LOGIC; | |
|
|
16 | 25 | |
|
|
26 | -- TIME | |
|
|
27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
|
28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
|
|
29 | -- | |
|
|
30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
|
32 | -- | |
|
|
33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
|
35 | -- | |
|
|
36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
|
38 | ||
|
|
39 | ||
|
|
40 | ||
|
|
41 | --------------------------------------------------------------------------- | |
|
|
42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
|
43 | ||
|
|
44 | -- | |
|
|
45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
|
49 | ||
|
|
50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); | |
|
|
51 | ||
|
|
52 | -- IN | |
|
|
53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
|
54 | ||
|
|
55 | ----------------------------------------------------------------------------- | |
|
|
56 | ||
|
|
57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
|
58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
|
59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
|
61 | ||
|
|
62 | SM_correlation_start : OUT STD_LOGIC; | |
|
|
63 | SM_correlation_auto : OUT STD_LOGIC; | |
|
|
64 | SM_correlation_done : IN STD_LOGIC | |
|
|
65 | ); | |
|
|
66 | END COMPONENT; | |
|
|
67 | ||
|
|
68 | ||
|
|
69 | ----------------------------------------------------------------------------- | |
|
|
17 | 70 | COMPONENT lpp_lfr_ms |
|
|
18 | 71 | GENERIC ( |
|
|
19 | 72 | Mem_use : INTEGER |
|
|
20 | 73 | ); |
|
|
21 | 74 | PORT ( |
|
|
22 | 75 | clk : IN STD_LOGIC; |
|
|
23 | 76 | rstn : IN STD_LOGIC; |
|
|
24 | 77 | |
|
|
25 | 78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
|
26 | 79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
|
27 | 80 | |
|
|
28 | 81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
29 | 82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
30 | 83 | |
|
|
31 | 84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
32 | 85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
33 | 86 | |
|
|
34 | 87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
|
35 | 88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
|
36 | 89 | |
|
|
37 | 90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
38 | 91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
39 | 92 | dma_valid : OUT STD_LOGIC; |
|
|
40 | 93 | dma_valid_burst : OUT STD_LOGIC; |
|
|
41 | 94 | dma_ren : IN STD_LOGIC; |
|
|
42 | 95 | dma_done : IN STD_LOGIC; |
|
|
43 | 96 | |
|
|
44 | 97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
|
45 | 98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
|
46 | 99 | ready_matrix_f1 : OUT STD_LOGIC; |
|
|
47 | 100 | ready_matrix_f2 : OUT STD_LOGIC; |
|
|
48 | 101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
|
49 | 102 | error_bad_component_error : OUT STD_LOGIC; |
|
|
50 | 103 | error_buffer_full : OUT STD_LOGIC; |
|
|
51 | 104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
|
52 | 105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
53 | 106 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
|
54 | 107 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
|
55 | 108 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
|
56 | 109 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
|
57 | 110 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|
58 | 111 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
|
59 | 112 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
|
60 | 113 | config_active_interruption_onError : IN STD_LOGIC; |
|
|
61 | 114 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
62 | 115 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
63 | 116 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
64 | 117 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
65 | 118 | |
|
|
66 | 119 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
67 | 120 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
68 | 121 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
69 | 122 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
|
70 | 123 | END COMPONENT; |
|
|
71 | 124 | |
|
|
72 | 125 | COMPONENT lpp_lfr_ms_fsmdma |
|
|
73 | 126 | PORT ( |
|
|
74 | 127 | HCLK : IN STD_ULOGIC; |
|
|
75 | 128 | HRESETn : IN STD_ULOGIC; |
|
|
76 | 129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
|
77 | 130 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|
78 | 131 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
79 | 132 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
80 | 133 | fifo_empty : IN STD_LOGIC; |
|
|
81 | 134 | fifo_ren : OUT STD_LOGIC; |
|
|
82 | 135 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
83 | 136 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
84 | 137 | --fifo_empty : IN STD_LOGIC; |
|
|
85 | 138 | --fifo_ren : OUT STD_LOGIC; |
|
|
86 | 139 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
87 | 140 | --header_val : IN STD_LOGIC; |
|
|
88 | 141 | --header_ack : OUT STD_LOGIC; |
|
|
89 | 142 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
90 | 143 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
91 | 144 | dma_valid : OUT STD_LOGIC; |
|
|
92 | 145 | dma_valid_burst : OUT STD_LOGIC; |
|
|
93 | 146 | dma_ren : IN STD_LOGIC; |
|
|
94 | 147 | dma_done : IN STD_LOGIC; |
|
|
95 | 148 | ready_matrix_f0 : OUT STD_LOGIC; |
|
|
96 | 149 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
|
97 | 150 | ready_matrix_f1 : OUT STD_LOGIC; |
|
|
98 | 151 | ready_matrix_f2 : OUT STD_LOGIC; |
|
|
99 | 152 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
|
100 | 153 | error_bad_component_error : OUT STD_LOGIC; |
|
|
101 | 154 | error_buffer_full : OUT STD_LOGIC; |
|
|
102 | 155 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
103 | 156 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
|
104 | 157 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
|
105 | 158 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
|
106 | 159 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
|
107 | 160 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
|
108 | 161 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
|
109 | 162 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
|
110 | 163 | config_active_interruption_onError : IN STD_LOGIC; |
|
|
111 | 164 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
112 | 165 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
113 | 166 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
114 | 167 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
|
115 | 168 | |
|
|
116 | 169 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
117 | 170 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
118 | 171 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
119 | 172 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
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120 | 173 | ); |
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121 | 174 | END COMPONENT; |
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122 | 175 | |
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176 | COMPONENT lpp_lfr_ms_FFT | |
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177 | PORT ( | |
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178 | clk : IN STD_LOGIC; | |
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179 | rstn : IN STD_LOGIC; | |
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180 | sample_valid : IN STD_LOGIC; | |
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181 | fft_read : IN STD_LOGIC; | |
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182 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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183 | sample_load : OUT STD_LOGIC; | |
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184 | fft_pong : OUT STD_LOGIC; | |
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185 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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186 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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187 | fft_data_valid : OUT STD_LOGIC; | |
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188 | fft_ready : OUT STD_LOGIC); | |
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189 | END COMPONENT; | |
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123 | 190 | |
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124 | 191 | COMPONENT lpp_lfr_filter |
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125 | 192 | GENERIC ( |
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126 | 193 | Mem_use : INTEGER); |
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127 | 194 | PORT ( |
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128 | 195 | sample : IN Samples(7 DOWNTO 0); |
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129 | 196 | sample_val : IN STD_LOGIC; |
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130 | 197 | clk : IN STD_LOGIC; |
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131 | 198 | rstn : IN STD_LOGIC; |
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132 | 199 | data_shaping_SP0 : IN STD_LOGIC; |
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133 | 200 | data_shaping_SP1 : IN STD_LOGIC; |
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134 | 201 | data_shaping_R0 : IN STD_LOGIC; |
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135 | 202 | data_shaping_R1 : IN STD_LOGIC; |
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136 | 203 | sample_f0_val : OUT STD_LOGIC; |
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137 | 204 | sample_f1_val : OUT STD_LOGIC; |
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138 | 205 | sample_f2_val : OUT STD_LOGIC; |
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139 | 206 | sample_f3_val : OUT STD_LOGIC; |
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140 | 207 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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141 | 208 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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142 | 209 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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143 | 210 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
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144 | 211 | END COMPONENT; |
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145 | 212 | |
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146 | 213 | COMPONENT lpp_lfr |
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147 | 214 | GENERIC ( |
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148 | 215 | Mem_use : INTEGER; |
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149 | 216 | nb_data_by_buffer_size : INTEGER; |
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150 | 217 | nb_word_by_buffer_size : INTEGER; |
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151 | 218 | nb_snapshot_param_size : INTEGER; |
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152 | 219 | delta_vector_size : INTEGER; |
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153 | 220 | delta_vector_size_f0_2 : INTEGER; |
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154 | 221 | pindex : INTEGER; |
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155 | 222 | paddr : INTEGER; |
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156 | 223 | pmask : INTEGER; |
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157 | 224 | pirq_ms : INTEGER; |
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158 | 225 | pirq_wfp : INTEGER; |
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159 | 226 | hindex : INTEGER; |
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160 | 227 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
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161 | 228 | ); |
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162 | 229 | PORT ( |
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163 | 230 | clk : IN STD_LOGIC; |
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164 | 231 | rstn : IN STD_LOGIC; |
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165 | 232 | sample_B : IN Samples(2 DOWNTO 0); |
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166 | 233 | sample_E : IN Samples(4 DOWNTO 0); |
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167 | 234 | sample_val : IN STD_LOGIC; |
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168 | 235 | apbi : IN apb_slv_in_type; |
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169 | 236 | apbo : OUT apb_slv_out_type; |
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170 | 237 | ahbi : IN AHB_Mst_In_Type; |
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171 | 238 | ahbo : OUT AHB_Mst_Out_Type; |
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172 | 239 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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173 | 240 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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174 | 241 | data_shaping_BW : OUT STD_LOGIC; |
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175 | 242 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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176 | 243 | ); |
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177 | 244 | END COMPONENT; |
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178 | 245 | |
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179 | 246 | ----------------------------------------------------------------------------- |
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180 | 247 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
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181 | 248 | ----------------------------------------------------------------------------- |
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182 | 249 | COMPONENT lpp_lfr_WFP_nMS |
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183 | 250 | GENERIC ( |
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184 | 251 | Mem_use : INTEGER; |
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185 | 252 | nb_data_by_buffer_size : INTEGER; |
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186 | 253 | nb_word_by_buffer_size : INTEGER; |
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187 | 254 | nb_snapshot_param_size : INTEGER; |
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188 | 255 | delta_vector_size : INTEGER; |
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189 | 256 | delta_vector_size_f0_2 : INTEGER; |
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190 | 257 | pindex : INTEGER; |
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191 | 258 | paddr : INTEGER; |
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192 | 259 | pmask : INTEGER; |
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193 | 260 | pirq_ms : INTEGER; |
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194 | 261 | pirq_wfp : INTEGER; |
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195 | 262 | hindex : INTEGER; |
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196 | 263 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
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197 | 264 | PORT ( |
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198 | 265 | clk : IN STD_LOGIC; |
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199 | 266 | rstn : IN STD_LOGIC; |
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200 | 267 | sample_B : IN Samples(2 DOWNTO 0); |
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201 | 268 | sample_E : IN Samples(4 DOWNTO 0); |
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202 | 269 | sample_val : IN STD_LOGIC; |
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203 | 270 | apbi : IN apb_slv_in_type; |
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204 | 271 | apbo : OUT apb_slv_out_type; |
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205 | 272 | ahbi : IN AHB_Mst_In_Type; |
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206 | 273 | ahbo : OUT AHB_Mst_Out_Type; |
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207 | 274 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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208 | 275 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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209 | 276 | data_shaping_BW : OUT STD_LOGIC; |
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210 | 277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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211 | 278 | END COMPONENT; |
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212 | 279 | ----------------------------------------------------------------------------- |
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213 | 280 | |
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214 | 281 | |
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215 | 282 | COMPONENT lpp_lfr_apbreg |
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216 | 283 | GENERIC ( |
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217 | 284 | nb_data_by_buffer_size : INTEGER; |
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218 | 285 | nb_word_by_buffer_size : INTEGER; |
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219 | 286 | nb_snapshot_param_size : INTEGER; |
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220 | 287 | delta_vector_size : INTEGER; |
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221 | 288 | delta_vector_size_f0_2 : INTEGER; |
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222 | 289 | pindex : INTEGER; |
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223 | 290 | paddr : INTEGER; |
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224 | 291 | pmask : INTEGER; |
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225 | 292 | pirq_ms : INTEGER; |
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226 | 293 | pirq_wfp : INTEGER; |
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227 | 294 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
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228 | 295 | PORT ( |
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229 | 296 | HCLK : IN STD_ULOGIC; |
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230 | 297 | HRESETn : IN STD_ULOGIC; |
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231 | 298 | apbi : IN apb_slv_in_type; |
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232 | 299 | apbo : OUT apb_slv_out_type; |
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233 | 300 | run_ms : OUT STD_LOGIC; |
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234 | 301 | ready_matrix_f0_0 : IN STD_LOGIC; |
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235 | 302 | ready_matrix_f0_1 : IN STD_LOGIC; |
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236 | 303 | ready_matrix_f1 : IN STD_LOGIC; |
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237 | 304 | ready_matrix_f2 : IN STD_LOGIC; |
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238 | 305 | error_anticipating_empty_fifo : IN STD_LOGIC; |
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239 | 306 | error_bad_component_error : IN STD_LOGIC; |
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240 | 307 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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241 | 308 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
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242 | 309 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
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243 | 310 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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244 | 311 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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245 | 312 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
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246 | 313 | status_error_bad_component_error : OUT STD_LOGIC; |
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247 | 314 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
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248 | 315 | config_active_interruption_onError : OUT STD_LOGIC; |
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249 | 316 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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250 | 317 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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251 | 318 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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252 | 319 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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253 | 320 | |
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254 | 321 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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255 | 322 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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256 | 323 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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257 | 324 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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258 | 325 | |
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259 | 326 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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260 | 327 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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261 | 328 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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262 | 329 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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263 | 330 | data_shaping_BW : OUT STD_LOGIC; |
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264 | 331 | data_shaping_SP0 : OUT STD_LOGIC; |
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265 | 332 | data_shaping_SP1 : OUT STD_LOGIC; |
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266 | 333 | data_shaping_R0 : OUT STD_LOGIC; |
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267 | 334 | data_shaping_R1 : OUT STD_LOGIC; |
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268 | 335 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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269 | 336 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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270 | 337 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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271 | 338 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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272 | 339 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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273 | 340 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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274 | 341 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
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275 | 342 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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276 | 343 | enable_f0 : OUT STD_LOGIC; |
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277 | 344 | enable_f1 : OUT STD_LOGIC; |
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278 | 345 | enable_f2 : OUT STD_LOGIC; |
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279 | 346 | enable_f3 : OUT STD_LOGIC; |
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280 | 347 | burst_f0 : OUT STD_LOGIC; |
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281 | 348 | burst_f1 : OUT STD_LOGIC; |
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282 | 349 | burst_f2 : OUT STD_LOGIC; |
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283 | 350 | run : OUT STD_LOGIC; |
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284 | 351 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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285 | 352 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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286 | 353 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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287 | 354 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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288 | 355 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
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|
289 | 356 | --------------------------------------------------------------------------- |
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290 | 357 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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291 | 358 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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292 | 359 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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293 | 360 | debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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294 | 361 | debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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295 | 362 | debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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296 | 363 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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297 | 364 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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298 | 365 | END COMPONENT; |
|
|
299 | 366 | |
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300 | 367 | COMPONENT lpp_top_ms |
|
|
301 | 368 | GENERIC ( |
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|
302 | 369 | Mem_use : INTEGER; |
|
|
303 | 370 | nb_burst_available_size : INTEGER; |
|
|
304 | 371 | nb_snapshot_param_size : INTEGER; |
|
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305 | 372 | delta_snapshot_size : INTEGER; |
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306 | 373 | delta_f2_f0_size : INTEGER; |
|
|
307 | 374 | delta_f2_f1_size : INTEGER; |
|
|
308 | 375 | pindex : INTEGER; |
|
|
309 | 376 | paddr : INTEGER; |
|
|
310 | 377 | pmask : INTEGER; |
|
|
311 | 378 | pirq_ms : INTEGER; |
|
|
312 | 379 | pirq_wfp : INTEGER; |
|
|
313 | 380 | hindex_wfp : INTEGER; |
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|
314 | 381 | hindex_ms : INTEGER); |
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315 | 382 | PORT ( |
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316 | 383 | clk : IN STD_LOGIC; |
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317 | 384 | rstn : IN STD_LOGIC; |
|
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318 | 385 | sample_B : IN Samples14v(2 DOWNTO 0); |
|
|
319 | 386 | sample_E : IN Samples14v(4 DOWNTO 0); |
|
|
320 | 387 | sample_val : IN STD_LOGIC; |
|
|
321 | 388 | apbi : IN apb_slv_in_type; |
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322 | 389 | apbo : OUT apb_slv_out_type; |
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323 | 390 | ahbi_ms : IN AHB_Mst_In_Type; |
|
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324 | 391 | ahbo_ms : OUT AHB_Mst_Out_Type; |
|
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325 | 392 | data_shaping_BW : OUT STD_LOGIC; |
|
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326 | 393 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
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327 | 394 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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328 | 395 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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329 | 396 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
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330 | 397 | |
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331 | 398 | ); |
|
|
332 | 399 | END COMPONENT; |
|
|
333 | 400 | |
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|
334 | 401 | END lpp_lfr_pkg; |
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