@@ -0,0 +1,36 | |||||
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1 | #GRLIB=../.. | |||
|
2 | TOP=leon3mp | |||
|
3 | BOARD=Projet-LeonLFR-A3P3K-Sheldon | |||
|
4 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |||
|
5 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
|
6 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |||
|
7 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
|
8 | EFFORT=high | |||
|
9 | XSTOPT= | |||
|
10 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
|
11 | VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd Top_Data_Acquisition.vhd | |||
|
12 | VHDLSIMFILES=testbench.vhd TB_Data_Acquisition.vhd | |||
|
13 | SIMTOP=testbench | |||
|
14 | SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |||
|
15 | SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |||
|
16 | PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc | |||
|
17 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |||
|
18 | CLEAN=soft-clean | |||
|
19 | ||||
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20 | TECHLIBS = proasic3 | |||
|
21 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
|
22 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
|
23 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
|
24 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 | |||
|
25 | ||||
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26 | FILESKIP = i2cmst.vhd | |||
|
27 | ||||
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28 | #TECHLIBS = unisim | |||
|
29 | include $(GRLIB)/bin/Makefile | |||
|
30 | include $(GRLIB)/software/leon3/Makefile | |||
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31 | ||||
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32 | my-clean: clean | |||
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33 | -rm -rf *~ | |||
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34 | ||||
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35 | ################## project specific targets ########################## | |||
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36 |
@@ -1,354 +1,355 | |||||
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1 | ||||
1 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
5 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
9 | -- |
|
10 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
14 | -- |
|
15 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
22 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
23 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
24 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
25 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
26 | LIBRARY ieee; |
|
27 | LIBRARY ieee; | |
27 | USE ieee.std_logic_1164.ALL; |
|
28 | USE ieee.std_logic_1164.ALL; | |
28 | USE ieee.numeric_std.ALL; |
|
29 | USE ieee.numeric_std.ALL; | |
29 | LIBRARY grlib; |
|
30 | LIBRARY grlib; | |
30 | USE grlib.amba.ALL; |
|
31 | USE grlib.amba.ALL; | |
31 | USE grlib.stdlib.ALL; |
|
32 | USE grlib.stdlib.ALL; | |
32 | USE grlib.devices.ALL; |
|
33 | USE grlib.devices.ALL; | |
33 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |
34 | --USE GRLIB.DMA2AHB_TestPackage.ALL; |
|
35 | --USE GRLIB.DMA2AHB_TestPackage.ALL; | |
35 | LIBRARY lpp; |
|
36 | LIBRARY lpp; | |
36 | USE lpp.lpp_amba.ALL; |
|
37 | USE lpp.lpp_amba.ALL; | |
37 | USE lpp.apb_devices_list.ALL; |
|
38 | USE lpp.apb_devices_list.ALL; | |
38 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
39 | USE lpp.lpp_dma_pkg.ALL; |
|
40 | USE lpp.lpp_dma_pkg.ALL; | |
40 | LIBRARY techmap; |
|
41 | LIBRARY techmap; | |
41 | USE techmap.gencomp.ALL; |
|
42 | USE techmap.gencomp.ALL; | |
42 |
|
43 | |||
43 |
|
44 | |||
44 | ENTITY lpp_dma_ip IS |
|
45 | ENTITY lpp_dma_ip IS | |
45 | GENERIC ( |
|
46 | GENERIC ( | |
46 | tech : INTEGER := inferred; |
|
47 | tech : INTEGER := inferred; | |
47 | hindex : INTEGER := 2; |
|
48 | hindex : INTEGER := 2; | |
48 | pindex : INTEGER := 4; |
|
49 | pindex : INTEGER := 4; | |
49 | paddr : INTEGER := 4; |
|
50 | paddr : INTEGER := 4; | |
50 | pmask : INTEGER := 16#fff#; |
|
51 | pmask : INTEGER := 16#fff#; | |
51 | pirq : INTEGER := 0); |
|
52 | pirq : INTEGER := 0); | |
52 | PORT ( |
|
53 | PORT ( | |
53 | -- AMBA AHB system signals |
|
54 | -- AMBA AHB system signals | |
54 | HCLK : IN STD_ULOGIC; |
|
55 | HCLK : IN STD_ULOGIC; | |
55 | HRESETn : IN STD_ULOGIC; |
|
56 | HRESETn : IN STD_ULOGIC; | |
56 |
|
57 | |||
57 | -- AMBA AHB Master Interface |
|
58 | -- AMBA AHB Master Interface | |
58 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
59 | AHB_Master_In : IN AHB_Mst_In_Type; | |
59 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
60 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
60 |
|
61 | |||
61 | -- fifo interface |
|
62 | -- fifo interface | |
62 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
63 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
63 | fifo_empty : IN STD_LOGIC; |
|
64 | fifo_empty : IN STD_LOGIC; | |
64 | fifo_ren : OUT STD_LOGIC; |
|
65 | fifo_ren : OUT STD_LOGIC; | |
65 |
|
66 | |||
66 | -- header |
|
67 | -- header | |
67 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
68 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
68 | header_val : IN STD_LOGIC; |
|
69 | header_val : IN STD_LOGIC; | |
69 | header_ack : OUT STD_LOGIC; |
|
70 | header_ack : OUT STD_LOGIC; | |
70 |
|
71 | |||
71 | -- Reg out |
|
72 | -- Reg out | |
72 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
73 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
73 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
74 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
74 | ready_matrix_f1 : OUT STD_LOGIC; |
|
75 | ready_matrix_f1 : OUT STD_LOGIC; | |
75 | ready_matrix_f2 : OUT STD_LOGIC; |
|
76 | ready_matrix_f2 : OUT STD_LOGIC; | |
76 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
77 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
77 | error_bad_component_error : OUT STD_LOGIC; |
|
78 | error_bad_component_error : OUT STD_LOGIC; | |
78 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
79 |
|
80 | |||
80 | -- Reg In |
|
81 | -- Reg In | |
81 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
|
82 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
82 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
|
83 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
83 | status_ready_matrix_f1 :IN STD_LOGIC; |
|
84 | status_ready_matrix_f1 :IN STD_LOGIC; | |
84 | status_ready_matrix_f2 :IN STD_LOGIC; |
|
85 | status_ready_matrix_f2 :IN STD_LOGIC; | |
85 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
|
86 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
86 | status_error_bad_component_error :IN STD_LOGIC; |
|
87 | status_error_bad_component_error :IN STD_LOGIC; | |
87 |
|
88 | |||
88 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
89 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
89 | config_active_interruption_onError : IN STD_LOGIC; |
|
90 | config_active_interruption_onError : IN STD_LOGIC; | |
90 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
93 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
94 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
94 | ); |
|
95 | ); | |
95 | END; |
|
96 | END; | |
96 |
|
97 | |||
97 | ARCHITECTURE Behavioral OF lpp_dma_ip IS |
|
98 | ARCHITECTURE Behavioral OF lpp_dma_ip IS | |
98 | ----------------------------------------------------------------------------- |
|
99 | ----------------------------------------------------------------------------- | |
99 | SIGNAL DMAIn : DMA_In_Type; |
|
100 | SIGNAL DMAIn : DMA_In_Type; | |
100 | SIGNAL header_dmai : DMA_In_Type; |
|
101 | SIGNAL header_dmai : DMA_In_Type; | |
101 | SIGNAL component_dmai : DMA_In_Type; |
|
102 | SIGNAL component_dmai : DMA_In_Type; | |
102 | SIGNAL DMAOut : DMA_OUt_Type; |
|
103 | SIGNAL DMAOut : DMA_OUt_Type; | |
103 | ----------------------------------------------------------------------------- |
|
104 | ----------------------------------------------------------------------------- | |
104 |
|
105 | |||
105 | ----------------------------------------------------------------------------- |
|
106 | ----------------------------------------------------------------------------- | |
106 | ----------------------------------------------------------------------------- |
|
107 | ----------------------------------------------------------------------------- | |
107 | TYPE state_DMAWriteBurst IS (IDLE, |
|
108 | TYPE state_DMAWriteBurst IS (IDLE, | |
108 | TRASH_FIFO, |
|
109 | TRASH_FIFO, | |
109 | WAIT_HEADER_ACK, |
|
110 | WAIT_HEADER_ACK, | |
110 | SEND_DATA, |
|
111 | SEND_DATA, | |
111 | WAIT_DATA_ACK, |
|
112 | WAIT_DATA_ACK, | |
112 | CHECK_LENGTH |
|
113 | CHECK_LENGTH | |
113 | ); |
|
114 | ); | |
114 | SIGNAL state : state_DMAWriteBurst := IDLE; |
|
115 | SIGNAL state : state_DMAWriteBurst := IDLE; | |
115 |
|
116 | |||
116 | SIGNAL nbSend : INTEGER; |
|
117 | SIGNAL nbSend : INTEGER; | |
117 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
118 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
118 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
119 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
119 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
120 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
120 | SIGNAL header_check_ok : STD_LOGIC; |
|
121 | SIGNAL header_check_ok : STD_LOGIC; | |
121 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
122 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
122 | SIGNAL send_matrix : STD_LOGIC; |
|
123 | SIGNAL send_matrix : STD_LOGIC; | |
123 | SIGNAL request : STD_LOGIC; |
|
124 | SIGNAL request : STD_LOGIC; | |
124 | SIGNAL remaining_data_request : INTEGER; |
|
125 | SIGNAL remaining_data_request : INTEGER; | |
125 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
126 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
126 | ----------------------------------------------------------------------------- |
|
127 | ----------------------------------------------------------------------------- | |
127 | ----------------------------------------------------------------------------- |
|
128 | ----------------------------------------------------------------------------- | |
128 | SIGNAL header_select : STD_LOGIC; |
|
129 | SIGNAL header_select : STD_LOGIC; | |
129 |
|
130 | |||
130 | SIGNAL header_send : STD_LOGIC; |
|
131 | SIGNAL header_send : STD_LOGIC; | |
131 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
132 | SIGNAL header_send_ok : STD_LOGIC; |
|
133 | SIGNAL header_send_ok : STD_LOGIC; | |
133 | SIGNAL header_send_ko : STD_LOGIC; |
|
134 | SIGNAL header_send_ko : STD_LOGIC; | |
134 |
|
135 | |||
135 | SIGNAL component_send : STD_LOGIC; |
|
136 | SIGNAL component_send : STD_LOGIC; | |
136 | SIGNAL component_send_ok : STD_LOGIC; |
|
137 | SIGNAL component_send_ok : STD_LOGIC; | |
137 | SIGNAL component_send_ko : STD_LOGIC; |
|
138 | SIGNAL component_send_ko : STD_LOGIC; | |
138 | ----------------------------------------------------------------------------- |
|
139 | ----------------------------------------------------------------------------- | |
139 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
140 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
140 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
141 | SIGNAL component_fifo_ren : STD_LOGIC; | |
141 |
|
142 | |||
142 | ----------------------------------------------------------------------------- |
|
143 | ----------------------------------------------------------------------------- | |
143 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
144 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
144 |
|
145 | |||
145 | BEGIN |
|
146 | BEGIN | |
146 |
|
147 | |||
147 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
148 | -- DMA to AHB interface |
|
149 | -- DMA to AHB interface | |
149 | ----------------------------------------------------------------------------- |
|
150 | ----------------------------------------------------------------------------- | |
150 |
|
151 | |||
151 | DMA2AHB_1 : DMA2AHB |
|
152 | DMA2AHB_1 : DMA2AHB | |
152 | GENERIC MAP ( |
|
153 | GENERIC MAP ( | |
153 | hindex => hindex, |
|
154 | hindex => hindex, | |
154 | vendorid => VENDOR_LPP, |
|
155 | vendorid => VENDOR_LPP, | |
155 | deviceid => 0, |
|
156 | deviceid => 0, | |
156 | version => 0, |
|
157 | version => 0, | |
157 | syncrst => 1, |
|
158 | syncrst => 1, | |
158 | boundary => 1) -- FIX 11/01/2013 |
|
159 | boundary => 1) -- FIX 11/01/2013 | |
159 | PORT MAP ( |
|
160 | PORT MAP ( | |
160 | HCLK => HCLK, |
|
161 | HCLK => HCLK, | |
161 | HRESETn => HRESETn, |
|
162 | HRESETn => HRESETn, | |
162 | DMAIn => DMAIn, |
|
163 | DMAIn => DMAIn, | |
163 | DMAOut => DMAOut, |
|
164 | DMAOut => DMAOut, | |
164 | AHBIn => AHB_Master_In, |
|
165 | AHBIn => AHB_Master_In, | |
165 | AHBOut => AHB_Master_Out); |
|
166 | AHBOut => AHB_Master_Out); | |
166 |
|
167 | |||
167 | debug_reg <= debug_reg_s; |
|
168 | debug_reg <= debug_reg_s; | |
168 |
|
169 | |||
169 | debug_info: PROCESS (HCLK, HRESETn) |
|
170 | debug_info: PROCESS (HCLK, HRESETn) | |
170 | BEGIN -- PROCESS debug_info |
|
171 | BEGIN -- PROCESS debug_info | |
171 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
172 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
172 | debug_reg <= (OTHERS => '0'); |
|
173 | debug_reg <= (OTHERS => '0'); | |
173 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
174 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
174 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); |
|
175 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); | |
175 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; |
|
176 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; | |
176 | IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF; |
|
177 | IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF; | |
177 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); |
|
178 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); | |
178 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); |
|
179 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); | |
179 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); |
|
180 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); | |
180 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); |
|
181 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); | |
181 |
|
182 | |||
182 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); |
|
183 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); | |
183 | END IF; |
|
184 | END IF; | |
184 | END PROCESS debug_info; |
|
185 | END PROCESS debug_info; | |
185 |
|
186 | |||
186 |
|
187 | |||
187 | matrix_type <= header(1 DOWNTO 0); |
|
188 | matrix_type <= header(1 DOWNTO 0); | |
188 | component_type <= header(5 DOWNTO 2); |
|
189 | component_type <= header(5 DOWNTO 2); | |
189 |
|
190 | |||
190 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
|
191 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
191 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
192 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
192 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
193 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
193 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
194 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
194 | '0'; |
|
195 | '0'; | |
195 |
|
196 | |||
196 | header_check_ok <= '0' WHEN component_type = "1111" ELSE |
|
197 | header_check_ok <= '0' WHEN component_type = "1111" ELSE | |
197 | '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE |
|
198 | '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE | |
198 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
199 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
199 | '0'; |
|
200 | '0'; | |
200 |
|
201 | |||
201 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
202 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
202 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
203 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
203 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
204 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
204 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
205 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
205 | (OTHERS => '0'); |
|
206 | (OTHERS => '0'); | |
206 |
|
207 | |||
207 | ----------------------------------------------------------------------------- |
|
208 | ----------------------------------------------------------------------------- | |
208 | -- DMA control |
|
209 | -- DMA control | |
209 | ----------------------------------------------------------------------------- |
|
210 | ----------------------------------------------------------------------------- | |
210 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
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211 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
211 | BEGIN -- PROCESS DMAWriteBurst_p |
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212 | BEGIN -- PROCESS DMAWriteBurst_p | |
212 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
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213 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
213 | state <= IDLE; |
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214 | state <= IDLE; | |
214 | header_ack <= '0'; |
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215 | header_ack <= '0'; | |
215 | ready_matrix_f0_0 <= '0'; |
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216 | ready_matrix_f0_0 <= '0'; | |
216 | ready_matrix_f0_1 <= '0'; |
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217 | ready_matrix_f0_1 <= '0'; | |
217 | ready_matrix_f1 <= '0'; |
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218 | ready_matrix_f1 <= '0'; | |
218 | ready_matrix_f2 <= '0'; |
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219 | ready_matrix_f2 <= '0'; | |
219 | error_anticipating_empty_fifo <= '0'; |
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220 | error_anticipating_empty_fifo <= '0'; | |
220 | error_bad_component_error <= '0'; |
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221 | error_bad_component_error <= '0'; | |
221 | component_type_pre <= "1110"; |
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222 | component_type_pre <= "1110"; | |
222 | fifo_ren_trash <= '1'; |
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223 | fifo_ren_trash <= '1'; | |
223 | component_send <= '0'; |
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224 | component_send <= '0'; | |
224 | address <= (OTHERS => '0'); |
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225 | address <= (OTHERS => '0'); | |
225 | header_select <= '0'; |
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226 | header_select <= '0'; | |
226 | header_send <= '0'; |
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227 | header_send <= '0'; | |
227 | header_data <= (OTHERS => '0'); |
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228 | header_data <= (OTHERS => '0'); | |
228 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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229 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
229 |
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230 | |||
230 | CASE state IS |
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231 | CASE state IS | |
231 | WHEN IDLE => |
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232 | WHEN IDLE => | |
232 | ready_matrix_f0_0 <= '0'; |
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233 | ready_matrix_f0_0 <= '0'; | |
233 | ready_matrix_f0_1 <= '0'; |
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234 | ready_matrix_f0_1 <= '0'; | |
234 | ready_matrix_f1 <= '0'; |
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235 | ready_matrix_f1 <= '0'; | |
235 | ready_matrix_f2 <= '0'; |
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236 | ready_matrix_f2 <= '0'; | |
236 | error_bad_component_error <= '0'; |
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237 | error_bad_component_error <= '0'; | |
237 | header_select <= '1'; |
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238 | header_select <= '1'; | |
238 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
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239 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
239 | IF header_check_ok = '1' THEN |
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240 | IF header_check_ok = '1' THEN | |
240 | header_data <= header; |
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241 | header_data <= header; | |
241 | component_type_pre <= header(5 DOWNTO 2); |
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242 | component_type_pre <= header(5 DOWNTO 2); | |
242 | header_ack <= '1'; |
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243 | header_ack <= '1'; | |
243 | -- |
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244 | -- | |
244 | header_send <= '1'; |
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245 | header_send <= '1'; | |
245 | IF component_type = "0000" THEN |
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246 | IF component_type = "0000" THEN | |
246 | address <= address_matrix; |
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247 | address <= address_matrix; | |
247 | END IF; |
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248 | END IF; | |
248 | header_data <= header; |
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249 | header_data <= header; | |
249 | -- |
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250 | -- | |
250 | state <= WAIT_HEADER_ACK; |
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251 | state <= WAIT_HEADER_ACK; | |
251 | ELSE |
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252 | ELSE | |
252 | error_bad_component_error <= '1'; |
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253 | error_bad_component_error <= '1'; | |
253 | component_type_pre <= "1110"; |
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254 | component_type_pre <= "1110"; | |
254 | header_ack <= '1'; |
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255 | header_ack <= '1'; | |
255 | state <= TRASH_FIFO; |
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256 | state <= TRASH_FIFO; | |
256 | END IF; |
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257 | END IF; | |
257 | END IF; |
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258 | END IF; | |
258 |
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259 | |||
259 | WHEN TRASH_FIFO => |
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260 | WHEN TRASH_FIFO => | |
260 | error_bad_component_error <= '0'; |
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261 | error_bad_component_error <= '0'; | |
261 | error_anticipating_empty_fifo <= '0'; |
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262 | error_anticipating_empty_fifo <= '0'; | |
262 | IF fifo_empty = '1' THEN |
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263 | IF fifo_empty = '1' THEN | |
263 | state <= IDLE; |
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264 | state <= IDLE; | |
264 | fifo_ren_trash <= '1'; |
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265 | fifo_ren_trash <= '1'; | |
265 | ELSE |
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266 | ELSE | |
266 | fifo_ren_trash <= '0'; |
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267 | fifo_ren_trash <= '0'; | |
267 | END IF; |
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268 | END IF; | |
268 |
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269 | |||
269 | WHEN WAIT_HEADER_ACK => |
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270 | WHEN WAIT_HEADER_ACK => | |
270 | header_send <= '0'; |
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271 | header_send <= '0'; | |
271 | IF header_send_ko = '1' THEN |
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272 | IF header_send_ko = '1' THEN | |
272 | state <= TRASH_FIFO; |
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273 | state <= TRASH_FIFO; | |
273 | error_anticipating_empty_fifo <= '1'; |
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274 | error_anticipating_empty_fifo <= '1'; | |
274 | -- TODO : error sending header |
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275 | -- TODO : error sending header | |
275 | ELSIF header_send_ok = '1' THEN |
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276 | ELSIF header_send_ok = '1' THEN | |
276 | header_select <= '0'; |
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277 | header_select <= '0'; | |
277 | state <= SEND_DATA; |
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278 | state <= SEND_DATA; | |
278 | address <= address + 4; |
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279 | address <= address + 4; | |
279 | END IF; |
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280 | END IF; | |
280 |
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281 | |||
281 | WHEN SEND_DATA => |
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282 | WHEN SEND_DATA => | |
282 | IF fifo_empty = '1' THEN |
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283 | IF fifo_empty = '1' THEN | |
283 | state <= IDLE; |
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284 | state <= IDLE; | |
284 | IF component_type = "1110" THEN |
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285 | IF component_type = "1110" THEN | |
285 | CASE matrix_type IS |
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286 | CASE matrix_type IS | |
286 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
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287 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
287 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
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288 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
288 | WHEN "10" => ready_matrix_f1 <= '1'; |
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289 | WHEN "10" => ready_matrix_f1 <= '1'; | |
289 | WHEN "11" => ready_matrix_f2 <= '1'; |
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290 | WHEN "11" => ready_matrix_f2 <= '1'; | |
290 | WHEN OTHERS => NULL; |
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291 | WHEN OTHERS => NULL; | |
291 | END CASE; |
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292 | END CASE; | |
292 | END IF; |
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293 | END IF; | |
293 | ELSE |
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294 | ELSE | |
294 | component_send <= '1'; |
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295 | component_send <= '1'; | |
295 | address <= address; |
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296 | address <= address; | |
296 | state <= WAIT_DATA_ACK; |
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297 | state <= WAIT_DATA_ACK; | |
297 | END IF; |
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298 | END IF; | |
298 |
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299 | |||
299 | WHEN WAIT_DATA_ACK => |
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300 | WHEN WAIT_DATA_ACK => | |
300 | component_send <= '0'; |
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301 | component_send <= '0'; | |
301 | IF component_send_ok = '1' THEN |
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302 | IF component_send_ok = '1' THEN | |
302 | address <= address + 64; |
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303 | address <= address + 64; | |
303 | state <= SEND_DATA; |
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304 | state <= SEND_DATA; | |
304 | ELSIF component_send_ko = '1' THEN |
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305 | ELSIF component_send_ko = '1' THEN | |
305 | error_anticipating_empty_fifo <= '0'; |
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306 | error_anticipating_empty_fifo <= '0'; | |
306 | state <= TRASH_FIFO; |
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307 | state <= TRASH_FIFO; | |
307 | END IF; |
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308 | END IF; | |
308 |
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309 | |||
309 | WHEN CHECK_LENGTH => |
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310 | WHEN CHECK_LENGTH => | |
310 | state <= IDLE; |
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311 | state <= IDLE; | |
311 | WHEN OTHERS => NULL; |
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312 | WHEN OTHERS => NULL; | |
312 | END CASE; |
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313 | END CASE; | |
313 |
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314 | |||
314 | END IF; |
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315 | END IF; | |
315 | END PROCESS DMAWriteFSM_p; |
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316 | END PROCESS DMAWriteFSM_p; | |
316 |
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317 | |||
317 | ----------------------------------------------------------------------------- |
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318 | ----------------------------------------------------------------------------- | |
318 | -- SEND 1 word by DMA |
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319 | -- SEND 1 word by DMA | |
319 | ----------------------------------------------------------------------------- |
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320 | ----------------------------------------------------------------------------- | |
320 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
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321 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |
321 | PORT MAP ( |
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322 | PORT MAP ( | |
322 | HCLK => HCLK, |
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323 | HCLK => HCLK, | |
323 | HRESETn => HRESETn, |
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324 | HRESETn => HRESETn, | |
324 | DMAIn => header_dmai, |
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325 | DMAIn => header_dmai, | |
325 | DMAOut => DMAOut, |
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326 | DMAOut => DMAOut, | |
326 |
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327 | |||
327 | send => header_send, |
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328 | send => header_send, | |
328 | address => address, |
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329 | address => address, | |
329 | data => header_data, |
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330 | data => header_data, | |
330 | send_ok => header_send_ok, |
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331 | send_ok => header_send_ok, | |
331 | send_ko => header_send_ko |
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332 | send_ko => header_send_ko | |
332 | ); |
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333 | ); | |
333 |
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334 | |||
334 | ----------------------------------------------------------------------------- |
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335 | ----------------------------------------------------------------------------- | |
335 | -- SEND 16 word by DMA (in burst mode) |
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336 | -- SEND 16 word by DMA (in burst mode) | |
336 | ----------------------------------------------------------------------------- |
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337 | ----------------------------------------------------------------------------- | |
337 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
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338 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
338 | PORT MAP ( |
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339 | PORT MAP ( | |
339 | HCLK => HCLK, |
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340 | HCLK => HCLK, | |
340 | HRESETn => HRESETn, |
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341 | HRESETn => HRESETn, | |
341 | DMAIn => component_dmai, |
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342 | DMAIn => component_dmai, | |
342 | DMAOut => DMAOut, |
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343 | DMAOut => DMAOut, | |
343 |
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344 | |||
344 | send => component_send, |
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345 | send => component_send, | |
345 | address => address, |
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346 | address => address, | |
346 | data => fifo_data, |
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347 | data => fifo_data, | |
347 | ren => component_fifo_ren, |
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348 | ren => component_fifo_ren, | |
348 | send_ok => component_send_ok, |
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349 | send_ok => component_send_ok, | |
349 | send_ko => component_send_ko); |
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350 | send_ko => component_send_ko); | |
350 |
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351 | |||
351 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; |
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352 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; | |
352 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; |
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353 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; | |
353 |
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354 | |||
354 | END Behavioral; |
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355 | END Behavioral; |
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