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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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--
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-- This program is free software; you can redistribute it and/or modify
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Author : Jean-christophe Pellion
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-- Author : Jean-christophe Pellion
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
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-- jean-christophe.pellion@easii-ic.com
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-- jean-christophe.pellion@easii-ic.com
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- 1.0 - initial version
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-- 1.0 - initial version
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-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
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-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY grlib;
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LIBRARY grlib;
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USE grlib.amba.ALL;
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USE grlib.amba.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.stdlib.ALL;
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USE grlib.devices.ALL;
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USE grlib.devices.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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USE GRLIB.DMA2AHB_Package.ALL;
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--USE GRLIB.DMA2AHB_TestPackage.ALL;
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--USE GRLIB.DMA2AHB_TestPackage.ALL;
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LIBRARY lpp;
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LIBRARY lpp;
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USE lpp.lpp_amba.ALL;
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USE lpp.lpp_amba.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.apb_devices_list.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_memory.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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USE lpp.lpp_dma_pkg.ALL;
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LIBRARY techmap;
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LIBRARY techmap;
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USE techmap.gencomp.ALL;
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USE techmap.gencomp.ALL;
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ENTITY lpp_dma_ip IS
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ENTITY lpp_dma_ip IS
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GENERIC (
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GENERIC (
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tech : INTEGER := inferred;
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tech : INTEGER := inferred;
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hindex : INTEGER := 2;
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hindex : INTEGER := 2;
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pindex : INTEGER := 4;
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pindex : INTEGER := 4;
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paddr : INTEGER := 4;
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paddr : INTEGER := 4;
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pmask : INTEGER := 16#fff#;
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pmask : INTEGER := 16#fff#;
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pirq : INTEGER := 0);
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pirq : INTEGER := 0);
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PORT (
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PORT (
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-- AMBA AHB system signals
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-- AMBA AHB system signals
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HCLK : IN STD_ULOGIC;
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HCLK : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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HRESETn : IN STD_ULOGIC;
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-- AMBA AHB Master Interface
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-- AMBA AHB Master Interface
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_In : IN AHB_Mst_In_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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AHB_Master_Out : OUT AHB_Mst_Out_Type;
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-- fifo interface
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-- fifo interface
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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fifo_empty : IN STD_LOGIC;
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fifo_empty : IN STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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fifo_ren : OUT STD_LOGIC;
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-- header
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-- header
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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header_val : IN STD_LOGIC;
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header_val : IN STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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header_ack : OUT STD_LOGIC;
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-- Reg out
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-- Reg out
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_0 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f0_1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f1 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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ready_matrix_f2 : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_anticipating_empty_fifo : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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error_bad_component_error : OUT STD_LOGIC;
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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-- Reg In
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-- Reg In
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status_ready_matrix_f0_0 :IN STD_LOGIC;
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status_ready_matrix_f0_0 :IN STD_LOGIC;
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status_ready_matrix_f0_1 :IN STD_LOGIC;
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status_ready_matrix_f0_1 :IN STD_LOGIC;
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status_ready_matrix_f1 :IN STD_LOGIC;
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status_ready_matrix_f1 :IN STD_LOGIC;
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status_ready_matrix_f2 :IN STD_LOGIC;
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status_ready_matrix_f2 :IN STD_LOGIC;
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status_error_anticipating_empty_fifo :IN STD_LOGIC;
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status_error_anticipating_empty_fifo :IN STD_LOGIC;
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status_error_bad_component_error :IN STD_LOGIC;
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status_error_bad_component_error :IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onNewMatrix : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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config_active_interruption_onError : IN STD_LOGIC;
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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);
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END;
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END;
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ARCHITECTURE Behavioral OF lpp_dma_ip IS
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ARCHITECTURE Behavioral OF lpp_dma_ip IS
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL DMAIn : DMA_In_Type;
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SIGNAL DMAIn : DMA_In_Type;
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SIGNAL header_dmai : DMA_In_Type;
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SIGNAL header_dmai : DMA_In_Type;
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SIGNAL component_dmai : DMA_In_Type;
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SIGNAL component_dmai : DMA_In_Type;
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SIGNAL DMAOut : DMA_OUt_Type;
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SIGNAL DMAOut : DMA_OUt_Type;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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TYPE state_DMAWriteBurst IS (IDLE,
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TYPE state_DMAWriteBurst IS (IDLE,
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TRASH_FIFO,
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TRASH_FIFO,
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WAIT_HEADER_ACK,
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WAIT_HEADER_ACK,
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SEND_DATA,
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SEND_DATA,
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WAIT_DATA_ACK,
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WAIT_DATA_ACK,
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CHECK_LENGTH
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CHECK_LENGTH
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);
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);
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SIGNAL state : state_DMAWriteBurst := IDLE;
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SIGNAL state : state_DMAWriteBurst := IDLE;
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SIGNAL nbSend : INTEGER;
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SIGNAL nbSend : INTEGER;
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SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL header_check_ok : STD_LOGIC;
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SIGNAL header_check_ok : STD_LOGIC;
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SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL send_matrix : STD_LOGIC;
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SIGNAL send_matrix : STD_LOGIC;
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SIGNAL request : STD_LOGIC;
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SIGNAL request : STD_LOGIC;
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SIGNAL remaining_data_request : INTEGER;
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SIGNAL remaining_data_request : INTEGER;
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SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL header_select : STD_LOGIC;
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SIGNAL header_select : STD_LOGIC;
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SIGNAL header_send : STD_LOGIC;
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SIGNAL header_send : STD_LOGIC;
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SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL header_send_ok : STD_LOGIC;
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SIGNAL header_send_ok : STD_LOGIC;
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SIGNAL header_send_ko : STD_LOGIC;
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SIGNAL header_send_ko : STD_LOGIC;
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SIGNAL component_send : STD_LOGIC;
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SIGNAL component_send : STD_LOGIC;
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SIGNAL component_send_ok : STD_LOGIC;
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SIGNAL component_send_ok : STD_LOGIC;
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SIGNAL component_send_ko : STD_LOGIC;
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SIGNAL component_send_ko : STD_LOGIC;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL fifo_ren_trash : STD_LOGIC;
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SIGNAL fifo_ren_trash : STD_LOGIC;
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SIGNAL component_fifo_ren : STD_LOGIC;
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SIGNAL component_fifo_ren : STD_LOGIC;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
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BEGIN
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BEGIN
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- DMA to AHB interface
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-- DMA to AHB interface
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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151
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DMA2AHB_1 : DMA2AHB
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DMA2AHB_1 : DMA2AHB
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GENERIC MAP (
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GENERIC MAP (
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hindex => hindex,
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hindex => hindex,
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vendorid => VENDOR_LPP,
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vendorid => VENDOR_LPP,
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deviceid => 0,
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deviceid => 0,
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version => 0,
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version => 0,
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syncrst => 1,
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syncrst => 1,
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boundary => 1) -- FIX 11/01/2013
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boundary => 1) -- FIX 11/01/2013
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PORT MAP (
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PORT MAP (
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HCLK => HCLK,
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HCLK => HCLK,
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HRESETn => HRESETn,
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HRESETn => HRESETn,
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DMAIn => DMAIn,
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DMAIn => DMAIn,
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DMAOut => DMAOut,
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DMAOut => DMAOut,
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AHBIn => AHB_Master_In,
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AHBIn => AHB_Master_In,
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AHBOut => AHB_Master_Out);
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AHBOut => AHB_Master_Out);
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166
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167
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167
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debug_reg <= debug_reg_s;
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debug_reg <= debug_reg_s;
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168
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169
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debug_info: PROCESS (HCLK, HRESETn)
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debug_info: PROCESS (HCLK, HRESETn)
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BEGIN -- PROCESS debug_info
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171
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BEGIN -- PROCESS debug_info
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171
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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172
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IF HRESETn = '0' THEN -- asynchronous reset (active low)
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172
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debug_reg <= (OTHERS => '0');
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173
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debug_reg <= (OTHERS => '0');
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173
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ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
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174
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ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
|
|
174
|
debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
|
|
175
|
debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
|
|
175
|
debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
|
|
176
|
debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
|
|
176
|
IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
|
|
177
|
IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
|
|
177
|
debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
|
|
178
|
debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
|
|
178
|
debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
|
|
179
|
debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
|
|
179
|
debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
|
|
180
|
debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
|
|
180
|
debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
|
|
181
|
debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
|
|
181
|
|
|
182
|
|
|
182
|
debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
|
|
183
|
debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
|
|
183
|
END IF;
|
|
184
|
END IF;
|
|
184
|
END PROCESS debug_info;
|
|
185
|
END PROCESS debug_info;
|
|
185
|
|
|
186
|
|
|
186
|
|
|
187
|
|
|
187
|
matrix_type <= header(1 DOWNTO 0);
|
|
188
|
matrix_type <= header(1 DOWNTO 0);
|
|
188
|
component_type <= header(5 DOWNTO 2);
|
|
189
|
component_type <= header(5 DOWNTO 2);
|
|
189
|
|
|
190
|
|
|
190
|
send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
|
|
191
|
send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
|
|
191
|
'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
|
|
192
|
'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
|
|
192
|
'1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
|
|
193
|
'1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
|
|
193
|
'1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
|
|
194
|
'1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
|
|
194
|
'0';
|
|
195
|
'0';
|
|
195
|
|
|
196
|
|
|
196
|
header_check_ok <= '0' WHEN component_type = "1111" ELSE
|
|
197
|
header_check_ok <= '0' WHEN component_type = "1111" ELSE
|
|
197
|
'1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
|
|
198
|
'1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
|
|
198
|
'1' WHEN component_type = component_type_pre + "0001" ELSE
|
|
199
|
'1' WHEN component_type = component_type_pre + "0001" ELSE
|
|
199
|
'0';
|
|
200
|
'0';
|
|
200
|
|
|
201
|
|
|
201
|
address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
|
|
202
|
address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
|
|
202
|
addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
|
|
203
|
addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
|
|
203
|
addr_matrix_f1 WHEN matrix_type = "10" ELSE
|
|
204
|
addr_matrix_f1 WHEN matrix_type = "10" ELSE
|
|
204
|
addr_matrix_f2 WHEN matrix_type = "11" ELSE
|
|
205
|
addr_matrix_f2 WHEN matrix_type = "11" ELSE
|
|
205
|
(OTHERS => '0');
|
|
206
|
(OTHERS => '0');
|
|
206
|
|
|
207
|
|
|
207
|
-----------------------------------------------------------------------------
|
|
208
|
-----------------------------------------------------------------------------
|
|
208
|
-- DMA control
|
|
209
|
-- DMA control
|
|
209
|
-----------------------------------------------------------------------------
|
|
210
|
-----------------------------------------------------------------------------
|
|
210
|
DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
|
|
211
|
DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
|
|
211
|
BEGIN -- PROCESS DMAWriteBurst_p
|
|
212
|
BEGIN -- PROCESS DMAWriteBurst_p
|
|
212
|
IF HRESETn = '0' THEN -- asynchronous reset (active low)
|
|
213
|
IF HRESETn = '0' THEN -- asynchronous reset (active low)
|
|
213
|
state <= IDLE;
|
|
214
|
state <= IDLE;
|
|
214
|
header_ack <= '0';
|
|
215
|
header_ack <= '0';
|
|
215
|
ready_matrix_f0_0 <= '0';
|
|
216
|
ready_matrix_f0_0 <= '0';
|
|
216
|
ready_matrix_f0_1 <= '0';
|
|
217
|
ready_matrix_f0_1 <= '0';
|
|
217
|
ready_matrix_f1 <= '0';
|
|
218
|
ready_matrix_f1 <= '0';
|
|
218
|
ready_matrix_f2 <= '0';
|
|
219
|
ready_matrix_f2 <= '0';
|
|
219
|
error_anticipating_empty_fifo <= '0';
|
|
220
|
error_anticipating_empty_fifo <= '0';
|
|
220
|
error_bad_component_error <= '0';
|
|
221
|
error_bad_component_error <= '0';
|
|
221
|
component_type_pre <= "1110";
|
|
222
|
component_type_pre <= "1110";
|
|
222
|
fifo_ren_trash <= '1';
|
|
223
|
fifo_ren_trash <= '1';
|
|
223
|
component_send <= '0';
|
|
224
|
component_send <= '0';
|
|
224
|
address <= (OTHERS => '0');
|
|
225
|
address <= (OTHERS => '0');
|
|
225
|
header_select <= '0';
|
|
226
|
header_select <= '0';
|
|
226
|
header_send <= '0';
|
|
227
|
header_send <= '0';
|
|
227
|
header_data <= (OTHERS => '0');
|
|
228
|
header_data <= (OTHERS => '0');
|
|
228
|
ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
|
|
229
|
ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
|
|
229
|
|
|
230
|
|
|
230
|
CASE state IS
|
|
231
|
CASE state IS
|
|
231
|
WHEN IDLE =>
|
|
232
|
WHEN IDLE =>
|
|
232
|
ready_matrix_f0_0 <= '0';
|
|
233
|
ready_matrix_f0_0 <= '0';
|
|
233
|
ready_matrix_f0_1 <= '0';
|
|
234
|
ready_matrix_f0_1 <= '0';
|
|
234
|
ready_matrix_f1 <= '0';
|
|
235
|
ready_matrix_f1 <= '0';
|
|
235
|
ready_matrix_f2 <= '0';
|
|
236
|
ready_matrix_f2 <= '0';
|
|
236
|
error_bad_component_error <= '0';
|
|
237
|
error_bad_component_error <= '0';
|
|
237
|
header_select <= '1';
|
|
238
|
header_select <= '1';
|
|
238
|
IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
|
|
239
|
IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
|
|
239
|
IF header_check_ok = '1' THEN
|
|
240
|
IF header_check_ok = '1' THEN
|
|
240
|
header_data <= header;
|
|
241
|
header_data <= header;
|
|
241
|
component_type_pre <= header(5 DOWNTO 2);
|
|
242
|
component_type_pre <= header(5 DOWNTO 2);
|
|
242
|
header_ack <= '1';
|
|
243
|
header_ack <= '1';
|
|
243
|
--
|
|
244
|
--
|
|
244
|
header_send <= '1';
|
|
245
|
header_send <= '1';
|
|
245
|
IF component_type = "0000" THEN
|
|
246
|
IF component_type = "0000" THEN
|
|
246
|
address <= address_matrix;
|
|
247
|
address <= address_matrix;
|
|
247
|
END IF;
|
|
248
|
END IF;
|
|
248
|
header_data <= header;
|
|
249
|
header_data <= header;
|
|
249
|
--
|
|
250
|
--
|
|
250
|
state <= WAIT_HEADER_ACK;
|
|
251
|
state <= WAIT_HEADER_ACK;
|
|
251
|
ELSE
|
|
252
|
ELSE
|
|
252
|
error_bad_component_error <= '1';
|
|
253
|
error_bad_component_error <= '1';
|
|
253
|
component_type_pre <= "1110";
|
|
254
|
component_type_pre <= "1110";
|
|
254
|
header_ack <= '1';
|
|
255
|
header_ack <= '1';
|
|
255
|
state <= TRASH_FIFO;
|
|
256
|
state <= TRASH_FIFO;
|
|
256
|
END IF;
|
|
257
|
END IF;
|
|
257
|
END IF;
|
|
258
|
END IF;
|
|
258
|
|
|
259
|
|
|
259
|
WHEN TRASH_FIFO =>
|
|
260
|
WHEN TRASH_FIFO =>
|
|
260
|
error_bad_component_error <= '0';
|
|
261
|
error_bad_component_error <= '0';
|
|
261
|
error_anticipating_empty_fifo <= '0';
|
|
262
|
error_anticipating_empty_fifo <= '0';
|
|
262
|
IF fifo_empty = '1' THEN
|
|
263
|
IF fifo_empty = '1' THEN
|
|
263
|
state <= IDLE;
|
|
264
|
state <= IDLE;
|
|
264
|
fifo_ren_trash <= '1';
|
|
265
|
fifo_ren_trash <= '1';
|
|
265
|
ELSE
|
|
266
|
ELSE
|
|
266
|
fifo_ren_trash <= '0';
|
|
267
|
fifo_ren_trash <= '0';
|
|
267
|
END IF;
|
|
268
|
END IF;
|
|
268
|
|
|
269
|
|
|
269
|
WHEN WAIT_HEADER_ACK =>
|
|
270
|
WHEN WAIT_HEADER_ACK =>
|
|
270
|
header_send <= '0';
|
|
271
|
header_send <= '0';
|
|
271
|
IF header_send_ko = '1' THEN
|
|
272
|
IF header_send_ko = '1' THEN
|
|
272
|
state <= TRASH_FIFO;
|
|
273
|
state <= TRASH_FIFO;
|
|
273
|
error_anticipating_empty_fifo <= '1';
|
|
274
|
error_anticipating_empty_fifo <= '1';
|
|
274
|
-- TODO : error sending header
|
|
275
|
-- TODO : error sending header
|
|
275
|
ELSIF header_send_ok = '1' THEN
|
|
276
|
ELSIF header_send_ok = '1' THEN
|
|
276
|
header_select <= '0';
|
|
277
|
header_select <= '0';
|
|
277
|
state <= SEND_DATA;
|
|
278
|
state <= SEND_DATA;
|
|
278
|
address <= address + 4;
|
|
279
|
address <= address + 4;
|
|
279
|
END IF;
|
|
280
|
END IF;
|
|
280
|
|
|
281
|
|
|
281
|
WHEN SEND_DATA =>
|
|
282
|
WHEN SEND_DATA =>
|
|
282
|
IF fifo_empty = '1' THEN
|
|
283
|
IF fifo_empty = '1' THEN
|
|
283
|
state <= IDLE;
|
|
284
|
state <= IDLE;
|
|
284
|
IF component_type = "1110" THEN
|
|
285
|
IF component_type = "1110" THEN
|
|
285
|
CASE matrix_type IS
|
|
286
|
CASE matrix_type IS
|
|
286
|
WHEN "00" => ready_matrix_f0_0 <= '1';
|
|
287
|
WHEN "00" => ready_matrix_f0_0 <= '1';
|
|
287
|
WHEN "01" => ready_matrix_f0_1 <= '1';
|
|
288
|
WHEN "01" => ready_matrix_f0_1 <= '1';
|
|
288
|
WHEN "10" => ready_matrix_f1 <= '1';
|
|
289
|
WHEN "10" => ready_matrix_f1 <= '1';
|
|
289
|
WHEN "11" => ready_matrix_f2 <= '1';
|
|
290
|
WHEN "11" => ready_matrix_f2 <= '1';
|
|
290
|
WHEN OTHERS => NULL;
|
|
291
|
WHEN OTHERS => NULL;
|
|
291
|
END CASE;
|
|
292
|
END CASE;
|
|
292
|
END IF;
|
|
293
|
END IF;
|
|
293
|
ELSE
|
|
294
|
ELSE
|
|
294
|
component_send <= '1';
|
|
295
|
component_send <= '1';
|
|
295
|
address <= address;
|
|
296
|
address <= address;
|
|
296
|
state <= WAIT_DATA_ACK;
|
|
297
|
state <= WAIT_DATA_ACK;
|
|
297
|
END IF;
|
|
298
|
END IF;
|
|
298
|
|
|
299
|
|
|
299
|
WHEN WAIT_DATA_ACK =>
|
|
300
|
WHEN WAIT_DATA_ACK =>
|
|
300
|
component_send <= '0';
|
|
301
|
component_send <= '0';
|
|
301
|
IF component_send_ok = '1' THEN
|
|
302
|
IF component_send_ok = '1' THEN
|
|
302
|
address <= address + 64;
|
|
303
|
address <= address + 64;
|
|
303
|
state <= SEND_DATA;
|
|
304
|
state <= SEND_DATA;
|
|
304
|
ELSIF component_send_ko = '1' THEN
|
|
305
|
ELSIF component_send_ko = '1' THEN
|
|
305
|
error_anticipating_empty_fifo <= '0';
|
|
306
|
error_anticipating_empty_fifo <= '0';
|
|
306
|
state <= TRASH_FIFO;
|
|
307
|
state <= TRASH_FIFO;
|
|
307
|
END IF;
|
|
308
|
END IF;
|
|
308
|
|
|
309
|
|
|
309
|
WHEN CHECK_LENGTH =>
|
|
310
|
WHEN CHECK_LENGTH =>
|
|
310
|
state <= IDLE;
|
|
311
|
state <= IDLE;
|
|
311
|
WHEN OTHERS => NULL;
|
|
312
|
WHEN OTHERS => NULL;
|
|
312
|
END CASE;
|
|
313
|
END CASE;
|
|
313
|
|
|
314
|
|
|
314
|
END IF;
|
|
315
|
END IF;
|
|
315
|
END PROCESS DMAWriteFSM_p;
|
|
316
|
END PROCESS DMAWriteFSM_p;
|
|
316
|
|
|
317
|
|
|
317
|
-----------------------------------------------------------------------------
|
|
318
|
-----------------------------------------------------------------------------
|
|
318
|
-- SEND 1 word by DMA
|
|
319
|
-- SEND 1 word by DMA
|
|
319
|
-----------------------------------------------------------------------------
|
|
320
|
-----------------------------------------------------------------------------
|
|
320
|
lpp_dma_send_1word_1 : lpp_dma_send_1word
|
|
321
|
lpp_dma_send_1word_1 : lpp_dma_send_1word
|
|
321
|
PORT MAP (
|
|
322
|
PORT MAP (
|
|
322
|
HCLK => HCLK,
|
|
323
|
HCLK => HCLK,
|
|
323
|
HRESETn => HRESETn,
|
|
324
|
HRESETn => HRESETn,
|
|
324
|
DMAIn => header_dmai,
|
|
325
|
DMAIn => header_dmai,
|
|
325
|
DMAOut => DMAOut,
|
|
326
|
DMAOut => DMAOut,
|
|
326
|
|
|
327
|
|
|
327
|
send => header_send,
|
|
328
|
send => header_send,
|
|
328
|
address => address,
|
|
329
|
address => address,
|
|
329
|
data => header_data,
|
|
330
|
data => header_data,
|
|
330
|
send_ok => header_send_ok,
|
|
331
|
send_ok => header_send_ok,
|
|
331
|
send_ko => header_send_ko
|
|
332
|
send_ko => header_send_ko
|
|
332
|
);
|
|
333
|
);
|
|
333
|
|
|
334
|
|
|
334
|
-----------------------------------------------------------------------------
|
|
335
|
-----------------------------------------------------------------------------
|
|
335
|
-- SEND 16 word by DMA (in burst mode)
|
|
336
|
-- SEND 16 word by DMA (in burst mode)
|
|
336
|
-----------------------------------------------------------------------------
|
|
337
|
-----------------------------------------------------------------------------
|
|
337
|
lpp_dma_send_16word_1 : lpp_dma_send_16word
|
|
338
|
lpp_dma_send_16word_1 : lpp_dma_send_16word
|
|
338
|
PORT MAP (
|
|
339
|
PORT MAP (
|
|
339
|
HCLK => HCLK,
|
|
340
|
HCLK => HCLK,
|
|
340
|
HRESETn => HRESETn,
|
|
341
|
HRESETn => HRESETn,
|
|
341
|
DMAIn => component_dmai,
|
|
342
|
DMAIn => component_dmai,
|
|
342
|
DMAOut => DMAOut,
|
|
343
|
DMAOut => DMAOut,
|
|
343
|
|
|
344
|
|
|
344
|
send => component_send,
|
|
345
|
send => component_send,
|
|
345
|
address => address,
|
|
346
|
address => address,
|
|
346
|
data => fifo_data,
|
|
347
|
data => fifo_data,
|
|
347
|
ren => component_fifo_ren,
|
|
348
|
ren => component_fifo_ren,
|
|
348
|
send_ok => component_send_ok,
|
|
349
|
send_ok => component_send_ok,
|
|
349
|
send_ko => component_send_ko);
|
|
350
|
send_ko => component_send_ko);
|
|
350
|
|
|
351
|
|
|
351
|
DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
|
|
352
|
DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
|
|
352
|
fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
|
|
353
|
fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
|
|
353
|
|
|
354
|
|
|
354
|
END Behavioral;
|
|
355
|
END Behavioral;
|