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1 #GRLIB=../..
2 TOP=leon3mp
3 BOARD=Projet-LeonLFR-A3P3K-Sheldon
4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8 EFFORT=high
9 XSTOPT=
10 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
11 VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd Top_Data_Acquisition.vhd
12 VHDLSIMFILES=testbench.vhd TB_Data_Acquisition.vhd
13 SIMTOP=testbench
14 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
15 SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
16 PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc
17 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
18 CLEAN=soft-clean
19
20 TECHLIBS = proasic3
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs pwm coremp7 spi ac97
25
26 FILESKIP = i2cmst.vhd
27
28 #TECHLIBS = unisim
29 include $(GRLIB)/bin/Makefile
30 include $(GRLIB)/software/leon3/Makefile
31
32 my-clean: clean
33 -rm -rf *~
34
35 ################## project specific targets ##########################
36
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1 1 GRLIB=../..
2 2 TOP=top
3 3 BOARD=Projet-LeonLFR-A3P3K-Sheldon
4 4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5 5 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6 6 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7 7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8 8 EFFORT=high
9 9 XSTOPT=
10 10 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
11 11 VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
12 VHDLSIMFILES=testbench.vhd
12 VHDLSIMFILES=testbench.vhd
13 13 SIMTOP=testbench
14 14 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
15 15 SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
16 16 PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc
17 17 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
18 18 CLEAN=soft-clean
19 19
20 20 TECHLIBS = proasic3
21 21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 22 tmtc openchip hynix ihp gleichmann micron usbhc
23 23 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 24 pci grusbhc haps slink ascs pwm coremp7 spi ac97
25 25
26 26 FILESKIP = i2cmst.vhd
27 27
28 28 include $(GRLIB)/bin/Makefile
29 29 include $(GRLIB)/software/leon3/Makefile
30 30
31 31 ################## project specific targets ##########################
32 32
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1
1 2 ------------------------------------------------------------------------------
2 3 -- This file is a part of the LPP VHDL IP LIBRARY
3 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 5 --
5 6 -- This program is free software; you can redistribute it and/or modify
6 7 -- it under the terms of the GNU General Public License as published by
7 8 -- the Free Software Foundation; either version 3 of the License, or
8 9 -- (at your option) any later version.
9 10 --
10 11 -- This program is distributed in the hope that it will be useful,
11 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 14 -- GNU General Public License for more details.
14 15 --
15 16 -- You should have received a copy of the GNU General Public License
16 17 -- along with this program; if not, write to the Free Software
17 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 19 -------------------------------------------------------------------------------
19 20 -- Author : Jean-christophe Pellion
20 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 22 -- jean-christophe.pellion@easii-ic.com
22 23 -------------------------------------------------------------------------------
23 24 -- 1.0 - initial version
24 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 26 -------------------------------------------------------------------------------
26 27 LIBRARY ieee;
27 28 USE ieee.std_logic_1164.ALL;
28 29 USE ieee.numeric_std.ALL;
29 30 LIBRARY grlib;
30 31 USE grlib.amba.ALL;
31 32 USE grlib.stdlib.ALL;
32 33 USE grlib.devices.ALL;
33 34 USE GRLIB.DMA2AHB_Package.ALL;
34 35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 36 LIBRARY lpp;
36 37 USE lpp.lpp_amba.ALL;
37 38 USE lpp.apb_devices_list.ALL;
38 39 USE lpp.lpp_memory.ALL;
39 40 USE lpp.lpp_dma_pkg.ALL;
40 41 LIBRARY techmap;
41 42 USE techmap.gencomp.ALL;
42 43
43 44
44 45 ENTITY lpp_dma_ip IS
45 46 GENERIC (
46 47 tech : INTEGER := inferred;
47 48 hindex : INTEGER := 2;
48 49 pindex : INTEGER := 4;
49 50 paddr : INTEGER := 4;
50 51 pmask : INTEGER := 16#fff#;
51 52 pirq : INTEGER := 0);
52 53 PORT (
53 54 -- AMBA AHB system signals
54 55 HCLK : IN STD_ULOGIC;
55 56 HRESETn : IN STD_ULOGIC;
56 57
57 58 -- AMBA AHB Master Interface
58 59 AHB_Master_In : IN AHB_Mst_In_Type;
59 60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60 61
61 62 -- fifo interface
62 63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 64 fifo_empty : IN STD_LOGIC;
64 65 fifo_ren : OUT STD_LOGIC;
65 66
66 67 -- header
67 68 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 69 header_val : IN STD_LOGIC;
69 70 header_ack : OUT STD_LOGIC;
70 71
71 72 -- Reg out
72 73 ready_matrix_f0_0 : OUT STD_LOGIC;
73 74 ready_matrix_f0_1 : OUT STD_LOGIC;
74 75 ready_matrix_f1 : OUT STD_LOGIC;
75 76 ready_matrix_f2 : OUT STD_LOGIC;
76 77 error_anticipating_empty_fifo : OUT STD_LOGIC;
77 78 error_bad_component_error : OUT STD_LOGIC;
78 79 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 80
80 81 -- Reg In
81 82 status_ready_matrix_f0_0 :IN STD_LOGIC;
82 83 status_ready_matrix_f0_1 :IN STD_LOGIC;
83 84 status_ready_matrix_f1 :IN STD_LOGIC;
84 85 status_ready_matrix_f2 :IN STD_LOGIC;
85 86 status_error_anticipating_empty_fifo :IN STD_LOGIC;
86 87 status_error_bad_component_error :IN STD_LOGIC;
87 88
88 89 config_active_interruption_onNewMatrix : IN STD_LOGIC;
89 90 config_active_interruption_onError : IN STD_LOGIC;
90 91 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 92 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 93 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 94 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
94 95 );
95 96 END;
96 97
97 98 ARCHITECTURE Behavioral OF lpp_dma_ip IS
98 99 -----------------------------------------------------------------------------
99 100 SIGNAL DMAIn : DMA_In_Type;
100 101 SIGNAL header_dmai : DMA_In_Type;
101 102 SIGNAL component_dmai : DMA_In_Type;
102 103 SIGNAL DMAOut : DMA_OUt_Type;
103 104 -----------------------------------------------------------------------------
104 105
105 106 -----------------------------------------------------------------------------
106 107 -----------------------------------------------------------------------------
107 108 TYPE state_DMAWriteBurst IS (IDLE,
108 109 TRASH_FIFO,
109 110 WAIT_HEADER_ACK,
110 111 SEND_DATA,
111 112 WAIT_DATA_ACK,
112 113 CHECK_LENGTH
113 114 );
114 115 SIGNAL state : state_DMAWriteBurst := IDLE;
115 116
116 117 SIGNAL nbSend : INTEGER;
117 118 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 119 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 120 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 121 SIGNAL header_check_ok : STD_LOGIC;
121 122 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 123 SIGNAL send_matrix : STD_LOGIC;
123 124 SIGNAL request : STD_LOGIC;
124 125 SIGNAL remaining_data_request : INTEGER;
125 126 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 127 -----------------------------------------------------------------------------
127 128 -----------------------------------------------------------------------------
128 129 SIGNAL header_select : STD_LOGIC;
129 130
130 131 SIGNAL header_send : STD_LOGIC;
131 132 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 133 SIGNAL header_send_ok : STD_LOGIC;
133 134 SIGNAL header_send_ko : STD_LOGIC;
134 135
135 136 SIGNAL component_send : STD_LOGIC;
136 137 SIGNAL component_send_ok : STD_LOGIC;
137 138 SIGNAL component_send_ko : STD_LOGIC;
138 139 -----------------------------------------------------------------------------
139 140 SIGNAL fifo_ren_trash : STD_LOGIC;
140 141 SIGNAL component_fifo_ren : STD_LOGIC;
141 142
142 143 -----------------------------------------------------------------------------
143 144 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 145
145 146 BEGIN
146 147
147 148 -----------------------------------------------------------------------------
148 149 -- DMA to AHB interface
149 150 -----------------------------------------------------------------------------
150 151
151 152 DMA2AHB_1 : DMA2AHB
152 153 GENERIC MAP (
153 154 hindex => hindex,
154 155 vendorid => VENDOR_LPP,
155 156 deviceid => 0,
156 157 version => 0,
157 158 syncrst => 1,
158 159 boundary => 1) -- FIX 11/01/2013
159 160 PORT MAP (
160 161 HCLK => HCLK,
161 162 HRESETn => HRESETn,
162 163 DMAIn => DMAIn,
163 164 DMAOut => DMAOut,
164 165 AHBIn => AHB_Master_In,
165 166 AHBOut => AHB_Master_Out);
166 167
167 168 debug_reg <= debug_reg_s;
168 169
169 170 debug_info: PROCESS (HCLK, HRESETn)
170 171 BEGIN -- PROCESS debug_info
171 172 IF HRESETn = '0' THEN -- asynchronous reset (active low)
172 173 debug_reg <= (OTHERS => '0');
173 174 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
174 175 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
175 176 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
176 177 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
177 178 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
178 179 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
179 180 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
180 181 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
181 182
182 183 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
183 184 END IF;
184 185 END PROCESS debug_info;
185 186
186 187
187 188 matrix_type <= header(1 DOWNTO 0);
188 189 component_type <= header(5 DOWNTO 2);
189 190
190 191 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
191 192 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
192 193 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
193 194 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
194 195 '0';
195 196
196 197 header_check_ok <= '0' WHEN component_type = "1111" ELSE
197 198 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
198 199 '1' WHEN component_type = component_type_pre + "0001" ELSE
199 200 '0';
200 201
201 202 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
202 203 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
203 204 addr_matrix_f1 WHEN matrix_type = "10" ELSE
204 205 addr_matrix_f2 WHEN matrix_type = "11" ELSE
205 206 (OTHERS => '0');
206 207
207 208 -----------------------------------------------------------------------------
208 209 -- DMA control
209 210 -----------------------------------------------------------------------------
210 211 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
211 212 BEGIN -- PROCESS DMAWriteBurst_p
212 213 IF HRESETn = '0' THEN -- asynchronous reset (active low)
213 214 state <= IDLE;
214 215 header_ack <= '0';
215 216 ready_matrix_f0_0 <= '0';
216 217 ready_matrix_f0_1 <= '0';
217 218 ready_matrix_f1 <= '0';
218 219 ready_matrix_f2 <= '0';
219 220 error_anticipating_empty_fifo <= '0';
220 221 error_bad_component_error <= '0';
221 222 component_type_pre <= "1110";
222 223 fifo_ren_trash <= '1';
223 224 component_send <= '0';
224 225 address <= (OTHERS => '0');
225 226 header_select <= '0';
226 227 header_send <= '0';
227 228 header_data <= (OTHERS => '0');
228 229 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
229 230
230 231 CASE state IS
231 232 WHEN IDLE =>
232 233 ready_matrix_f0_0 <= '0';
233 234 ready_matrix_f0_1 <= '0';
234 235 ready_matrix_f1 <= '0';
235 236 ready_matrix_f2 <= '0';
236 237 error_bad_component_error <= '0';
237 238 header_select <= '1';
238 239 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
239 240 IF header_check_ok = '1' THEN
240 241 header_data <= header;
241 242 component_type_pre <= header(5 DOWNTO 2);
242 243 header_ack <= '1';
243 244 --
244 245 header_send <= '1';
245 246 IF component_type = "0000" THEN
246 247 address <= address_matrix;
247 248 END IF;
248 249 header_data <= header;
249 250 --
250 251 state <= WAIT_HEADER_ACK;
251 252 ELSE
252 253 error_bad_component_error <= '1';
253 254 component_type_pre <= "1110";
254 255 header_ack <= '1';
255 256 state <= TRASH_FIFO;
256 257 END IF;
257 258 END IF;
258 259
259 260 WHEN TRASH_FIFO =>
260 261 error_bad_component_error <= '0';
261 262 error_anticipating_empty_fifo <= '0';
262 263 IF fifo_empty = '1' THEN
263 264 state <= IDLE;
264 265 fifo_ren_trash <= '1';
265 266 ELSE
266 267 fifo_ren_trash <= '0';
267 268 END IF;
268 269
269 270 WHEN WAIT_HEADER_ACK =>
270 271 header_send <= '0';
271 272 IF header_send_ko = '1' THEN
272 273 state <= TRASH_FIFO;
273 274 error_anticipating_empty_fifo <= '1';
274 275 -- TODO : error sending header
275 276 ELSIF header_send_ok = '1' THEN
276 277 header_select <= '0';
277 278 state <= SEND_DATA;
278 279 address <= address + 4;
279 280 END IF;
280 281
281 282 WHEN SEND_DATA =>
282 283 IF fifo_empty = '1' THEN
283 284 state <= IDLE;
284 285 IF component_type = "1110" THEN
285 286 CASE matrix_type IS
286 287 WHEN "00" => ready_matrix_f0_0 <= '1';
287 288 WHEN "01" => ready_matrix_f0_1 <= '1';
288 289 WHEN "10" => ready_matrix_f1 <= '1';
289 290 WHEN "11" => ready_matrix_f2 <= '1';
290 291 WHEN OTHERS => NULL;
291 292 END CASE;
292 293 END IF;
293 294 ELSE
294 295 component_send <= '1';
295 296 address <= address;
296 297 state <= WAIT_DATA_ACK;
297 298 END IF;
298 299
299 300 WHEN WAIT_DATA_ACK =>
300 301 component_send <= '0';
301 302 IF component_send_ok = '1' THEN
302 303 address <= address + 64;
303 304 state <= SEND_DATA;
304 305 ELSIF component_send_ko = '1' THEN
305 306 error_anticipating_empty_fifo <= '0';
306 307 state <= TRASH_FIFO;
307 308 END IF;
308 309
309 310 WHEN CHECK_LENGTH =>
310 311 state <= IDLE;
311 312 WHEN OTHERS => NULL;
312 313 END CASE;
313 314
314 315 END IF;
315 316 END PROCESS DMAWriteFSM_p;
316 317
317 318 -----------------------------------------------------------------------------
318 319 -- SEND 1 word by DMA
319 320 -----------------------------------------------------------------------------
320 321 lpp_dma_send_1word_1 : lpp_dma_send_1word
321 322 PORT MAP (
322 323 HCLK => HCLK,
323 324 HRESETn => HRESETn,
324 325 DMAIn => header_dmai,
325 326 DMAOut => DMAOut,
326 327
327 328 send => header_send,
328 329 address => address,
329 330 data => header_data,
330 331 send_ok => header_send_ok,
331 332 send_ko => header_send_ko
332 333 );
333 334
334 335 -----------------------------------------------------------------------------
335 336 -- SEND 16 word by DMA (in burst mode)
336 337 -----------------------------------------------------------------------------
337 338 lpp_dma_send_16word_1 : lpp_dma_send_16word
338 339 PORT MAP (
339 340 HCLK => HCLK,
340 341 HRESETn => HRESETn,
341 342 DMAIn => component_dmai,
342 343 DMAOut => DMAOut,
343 344
344 345 send => component_send,
345 346 address => address,
346 347 data => fifo_data,
347 348 ren => component_fifo_ren,
348 349 send_ok => component_send_ok,
349 350 send_ko => component_send_ko);
350 351
351 352 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
352 353 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
353 354
354 355 END Behavioral;
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