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1 | #GRLIB=../.. | |||
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2 | TOP=leon3mp | |||
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3 | BOARD=Projet-LeonLFR-A3P3K-Sheldon | |||
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4 | include $(GRLIB)/boards/$(BOARD)/Makefile.inc | |||
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5 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |||
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6 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |||
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7 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |||
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8 | EFFORT=high | |||
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9 | XSTOPT= | |||
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10 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |||
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11 | VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd Top_Data_Acquisition.vhd | |||
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12 | VHDLSIMFILES=testbench.vhd TB_Data_Acquisition.vhd | |||
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13 | SIMTOP=testbench | |||
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14 | SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |||
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15 | SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc | |||
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16 | PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc | |||
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17 | BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut | |||
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18 | CLEAN=soft-clean | |||
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19 | ||||
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20 | TECHLIBS = proasic3 | |||
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21 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |||
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22 | tmtc openchip hynix ihp gleichmann micron usbhc | |||
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23 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |||
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24 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 | |||
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25 | ||||
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26 | FILESKIP = i2cmst.vhd | |||
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27 | ||||
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28 | #TECHLIBS = unisim | |||
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29 | include $(GRLIB)/bin/Makefile | |||
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30 | include $(GRLIB)/software/leon3/Makefile | |||
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31 | ||||
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32 | my-clean: clean | |||
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33 | -rm -rf *~ | |||
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34 | ||||
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35 | ################## project specific targets ########################## | |||
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36 |
@@ -1,3 +1,4 | |||||
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1 | ||||
1 | ------------------------------------------------------------------------------ |
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2 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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