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debug lpp_uart and comment lpp_cna
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1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 #ifndef APB_CNA_DRIVER_H
22 #ifndef APB_CNA_DRIVER_H
20 #define APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
21
24
22 #define DAC_ready 3
25 #define DAC_ready 3
23 #define DAC_enable 1
26 #define DAC_enable 1
24 #define DAC_disable 0
27 #define DAC_disable 0
25
28
26
29
27 /*===================================================
30 /*===================================================
28 T Y P E S D E F
31 T Y P E S D E F
29 ====================================================*/
32 ====================================================*/
30
33
34 /** Structure reprοΏ½sentant le registre du CNA */
31 struct DAC_Driver
35 struct DAC_Driver
32 {
36 {
33 int configReg;
37 int configReg; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
34 int dataReg;
38 int dataReg; /**< Registre de donnοΏ½e sur 16 bits */
35 };
39 };
36
40
37 typedef struct DAC_Driver DAC_Device;
41 typedef struct DAC_Driver DAC_Device;
38
42
39 /*===================================================
43 /*===================================================
40 F U N C T I O N S
44 F U N C T I O N S
41 ====================================================*/
45 ====================================================*/
42
46
47 /** Ouvre l'accοΏ½ au CNA */
43 DAC_Device* DacOpen(int count);
48 DAC_Device* DacOpen(int count);
44
49
45 //DAC_Device* DacClose(int count);
50 //DAC_Device* DacClose(int count);
46
51
52 /** Les donnοΏ½es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
47 int DacTable();
53 int DacTable();
48
54
55 /** Les donnοΏ½es sont entrοΏ½e par l'utilisateur, la conversion se fait a chaque nouvelle donnοΏ½e */
49 int DacConst();
56 int DacConst();
50
57
51
58
52
59
53 #endif
60 #endif
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@@ -1,95 +1,98
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
19 #ifndef APB_LCD_DRIVER_H
22 #ifndef APB_LCD_DRIVER_H
20 #define APB_LCD_DRIVER_H
23 #define APB_LCD_DRIVER_H
21
24
22 #define readyFlag 1024
25 #define readyFlag 1024
23 #define lcdCharCnt 80
26 #define lcdCharCnt 80
24
27
25
28
26 /** @todo implemente some shift functions */
29 /** @todo implemente some shift functions */
27
30
28
31
29 /*===================================================
32 /*===================================================
30 T Y P E S D E F
33 T Y P E S D E F
31 ====================================================*/
34 ====================================================*/
32
35
33
36
34
37
35 /** error type used for most of lcd functions */
38 /** error type used for most of lcd functions */
36 typedef int lcd_err;
39 typedef int lcd_err;
37
40
38 /** lcd error ennum for higher abstraction level when error decoding */
41 /** lcd error ennum for higher abstraction level when error decoding */
39 enum lcd_error
42 enum lcd_error
40 {
43 {
41 lcd_error_no_error, /**< no error append while function execution */
44 lcd_error_no_error, /**< no error append while function execution */
42 lcd_error_not_ready, /**< the lcd isn't available*/
45 lcd_error_not_ready, /**< the lcd isn't available*/
43 lcd_error_not_openned, /**< the device guiven to the function isn't opened*/
46 lcd_error_not_openned, /**< the device guiven to the function isn't opened*/
44 lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */
47 lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */
45 };
48 };
46
49
47
50
48 /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */
51 /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */
49 enum lcd_CMD_time
52 enum lcd_CMD_time
50 {
53 {
51 lcd_4us = 0x0FF,
54 lcd_4us = 0x0FF,
52 lcd_100us = 0x1FF,
55 lcd_100us = 0x1FF,
53 lcd_4ms = 0x2FF,
56 lcd_4ms = 0x2FF,
54 lcd_20ms = 0x3FF
57 lcd_20ms = 0x3FF
55 };
58 };
56
59
57 /** list of availiable lcd commands use whith an AND mask whith cmd time */
60 /** list of availiable lcd commands use whith an AND mask whith cmd time */
58 enum lcd_CMD
61 enum lcd_CMD
59 {
62 {
60 CursorON = 0xF0E,
63 CursorON = 0xF0E,
61 CursorOFF = 0xF0C
64 CursorOFF = 0xF0C
62 };
65 };
63
66
64 /** structure representing the lcd registers */
67 /** structure representing the lcd registers */
65 struct lcd_driver
68 struct lcd_driver
66 {
69 {
67 int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8], CMD to send [7:0]*/
70 int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8], CMD to send [7:0]*/
68 int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */
71 int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */
69 };
72 };
70
73
71 typedef struct lcd_driver lcd_device;
74 typedef struct lcd_driver lcd_device;
72
75
73 /*===================================================
76 /*===================================================
74 F U N C T I O N S
77 F U N C T I O N S
75 ====================================================*/
78 ====================================================*/
76
79
77 /** says if the lcd is busy */
80 /** says if the lcd is busy */
78 int lcdbusy(lcd_device * lcd);
81 int lcdbusy(lcd_device * lcd);
79
82
80 /** Opens and returns the counth lcd found on APB bus else NULL */
83 /** Opens and returns the counth lcd found on APB bus else NULL */
81 lcd_device* lcdopen(int count);
84 lcd_device* lcdopen(int count);
82
85
83 /** Sends a command to the given device, don't forget to guive the time of the cmd */
86 /** Sends a command to the given device, don't forget to guive the time of the cmd */
84 lcd_err lcdsendcmd(lcd_device* lcd,int cmd);
87 lcd_err lcdsendcmd(lcd_device* lcd,int cmd);
85
88
86 /** Sets a char on the given device at given position */
89 /** Sets a char on the given device at given position */
87 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value);
90 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value);
88
91
89 /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */
92 /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */
90 lcd_err lcdprint(lcd_device* lcd,int position,const char* value);
93 lcd_err lcdprint(lcd_device* lcd,int position,const char* value);
91
94
92 /** Writes space character on each adress of the lcd screen */
95 /** Writes space character on each adress of the lcd screen */
93 lcd_err lcdclear(lcd_device* lcd);
96 lcd_err lcdclear(lcd_device* lcd);
94
97
95 #endif
98 #endif
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@@ -1,59 +1,62
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
18 -------------------------------------------------------------------------------*/
19 /*-- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------*/
19 #ifndef LPP_APB_FUNCTIONS_H
22 #ifndef LPP_APB_FUNCTIONS_H
20 #define LPP_APB_FUNCTIONS_H
23 #define LPP_APB_FUNCTIONS_H
21
24
22 #define APB_TBL_HEAD 0x800FF000
25 #define APB_TBL_HEAD 0x800FF000
23 #define APB_BASE_ADDRS 0x80000000
26 #define APB_BASE_ADDRS 0x80000000
24 #define APB_MAX_DEVICES 256
27 #define APB_MAX_DEVICES 256
25
28
26 #include "apb_devices_list.h"
29 #include "apb_devices_list.h"
27
30
28 /** @todo implemente a descriptor structure for any APB device */
31 /** @todo implemente a descriptor structure for any APB device */
29
32
30
33
31 /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
34 /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
32 struct apbPnPreg
35 struct apbPnPreg
33 {
36 {
34 int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
37 int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
35 int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
38 int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
36 };
39 };
37
40
38 struct apbdevinfo
41 struct apbdevinfo
39 {
42 {
40 int vendorID;
43 int vendorID;
41 int productID;
44 int productID;
42 int version;
45 int version;
43 int irq;
46 int irq;
44 int address;
47 int address;
45 int mask;
48 int mask;
46 };
49 };
47
50
48 /** This Function scans APB devices table and returns counth device according to VID and PID */
51 /** This Function scans APB devices table and returns counth device according to VID and PID */
49 int* apbgetdevice(int PID,int VID,int count);
52 int* apbgetdevice(int PID,int VID,int count);
50 /** This Function scans APB devices table and returns counth device informations according VID and PID */
53 /** This Function scans APB devices table and returns counth device informations according VID and PID */
51 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
54 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
52
55
53 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
56 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
54
57
55
58
56 void apbprintdeviceinfo(struct apbdevinfo devinfo);
59 void apbprintdeviceinfo(struct apbdevinfo devinfo);
57
60
58 void apbprintdeviceslist();
61 void apbprintdeviceslist();
59 #endif // LPP_APB_FUNCTIONS_H
62 #endif // LPP_APB_FUNCTIONS_H
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@@ -1,86 +1,89
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 #include "apb_dac_Driver.h"
22 #include "apb_dac_Driver.h"
20 #include "lpp_apb_functions.h"
23 #include "lpp_apb_functions.h"
21 #include <stdio.h>
24 #include <stdio.h>
22
25
23
26
24 DAC_Device* DacOpen(int count)
27 DAC_Device* DacOpen(int count)
25 {
28 {
26 DAC_Device* dac0;
29 DAC_Device* dac0;
27 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
30 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
28 dac0->configReg = DAC_enable;
31 dac0->configReg = DAC_enable;
29 return dac0;
32 return dac0;
30 }
33 }
31
34
32 /*
35 /*
33 DAC_Device* DacClose(int count)
36 DAC_Device* DacClose(int count)
34 {
37 {
35 DAC_Device* dac1;
38 DAC_Device* dac1;
36 dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
39 dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
37 dac1->configReg = DAC_disable;
40 dac1->configReg = DAC_disable;
38 return dac1;
41 return dac1;
39 }
42 }
40 */
43 */
41
44
42
45
43 int DacTable()
46 int DacTable()
44 {
47 {
45 int i;
48 int i;
46 DAC_Device* dac2;
49 DAC_Device* dac2;
47 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
50 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
48 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
51 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
49 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
52 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
50 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
53 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
51 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
54 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
52 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
55 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
53 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
56 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
54 dac2 = (DAC_Device*)0x80000800;
57 dac2 = (DAC_Device*)0x80000800;
55 dac2->configReg = DAC_enable;
58 dac2->configReg = DAC_enable;
56 dac2->dataReg = tablo[0];
59 dac2->dataReg = tablo[0];
57
60
58 while(1)
61 while(1)
59 {
62 {
60 for (i = 0 ; i < 251 ; i++)
63 for (i = 0 ; i < 251 ; i++)
61 {
64 {
62 while(!((dac2->configReg & DAC_ready) == DAC_ready));
65 while(!((dac2->configReg & DAC_ready) == DAC_ready));
63 dac2->dataReg = tablo[i];
66 dac2->dataReg = tablo[i];
64 while((dac2->configReg & DAC_ready) == DAC_ready);
67 while((dac2->configReg & DAC_ready) == DAC_ready);
65 }
68 }
66 }
69 }
67 return 0;
70 return 0;
68 }
71 }
69
72
70
73
71
74
72 int DacConst()
75 int DacConst()
73 {
76 {
74 DAC_Device* dac3;
77 DAC_Device* dac3;
75 int Value = 0x1FFF;
78 int Value = 0x1FFF;
76 dac3 = (DAC_Device*)0x80000800;
79 dac3 = (DAC_Device*)0x80000800;
77 dac3->configReg = DAC_enable;
80 dac3->configReg = DAC_enable;
78 while(1)
81 while(1)
79 {
82 {
80 printf("\nEntrer une valeur entre 4096 et 8191 : ");
83 printf("\nEntrer une valeur entre 4096 et 8191 : ");
81 scanf("%d",&Value);
84 scanf("%d",&Value);
82 dac3->dataReg = Value;
85 dac3->dataReg = Value;
83 }
86 }
84 return 0;
87 return 0;
85 }
88 }
86
89
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@@ -1,53 +1,60
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 #ifndef APB_CNA_DRIVER_H
22 #ifndef APB_CNA_DRIVER_H
20 #define APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
21
24
22 #define DAC_ready 3
25 #define DAC_ready 3
23 #define DAC_enable 1
26 #define DAC_enable 1
24 #define DAC_disable 0
27 #define DAC_disable 0
25
28
26
29
27 /*===================================================
30 /*===================================================
28 T Y P E S D E F
31 T Y P E S D E F
29 ====================================================*/
32 ====================================================*/
30
33
34 /** Structure reprοΏ½sentant le registre du CNA */
31 struct DAC_Driver
35 struct DAC_Driver
32 {
36 {
33 int configReg;
37 int configReg; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
34 int dataReg;
38 int dataReg; /**< Registre de donnοΏ½e sur 16 bits */
35 };
39 };
36
40
37 typedef struct DAC_Driver DAC_Device;
41 typedef struct DAC_Driver DAC_Device;
38
42
39 /*===================================================
43 /*===================================================
40 F U N C T I O N S
44 F U N C T I O N S
41 ====================================================*/
45 ====================================================*/
42
46
47 /** Ouvre l'accοΏ½ au CNA */
43 DAC_Device* DacOpen(int count);
48 DAC_Device* DacOpen(int count);
44
49
45 //DAC_Device* DacClose(int count);
50 //DAC_Device* DacClose(int count);
46
51
52 /** Les donnοΏ½es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
47 int DacTable();
53 int DacTable();
48
54
55 /** Les donnοΏ½es sont entrοΏ½e par l'utilisateur, la conversion se fait a chaque nouvelle donnοΏ½e */
49 int DacConst();
56 int DacConst();
50
57
51
58
52
59
53 #endif
60 #endif
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@@ -1,9 +1,9
1 amba_lcd_16x2_ctrlr.vhd
2 apb_lcd_ctrlr.vhd
3 FRAME_CLK.vhd
1 FRAME_CLK.vhd
4 LCD_16x2_CFG.vhd
2 LCD_16x2_CFG.vhd
5 LCD_16x2_DRVR.vhd
3 LCD_16x2_DRVR.vhd
6 LCD_16x2_ENGINE.vhd
4 LCD_16x2_ENGINE.vhd
7 LCD_2x16_DRIVER.vhd
5 LCD_2x16_DRIVER.vhd
8 LCD_CLK_GENERATOR.vhd
6 LCD_CLK_GENERATOR.vhd
9 Top_LCD.vhd
7 Top_LCD.vhd
8 amba_lcd_16x2_ctrlr.vhd
9 apb_lcd_ctrlr.vhd
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@@ -1,12 +1,12
1 APB_IIR_CEL.vhd
1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
2 FILTERcfg.vhd
4 FILTERcfg.vhd
3 FilterCTRLR.vhd
5 FilterCTRLR.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTER.vhd
6 IIR_CEL_CTRLR.vhd
6 IIR_CEL_CTRLR.vhd
7 IIR_CEL_FILTER.vhd
7 IIR_CEL_FILTER.vhd
8 iir_filter.vhd
8 RAM.vhd
9 RAM_CEL.vhd
9 RAM_CEL.vhd
10 RAM_CTRLR2.vhd
10 RAM_CTRLR2.vhd
11 RAM.vhd
12 Top_Filtre_IIR.vhd
11 Top_Filtre_IIR.vhd
12 iir_filter.vhd
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@@ -1,14 +1,14
1 Adder.vhd
2 ADDRcntr.vhd
1 ADDRcntr.vhd
3 ALU.vhd
2 ALU.vhd
3 Adder.vhd
4 Clk_divider.vhd
4 Clk_divider.vhd
5 general_purpose.vhd
5 MAC.vhd
6 MAC_CONTROLER.vhd
6 MAC_CONTROLER.vhd
7 MAC_MUX2.vhd
8 MAC_MUX.vhd
7 MAC_MUX.vhd
8 MAC_MUX2.vhd
9 MAC_REG.vhd
9 MAC_REG.vhd
10 MAC.vhd
10 MUX2.vhd
11 Multiplier.vhd
11 Multiplier.vhd
12 MUX2.vhd
13 REG.vhd
12 REG.vhd
14 Shifter.vhd
13 Shifter.vhd
14 general_purpose.vhd
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@@ -1,105 +1,109
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 library ieee;
22 library ieee;
20 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
21 --use ieee.numeric_std.all;
24 --use ieee.numeric_std.all;
22 library grlib;
25 library grlib;
23 use grlib.amba.all;
26 use grlib.amba.all;
24 use grlib.stdlib.all;
27 use grlib.stdlib.all;
25 use grlib.devices.all;
28 use grlib.devices.all;
26 library lpp;
29 library lpp;
30 use lpp.apb_devices_list.all;
27 use lpp.lpp_amba.all;
31 use lpp.lpp_amba.all;
28
32
29
33
30 entity APB_MULTI_DIODE is
34 entity APB_MULTI_DIODE is
31 generic (
35 generic (
32 pindex : integer := 0;
36 pindex : integer := 0;
33 paddr : integer := 0;
37 paddr : integer := 0;
34 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
35 pirq : integer := 0;
39 pirq : integer := 0;
36 abits : integer := 8);
40 abits : integer := 8);
37 port (
41 port (
38 rst : in std_ulogic;
42 rst : in std_ulogic;
39 clk : in std_ulogic;
43 clk : in std_ulogic;
40 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
41 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
42 LED : out std_logic_vector(2 downto 0)
46 LED : out std_logic_vector(2 downto 0)
43 );
47 );
44 end;
48 end;
45
49
46
50
47 architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
51 architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
48
52
49 constant REVISION : integer := 1;
53 constant REVISION : integer := 1;
50
54
51 constant pconfig : apb_config_type := (
55 constant pconfig : apb_config_type := (
52 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
56 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
53 1 => apb_iobar(paddr, pmask));
57 1 => apb_iobar(paddr, pmask));
54
58
55
59
56
60
57 type LEDregs is record
61 type LEDregs is record
58 DATAin : std_logic_vector(31 downto 0);
62 DATAin : std_logic_vector(31 downto 0);
59 DATAout : std_logic_vector(31 downto 0);
63 DATAout : std_logic_vector(31 downto 0);
60 end record;
64 end record;
61
65
62 signal r : LEDregs;
66 signal r : LEDregs;
63 signal Rdata : std_logic_vector(31 downto 0);
67 signal Rdata : std_logic_vector(31 downto 0);
64
68
65
69
66 begin
70 begin
67
71
68 r.DATAout <= r.DATAin xor X"FFFFFFFF";
72 r.DATAout <= r.DATAin xor X"FFFFFFFF";
69
73
70 process(rst,clk)
74 process(rst,clk)
71 begin
75 begin
72 if rst = '0' then
76 if rst = '0' then
73 LED <= "000";
77 LED <= "000";
74 r.DATAin <= (others => '0');
78 r.DATAin <= (others => '0');
75
79
76 elsif clk'event and clk = '1' then
80 elsif clk'event and clk = '1' then
77
81
78 LED <= r.DATAin(2 downto 0);
82 LED <= r.DATAin(2 downto 0);
79
83
80 --APB Write OP
84 --APB Write OP
81 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
85 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
82 case apbi.paddr(abits-1 downto 2) is
86 case apbi.paddr(abits-1 downto 2) is
83 when "000000" =>
87 when "000000" =>
84 r.DATAin <= apbi.pwdata;
88 r.DATAin <= apbi.pwdata;
85 when others =>
89 when others =>
86 null;
90 null;
87 end case;
91 end case;
88 end if;
92 end if;
89
93
90 --APB READ OP
94 --APB READ OP
91 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
95 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
92 case apbi.paddr(abits-1 downto 2) is
96 case apbi.paddr(abits-1 downto 2) is
93 when "000000" =>
97 when "000000" =>
94 Rdata <= r.DATAin;
98 Rdata <= r.DATAin;
95 when others =>
99 when others =>
96 Rdata <= r.DATAout;
100 Rdata <= r.DATAout;
97 end case;
101 end case;
98 end if;
102 end if;
99
103
100 end if;
104 end if;
101 apbo.pconfig <= pconfig;
105 apbo.pconfig <= pconfig;
102 end process;
106 end process;
103
107
104 apbo.prdata <= Rdata when apbi.penable = '1';
108 apbo.prdata <= Rdata when apbi.penable = '1';
105 end ar_APB_MULTI_DIODE;
109 end ar_APB_MULTI_DIODE;
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@@ -1,130 +1,131
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 --use ieee.numeric_std.all;
24 --use ieee.numeric_std.all;
25 library grlib;
25 library grlib;
26 use grlib.amba.all;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
28 use grlib.devices.all;
29 library lpp;
29 library lpp;
30 use lpp.apb_devices_list.all;
30 use lpp.lpp_amba.all;
31 use lpp.lpp_amba.all;
31
32
32
33
33 entity APB_SIMPLE_DIODE is
34 entity APB_SIMPLE_DIODE is
34 generic (
35 generic (
35 pindex : integer := 0;
36 pindex : integer := 0;
36 paddr : integer := 0;
37 paddr : integer := 0;
37 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
38 pirq : integer := 0;
39 pirq : integer := 0;
39 abits : integer := 8);
40 abits : integer := 8);
40 port (
41 port (
41 rst : in std_ulogic;
42 rst : in std_ulogic;
42 clk : in std_ulogic;
43 clk : in std_ulogic;
43 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
44 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
45 LED : out std_ulogic
46 LED : out std_ulogic
46 );
47 );
47 end;
48 end;
48
49
49
50
50 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
51 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
51
52
52 constant REVISION : integer := 1;
53 constant REVISION : integer := 1;
53
54
54 constant pconfig : apb_config_type := (
55 constant pconfig : apb_config_type := (
55 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
56 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
56 1 => apb_iobar(paddr, pmask));
57 1 => apb_iobar(paddr, pmask));
57
58
58
59
59
60
60 type LEDregs is record
61 type LEDregs is record
61 DATAin : std_logic_vector(31 downto 0);
62 DATAin : std_logic_vector(31 downto 0);
62 DATAout : std_logic_vector(31 downto 0);
63 DATAout : std_logic_vector(31 downto 0);
63 end record;
64 end record;
64
65
65 signal r : LEDregs;
66 signal r : LEDregs;
66 signal Rdata : std_logic_vector(31 downto 0);
67 signal Rdata : std_logic_vector(31 downto 0);
67
68
68 begin
69 begin
69
70
70 r.DATAout <= r.DATAin xor X"FFFFFFFF";
71 r.DATAout <= r.DATAin xor X"FFFFFFFF";
71
72
72 process(rst,clk)
73 process(rst,clk)
73 begin
74 begin
74 if rst = '0' then
75 if rst = '0' then
75 LED <= '0';
76 LED <= '0';
76 r.DATAin <= (others => '0');
77 r.DATAin <= (others => '0');
77
78
78 elsif clk'event and clk = '1' then
79 elsif clk'event and clk = '1' then
79
80
80 LED <= r.DATAin(0);
81 LED <= r.DATAin(0);
81
82
82 --APB Write OP
83 --APB Write OP
83 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
84 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
84 case apbi.paddr(abits-1 downto 2) is
85 case apbi.paddr(abits-1 downto 2) is
85 when "000000" =>
86 when "000000" =>
86 r.DATAin <= apbi.pwdata;
87 r.DATAin <= apbi.pwdata;
87 when others =>
88 when others =>
88 null;
89 null;
89 end case;
90 end case;
90 end if;
91 end if;
91
92
92 --APB READ OP
93 --APB READ OP
93 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
94 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
94 case apbi.paddr(abits-1 downto 2) is
95 case apbi.paddr(abits-1 downto 2) is
95 when "000000" =>
96 when "000000" =>
96 Rdata <= r.DATAin;
97 Rdata <= r.DATAin;
97 when others =>
98 when others =>
98 Rdata <= r.DATAout;
99 Rdata <= r.DATAout;
99 end case;
100 end case;
100 end if;
101 end if;
101
102
102 end if;
103 end if;
103 apbo.pconfig <= pconfig;
104 apbo.pconfig <= pconfig;
104 end process;
105 end process;
105
106
106 apbo.prdata <= Rdata when apbi.penable = '1';
107 apbo.prdata <= Rdata when apbi.penable = '1';
107
108
108 -- pragma translate_off
109 -- pragma translate_off
109 -- bootmsg : report_version
110 -- bootmsg : report_version
110 -- generic map ("apbuart" & tost(pindex) &
111 -- generic map ("apbuart" & tost(pindex) &
111 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
112 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
112 -- ", irq " & tost(pirq));
113 -- ", irq " & tost(pirq));
113 -- pragma translate_on
114 -- pragma translate_on
114
115
115
116
116
117
117 end ar_APB_SIMPLE_DIODE;
118 end ar_APB_SIMPLE_DIODE;
118
119
119
120
120
121
121
122
122
123
123
124
124
125
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126
126
127
127
128
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131
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@@ -1,6 +1,4
1 APB_MULTI_DIODE.vhd
2 APB_SIMPLE_DIODE.vhd
1 apb_devices_list.vhd
3 apb_devices_list.vhd
2 APB_MULTI_DIODE.vhd
3 APB_MULTI_DIODE.vhd.orig
4 APB_SIMPLE_DIODE.vhd
5 APB_SIMPLE_DIODE.vhd.orig
6 lpp_amba.vhd
4 lpp_amba.vhd
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@@ -1,119 +1,123
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- APB_CNA.vhd
19 -- Author : Martin Morlot
20
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 library ieee;
22 library ieee;
22 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
23 library grlib;
24 library grlib;
24 use grlib.amba.all;
25 use grlib.amba.all;
25 use grlib.stdlib.all;
26 use grlib.stdlib.all;
26 use grlib.devices.all;
27 use grlib.devices.all;
27 library lpp;
28 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
29 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
30 use lpp.lpp_cna.all;
31 use lpp.lpp_cna.all;
31
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
32
34
33 entity APB_CNA is
35 entity APB_CNA is
34 generic (
36 generic (
35 pindex : integer := 0;
37 pindex : integer := 0;
36 paddr : integer := 0;
38 paddr : integer := 0;
37 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
38 pirq : integer := 0;
40 pirq : integer := 0;
39 abits : integer := 8);
41 abits : integer := 8);
40 port (
42 port (
41 clk : in std_logic;
43 clk : in std_logic; --! Horloge du composant
42 rst : in std_logic;
44 rst : in std_logic; --! Reset general du composant
43 apbi : in apb_slv_in_type;
45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
44 apbo : out apb_slv_out_type;
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
45 SYNC : out std_logic;
47 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
46 SCLK : out std_logic;
48 SCLK : out std_logic; --! Horloge systeme du convertisseur
47 DATA : out std_logic
49 DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
48 );
50 );
49 end APB_CNA;
51 end APB_CNA;
50
52
53 --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus
54 --! et les sorties seront cablοΏ½es vers le convertisseur.
51
55
52 architecture ar_APB_CNA of APB_CNA is
56 architecture ar_APB_CNA of APB_CNA is
53
57
54 constant REVISION : integer := 1;
58 constant REVISION : integer := 1;
55
59
56 constant pconfig : apb_config_type := (
60 constant pconfig : apb_config_type := (
57 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
61 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
58 1 => apb_iobar(paddr, pmask));
62 1 => apb_iobar(paddr, pmask));
59
63
60 signal enable : std_logic;
64 signal enable : std_logic;
61 signal flag_sd : std_logic;
65 signal flag_sd : std_logic;
62
66
63 type CNA_ctrlr_Reg is record
67 type CNA_ctrlr_Reg is record
64 CNA_Cfg : std_logic_vector(1 downto 0);
68 CNA_Cfg : std_logic_vector(1 downto 0);
65 CNA_Data : std_logic_vector(15 downto 0);
69 CNA_Data : std_logic_vector(15 downto 0);
66 end record;
70 end record;
67
71
68 signal Rec : CNA_ctrlr_Reg;
72 signal Rec : CNA_ctrlr_Reg;
69 signal Rdata : std_logic_vector(31 downto 0);
73 signal Rdata : std_logic_vector(31 downto 0);
70
74
71 begin
75 begin
72
76
73 enable <= Rec.CNA_Cfg(0);
77 enable <= Rec.CNA_Cfg(0);
74 Rec.CNA_Cfg(1) <= flag_sd;
78 Rec.CNA_Cfg(1) <= flag_sd;
75
79
76 CONVERTER : entity Work.CNA_TabloC
80 CONVERTER : entity Work.CNA_TabloC
77 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
81 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
78
82
79
83
80 process(rst,clk)
84 process(rst,clk)
81 begin
85 begin
82 if(rst='0')then
86 if(rst='0')then
83 Rec.CNA_Data <= (others => '0');
87 Rec.CNA_Data <= (others => '0');
84
88
85 elsif(clk'event and clk='1')then
89 elsif(clk'event and clk='1')then
86
90
87
91
88 --APB Write OP
92 --APB Write OP
89 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
90 case apbi.paddr(abits-1 downto 2) is
94 case apbi.paddr(abits-1 downto 2) is
91 when "000000" =>
95 when "000000" =>
92 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
96 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
93 when "000001" =>
97 when "000001" =>
94 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
98 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
95 when others =>
99 when others =>
96 null;
100 null;
97 end case;
101 end case;
98 end if;
102 end if;
99
103
100 --APB READ OP
104 --APB READ OP
101 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
102 case apbi.paddr(abits-1 downto 2) is
106 case apbi.paddr(abits-1 downto 2) is
103 when "000000" =>
107 when "000000" =>
104 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
108 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
105 Rdata(1 downto 0) <= Rec.CNA_Cfg;
109 Rdata(1 downto 0) <= Rec.CNA_Cfg;
106 when "000001" =>
110 when "000001" =>
107 Rdata(31 downto 16) <= X"FD18";
111 Rdata(31 downto 16) <= X"FD18";
108 Rdata(15 downto 0) <= Rec.CNA_Data;
112 Rdata(15 downto 0) <= Rec.CNA_Data;
109 when others =>
113 when others =>
110 Rdata <= (others => '0');
114 Rdata <= (others => '0');
111 end case;
115 end case;
112 end if;
116 end if;
113
117
114 end if;
118 end if;
115 apbo.pconfig <= pconfig;
119 apbo.pconfig <= pconfig;
116 end process;
120 end process;
117
121
118 apbo.prdata <= Rdata when apbi.penable = '1';
122 apbo.prdata <= Rdata when apbi.penable = '1';
119 end ar_APB_CNA;
123 end ar_APB_CNA;
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@@ -1,85 +1,82
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- CNA_TabloC.vhd
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 library IEEE;
22 library IEEE;
21 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
22 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
23 use work.Convertisseur_config.all;
25 use work.Convertisseur_config.all;
24
26
27 --! Programme du Convertisseur NumοΏ½rique/Analogique
28
25 entity CNA_TabloC is
29 entity CNA_TabloC is
26 port(
30 port(
27 clock : in std_logic;
31 clock : in std_logic; --! Horloge du composant
28 rst : in std_logic;
32 rst : in std_logic; --! Reset general du composant
29 enable : in std_logic;
33 enable : in std_logic; --! Autorise ou non l'utilisation du composant
30 --bp : in std_logic;
34 Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits
31 Data_C : in std_logic_vector(15 downto 0);
35 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
32 SYNC : out std_logic;
36 SCLK : out std_logic; --! Horloge systeme du convertisseur
33 SCLK : out std_logic;
37 flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e
34 --Rz : out std_logic;
38 Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
35 flag_sd : out std_logic;
39 );
36 Data : out std_logic
37 );
38 end CNA_TabloC;
40 end CNA_TabloC;
39
41
42 --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits,
43 --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur.
40
44
41 architecture ar_CNA_TabloC of CNA_TabloC is
45 architecture ar_CNA_TabloC of CNA_TabloC is
42
46
43 component CLKINT
47 component CLKINT
44 port( A : in std_logic := 'U';
48 port( A : in std_logic := 'U';
45 Y : out std_logic);
49 Y : out std_logic);
46 end component;
50 end component;
47
51
48 signal clk : std_logic;
52 signal clk : std_logic;
49
53
50 signal raz : std_logic;
54 signal raz : std_logic;
51 signal s_SCLK : std_logic;
55 signal s_SCLK : std_logic;
52 signal OKAI_send : std_logic;
56 signal OKAI_send : std_logic;
53 --signal Data_int : std_logic_vector(15 downto 0);
54
57
55 begin
58 begin
56
59
57
58 CLKINT_0 : CLKINT
60 CLKINT_0 : CLKINT
59 port map(A => clock, Y => clk);
61 port map(A => clock, Y => clk);
60
62
61 CLKINT_1 : CLKINT
63 CLKINT_1 : CLKINT
62 port map(A => rst, Y => raz);
64 port map(A => rst, Y => raz);
63
65
64
66
65 SystemCLK : entity work.Systeme_Clock
67 SystemCLK : entity work.Systeme_Clock
66 generic map (nb_serial)
68 generic map (nb_serial)
67 port map (clk,raz,s_SCLK);
69 port map (clk,raz,s_SCLK);
68
70
69
71
70 Signal_sync : entity work.Gene_SYNC
72 Signal_sync : entity work.Gene_SYNC
71 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
73 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
72
74
73
75
74 Serial : entity work.serialize
76 Serial : entity work.serialize
75 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
77 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
76
78
77
79
78 --Rz <= raz;
79 SCLK <= s_SCLK;
80 SCLK <= s_SCLK;
80
81
81 --with bp select
82 -- Data_int <= X"9555" when '1',
83 -- Data_C when others;
84
85 end ar_CNA_TabloC; No newline at end of file
82 end ar_CNA_TabloC;
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@@ -1,42 +1,34
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Convertisseur_config.vhd
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 library IEEE;
22 library IEEE;
21 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
22 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
23
25
24 Package Convertisseur_config is
26 Package Convertisseur_config is
25
27
26
27 --===========================================================|
28 --================= Valeurs Sinus 1Khz ======================|
29 --===========================================================|
30 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
31 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
32
33 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
34
35
36 --===========================================================|
28 --===========================================================|
37 --============= FrοΏ½quence de sοΏ½rialisation ==================|
29 --============= FrοΏ½quence de sοΏ½rialisation ==================|
38 --===========================================================|
30 --===========================================================|
39 constant Freq_serial : integer := 5_000_000;
31 constant Freq_serial : integer := 5_000_000;
40 constant nb_serial : integer := 30_000_000 / Freq_serial;
32 constant nb_serial : integer := 30_000_000 / Freq_serial;
41
33
42 end; No newline at end of file
34 end;
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@@ -1,71 +1,69
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Gene_SYNC.vhd
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 library IEEE;
22 library IEEE;
21 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
22 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
23
25
24 entity Gene_SYNC is
26 --! Programme qui va permettre de gοΏ½nοΏ½rer le signal SYNC
25
27
26 port(
28 entity Gene_SYNC is
27 SCLK,raz : in std_logic;
29 port(
28 enable : in std_logic;
30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
29 -- Sysclk : in std_logic;
31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
30 OKAI_send : out std_logic;
32 OKAI_send : out std_logic; --! Flag, Autorise l'envoi (sοΏ½rialisation) d'une nouvelle donnοΏ½e
31 SYNC : out std_logic
33 SYNC : out std_logic --! Signal de synchronisation du convertisseur gοΏ½nοΏ½rοΏ½
32 );
34 );
33
34 end Gene_SYNC;
35 end Gene_SYNC;
35
36
37 --! @details NB: Ce programme est uniquement synchronisοΏ½ sur l'horloge Systeme (sclk)
36
38
37 architecture ar_Gene_SYNC of Gene_SYNC is
39 architecture ar_Gene_SYNC of Gene_SYNC is
38
40
39 --signal Sysclk_reg : std_logic;
40 signal count : integer;
41 signal count : integer;
41
42
42
43 begin
43 begin
44 process (SCLK,raz)
44 process (SCLK,raz)
45 begin
45 begin
46 if(raz='0')then
46 if(raz='0')then
47 SYNC <= '0';
47 SYNC <= '0';
48 -- Sysclk_reg <= '0';
49 count <= 14;
48 count <= 14;
50 OKAI_send <= '0';
49 OKAI_send <= '0';
51
50
52 elsif(SCLK' event and SCLK='1')then
51 elsif(SCLK' event and SCLK='1')then
53 if(enable='1')then
52 if(enable='1')then
54
53
55 -- Sysclk_reg <= Sysclk;
56 if(count=15)then
54 if(count=15)then
57 SYNC <= '1';
55 SYNC <= '1';
58 count <= count+1;
56 count <= count+1;
59 elsif(count=16)then
57 elsif(count=16)then
60 count <= 0;
58 count <= 0;
61 SYNC <= '0';
59 SYNC <= '0';
62 OKAI_send <= '1';
60 OKAI_send <= '1';
63 else
61 else
64 count <= count+1;
62 count <= count+1;
65 OKAI_send <= '0';
63 OKAI_send <= '0';
66 end if;
64 end if;
65
67 end if;
66 end if;
68 end if;
67 end if;
69 end process;
68 end process;
70
71 end ar_Gene_SYNC; No newline at end of file
69 end ar_Gene_SYNC;
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@@ -1,104 +1,107
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Serialize.vhd
19 -- Author : Martin Morlot
20 library IEEE;
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 use IEEE.numeric_std.all;
21 ------------------------------------------------------------------------------
22 use IEEE.std_logic_1164.all;
22 library IEEE;
23
23 use IEEE.numeric_std.all;
24 entity Serialize is
24 use IEEE.std_logic_1164.all;
25
25
26 port(
26 --! Programme qui permet de sοΏ½rialiser un vecteur
27 clk,raz : in std_logic;
27
28 sclk : in std_logic;
28 entity Serialize is
29 vectin : in std_logic_vector(15 downto 0);
29 port(
30 send : in std_logic;
30 clk,raz : in std_logic; --! Horloge et Reset du composant
31 sended : out std_logic;
31 sclk : in std_logic; --! Horloge Systeme
32 Data : out std_logic);
32 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entrοΏ½e
33
33 send : in std_logic; --! Flag, Une nouvelle donnοΏ½e est prοΏ½sente
34 end Serialize;
34 sended : out std_logic; --! Flag, La donnοΏ½e a οΏ½tοΏ½ sοΏ½rialisοΏ½e
35
35 Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
36
36 );
37 architecture ar_Serialize of Serialize is
37 end Serialize;
38
38
39 type etat is (attente,serialize);
39
40 signal ect : etat;
40 architecture ar_Serialize of Serialize is
41
41
42 type etat is (attente,serialize);
43 signal ect : etat;
44
42 signal vector_int : std_logic_vector(16 downto 0);
45 signal vector_int : std_logic_vector(16 downto 0);
43 signal vectin_reg : std_logic_vector(15 downto 0);
46 signal vectin_reg : std_logic_vector(15 downto 0);
44 signal load : std_logic;
47 signal load : std_logic;
45 signal N : integer range 0 to 16;
48 signal N : integer range 0 to 16;
46 signal CPT_ended : std_logic:='0';
49 signal CPT_ended : std_logic:='0';
47
50
48 begin
51 begin
49 process(clk,raz)
52 process(clk,raz)
50 begin
53 begin
51 if(raz='0')then
54 if(raz='0')then
52 ect <= attente;
55 ect <= attente;
53 vectin_reg <= (others=> '0');
56 vectin_reg <= (others=> '0');
54 load <= '0';
57 load <= '0';
55 sended <= '1';
58 sended <= '1';
56
59
57 elsif(clk'event and clk='1')then
60 elsif(clk'event and clk='1')then
58 vectin_reg <= vectin;
61 vectin_reg <= vectin;
59
62
60 case ect is
63 case ect is
61 when attente =>
64 when attente =>
62 if (send='1') then
65 if (send='1') then
63 sended <= '0';
66 sended <= '0';
64 load <= '1';
67 load <= '1';
65 ect <= serialize;
68 ect <= serialize;
66 else
69 else
67 ect <= attente;
70 ect <= attente;
68 end if;
71 end if;
69
72
70 when serialize =>
73 when serialize =>
71 load <= '0';
74 load <= '0';
72 if(CPT_ended='1')then
75 if(CPT_ended='1')then
73 ect <= attente;
76 ect <= attente;
74 sended <= '1';
77 sended <= '1';
75 end if;
78 end if;
76
79
77 end case;
80 end case;
78 end if;
81 end if;
79 end process;
82 end process;
80
83
81 process(sclk,load,raz)
84 process(sclk,load,raz)
82 begin
85 begin
83 if (raz='0')then
86 if (raz='0')then
84 vector_int <= (others=> '0');
87 vector_int <= (others=> '0');
85 N <= 16;
88 N <= 16;
86 elsif(load='1')then
89 elsif(load='1')then
87 vector_int <= vectin & '0';
90 vector_int <= vectin & '0';
88 N <= 0;
91 N <= 0;
89 elsif(sclk'event and sclk='1')then
92 elsif(sclk'event and sclk='1')then
90 if (CPT_ended='0') then
93 if (CPT_ended='0') then
91 vector_int <= vector_int(15 downto 0) & '0';
94 vector_int <= vector_int(15 downto 0) & '0';
92 N <= N+1;
95 N <= N+1;
93 end if;
96 end if;
94 end if;
97 end if;
95 end process;
98 end process;
96
99
97 CPT_ended <= '1' when N = 16 else '0';
100 CPT_ended <= '1' when N = 16 else '0';
98
101
99 with ect select
102 with ect select
100 Data <= vector_int(16) when serialize,
103 Data <= vector_int(16) when serialize,
101 '0' when others;
104 '0' when others;
102
105
103 end ar_Serialize;
106 end ar_Serialize;
104
107
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@@ -1,58 +1,61
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Systeme_Clock.vhd
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 library IEEE;
22 library IEEE;
21 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
22 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
23
25
24 --! Programme qui va permetre de gοΏ½nοΏ½rer l'horloge systeme (sclk)
26 --! Programme qui va permetre de gοΏ½nοΏ½rer l'horloge systeme (sclk)
25
27
26 entity Systeme_Clock is
28 entity Systeme_Clock is
27 generic(N :integer := 695); --! GοΏ½nοΏ½rique contenant le rοΏ½sultat de la division clk/sclk
29 generic(N :integer := 695); --! GοΏ½nοΏ½rique contenant le rοΏ½sultat de la division clk/sclk
28 port(
30 port(
29 clk, raz : in std_logic; --! Horloge et Reset globale
31 clk, raz : in std_logic; --! Horloge et Reset globale du composant
30 sclk : out std_logic --! Horloge Systeme gοΏ½nοΏ½rοΏ½e
32 sclk : out std_logic --! Horloge Systeme gοΏ½nοΏ½rοΏ½e
31 );
33 );
32 end Systeme_Clock;
34 end Systeme_Clock;
33
35
34 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
36 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
37
35 architecture ar_Systeme_Clock of Systeme_Clock is
38 architecture ar_Systeme_Clock of Systeme_Clock is
36
39
37 signal clockint : std_logic;
40 signal clockint : std_logic;
38 signal countint : integer range 0 to N/2-1;
41 signal countint : integer range 0 to N/2-1;
39
42
40 begin
43 begin
41 process (clk,raz)
44 process (clk,raz)
42 begin
45 begin
43 if(raz = '0') then
46 if(raz = '0') then
44 countint <= 0;
47 countint <= 0;
45 clockint <= '0';
48 clockint <= '0';
46 elsif (clk' event and clk='1') then
49 elsif (clk' event and clk='1') then
47 if (countint = N/2-1) then
50 if (countint = N/2-1) then
48 countint <= 0;
51 countint <= 0;
49 clockint <= not clockint;
52 clockint <= not clockint;
50 else
53 else
51 countint <= countint+1;
54 countint <= countint+1;
52 end if;
55 end if;
53 end if;
56 end if;
54 end process;
57 end process;
55
58
56 sclk <= clockint;
59 sclk <= clockint;
57
60
58 end ar_Systeme_Clock; No newline at end of file
61 end ar_Systeme_Clock;
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@@ -1,95 +1,97
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 library ieee;
22 library ieee;
20 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
21 library grlib;
24 library grlib;
22 use grlib.amba.all;
25 use grlib.amba.all;
23 -- pragma translate_off
24 use std.textio.all;
26 use std.textio.all;
25 -- pragma translate_on
26 library lpp;
27 library lpp;
27 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
28
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
29
31
30 package lpp_cna is
32 package lpp_cna is
31
33
32 component APB_CNA is
34 component APB_CNA is
33 generic (
35 generic (
34 pindex : integer := 0;
36 pindex : integer := 0;
35 paddr : integer := 0;
37 paddr : integer := 0;
36 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
37 pirq : integer := 0;
39 pirq : integer := 0;
38 abits : integer := 8);
40 abits : integer := 8);
39 port (
41 port (
40 clk : in std_logic;
42 clk : in std_logic;
41 rst : in std_logic;
43 rst : in std_logic;
42 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
43 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
44 SYNC : out std_logic;
46 SYNC : out std_logic;
45 SCLK : out std_logic;
47 SCLK : out std_logic;
46 DATA : out std_logic
48 DATA : out std_logic
47 );
49 );
48 end component;
50 end component;
49
51
50
52
51 component CNA_TabloC is
53 component CNA_TabloC is
52 port(
54 port(
53 clock : in std_logic;
55 clock : in std_logic;
54 rst : in std_logic;
56 rst : in std_logic;
55 flag_nw : in std_logic;
57 flag_nw : in std_logic;
56 bp : in std_logic;
58 bp : in std_logic;
57 Data_C : in std_logic_vector(15 downto 0);
59 Data_C : in std_logic_vector(15 downto 0);
58 SYNC : out std_logic;
60 SYNC : out std_logic;
59 SCLK : out std_logic;
61 SCLK : out std_logic;
60 Rz : out std_logic;
62 Rz : out std_logic;
61 flag_sd : out std_logic;
63 flag_sd : out std_logic;
62 Data : out std_logic
64 Data : out std_logic
63 );
65 );
64 end component;
66 end component;
65
67
66
68
67 component Systeme_Clock is
69 component Systeme_Clock is
68 generic(N :integer := 695);
70 generic(N :integer := 695);
69 port(
71 port(
70 clk, raz : in std_logic ;
72 clk, raz : in std_logic ;
71 clock : out std_logic);
73 clock : out std_logic);
72 end component;
74 end component;
73
75
74
76
75 component Gene_SYNC is
77 component Gene_SYNC is
76 port(
78 port(
77 clk,raz : in std_logic;
79 clk,raz : in std_logic;
78 send : in std_logic;
80 send : in std_logic;
79 Sysclk : in std_logic;
81 Sysclk : in std_logic;
80 OKAI_send : out std_logic;
82 OKAI_send : out std_logic;
81 SYNC : out std_logic);
83 SYNC : out std_logic);
82 end component;
84 end component;
83
85
84
86
85 component Serialize is
87 component Serialize is
86 port(
88 port(
87 clk,raz : in std_logic;
89 clk,raz : in std_logic;
88 sclk : in std_logic;
90 sclk : in std_logic;
89 vectin : in std_logic_vector(15 downto 0);
91 vectin : in std_logic_vector(15 downto 0);
90 send : in std_logic;
92 send : in std_logic;
91 sended : out std_logic;
93 sended : out std_logic;
92 Data : out std_logic);
94 Data : out std_logic);
93 end component;
95 end component;
94
96
95 end;
97 end;
Show file before | Show file after | Hide comments
@@ -1,136 +1,152
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 library ieee;
22 library ieee;
20 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
21 library grlib;
24 library grlib;
22 use grlib.amba.all;
25 use grlib.amba.all;
23 use grlib.stdlib.all;
26 use grlib.stdlib.all;
24 use grlib.devices.all;
27 use grlib.devices.all;
25 library lpp;
28 library lpp;
26 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
27 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
28 use lpp.lpp_uart.all;
31 use lpp.lpp_uart.all;
29
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba
34
30 entity APB_UART is
35 entity APB_UART is
31 generic (
36 generic (
32 pindex : integer := 0;
37 pindex : integer := 0;
33 paddr : integer := 0;
38 paddr : integer := 0;
34 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
35 pirq : integer := 0;
40 pirq : integer := 0;
36 abits : integer := 8;
41 abits : integer := 8;
37 Data_sz : integer := 8);
42 Data_sz : integer := 8);
38 port (
43 port (
39 clk : in std_logic;
44 clk : in std_logic; --! Horloge du composant
40 rst : in std_logic;
45 rst : in std_logic; --! Reset general du composant
41 apbi : in apb_slv_in_type;
46 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
42 apbo : out apb_slv_out_type;
47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
43 TXD : out std_logic;
48 TXD : out std_logic; --! Transmission sοΏ½rie, cοΏ½tοΏ½ composant
44 RXD : in std_logic
49 RXD : in std_logic --! Reception sοΏ½rie, cοΏ½tοΏ½ composant
45 );
50 );
46 end APB_UART;
51 end APB_UART;
47
52
48
53
49 architecture ar_APB_UART of APB_UART is
54 architecture ar_APB_UART of APB_UART is
50
55
51 constant REVISION : integer := 1;
56 constant REVISION : integer := 1;
52
57
53 constant pconfig : apb_config_type := (
58 constant pconfig : apb_config_type := (
54 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
59 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
55 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask));
56
61
57 signal NwData : std_logic;
62 signal NwData : std_logic;
58 signal ACK : std_logic;
63 signal ACK : std_logic;
59 signal Capture : std_logic;
64 signal Capture : std_logic;
60 signal Send : std_logic;
65 signal Send : std_logic;
61 signal Sended : std_logic;
66 signal Sended : std_logic;
62
67
63 type UART_ctrlr_Reg is record
68 type UART_ctrlr_Reg is record
64 UART_Cfg : std_logic_vector(4 downto 0);
69 UART_Cfg : std_logic_vector(2 downto 0);
65 UART_Wdata : std_logic_vector(7 downto 0);
70 UART_Wdata : std_logic_vector(7 downto 0);
66 UART_Rdata : std_logic_vector(7 downto 0);
71 UART_Rdata : std_logic_vector(7 downto 0);
67 UART_BTrig : std_logic_vector(11 downto 0);
72 UART_BTrig : std_logic_vector(11 downto 0);
68 end record;
73 end record;
69
74
70 signal Rec : UART_ctrlr_Reg;
75 signal Rec : UART_ctrlr_Reg;
71 signal Rdata : std_logic_vector(31 downto 0);
76 signal Rdata : std_logic_vector(31 downto 0);
77 signal temp_ND : std_logic;
72
78
73 begin
79 begin
74
80
75 Capture <= Rec.UART_Cfg(0);
81 Capture <= Rec.UART_Cfg(0);
76 --ACK <= Rec.UART_Cfg(1);
82 --ACK <= Rec.UART_Cfg(1);
77 --Send <= Rec.UART_Cfg(2);
83 --Send <= Rec.UART_Cfg(1);
78 Rec.UART_Cfg(3) <= Sended;
84 Rec.UART_Cfg(1) <= Sended;
79 Rec.UART_Cfg(4) <= NwData;
85 Rec.UART_Cfg(2) <= NwData;
80
86
81
87
82 COM0 : entity work.UART
88 COM0 : entity work.UART
83 generic map (Data_sz)
89 generic map (Data_sz)
84 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
90 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
85
91
86
92
87 process(rst,clk)
93 process(rst,clk)
88 begin
94 begin
89 if(rst='0')then
95 if(rst='0')then
90 Rec.UART_Wdata <= (others => '0');
96 Rec.UART_Wdata <= (others => '0');
91
97
92
98
93 elsif(clk'event and clk='1')then
99 elsif(clk'event and clk='1')then
94
100 temp_ND <= NwData;
101 if(NwData='1' and temp_ND='1')then
102 ACK <= '1';
103 else
104 ACK <= '0';
105 end if;
95
106
96 --APB Write OP
107 --APB Write OP
97 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
108 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 case apbi.paddr(7 downto 2) is
109 case apbi.paddr(7 downto 2) is
99 when "000000" =>
110 when "000000" =>
100 Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
111 Rec.UART_Cfg(0) <= apbi.pwdata(0);
112 --Rec.UART_Cfg(1) <= apbi.pwdata(4);
101 when "000001" =>
113 when "000001" =>
102 Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
114 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
103 Send <= '1';
115 Send <= '1';
104 when others =>
116 when others =>
105 null;
117 null;
106 end case;
118 end case;
107 else
119 else
108 Send <= '0';
120 Send <= '0';
109 end if;
121 end if;
110
122
111 --APB READ OP
123 --APB READ OP
112 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
124 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
113 case apbi.paddr(7 downto 2) is
125 case apbi.paddr(7 downto 2) is
114 when "000000" =>
126 when "000000" =>
115 Rdata(4 downto 0) <= Rec.UART_Cfg;
127 Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0);
116 Rdata(26 downto 12) <= (others => '0');
128 Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1);
117 Rdata(27 downto 16) <= Rec.UART_BTrig;
129 Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2);
130 Rdata(19 downto 12) <= X"EE";
131 Rdata(31 downto 20) <= Rec.UART_BTrig;
118 when "000001" =>
132 when "000001" =>
133 Rdata(31 downto 8) <= X"EEEEEE";
119 Rdata(7 downto 0) <= Rec.UART_Wdata;
134 Rdata(7 downto 0) <= Rec.UART_Wdata;
120 when "000010" =>
135 when "000010" =>
136 Rdata(31 downto 8) <= X"EEEEEE";
121 Rdata(7 downto 0) <= Rec.UART_Rdata;
137 Rdata(7 downto 0) <= Rec.UART_Rdata;
122 Ack <= '1';
138 --Ack <= '1';
123 when others =>
139 when others =>
124 Rdata <= (others => '0');
140 Rdata <= (others => '0');
125 end case;
141 end case;
126 else
142 --else
127 Ack <= '0';
143 --Ack <= '0';
128 end if;
144 end if;
129
145
130 end if;
146 end if;
131 apbo.pconfig <= pconfig;
147 apbo.pconfig <= pconfig;
132 end process;
148 end process;
133
149
134 apbo.prdata <= Rdata when apbi.penable = '1';
150 apbo.prdata <= Rdata when apbi.penable = '1';
135
151
136 end ar_APB_UART;
152 end ar_APB_UART;
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@@ -1,112 +1,115
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 --! Gestion Reception/Transmission
26 --! Gestion Reception/Transmission
27
27
28 entity Shift_REG is
28 entity Shift_REG is
29 generic(Data_sz : integer := 10);
29 generic(Data_sz : integer := 10);
30 port(
30 port(
31 clk : in std_logic;
31 clk : in std_logic;
32 Sclk : in std_logic;
32 Sclk : in std_logic;
33 reset : in std_logic;
33 reset : in std_logic;
34 SIN : in std_logic;
34 SIN : in std_logic;
35 SOUT : out std_logic;
35 SOUT : out std_logic;
36 Serialize : in std_logic;
36 Serialize : in std_logic;
37 Serialized : out std_logic;
37 Serialized : out std_logic;
38 D : in std_logic_vector(Data_sz-1 downto 0);
38 D : in std_logic_vector(Data_sz-1 downto 0);
39 Q : out std_logic_vector(Data_sz-1 downto 0)
39 Q : out std_logic_vector(Data_sz-1 downto 0)
40 );
40 );
41 end entity;
41 end entity;
42
42
43
43
44 architecture ar_Shift_REG of Shift_REG is
44 architecture ar_Shift_REG of Shift_REG is
45
45
46 signal REG : std_logic_vector(Data_sz-1 downto 0);
46 signal REG : std_logic_vector(Data_sz-1 downto 0);
47 signal Serialized_int : std_logic;
47 signal Serialized_int : std_logic;
48 signal Serialize_reg : std_logic;
48 signal Serialize_reg : std_logic;
49 signal Serial_reg : std_logic;
49 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
50 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
50 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
51 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
51 signal CptBits_flag : std_logic;
52 signal CptBits_flag : std_logic;
52 signal CptBits_flag_reg : std_logic;
53 signal CptBits_flag_reg : std_logic;
53
54
54 begin
55 begin
55
56
56 Serialized <= Serialized_int;
57 Serialized <= Serialized_int;
57 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
58 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
58
59
59 process(reset,clk)
60 process(reset,clk)
60 begin
61 begin
61 if reset = '0' then
62 if reset = '0' then
62 Serialized_int <= '1';
63 Serialized_int <= '1';
63 CptBits_flag_reg <= '0';
64 CptBits_flag_reg <= '0';
65 Serial_reg <= '0';
64 Q <= (others => '0');
66 Q <= (others => '0');
65 elsif clk'event and clk = '1' then
67 elsif clk'event and clk = '1' then
66 CptBits_flag_reg <= CptBits_flag;
68 CptBits_flag_reg <= CptBits_flag;
69 Serial_reg <= Serialize;
67
70
68 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
71 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
69 Serialized_int <= '1';
72 Serialized_int <= '1';
70 Q <= REG;
73 Q <= REG;
71 elsif Serialize = '1' then
74 elsif(Serial_reg='0' and Serialize='1')then
72 Serialized_int <= '0';
75 Serialized_int <= '0';
73 end if;
76 end if;
74 end if;
77 end if;
75 end process;
78 end process;
76
79
77
80
78 process(reset,Sclk)
81 process(reset,Sclk)
79 begin
82 begin
80 if reset = '0' then
83 if reset = '0' then
81 CptBits <= (others => '0');
84 CptBits <= (others => '0');
82 REG <= (others => '0');
85 REG <= (others => '0');
83 SOUT <= '1';
86 SOUT <= '1';
84 Serialize_reg <= '0';
87 Serialize_reg <= '0';
85 elsif Sclk'event and Sclk = '1' then
88 elsif Sclk'event and Sclk = '1' then
86 Serialize_reg <= Serialized_int;
89 Serialize_reg <= Serialized_int;
87 if (Serialized_int = '0' and Serialize_reg ='1') then
90 if (Serialized_int = '0' and Serialize_reg ='1') then
88 REG <= SIN & D(Data_sz-1 downto 1);
91 REG <= SIN & D(Data_sz-1 downto 1);
89 SOUT <= D(0);
92 SOUT <= D(0);
90 elsif CptBits_flag ='1' then
93 elsif CptBits_flag ='1' then
91 REG <= SIN & D(Data_sz-1 downto 1);
94 REG <= SIN & D(Data_sz-1 downto 1);
92 SOUT <= D(0);
95 SOUT <= D(0);
93 elsif Serialized_int = '0' then
96 elsif Serialized_int = '0' then
94 REG <= SIN & REG(Data_sz-1 downto 1);
97 REG <= SIN & REG(Data_sz-1 downto 1);
95 SOUT <= REG(0);
98 SOUT <= REG(0);
96 else
99 else
97 SOUT <= '1';
100 SOUT <= '1';
98 end if;
101 end if;
99 if Serialized_int = '0' then
102 if Serialized_int = '0' then
100 if CptBits_flag = '1' then
103 if CptBits_flag = '1' then
101 CptBits <= (others => '0');
104 CptBits <= (others => '0');
102 else
105 else
103 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
106 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
104 end if;
107 end if;
105 else
108 else
106 CptBits <= (others => '0');
109 CptBits <= (others => '0');
107 end if;
110 end if;
108
111
109 end if;
112 end if;
110 end process;
113 end process;
111
114
112 end ar_Shift_REG;
115 end ar_Shift_REG;
Show file before | Show file after | Hide comments
@@ -1,106 +1,106
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_uart.all;
26 use lpp.lpp_uart.all;
27
27
28 --! Programme qui va gerer toute la communication entre le PC et le FPGA
28 --! Programme qui va gerer toute la communication entre le PC et le FPGA
29
29
30 entity UART is
30 entity UART is
31 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
31 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
32 port(
32 port(
33 clk : in std_logic; --! Horloge a 25Mhz du systeme
33 clk : in std_logic; --! Horloge a 25Mhz du systeme
34 reset : in std_logic; --! Reset du systeme
34 reset : in std_logic; --! Reset du systeme
35 TXD : out std_logic; --! Transmission, cote PC
35 TXD : out std_logic; --! Transmission, cote PC
36 RXD : in std_logic; --! Reception, cote PC
36 RXD : in std_logic; --! Reception, cote PC
37 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
37 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
38 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
38 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
39 ACK : in std_logic; --! Flag, Reponse au flag precedent
39 ACK : in std_logic; --! Flag, Reponse au flag precedent
40 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
40 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
41 Sended : out std_logic; --! Flag, Envoi termine
41 Sended : out std_logic; --! Flag, Envoi termine
42 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
42 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
43 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
43 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
44 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
44 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
45 );
45 );
46 end entity;
46 end entity;
47
47
48
49 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
48 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
50 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
49 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
50
51 architecture ar_UART of UART is
51 architecture ar_UART of UART is
52 signal Bclk : std_logic;
52 signal Bclk : std_logic;
53
53
54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
56
56
57 signal TXD_Dummy : std_logic;
57 signal TXD_Dummy : std_logic;
58 signal NwDat_int : std_logic;
58 signal NwDat_int : std_logic;
59 signal NwDat_int_reg : std_logic;
59 signal NwDat_int_reg : std_logic;
60 signal receive : std_logic;
60 signal receive : std_logic;
61 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
61 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
62
62
63 begin
63 begin
64
64
65
65
66
66
67 WDATA_int <= '1' & WDATA & '0';
67 WDATA_int <= '1' & WDATA & '0';
68
68
69 BaudGenerator : BaudGen
69 BaudGenerator : BaudGen
70 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
70 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
71
71
72
72
73 RX_REG : Shift_REG
73 RX_REG : Shift_REG
74 generic map(Data_sz+2)
74 generic map(Data_sz+2)
75 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
75 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
76
76
77 TX_REG : Shift_REG
77 TX_REG : Shift_REG
78 generic map(Data_sz+2)
78 generic map(Data_sz+2)
79 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
79 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
80
80
81
81
82
82
83 process(clk,reset)
83 process(clk,reset)
84 begin
84 begin
85 if reset = '0' then
85 if reset = '0' then
86 NwDat <= '0';
86 NwDat <= '0';
87 elsif clk'event and clk = '1' then
87 elsif clk'event and clk = '1' then
88 NwDat_int_reg <= NwDat_int;
88 NwDat_int_reg <= NwDat_int;
89 if RXD = '1' and NwDat_int = '1' then
89 if RXD = '1' and NwDat_int = '1' then
90 receive <= '0';
90 receive <= '0';
91 elsif RXD = '0' then
91 elsif RXD = '0' then
92 receive <= '1';
92 receive <= '1';
93 end if;
93 end if;
94 if NwDat_int_reg = '0' and NwDat_int = '1' then
94 if NwDat_int_reg = '0' and NwDat_int = '1' then
95 NwDat <= '1';
95 NwDat <= '1';
96 RDATA <= RDATA_int(8 downto 1);
96 RDATA <= RDATA_int(8 downto 1);
97 elsif ack = '1' then
97 elsif ack = '1' then
98 NwDat <= '0';
98 NwDat <= '0';
99 end if;
99 end if;
100 end if;
100 end if;
101 end process;
101 end process;
102
102
103 end ar_UART;
103 end ar_UART;
104
104
105
105
106
106
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