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(MINI_LFR) WaveFormPicker.0.0.0B : Update to correctly soft reset the Waveform_FIFO
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r291:53b6541de175 WaveFormPicker-0-0-0B (MINI-LFR) JC
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@@ -2,13 +2,13 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
3 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
4 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
4 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run
5 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
5 add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out
6 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
6 add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out
7 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
7 add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out
8 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
8 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid
9 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
9 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid
10 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
10 add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid
11 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
11 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd
12 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
12 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address
13 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
13 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
14 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
14 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
@@ -23,20 +23,20 add wave -noupdate -group DMA_S_or_B /te
23 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
23 add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
24 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
24 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin
25 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
25 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout
26 add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
26 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain
27 add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data
27 add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data
28 add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant
28 add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant
29 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
29 add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout
30 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0
30 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0
31 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0
31 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0
32 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1
32 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1
33 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1
33 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1
34 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2
34 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2
35 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
35 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2
36 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3
36 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3
37 add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3
37 add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3
38 TreeUpdate [SetDefaultTree]
38 TreeUpdate [SetDefaultTree]
39 WaveRestoreCursors {{Cursor 1} {12913873180 ps} 0}
39 WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0}
40 configure wave -namecolwidth 540
40 configure wave -namecolwidth 540
41 configure wave -valuecolwidth 316
41 configure wave -valuecolwidth 316
42 configure wave -justifyvalue left
42 configure wave -justifyvalue left
@@ -51,4 +51,4 configure wave -griddelta 40
51 configure wave -timeline 0
51 configure wave -timeline 0
52 configure wave -timelineunits ns
52 configure wave -timelineunits ns
53 update
53 update
54 WaveRestoreZoom {0 ps} {63240778126 ps}
54 WaveRestoreZoom {0 ps} {628873035 ns}
Show file before | Show file after | Hide comments
@@ -131,7 +131,7 ARCHITECTURE beh OF MINI_LFR_top IS
131 SIGNAL I00_s : STD_LOGIC;
131 SIGNAL I00_s : STD_LOGIC;
132
132
133 -- CONSTANTS
133 -- CONSTANTS
134 constant CFG_PADTECH : integer := inferred;
134 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 --
135 --
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
136 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
137 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
@@ -148,9 +148,9 ARCHITECTURE beh OF MINI_LFR_top IS
148 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxtxclk : std_ulogic;
151 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxclkn : std_ulogic;
152 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_clk : std_logic;
153 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL swni : grspw_in_type;
154 SIGNAL swni : grspw_in_type;
155 SIGNAL swno : grspw_out_type;
155 SIGNAL swno : grspw_out_type;
156 -- SIGNAL clkmn : STD_ULOGIC;
156 -- SIGNAL clkmn : STD_ULOGIC;
@@ -208,7 +208,7 BEGIN -- beh
208 --IO9 <= '0';
208 --IO9 <= '0';
209 --IO10 <= '0';
209 --IO10 <= '0';
210 --IO11 <= '0';
210 --IO11 <= '0';
211 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
211 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
212 LED0 <= '0';
212 LED0 <= '0';
213 LED1 <= '1';
213 LED1 <= '1';
214 LED2 <= BP0;
214 LED2 <= BP0;
@@ -230,7 +230,7 BEGIN -- beh
230 BEGIN -- PROCESS
230 BEGIN -- PROCESS
231 IF reset = '0' THEN -- asynchronous reset (active low)
231 IF reset = '0' THEN -- asynchronous reset (active low)
232 I00_s <= '0';
232 I00_s <= '0';
233 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
233 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
234 I00_s <= NOT I00_s;
234 I00_s <= NOT I00_s;
235 END IF;
235 END IF;
236 END PROCESS;
236 END PROCESS;
@@ -318,47 +318,47 BEGIN -- beh
318
318
319 spw_clk <= clk_50_s;
319 spw_clk <= clk_50_s;
320 spw_rxtxclk <= spw_clk;
320 spw_rxtxclk <= spw_clk;
321 spw_rxclkn <= not spw_rxtxclk;
321 spw_rxclkn <= NOT spw_rxtxclk;
322
322
323 -- PADS for SPW1
323 -- PADS for SPW1
324 spw1_rxd_pad : inpad generic map (tech => inferred)
324 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
325 port map (SPW_NOM_DIN, dtmp(0));
325 PORT MAP (SPW_NOM_DIN, dtmp(0));
326 spw1_rxs_pad : inpad generic map (tech => inferred)
326 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
327 port map (SPW_NOM_SIN, stmp(0));
327 PORT MAP (SPW_NOM_SIN, stmp(0));
328 spw1_txd_pad : outpad generic map (tech => inferred)
328 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
329 port map (SPW_NOM_DOUT, swno.d(0));
329 PORT MAP (SPW_NOM_DOUT, swno.d(0));
330 spw1_txs_pad : outpad generic map (tech => inferred)
330 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
331 port map (SPW_NOM_SOUT, swno.s(0));
331 PORT MAP (SPW_NOM_SOUT, swno.s(0));
332 -- PADS FOR SPW2
332 -- PADS FOR SPW2
333 spw2_rxd_pad : inpad generic map (tech => inferred) -- bad naming of the MINI-LFR /!\
333 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
334 port map (SPW_RED_SIN, dtmp(1));
334 PORT MAP (SPW_RED_SIN, dtmp(1));
335 spw2_rxs_pad : inpad generic map (tech => inferred) -- bad naming of the MINI-LFR /!\
335 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 port map (SPW_RED_DIN, stmp(1));
336 PORT MAP (SPW_RED_DIN, stmp(1));
337 spw2_txd_pad : outpad generic map (tech => inferred)
337 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
338 port map (SPW_RED_DOUT, swno.d(1));
338 PORT MAP (SPW_RED_DOUT, swno.d(1));
339 spw2_txs_pad : outpad generic map (tech => inferred)
339 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
340 port map (SPW_RED_SOUT, swno.s(1));
340 PORT MAP (SPW_RED_SOUT, swno.s(1));
341
341
342 -- GRSPW PHY
342 -- GRSPW PHY
343 --spw1_input: if CFG_SPW_GRSPW = 1 generate
343 --spw1_input: if CFG_SPW_GRSPW = 1 generate
344 spw_inputloop: for j in 0 to 1 generate
344 spw_inputloop : FOR j IN 0 TO 1 GENERATE
345 spw_phy0 : grspw_phy
345 spw_phy0 : grspw_phy
346 generic map(
346 GENERIC MAP(
347 tech => apa3e,
347 tech => apa3e,
348 rxclkbuftype => 1,
348 rxclkbuftype => 1,
349 scantest => 0)
349 scantest => 0)
350 port map(
350 PORT MAP(
351 rxrst => swno.rxrst,
351 rxrst => swno.rxrst,
352 di => dtmp(j),
352 di => dtmp(j),
353 si => stmp(j),
353 si => stmp(j),
354 rxclko => spw_rxclk(j),
354 rxclko => spw_rxclk(j),
355 do => swni.d(j),
355 do => swni.d(j),
356 ndo => swni.nd(j*5+4 downto j*5),
356 ndo => swni.nd(j*5+4 DOWNTO j*5),
357 dconnect => swni.dconnect(j*2+1 downto j*2));
357 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
358 end generate spw_inputloop;
358 END GENERATE spw_inputloop;
359
359
360 -- SPW core
360 -- SPW core
361 sw0 : grspwm generic map(
361 sw0 : grspwm GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 hindex => 1,
363 hindex => 1,
364 pindex => 5,
364 pindex => 5,
@@ -383,7 +383,7 BEGIN -- beh
383 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
383 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
384 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
384 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
385 )
385 )
386 port map(reset, clk_25, spw_rxclk(0),
386 PORT MAP(reset, clk_25, spw_rxclk(0),
387 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
387 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
388 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
388 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
389 swni, swno);
389 swni, swno);
@@ -392,9 +392,9 BEGIN -- beh
392 swni.rmapen <= '1';
392 swni.rmapen <= '1';
393 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
393 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
394 swni.tickinraw <= '0';
394 swni.tickinraw <= '0';
395 swni.timein <= (others => '0');
395 swni.timein <= (OTHERS => '0');
396 swni.dcrstval <= (others => '0');
396 swni.dcrstval <= (OTHERS => '0');
397 swni.timerrstval <= (others => '0');
397 swni.timerrstval <= (OTHERS => '0');
398
398
399 -------------------------------------------------------------------------------
399 -------------------------------------------------------------------------------
400 -- LFR ------------------------------------------------------------------------
400 -- LFR ------------------------------------------------------------------------
@@ -498,32 +498,16 BEGIN -- beh
498 ----------------------------------------------------------------------
498 ----------------------------------------------------------------------
499
499
500 grgpio0: grgpio
500 grgpio0 : grgpio
501 generic map( pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
501 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
502 port map( reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
502 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
503
503
504 pio_pad_0 : iopad
504 pio_pad_0 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
505 generic map (tech => CFG_PADTECH)
505 pio_pad_1 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
506 port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
506 pio_pad_2 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
507 pio_pad_1 : iopad
507 pio_pad_3 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
508 generic map (tech => CFG_PADTECH)
508 pio_pad_4 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
509 port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
509 pio_pad_5 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
510 pio_pad_2 : iopad
510 pio_pad_6 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 generic map (tech => CFG_PADTECH)
511 pio_pad_7 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
512 port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
513 pio_pad_3 : iopad
514 generic map (tech => CFG_PADTECH)
515 port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
516 pio_pad_4 : iopad
517 generic map (tech => CFG_PADTECH)
518 port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
519 pio_pad_5 : iopad
520 generic map (tech => CFG_PADTECH)
521 port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
522 pio_pad_6 : iopad
523 generic map (tech => CFG_PADTECH)
524 port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
525 pio_pad_7 : iopad
526 generic map (tech => CFG_PADTECH)
527 port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
528
512
529 END beh; No newline at end of file
513 END beh;
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@@ -413,7 +413,7 BEGIN -- beh
413 pirq_ms => 6,
413 pirq_ms => 6,
414 pirq_wfp => 14,
414 pirq_wfp => 14,
415 hindex => 2,
415 hindex => 2,
416 top_lfr_version => X"0000000A")
416 top_lfr_version => X"0000000B")
417 PORT MAP (
417 PORT MAP (
418 clk => clk_25,
418 clk => clk_25,
419 rstn => reset,
419 rstn => reset,
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@@ -69,7 +69,7 BEGIN
69 END IF;
69 END IF;
70 END PROCESS;
70 END PROCESS;
71
71
72 cnv <= not(cnv_s);
72 cnv <= NOT(cnv_s);
73
73
74 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
75 -- SYNC CNV
75 -- SYNC CNV
@@ -86,7 +86,7 BEGIN
86
86
87 -----------------------------------------------------------------------------
87 -----------------------------------------------------------------------------
88
88
89 cnv_sync_not <= not(cnv_sync);
89 cnv_sync_not <= NOT(cnv_sync);
90
90
91 ADS7886_drvr_v2_1 : ADS7886_drvr_v2
91 ADS7886_drvr_v2_1 : ADS7886_drvr_v2
92 GENERIC MAP(
92 GENERIC MAP(
@@ -109,23 +109,20 PROCESS (clk, rstn)
109 BEGIN -- PROCESS
109 BEGIN -- PROCESS
110 IF rstn = '0' THEN -- asynchronous reset (active low)
110 IF rstn = '0' THEN -- asynchronous reset (active low)
111 FOR k IN 0 TO ChannelCount-1 LOOP
111 FOR k IN 0 TO ChannelCount-1 LOOP
112 sample(k)(13 downto 0) <= (OTHERS => '0');
112 sample(k)(13 DOWNTO 0) <= (OTHERS => '0');
113 END LOOP;
113 END LOOP;
114 sample_val <= '0';
114 sample_val <= '0';
115 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
115 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
116 IF sample_val_adc ='1' THEN
116 IF sample_val_adc = '1' THEN
117 FOR k IN 0 TO ChannelCount-1 LOOP
117 FOR k IN 0 TO ChannelCount-1 LOOP
118 IF ( unsigned(sample_adc(k)(11 downto 0)) >= 2048) THEN
118 IF (UNSIGNED(sample_adc(k)(11 DOWNTO 0)) >= 2048) THEN
119 sample(k)(13 downto 0) <= "00" &
119 sample(k)(13 DOWNTO 0) <= "00" &
120 std_logic_vector( unsigned(sample_adc(k)(11 downto 0)) - 2048 );
120 STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048);
121 ELSE
121 ELSE
122 sample(k)(13 downto 0) <= "11" &
122 sample(k)(13 DOWNTO 0) <= "11" &
123 std_logic_vector( unsigned(sample_adc(k)(11 downto 0)) - 2048 );
123 STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048);
124 END IF;
124 END IF;
125 END LOOP;
125 END LOOP;
126 -- FOR k IN 0 TO ChannelCount-1 LOOP
127 -- sample(k) <= sample_adc(k)(13 downto 0);
128 -- END LOOP;
129 sample_val <= sample_val_adc;
126 sample_val <= sample_val_adc;
130 ELSE
127 ELSE
131 sample_val <= '0';
128 sample_val <= '0';
@@ -133,4 +130,4 PROCESS (clk, rstn)
133 END IF;
130 END IF;
134 END PROCESS;
131 END PROCESS;
135
132
136 END ar_top_ad_conv_ADS7886_v2; No newline at end of file
133 END ar_top_ad_conv_ADS7886_v2;
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@@ -573,6 +573,7 BEGIN
573 dma_send <= '0';
573 dma_send <= '0';
574 dma_valid_burst <= '0';
574 dma_valid_burst <= '0';
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
576 IF run = '1' THEN
576 -- IF dma_sel = "0000" OR dma_send = '1' THEN
577 -- IF dma_sel = "0000" OR dma_send = '1' THEN
577 IF dma_sel = "0000" OR dma_done = '1' THEN
578 IF dma_sel = "0000" OR dma_done = '1' THEN
578 dma_sel <= dma_rr_grant;
579 dma_sel <= dma_rr_grant;
@@ -597,6 +598,11 BEGIN
597 dma_sel <= dma_sel;
598 dma_sel <= dma_sel;
598 dma_send <= '0';
599 dma_send <= '0';
599 END IF;
600 END IF;
601 ELSE
602 dma_sel <= (OTHERS => '0');
603 dma_send <= '0';
604 dma_valid_burst <= '0';
605 END IF;
600 END IF;
606 END IF;
601 END PROCESS;
607 END PROCESS;
602
608
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@@ -78,7 +78,11 BEGIN
78 IF rstn = '0' THEN
78 IF rstn = '0' THEN
79 s_ren_reg <= (OTHERS => '1');
79 s_ren_reg <= (OTHERS => '1');
80 ELSIF clk'EVENT AND clk = '1' THEN
80 ELSIF clk'EVENT AND clk = '1' THEN
81 IF run = '1' THEN
81 s_ren_reg <= s_ren;
82 s_ren_reg <= s_ren;
83 ELSE
84 s_ren_reg <= (OTHERS => '1');
85 END IF;
82 END IF;
86 END IF;
83 END PROCESS;
87 END PROCESS;
84
88
@@ -118,10 +122,17 BEGIN
118 s_rdata_2 <= (OTHERS => '0');
122 s_rdata_2 <= (OTHERS => '0');
119 s_rdata_3 <= (OTHERS => '0');
123 s_rdata_3 <= (OTHERS => '0');
120 ELSIF clk'EVENT AND clk = '1' THEN
124 ELSIF clk'EVENT AND clk = '1' THEN
125 IF run = '1' THEN
121 IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
126 IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
122 IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
127 IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
123 IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
128 IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
124 IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
129 IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
130 ELSE
131 s_rdata_0 <= (OTHERS => '0');
132 s_rdata_1 <= (OTHERS => '0');
133 s_rdata_2 <= (OTHERS => '0');
134 s_rdata_3 <= (OTHERS => '0');
135 END IF;
125 END IF;
136 END IF;
126 END PROCESS;
137 END PROCESS;
127
138
@@ -132,11 +143,15 BEGIN
132 reg_full(I) <= '0';
143 reg_full(I) <= '0';
133 ELSIF clk'EVENT AND clk = '1' THEN
144 ELSIF clk'EVENT AND clk = '1' THEN
134 -- IF s_ren_reg(I) = '0' THEN
145 -- IF s_ren_reg(I) = '0' THEN
146 IF run = '1' THEN
135 IF s_ren(I) = '0' THEN
147 IF s_ren(I) = '0' THEN
136 reg_full(I) <= '1';
148 reg_full(I) <= '1';
137 ELSIF o_data_ren(I) = '0' THEN
149 ELSIF o_data_ren(I) = '0' THEN
138 reg_full(I) <= '0';
150 reg_full(I) <= '0';
139 END IF;
151 END IF;
152 ELSE
153 reg_full(I) <= '0';
154 END IF;
140 END IF;
155 END IF;
141 END PROCESS;
156 END PROCESS;
142 END GENERATE all_reg_full;
157 END GENERATE all_reg_full;
@@ -157,7 +172,7 BEGIN
157 IF rstn = '0' THEN -- asynchronous reset (active low)
172 IF rstn = '0' THEN -- asynchronous reset (active low)
158 s_empty_almost(I) <= '1';
173 s_empty_almost(I) <= '1';
159 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
174 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
160 -- IF s_ren_reg(I) = '0' THEN
175 IF run = '1' THEN
161 IF s_ren(I) = '0' THEN
176 IF s_ren(I) = '0' THEN
162 s_empty_almost(I) <= i_empty_almost(I);
177 s_empty_almost(I) <= i_empty_almost(I);
163 ELSIF o_data_ren(I) = '0' THEN
178 ELSIF o_data_ren(I) = '0' THEN
@@ -167,6 +182,9 BEGIN
167 s_empty_almost(I) <= '0';
182 s_empty_almost(I) <= '0';
168 END IF;
183 END IF;
169 END IF;
184 END IF;
185 ELSE
186 s_empty_almost(I) <= '1';
187 END IF;
170 END IF;
188 END IF;
171 END PROCESS;
189 END PROCESS;
172 END GENERATE all_empty_almost;
190 END GENERATE all_empty_almost;
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