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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY LFR_em IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk100MHz : IN STD_ULOGIC; |
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52 | 52 | clk49_152MHz : IN STD_ULOGIC; |
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53 | 53 | reset : IN STD_ULOGIC; |
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54 | 54 | |
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55 | 55 | -- TAG -------------------------------------------------------------------- |
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56 | 56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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57 | 57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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58 | 58 | -- UART APB --------------------------------------------------------------- |
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59 | 59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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60 | 60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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61 | 61 | -- RAM -------------------------------------------------------------------- |
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62 | 62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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63 | 63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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64 | 64 | nSRAM_BE0 : OUT STD_LOGIC; |
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65 | 65 | nSRAM_BE1 : OUT STD_LOGIC; |
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66 | 66 | nSRAM_BE2 : OUT STD_LOGIC; |
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67 | 67 | nSRAM_BE3 : OUT STD_LOGIC; |
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68 | 68 | nSRAM_WE : OUT STD_LOGIC; |
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69 | 69 | nSRAM_CE : OUT STD_LOGIC; |
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70 | 70 | nSRAM_OE : OUT STD_LOGIC; |
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71 | 71 | -- SPW -------------------------------------------------------------------- |
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72 | 72 | spw1_din : IN STD_LOGIC; |
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73 | 73 | spw1_sin : IN STD_LOGIC; |
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74 | 74 | spw1_dout : OUT STD_LOGIC; |
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75 | 75 | spw1_sout : OUT STD_LOGIC; |
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76 | 76 | spw2_din : IN STD_LOGIC; |
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77 | 77 | spw2_sin : IN STD_LOGIC; |
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78 | 78 | spw2_dout : OUT STD_LOGIC; |
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79 | 79 | spw2_sout : OUT STD_LOGIC; |
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80 | 80 | -- ADC -------------------------------------------------------------------- |
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81 | 81 | bias_fail_sw : OUT STD_LOGIC; |
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82 | 82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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83 | 83 | ADC_smpclk : OUT STD_LOGIC; |
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84 | 84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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85 | 85 | --------------------------------------------------------------------------- |
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86 | 86 | TAG8 : OUT STD_LOGIC; |
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87 | 87 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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88 | 88 | ); |
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89 | 89 | |
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90 | 90 | END LFR_em; |
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91 | 91 | |
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92 | 92 | |
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93 | 93 | ARCHITECTURE beh OF LFR_em IS |
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94 | 94 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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95 | 95 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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96 | 96 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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97 | 97 | ----------------------------------------------------------------------------- |
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98 | 98 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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99 | 99 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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100 | 100 | |
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101 | 101 | -- CONSTANTS |
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102 | 102 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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103 | 103 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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104 | 104 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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105 | 105 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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106 | 106 | |
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107 | 107 | SIGNAL apbi_ext : apb_slv_in_type; |
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108 | 108 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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109 | 109 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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110 | 110 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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111 | 111 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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112 | 112 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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113 | 113 | |
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114 | 114 | -- Spacewire signals |
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115 | 115 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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116 | 116 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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117 | 117 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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118 | 118 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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119 | 119 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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120 | 120 | SIGNAL spw_clk : STD_LOGIC; |
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121 | 121 | SIGNAL swni : grspw_in_type; |
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122 | 122 | SIGNAL swno : grspw_out_type; |
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123 | 123 | |
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124 | 124 | --GPIO |
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125 | 125 | SIGNAL gpioi : gpio_in_type; |
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126 | 126 | SIGNAL gpioo : gpio_out_type; |
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127 | 127 | |
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128 | 128 | -- AD Converter ADS7886 |
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129 | 129 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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130 | 130 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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131 | 131 | SIGNAL sample_val : STD_LOGIC; |
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132 | 132 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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133 | 133 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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134 | 134 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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135 | 135 | |
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136 | 136 | ----------------------------------------------------------------------------- |
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137 | 137 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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138 | 138 | |
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139 | 139 | ----------------------------------------------------------------------------- |
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140 | 140 | SIGNAL rstn : STD_LOGIC; |
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141 | ||
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142 | SIGNAL ADC_smpclk_s : STD_LOGIC; | |
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143 | ||
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141 | 144 | BEGIN -- beh |
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142 | 145 | |
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143 | 146 | ----------------------------------------------------------------------------- |
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144 | 147 | -- CLK |
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145 | 148 | ----------------------------------------------------------------------------- |
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146 | 149 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); |
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147 | 150 | |
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148 | 151 | PROCESS(clk100MHz) |
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149 | 152 | BEGIN |
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150 | 153 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
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151 | 154 | clk_50_s <= NOT clk_50_s; |
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152 | 155 | END IF; |
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153 | 156 | END PROCESS; |
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154 | 157 | |
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155 | 158 | PROCESS(clk_50_s) |
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156 | 159 | BEGIN |
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157 | 160 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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158 | 161 | clk_25 <= NOT clk_25; |
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159 | 162 | END IF; |
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160 | 163 | END PROCESS; |
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161 | 164 | |
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162 | 165 | PROCESS(clk49_152MHz) |
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163 | 166 | BEGIN |
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164 | 167 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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165 | 168 | clk_24 <= NOT clk_24; |
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166 | 169 | END IF; |
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167 | 170 | END PROCESS; |
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168 | 171 | |
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169 | 172 | ----------------------------------------------------------------------------- |
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170 | 173 | |
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171 | 174 | PROCESS (clk_25, rstn) |
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172 | 175 | BEGIN -- PROCESS |
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173 | 176 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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174 | 177 | led(0) <= '0'; |
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175 | 178 | led(1) <= '0'; |
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176 | 179 | led(2) <= '0'; |
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177 | 180 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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178 | 181 | led(0) <= '0'; |
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179 | 182 | led(1) <= '1'; |
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180 | 183 | led(2) <= '1'; |
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181 | 184 | END IF; |
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182 | 185 | END PROCESS; |
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183 | 186 | |
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184 | 187 | -- |
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185 | 188 | leon3_soc_1 : leon3_soc |
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186 | 189 | GENERIC MAP ( |
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187 | 190 | fabtech => apa3e, |
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188 | 191 | memtech => apa3e, |
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189 | 192 | padtech => inferred, |
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190 | 193 | clktech => inferred, |
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191 | 194 | disas => 0, |
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192 | 195 | dbguart => 0, |
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193 | 196 | pclow => 2, |
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194 | 197 | clk_freq => 25000, |
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195 | 198 | NB_CPU => 1, |
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196 | 199 | ENABLE_FPU => 1, |
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197 | 200 | FPU_NETLIST => 0, |
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198 | 201 | ENABLE_DSU => 1, |
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199 | 202 | ENABLE_AHB_UART => 1, |
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200 | 203 | ENABLE_APB_UART => 1, |
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201 | 204 | ENABLE_IRQMP => 1, |
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202 | 205 | ENABLE_GPT => 1, |
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203 | 206 | NB_AHB_MASTER => NB_AHB_MASTER, |
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204 | 207 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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205 | 208 | NB_APB_SLAVE => NB_APB_SLAVE) |
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206 | 209 | PORT MAP ( |
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207 | 210 | clk => clk_25, |
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208 | 211 | reset => rstn, |
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209 | 212 | errorn => OPEN, |
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210 | 213 | |
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211 | 214 | ahbrxd => TAG1, |
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212 | 215 | ahbtxd => TAG3, |
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213 | 216 | urxd1 => TAG2, |
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214 | 217 | utxd1 => TAG4, |
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215 | 218 | |
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216 | 219 | address => address, |
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217 | 220 | data => data, |
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218 | 221 | nSRAM_BE0 => nSRAM_BE0, |
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219 | 222 | nSRAM_BE1 => nSRAM_BE1, |
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220 | 223 | nSRAM_BE2 => nSRAM_BE2, |
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221 | 224 | nSRAM_BE3 => nSRAM_BE3, |
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222 | 225 | nSRAM_WE => nSRAM_WE, |
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223 | 226 | nSRAM_CE => nSRAM_CE, |
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224 | 227 | nSRAM_OE => nSRAM_OE, |
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225 | 228 | |
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226 | 229 | apbi_ext => apbi_ext, |
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227 | 230 | apbo_ext => apbo_ext, |
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228 | 231 | ahbi_s_ext => ahbi_s_ext, |
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229 | 232 | ahbo_s_ext => ahbo_s_ext, |
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230 | 233 | ahbi_m_ext => ahbi_m_ext, |
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231 | 234 | ahbo_m_ext => ahbo_m_ext); |
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232 | 235 | |
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233 | 236 | |
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234 | 237 | ------------------------------------------------------------------------------- |
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235 | 238 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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236 | 239 | ------------------------------------------------------------------------------- |
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237 | 240 | apb_lfr_time_management_1 : apb_lfr_time_management |
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238 | 241 | GENERIC MAP ( |
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239 | 242 | pindex => 6, |
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240 | 243 | paddr => 6, |
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241 | 244 | pmask => 16#fff#, |
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242 | 245 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
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243 | 246 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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244 | 247 | PORT MAP ( |
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245 | 248 | clk25MHz => clk_25, |
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246 | 249 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
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247 | 250 | resetn => rstn, |
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248 | 251 | grspw_tick => swno.tickout, |
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249 | 252 | apbi => apbi_ext, |
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250 | 253 | apbo => apbo_ext(6), |
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251 | 254 | coarse_time => coarse_time, |
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252 | 255 | fine_time => fine_time); |
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253 | 256 | |
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254 | 257 | ----------------------------------------------------------------------- |
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255 | 258 | --- SpaceWire -------------------------------------------------------- |
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256 | 259 | ----------------------------------------------------------------------- |
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257 | 260 | |
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258 | 261 | -- SPW_EN <= '1'; |
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259 | 262 | |
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260 | 263 | spw_clk <= clk_50_s; |
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261 | 264 | spw_rxtxclk <= spw_clk; |
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262 | 265 | spw_rxclkn <= NOT spw_rxtxclk; |
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263 | 266 | |
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264 | 267 | -- PADS for SPW1 |
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265 | 268 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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266 | 269 | PORT MAP (spw1_din, dtmp(0)); |
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267 | 270 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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268 | 271 | PORT MAP (spw1_sin, stmp(0)); |
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269 | 272 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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270 | 273 | PORT MAP (spw1_dout, swno.d(0)); |
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271 | 274 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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272 | 275 | PORT MAP (spw1_sout, swno.s(0)); |
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273 | 276 | -- PADS FOR SPW2 |
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274 | 277 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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275 | 278 | PORT MAP (spw2_sin, dtmp(1)); |
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276 | 279 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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277 | 280 | PORT MAP (spw2_din, stmp(1)); |
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278 | 281 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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279 | 282 | PORT MAP (spw2_dout, swno.d(1)); |
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280 | 283 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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281 | 284 | PORT MAP (spw2_sout, swno.s(1)); |
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282 | 285 | |
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283 | 286 | -- GRSPW PHY |
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284 | 287 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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285 | 288 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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286 | 289 | spw_phy0 : grspw_phy |
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287 | 290 | GENERIC MAP( |
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288 | 291 | tech => apa3e, |
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289 | 292 | rxclkbuftype => 1, |
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290 | 293 | scantest => 0) |
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291 | 294 | PORT MAP( |
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292 | 295 | rxrst => swno.rxrst, |
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293 | 296 | di => dtmp(j), |
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294 | 297 | si => stmp(j), |
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295 | 298 | rxclko => spw_rxclk(j), |
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296 | 299 | do => swni.d(j), |
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297 | 300 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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298 | 301 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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299 | 302 | END GENERATE spw_inputloop; |
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300 | 303 | |
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301 | 304 | -- SPW core |
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302 | 305 | sw0 : grspwm GENERIC MAP( |
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303 | 306 | tech => apa3e, |
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304 | 307 | hindex => 1, |
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305 | 308 | pindex => 5, |
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306 | 309 | paddr => 5, |
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307 | 310 | pirq => 11, |
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308 | 311 | sysfreq => 25000, -- CPU_FREQ |
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309 | 312 | rmap => 1, |
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310 | 313 | rmapcrc => 1, |
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311 | 314 | fifosize1 => 16, |
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312 | 315 | fifosize2 => 16, |
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313 | 316 | rxclkbuftype => 1, |
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314 | 317 | rxunaligned => 0, |
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315 | 318 | rmapbufs => 4, |
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316 | 319 | ft => 0, |
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317 | 320 | netlist => 0, |
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318 | 321 | ports => 2, |
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319 | 322 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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320 | 323 | memtech => apa3e, |
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321 | 324 | destkey => 2, |
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322 | 325 | spwcore => 1 |
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323 | 326 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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324 | 327 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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325 | 328 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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326 | 329 | ) |
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327 | 330 | PORT MAP(rstn, clk_25, spw_rxclk(0), |
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328 | 331 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
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329 | 332 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
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330 | 333 | swni, swno); |
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331 | 334 | |
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332 | 335 | swni.tickin <= '0'; |
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333 | 336 | swni.rmapen <= '1'; |
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334 | 337 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
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335 | 338 | swni.tickinraw <= '0'; |
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336 | 339 | swni.timein <= (OTHERS => '0'); |
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337 | 340 | swni.dcrstval <= (OTHERS => '0'); |
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338 | 341 | swni.timerrstval <= (OTHERS => '0'); |
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339 | 342 | |
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340 | 343 | ------------------------------------------------------------------------------- |
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341 | 344 | -- LFR ------------------------------------------------------------------------ |
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342 | 345 | ------------------------------------------------------------------------------- |
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343 | 346 | lpp_lfr_1 : lpp_lfr |
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344 | 347 | GENERIC MAP ( |
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345 | 348 | Mem_use => use_RAM, |
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346 | 349 | nb_data_by_buffer_size => 32, |
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347 | 350 | nb_word_by_buffer_size => 30, |
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348 | 351 | nb_snapshot_param_size => 32, |
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349 | 352 | delta_vector_size => 32, |
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350 | 353 | delta_vector_size_f0_2 => 7, -- log2(96) |
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351 | 354 | pindex => 15, |
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352 | 355 | paddr => 15, |
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353 | 356 | pmask => 16#fff#, |
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354 | 357 | pirq_ms => 6, |
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355 | 358 | pirq_wfp => 14, |
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356 | 359 | hindex => 2, |
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357 | 360 | top_lfr_version => X"010117") -- aa.bb.cc version |
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358 | 361 | -- AA : BOARD NUMBER |
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359 | 362 | -- 0 => MINI_LFR |
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360 | 363 | -- 1 => EM |
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361 | 364 | PORT MAP ( |
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362 | 365 | clk => clk_25, |
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363 | 366 | rstn => rstn, |
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364 | 367 | sample_B => sample_s(2 DOWNTO 0), |
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365 | 368 | sample_E => sample_s(7 DOWNTO 3), |
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366 | 369 | sample_val => sample_val, |
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367 | 370 | apbi => apbi_ext, |
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368 | 371 | apbo => apbo_ext(15), |
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369 | 372 | ahbi => ahbi_m_ext, |
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370 | 373 | ahbo => ahbo_m_ext(2), |
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371 | 374 | coarse_time => coarse_time, |
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372 | 375 | fine_time => fine_time, |
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373 | 376 | data_shaping_BW => bias_fail_sw, |
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377 | observation_vector_0 => OPEN, | |
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378 | observation_vector_1 => OPEN, | |
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374 | 379 | observation_reg => observation_reg); |
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375 | 380 | |
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376 | 381 | |
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377 | 382 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
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378 | 383 | sample_s(I) <= sample(I) & '0' & '0'; |
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379 | 384 | END GENERATE all_sample; |
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380 | 385 | |
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381 | 386 | ----------------------------------------------------------------------------- |
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382 | 387 | -- |
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383 | 388 | ----------------------------------------------------------------------------- |
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384 | 389 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
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385 | 390 | GENERIC MAP ( |
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386 | 391 | ChanelCount => 8, |
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387 | 392 | ncycle_cnv_high => 40, -- TODO : 79 |
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388 | 393 | ncycle_cnv => 250) -- TODO : 500 |
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389 | 394 | PORT MAP ( |
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390 | 395 | cnv_clk => clk_24, -- TODO : 49.152 |
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391 | 396 | cnv_rstn => rstn, -- ok |
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392 | cnv => ADC_smpclk, -- ok | |
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397 | cnv => ADC_smpclk_s, -- ok | |
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393 | 398 | clk => clk_25, -- ok |
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394 | 399 | rstn => rstn, -- ok |
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395 | 400 | ADC_data => ADC_data, -- ok |
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396 | 401 | ADC_nOE => ADC_OEB_bar_CH, -- ok |
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397 | 402 | sample => sample, -- ok |
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398 | 403 | sample_val => sample_val); -- ok |
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399 | 404 | |
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400 |
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405 | ADC_smpclk <= ADC_smpclk_s; | |
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406 | ||
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407 | TAG8 <= ADC_smpclk_s; | |
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401 | 408 | |
|
402 | 409 | END beh; |
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