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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 ---------------------------------------------------------------------------
86 86 TAG8 : OUT STD_LOGIC;
87 87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 88 );
89 89
90 90 END LFR_em;
91 91
92 92
93 93 ARCHITECTURE beh OF LFR_em IS
94 94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 95 SIGNAL clk_25 : STD_LOGIC := '0';
96 96 SIGNAL clk_24 : STD_LOGIC := '0';
97 97 -----------------------------------------------------------------------------
98 98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 100
101 101 -- CONSTANTS
102 102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106 106
107 107 SIGNAL apbi_ext : apb_slv_in_type;
108 108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113 113
114 114 -- Spacewire signals
115 115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 120 SIGNAL spw_clk : STD_LOGIC;
121 121 SIGNAL swni : grspw_in_type;
122 122 SIGNAL swno : grspw_out_type;
123 123
124 124 --GPIO
125 125 SIGNAL gpioi : gpio_in_type;
126 126 SIGNAL gpioo : gpio_out_type;
127 127
128 128 -- AD Converter ADS7886
129 129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 131 SIGNAL sample_val : STD_LOGIC;
132 132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135 135
136 136 -----------------------------------------------------------------------------
137 137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 138
139 139 -----------------------------------------------------------------------------
140 140 SIGNAL rstn : STD_LOGIC;
141
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
143
141 144 BEGIN -- beh
142 145
143 146 -----------------------------------------------------------------------------
144 147 -- CLK
145 148 -----------------------------------------------------------------------------
146 149 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
147 150
148 151 PROCESS(clk100MHz)
149 152 BEGIN
150 153 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
151 154 clk_50_s <= NOT clk_50_s;
152 155 END IF;
153 156 END PROCESS;
154 157
155 158 PROCESS(clk_50_s)
156 159 BEGIN
157 160 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
158 161 clk_25 <= NOT clk_25;
159 162 END IF;
160 163 END PROCESS;
161 164
162 165 PROCESS(clk49_152MHz)
163 166 BEGIN
164 167 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
165 168 clk_24 <= NOT clk_24;
166 169 END IF;
167 170 END PROCESS;
168 171
169 172 -----------------------------------------------------------------------------
170 173
171 174 PROCESS (clk_25, rstn)
172 175 BEGIN -- PROCESS
173 176 IF rstn = '0' THEN -- asynchronous reset (active low)
174 177 led(0) <= '0';
175 178 led(1) <= '0';
176 179 led(2) <= '0';
177 180 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
178 181 led(0) <= '0';
179 182 led(1) <= '1';
180 183 led(2) <= '1';
181 184 END IF;
182 185 END PROCESS;
183 186
184 187 --
185 188 leon3_soc_1 : leon3_soc
186 189 GENERIC MAP (
187 190 fabtech => apa3e,
188 191 memtech => apa3e,
189 192 padtech => inferred,
190 193 clktech => inferred,
191 194 disas => 0,
192 195 dbguart => 0,
193 196 pclow => 2,
194 197 clk_freq => 25000,
195 198 NB_CPU => 1,
196 199 ENABLE_FPU => 1,
197 200 FPU_NETLIST => 0,
198 201 ENABLE_DSU => 1,
199 202 ENABLE_AHB_UART => 1,
200 203 ENABLE_APB_UART => 1,
201 204 ENABLE_IRQMP => 1,
202 205 ENABLE_GPT => 1,
203 206 NB_AHB_MASTER => NB_AHB_MASTER,
204 207 NB_AHB_SLAVE => NB_AHB_SLAVE,
205 208 NB_APB_SLAVE => NB_APB_SLAVE)
206 209 PORT MAP (
207 210 clk => clk_25,
208 211 reset => rstn,
209 212 errorn => OPEN,
210 213
211 214 ahbrxd => TAG1,
212 215 ahbtxd => TAG3,
213 216 urxd1 => TAG2,
214 217 utxd1 => TAG4,
215 218
216 219 address => address,
217 220 data => data,
218 221 nSRAM_BE0 => nSRAM_BE0,
219 222 nSRAM_BE1 => nSRAM_BE1,
220 223 nSRAM_BE2 => nSRAM_BE2,
221 224 nSRAM_BE3 => nSRAM_BE3,
222 225 nSRAM_WE => nSRAM_WE,
223 226 nSRAM_CE => nSRAM_CE,
224 227 nSRAM_OE => nSRAM_OE,
225 228
226 229 apbi_ext => apbi_ext,
227 230 apbo_ext => apbo_ext,
228 231 ahbi_s_ext => ahbi_s_ext,
229 232 ahbo_s_ext => ahbo_s_ext,
230 233 ahbi_m_ext => ahbi_m_ext,
231 234 ahbo_m_ext => ahbo_m_ext);
232 235
233 236
234 237 -------------------------------------------------------------------------------
235 238 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
236 239 -------------------------------------------------------------------------------
237 240 apb_lfr_time_management_1 : apb_lfr_time_management
238 241 GENERIC MAP (
239 242 pindex => 6,
240 243 paddr => 6,
241 244 pmask => 16#fff#,
242 245 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
243 246 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
244 247 PORT MAP (
245 248 clk25MHz => clk_25,
246 249 clk24_576MHz => clk_24, -- 49.152MHz/2
247 250 resetn => rstn,
248 251 grspw_tick => swno.tickout,
249 252 apbi => apbi_ext,
250 253 apbo => apbo_ext(6),
251 254 coarse_time => coarse_time,
252 255 fine_time => fine_time);
253 256
254 257 -----------------------------------------------------------------------
255 258 --- SpaceWire --------------------------------------------------------
256 259 -----------------------------------------------------------------------
257 260
258 261 -- SPW_EN <= '1';
259 262
260 263 spw_clk <= clk_50_s;
261 264 spw_rxtxclk <= spw_clk;
262 265 spw_rxclkn <= NOT spw_rxtxclk;
263 266
264 267 -- PADS for SPW1
265 268 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
266 269 PORT MAP (spw1_din, dtmp(0));
267 270 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
268 271 PORT MAP (spw1_sin, stmp(0));
269 272 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
270 273 PORT MAP (spw1_dout, swno.d(0));
271 274 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
272 275 PORT MAP (spw1_sout, swno.s(0));
273 276 -- PADS FOR SPW2
274 277 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
275 278 PORT MAP (spw2_sin, dtmp(1));
276 279 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
277 280 PORT MAP (spw2_din, stmp(1));
278 281 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
279 282 PORT MAP (spw2_dout, swno.d(1));
280 283 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
281 284 PORT MAP (spw2_sout, swno.s(1));
282 285
283 286 -- GRSPW PHY
284 287 --spw1_input: if CFG_SPW_GRSPW = 1 generate
285 288 spw_inputloop : FOR j IN 0 TO 1 GENERATE
286 289 spw_phy0 : grspw_phy
287 290 GENERIC MAP(
288 291 tech => apa3e,
289 292 rxclkbuftype => 1,
290 293 scantest => 0)
291 294 PORT MAP(
292 295 rxrst => swno.rxrst,
293 296 di => dtmp(j),
294 297 si => stmp(j),
295 298 rxclko => spw_rxclk(j),
296 299 do => swni.d(j),
297 300 ndo => swni.nd(j*5+4 DOWNTO j*5),
298 301 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
299 302 END GENERATE spw_inputloop;
300 303
301 304 -- SPW core
302 305 sw0 : grspwm GENERIC MAP(
303 306 tech => apa3e,
304 307 hindex => 1,
305 308 pindex => 5,
306 309 paddr => 5,
307 310 pirq => 11,
308 311 sysfreq => 25000, -- CPU_FREQ
309 312 rmap => 1,
310 313 rmapcrc => 1,
311 314 fifosize1 => 16,
312 315 fifosize2 => 16,
313 316 rxclkbuftype => 1,
314 317 rxunaligned => 0,
315 318 rmapbufs => 4,
316 319 ft => 0,
317 320 netlist => 0,
318 321 ports => 2,
319 322 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
320 323 memtech => apa3e,
321 324 destkey => 2,
322 325 spwcore => 1
323 326 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
324 327 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
325 328 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
326 329 )
327 330 PORT MAP(rstn, clk_25, spw_rxclk(0),
328 331 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
329 332 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
330 333 swni, swno);
331 334
332 335 swni.tickin <= '0';
333 336 swni.rmapen <= '1';
334 337 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
335 338 swni.tickinraw <= '0';
336 339 swni.timein <= (OTHERS => '0');
337 340 swni.dcrstval <= (OTHERS => '0');
338 341 swni.timerrstval <= (OTHERS => '0');
339 342
340 343 -------------------------------------------------------------------------------
341 344 -- LFR ------------------------------------------------------------------------
342 345 -------------------------------------------------------------------------------
343 346 lpp_lfr_1 : lpp_lfr
344 347 GENERIC MAP (
345 348 Mem_use => use_RAM,
346 349 nb_data_by_buffer_size => 32,
347 350 nb_word_by_buffer_size => 30,
348 351 nb_snapshot_param_size => 32,
349 352 delta_vector_size => 32,
350 353 delta_vector_size_f0_2 => 7, -- log2(96)
351 354 pindex => 15,
352 355 paddr => 15,
353 356 pmask => 16#fff#,
354 357 pirq_ms => 6,
355 358 pirq_wfp => 14,
356 359 hindex => 2,
357 360 top_lfr_version => X"010117") -- aa.bb.cc version
358 361 -- AA : BOARD NUMBER
359 362 -- 0 => MINI_LFR
360 363 -- 1 => EM
361 364 PORT MAP (
362 365 clk => clk_25,
363 366 rstn => rstn,
364 367 sample_B => sample_s(2 DOWNTO 0),
365 368 sample_E => sample_s(7 DOWNTO 3),
366 369 sample_val => sample_val,
367 370 apbi => apbi_ext,
368 371 apbo => apbo_ext(15),
369 372 ahbi => ahbi_m_ext,
370 373 ahbo => ahbo_m_ext(2),
371 374 coarse_time => coarse_time,
372 375 fine_time => fine_time,
373 376 data_shaping_BW => bias_fail_sw,
377 observation_vector_0 => OPEN,
378 observation_vector_1 => OPEN,
374 379 observation_reg => observation_reg);
375 380
376 381
377 382 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
378 383 sample_s(I) <= sample(I) & '0' & '0';
379 384 END GENERATE all_sample;
380 385
381 386 -----------------------------------------------------------------------------
382 387 --
383 388 -----------------------------------------------------------------------------
384 389 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
385 390 GENERIC MAP (
386 391 ChanelCount => 8,
387 392 ncycle_cnv_high => 40, -- TODO : 79
388 393 ncycle_cnv => 250) -- TODO : 500
389 394 PORT MAP (
390 395 cnv_clk => clk_24, -- TODO : 49.152
391 396 cnv_rstn => rstn, -- ok
392 cnv => ADC_smpclk, -- ok
397 cnv => ADC_smpclk_s, -- ok
393 398 clk => clk_25, -- ok
394 399 rstn => rstn, -- ok
395 400 ADC_data => ADC_data, -- ok
396 401 ADC_nOE => ADC_OEB_bar_CH, -- ok
397 402 sample => sample, -- ok
398 403 sample_val => sample_val); -- ok
399
400 TAG8 <= ADC_smpclk;
404
405 ADC_smpclk <= ADC_smpclk_s;
406
407 TAG8 <= ADC_smpclk_s;
401 408
402 409 END beh;
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