@@ -138,6 +138,9 ARCHITECTURE beh OF LFR_em IS | |||
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138 | 138 | |
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139 | 139 | ----------------------------------------------------------------------------- |
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140 | 140 | SIGNAL rstn : STD_LOGIC; |
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141 | ||
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142 | SIGNAL ADC_smpclk_s : STD_LOGIC; | |
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143 | ||
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141 | 144 | BEGIN -- beh |
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142 | 145 | |
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143 | 146 | ----------------------------------------------------------------------------- |
@@ -371,6 +374,8 BEGIN -- beh | |||
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371 | 374 | coarse_time => coarse_time, |
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372 | 375 | fine_time => fine_time, |
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373 | 376 | data_shaping_BW => bias_fail_sw, |
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377 | observation_vector_0 => OPEN, | |
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378 | observation_vector_1 => OPEN, | |
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374 | 379 | observation_reg => observation_reg); |
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375 | 380 | |
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376 | 381 | |
@@ -389,14 +394,16 BEGIN -- beh | |||
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389 | 394 | PORT MAP ( |
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390 | 395 | cnv_clk => clk_24, -- TODO : 49.152 |
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391 | 396 | cnv_rstn => rstn, -- ok |
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392 | cnv => ADC_smpclk, -- ok | |
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397 | cnv => ADC_smpclk_s, -- ok | |
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393 | 398 | clk => clk_25, -- ok |
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394 | 399 | rstn => rstn, -- ok |
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395 | 400 | ADC_data => ADC_data, -- ok |
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396 | 401 | ADC_nOE => ADC_OEB_bar_CH, -- ok |
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397 | 402 | sample => sample, -- ok |
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398 | 403 | sample_val => sample_val); -- ok |
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399 | ||
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400 |
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404 | ||
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405 | ADC_smpclk <= ADC_smpclk_s; | |
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406 | ||
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407 | TAG8 <= ADC_smpclk_s; | |
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401 | 408 | |
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402 | 409 | END beh; |
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