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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Alexis Jeandet |
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19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
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20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
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21 | ---------------------------------------------------------------------------- | |
22 |
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22 | |||
23 | LIBRARY IEEE; |
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23 | LIBRARY IEEE; | |
24 | USE IEEE.STD_LOGIC_1164.ALL; |
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24 | USE IEEE.STD_LOGIC_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | USE grlib.devices.ALL; |
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28 | USE grlib.devices.ALL; | |
29 |
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29 | |||
30 | PACKAGE lpp_ad_conv IS |
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30 | PACKAGE lpp_ad_conv IS | |
31 |
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31 | |||
32 |
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32 | |||
33 | --CONSTANT AD7688 : INTEGER := 0; |
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33 | --CONSTANT AD7688 : INTEGER := 0; | |
34 | --CONSTANT ADS7886 : INTEGER := 1; |
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34 | --CONSTANT ADS7886 : INTEGER := 1; | |
35 |
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35 | |||
36 |
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36 | |||
37 | --TYPE AD7688_out IS |
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37 | --TYPE AD7688_out IS | |
38 | --RECORD |
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38 | --RECORD | |
39 | -- CNV : STD_LOGIC; |
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39 | -- CNV : STD_LOGIC; | |
40 | -- SCK : STD_LOGIC; |
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40 | -- SCK : STD_LOGIC; | |
41 | --END RECORD; |
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41 | --END RECORD; | |
42 |
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42 | |||
43 | --TYPE AD7688_in_element IS |
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43 | --TYPE AD7688_in_element IS | |
44 | --RECORD |
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44 | --RECORD | |
45 | -- SDI : STD_LOGIC; |
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45 | -- SDI : STD_LOGIC; | |
46 | --END RECORD; |
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46 | --END RECORD; | |
47 |
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47 | |||
48 | --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; |
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48 | --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element; | |
49 |
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49 | |||
50 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
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50 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
51 |
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51 | |||
52 | SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0); |
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52 | SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0); | |
53 |
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53 | |||
54 | SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0); |
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54 | SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0); | |
55 |
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55 | |||
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56 | SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0); | |||
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57 | ||||
56 | SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0); |
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58 | SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0); | |
57 |
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59 | |||
58 | SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0); |
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60 | SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0); | |
59 |
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61 | |||
60 | SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0); |
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62 | SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0); | |
61 |
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63 | |||
62 | SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0); |
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64 | SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0); | |
63 |
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65 | |||
64 | TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24; |
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66 | TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24; | |
65 |
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67 | |||
66 | TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16; |
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68 | TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16; | |
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69 | ||||
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70 | TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15; | |||
67 |
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71 | |||
68 | TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14; |
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72 | TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14; | |
69 |
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73 | |||
70 | TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12; |
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74 | TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12; | |
71 |
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75 | |||
72 | TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10; |
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76 | TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10; | |
73 |
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77 | |||
74 | TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8; |
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78 | TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8; | |
75 |
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79 | |||
76 | COMPONENT AD7688_drvr |
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80 | COMPONENT AD7688_drvr | |
77 | GENERIC ( |
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81 | GENERIC ( | |
78 | ChanelCount : INTEGER; |
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82 | ChanelCount : INTEGER; | |
79 | ncycle_cnv_high : INTEGER := 79; |
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83 | ncycle_cnv_high : INTEGER := 79; | |
80 | ncycle_cnv : INTEGER := 500); |
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84 | ncycle_cnv : INTEGER := 500); | |
81 | PORT ( |
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85 | PORT ( | |
82 | cnv_clk : IN STD_LOGIC; |
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86 | cnv_clk : IN STD_LOGIC; | |
83 | cnv_rstn : IN STD_LOGIC; |
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87 | cnv_rstn : IN STD_LOGIC; | |
84 | cnv_run : IN STD_LOGIC; |
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88 | cnv_run : IN STD_LOGIC; | |
85 | cnv : OUT STD_LOGIC; |
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89 | cnv : OUT STD_LOGIC; | |
86 | clk : IN STD_LOGIC; |
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90 | clk : IN STD_LOGIC; | |
87 | rstn : IN STD_LOGIC; |
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91 | rstn : IN STD_LOGIC; | |
88 | sck : OUT STD_LOGIC; |
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92 | sck : OUT STD_LOGIC; | |
89 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
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93 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
90 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); |
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94 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); | |
91 | sample_val : OUT STD_LOGIC); |
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95 | sample_val : OUT STD_LOGIC); | |
92 | END COMPONENT; |
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96 | END COMPONENT; | |
93 |
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97 | |||
94 | COMPONENT RHF1401_drvr IS |
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98 | COMPONENT RHF1401_drvr IS | |
95 | GENERIC( |
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99 | GENERIC( | |
96 | ChanelCount : INTEGER := 8); |
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100 | ChanelCount : INTEGER := 8); | |
97 | PORT ( |
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101 | PORT ( | |
98 | cnv_clk : IN STD_LOGIC; |
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102 | cnv_clk : IN STD_LOGIC; | |
99 | clk : IN STD_LOGIC; |
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103 | clk : IN STD_LOGIC; | |
100 | rstn : IN STD_LOGIC; |
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104 | rstn : IN STD_LOGIC; | |
101 | ADC_data : IN Samples14; |
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105 | ADC_data : IN Samples14; | |
102 | --ADC_smpclk : OUT STD_LOGIC; |
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106 | --ADC_smpclk : OUT STD_LOGIC; | |
103 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
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107 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
104 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
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108 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); | |
105 | sample_val : OUT STD_LOGIC |
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109 | sample_val : OUT STD_LOGIC | |
106 | ); |
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110 | ); | |
107 | END COMPONENT; |
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111 | END COMPONENT; | |
108 |
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112 | |||
109 | COMPONENT top_ad_conv_RHF1401 |
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113 | COMPONENT top_ad_conv_RHF1401 | |
110 | GENERIC ( |
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114 | GENERIC ( | |
111 | ChanelCount : INTEGER; |
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115 | ChanelCount : INTEGER; | |
112 | ncycle_cnv_high : INTEGER := 79; |
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116 | ncycle_cnv_high : INTEGER := 79; | |
113 | ncycle_cnv : INTEGER := 500); |
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117 | ncycle_cnv : INTEGER := 500); | |
114 | PORT ( |
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118 | PORT ( | |
115 | cnv_clk : IN STD_LOGIC; |
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119 | cnv_clk : IN STD_LOGIC; | |
116 | cnv_rstn : IN STD_LOGIC; |
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120 | cnv_rstn : IN STD_LOGIC; | |
117 | cnv : OUT STD_LOGIC; |
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121 | cnv : OUT STD_LOGIC; | |
118 | clk : IN STD_LOGIC; |
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122 | clk : IN STD_LOGIC; | |
119 | rstn : IN STD_LOGIC; |
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123 | rstn : IN STD_LOGIC; | |
120 | ADC_data : IN Samples14; |
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124 | ADC_data : IN Samples14; | |
121 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
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125 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
122 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
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126 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); | |
123 | sample_val : OUT STD_LOGIC); |
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127 | sample_val : OUT STD_LOGIC); | |
124 | END COMPONENT; |
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128 | END COMPONENT; | |
125 |
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129 | |||
126 |
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130 | |||
127 | COMPONENT AD7688_drvr_sync |
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131 | COMPONENT AD7688_drvr_sync | |
128 | GENERIC ( |
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132 | GENERIC ( | |
129 | ChanelCount : INTEGER; |
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133 | ChanelCount : INTEGER; | |
130 | ncycle_cnv_high : INTEGER; |
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134 | ncycle_cnv_high : INTEGER; | |
131 | ncycle_cnv : INTEGER); |
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135 | ncycle_cnv : INTEGER); | |
132 | PORT ( |
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136 | PORT ( | |
133 | cnv_clk : IN STD_LOGIC; |
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137 | cnv_clk : IN STD_LOGIC; | |
134 | cnv_rstn : IN STD_LOGIC; |
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138 | cnv_rstn : IN STD_LOGIC; | |
135 | cnv_run : IN STD_LOGIC; |
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139 | cnv_run : IN STD_LOGIC; | |
136 | cnv : OUT STD_LOGIC; |
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140 | cnv : OUT STD_LOGIC; | |
137 | sck : OUT STD_LOGIC; |
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141 | sck : OUT STD_LOGIC; | |
138 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
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142 | sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
139 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); |
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143 | sample : OUT Samples(ChanelCount-1 DOWNTO 0); | |
140 | sample_val : OUT STD_LOGIC); |
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144 | sample_val : OUT STD_LOGIC); | |
141 | END COMPONENT; |
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145 | END COMPONENT; | |
142 |
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146 | |||
143 | COMPONENT TestModule_RHF1401 |
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147 | COMPONENT TestModule_RHF1401 | |
144 | GENERIC ( |
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148 | GENERIC ( | |
145 | freq : INTEGER; |
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149 | freq : INTEGER; | |
146 | amplitude : INTEGER; |
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150 | amplitude : INTEGER; | |
147 | impulsion : INTEGER); |
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151 | impulsion : INTEGER); | |
148 | PORT ( |
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152 | PORT ( | |
149 | ADC_smpclk : IN STD_LOGIC; |
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153 | ADC_smpclk : IN STD_LOGIC; | |
150 | ADC_OEB_bar : IN STD_LOGIC; |
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154 | ADC_OEB_bar : IN STD_LOGIC; | |
151 | ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)); |
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155 | ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)); | |
152 | END COMPONENT; |
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156 | END COMPONENT; | |
153 |
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157 | |||
154 | --COMPONENT AD7688_drvr IS |
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158 | --COMPONENT AD7688_drvr IS | |
155 | -- GENERIC(ChanelCount : INTEGER; |
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159 | -- GENERIC(ChanelCount : INTEGER; | |
156 | -- clkkHz : INTEGER); |
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160 | -- clkkHz : INTEGER); | |
157 | -- PORT (clk : IN STD_LOGIC; |
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161 | -- PORT (clk : IN STD_LOGIC; | |
158 | -- rstn : IN STD_LOGIC; |
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162 | -- rstn : IN STD_LOGIC; | |
159 | -- enable : IN STD_LOGIC; |
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163 | -- enable : IN STD_LOGIC; | |
160 | -- smplClk : IN STD_LOGIC; |
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164 | -- smplClk : IN STD_LOGIC; | |
161 | -- DataReady : OUT STD_LOGIC; |
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165 | -- DataReady : OUT STD_LOGIC; | |
162 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); |
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166 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); | |
163 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); |
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167 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
164 | -- AD_out : OUT AD7688_out); |
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168 | -- AD_out : OUT AD7688_out); | |
165 | --END COMPONENT; |
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169 | --END COMPONENT; | |
166 |
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170 | |||
167 |
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171 | |||
168 | --COMPONENT AD7688_spi_if IS |
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172 | --COMPONENT AD7688_spi_if IS | |
169 | -- GENERIC(ChanelCount : INTEGER); |
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173 | -- GENERIC(ChanelCount : INTEGER); | |
170 | -- PORT(clk : IN STD_LOGIC; |
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174 | -- PORT(clk : IN STD_LOGIC; | |
171 | -- reset : IN STD_LOGIC; |
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175 | -- reset : IN STD_LOGIC; | |
172 | -- cnv : IN STD_LOGIC; |
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176 | -- cnv : IN STD_LOGIC; | |
173 | -- DataReady : OUT STD_LOGIC; |
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177 | -- DataReady : OUT STD_LOGIC; | |
174 | -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); |
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178 | -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
175 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0) |
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179 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0) | |
176 | -- ); |
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180 | -- ); | |
177 | --END COMPONENT; |
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181 | --END COMPONENT; | |
178 |
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182 | |||
179 |
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183 | |||
180 | --COMPONENT lpp_apb_ad_conv |
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184 | --COMPONENT lpp_apb_ad_conv | |
181 | -- GENERIC( |
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185 | -- GENERIC( | |
182 | -- pindex : INTEGER := 0; |
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186 | -- pindex : INTEGER := 0; | |
183 | -- paddr : INTEGER := 0; |
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187 | -- paddr : INTEGER := 0; | |
184 | -- pmask : INTEGER := 16#fff#; |
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188 | -- pmask : INTEGER := 16#fff#; | |
185 | -- pirq : INTEGER := 0; |
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189 | -- pirq : INTEGER := 0; | |
186 | -- abits : INTEGER := 8; |
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190 | -- abits : INTEGER := 8; | |
187 | -- ChanelCount : INTEGER := 1; |
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191 | -- ChanelCount : INTEGER := 1; | |
188 | -- clkkHz : INTEGER := 50000; |
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192 | -- clkkHz : INTEGER := 50000; | |
189 | -- smpClkHz : INTEGER := 100; |
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193 | -- smpClkHz : INTEGER := 100; | |
190 | -- ADCref : INTEGER := AD7688); |
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194 | -- ADCref : INTEGER := AD7688); | |
191 | -- PORT ( |
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195 | -- PORT ( | |
192 | -- clk : IN STD_LOGIC; |
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196 | -- clk : IN STD_LOGIC; | |
193 | -- reset : IN STD_LOGIC; |
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197 | -- reset : IN STD_LOGIC; | |
194 | -- apbi : IN apb_slv_in_type; |
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198 | -- apbi : IN apb_slv_in_type; | |
195 | -- apbo : OUT apb_slv_out_type; |
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199 | -- apbo : OUT apb_slv_out_type; | |
196 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); |
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200 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
197 | -- AD_out : OUT AD7688_out); |
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201 | -- AD_out : OUT AD7688_out); | |
198 | --END COMPONENT; |
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202 | --END COMPONENT; | |
199 |
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203 | |||
200 | --COMPONENT ADS7886_drvr IS |
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204 | --COMPONENT ADS7886_drvr IS | |
201 | -- GENERIC(ChanelCount : INTEGER; |
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205 | -- GENERIC(ChanelCount : INTEGER; | |
202 | -- clkkHz : INTEGER); |
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206 | -- clkkHz : INTEGER); | |
203 | -- PORT ( |
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207 | -- PORT ( | |
204 | -- clk : IN STD_LOGIC; |
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208 | -- clk : IN STD_LOGIC; | |
205 | -- reset : IN STD_LOGIC; |
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209 | -- reset : IN STD_LOGIC; | |
206 | -- smplClk : IN STD_LOGIC; |
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210 | -- smplClk : IN STD_LOGIC; | |
207 | -- DataReady : OUT STD_LOGIC; |
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211 | -- DataReady : OUT STD_LOGIC; | |
208 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); |
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212 | -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0); | |
209 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); |
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213 | -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0); | |
210 | -- AD_out : OUT AD7688_out |
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214 | -- AD_out : OUT AD7688_out | |
211 | -- ); |
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215 | -- ); | |
212 | --END COMPONENT; |
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216 | --END COMPONENT; | |
213 |
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217 | |||
214 | --COMPONENT WriteGen_ADC IS |
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218 | --COMPONENT WriteGen_ADC IS | |
215 | -- PORT( |
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219 | -- PORT( | |
216 | -- clk : IN STD_LOGIC; |
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220 | -- clk : IN STD_LOGIC; | |
217 | -- rstn : IN STD_LOGIC; |
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221 | -- rstn : IN STD_LOGIC; | |
218 | -- SmplCLK : IN STD_LOGIC; |
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222 | -- SmplCLK : IN STD_LOGIC; | |
219 | -- DataReady : IN STD_LOGIC; |
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223 | -- DataReady : IN STD_LOGIC; | |
220 | -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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224 | -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
221 | -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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225 | -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
222 | -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) |
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226 | -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) | |
223 | -- ); |
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227 | -- ); | |
224 | --END COMPONENT; |
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228 | --END COMPONENT; | |
225 |
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229 | |||
226 |
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230 | |||
227 | --===========================================================| |
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231 | --===========================================================| | |
228 | --======================= ADS 127X =========================| |
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232 | --======================= ADS 127X =========================| | |
229 | --===========================================================| |
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233 | --===========================================================| | |
230 |
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234 | |||
231 | TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC; |
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235 | TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC; | |
232 | CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010"; |
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236 | CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010"; | |
233 | CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101"; |
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237 | CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101"; | |
234 |
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238 | |||
235 | TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC; |
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239 | TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC; | |
236 | CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10"; |
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240 | CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10"; | |
237 | CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11"; |
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241 | CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11"; | |
238 | CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01"; |
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242 | CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01"; | |
239 |
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243 | |||
240 | TYPE ADS127X_config IS |
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244 | TYPE ADS127X_config IS | |
241 | RECORD |
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245 | RECORD | |
242 | SYNC : STD_LOGIC; |
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246 | SYNC : STD_LOGIC; | |
243 | CLKDIV : STD_LOGIC; |
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247 | CLKDIV : STD_LOGIC; | |
244 | FORMAT : ADS127X_FORMAT_Type; |
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248 | FORMAT : ADS127X_FORMAT_Type; | |
245 | MODE : ADS127X_MODE_Type; |
|
249 | MODE : ADS127X_MODE_Type; | |
246 | END RECORD; |
|
250 | END RECORD; | |
247 |
|
251 | |||
248 | COMPONENT ADS1274_DRIVER IS |
|
252 | COMPONENT ADS1274_DRIVER IS | |
249 | GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); |
|
253 | GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT); | |
250 | PORT( |
|
254 | PORT( | |
251 | Clk : IN STD_LOGIC; |
|
255 | Clk : IN STD_LOGIC; | |
252 | reset : IN STD_LOGIC; |
|
256 | reset : IN STD_LOGIC; | |
253 | SpiClk : OUT STD_LOGIC; |
|
257 | SpiClk : OUT STD_LOGIC; | |
254 | DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
258 | DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
255 | Ready : IN STD_LOGIC; |
|
259 | Ready : IN STD_LOGIC; | |
256 | Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
260 | Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
257 | Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
261 | Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
258 | ClkDiv : OUT STD_LOGIC; |
|
262 | ClkDiv : OUT STD_LOGIC; | |
259 | PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
263 | PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
260 | SmplClk : IN STD_LOGIC; |
|
264 | SmplClk : IN STD_LOGIC; | |
261 | OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
265 | OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
262 | OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
266 | OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
263 | OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
267 | OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
264 | OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
268 | OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
265 | FSynch : OUT STD_LOGIC; |
|
269 | FSynch : OUT STD_LOGIC; | |
266 | test : OUT STD_LOGIC |
|
270 | test : OUT STD_LOGIC | |
267 | ); |
|
271 | ); | |
268 | END COMPONENT; |
|
272 | END COMPONENT; | |
269 |
|
273 | |||
270 | -- todo clean file |
|
274 | -- todo clean file | |
271 | COMPONENT DUAL_ADS1278_DRIVER IS |
|
275 | COMPONENT DUAL_ADS1278_DRIVER IS | |
272 | PORT( |
|
276 | PORT( | |
273 | Clk : IN STD_LOGIC; |
|
277 | Clk : IN STD_LOGIC; | |
274 | reset : IN STD_LOGIC; |
|
278 | reset : IN STD_LOGIC; | |
275 | SpiClk : OUT STD_LOGIC; |
|
279 | SpiClk : OUT STD_LOGIC; | |
276 | DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
280 | DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
277 | SmplClk : IN STD_LOGIC; |
|
281 | SmplClk : IN STD_LOGIC; | |
278 | OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
282 | OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
279 | OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
283 | OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
280 | OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
284 | OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
281 | OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
285 | OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
282 | OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
286 | OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
283 | OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
287 | OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
284 | OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
288 | OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
285 | OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
289 | OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
286 | OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
290 | OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
287 | OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
291 | OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
288 | OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
292 | OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
289 | OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
293 | OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
290 | OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
294 | OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
291 | OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
295 | OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
292 | OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
296 | OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
293 | OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
297 | OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); | |
294 | FSynch : OUT STD_LOGIC |
|
298 | FSynch : OUT STD_LOGIC | |
295 | ); |
|
299 | ); | |
296 | END COMPONENT; |
|
300 | END COMPONENT; | |
297 |
|
301 | |||
298 | --===========================================================| |
|
302 | --===========================================================| | |
299 | -- DRIVER ADS7886 |
|
303 | -- DRIVER ADS7886 | |
300 | --===========================================================| |
|
304 | --===========================================================| | |
301 | COMPONENT top_ad_conv_ADS7886_v2 IS |
|
305 | COMPONENT top_ad_conv_ADS7886_v2 IS | |
302 | GENERIC( |
|
306 | GENERIC( | |
303 | ChannelCount : INTEGER := 8; |
|
307 | ChannelCount : INTEGER := 8; | |
304 | SampleNbBits : INTEGER := 14; |
|
308 | SampleNbBits : INTEGER := 14; | |
305 | ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles |
|
309 | ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles | |
306 | ncycle_cnv : INTEGER := 500); |
|
310 | ncycle_cnv : INTEGER := 500); | |
307 | PORT ( |
|
311 | PORT ( | |
308 | -- CONV |
|
312 | -- CONV | |
309 | cnv_clk : IN STD_LOGIC; |
|
313 | cnv_clk : IN STD_LOGIC; | |
310 | cnv_rstn : IN STD_LOGIC; |
|
314 | cnv_rstn : IN STD_LOGIC; | |
311 | cnv : OUT STD_LOGIC; |
|
315 | cnv : OUT STD_LOGIC; | |
312 | -- DATA |
|
316 | -- DATA | |
313 | clk : IN STD_LOGIC; |
|
317 | clk : IN STD_LOGIC; | |
314 | rstn : IN STD_LOGIC; |
|
318 | rstn : IN STD_LOGIC; | |
315 | sck : OUT STD_LOGIC; |
|
319 | sck : OUT STD_LOGIC; | |
316 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); |
|
320 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); | |
317 | -- SAMPLE |
|
321 | -- SAMPLE | |
318 | sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); |
|
322 | sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); | |
319 | sample_val : OUT STD_LOGIC |
|
323 | sample_val : OUT STD_LOGIC | |
320 | ); |
|
324 | ); | |
321 | END COMPONENT; |
|
325 | END COMPONENT; | |
322 |
|
326 | |||
323 | COMPONENT ADS7886_drvr_v2 IS |
|
327 | COMPONENT ADS7886_drvr_v2 IS | |
324 | GENERIC( |
|
328 | GENERIC( | |
325 | ChannelCount : INTEGER := 8; |
|
329 | ChannelCount : INTEGER := 8; | |
326 | NbBitsSamples : INTEGER := 16); |
|
330 | NbBitsSamples : INTEGER := 16); | |
327 | PORT ( |
|
331 | PORT ( | |
328 | -- CONV -- |
|
332 | -- CONV -- | |
329 | cnv_clk : IN STD_LOGIC; |
|
333 | cnv_clk : IN STD_LOGIC; | |
330 | cnv_rstn : IN STD_LOGIC; |
|
334 | cnv_rstn : IN STD_LOGIC; | |
331 | -- DATA -- |
|
335 | -- DATA -- | |
332 | clk : IN STD_LOGIC; |
|
336 | clk : IN STD_LOGIC; | |
333 | rstn : IN STD_LOGIC; |
|
337 | rstn : IN STD_LOGIC; | |
334 | sck : OUT STD_LOGIC; |
|
338 | sck : OUT STD_LOGIC; | |
335 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); |
|
339 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); | |
336 | -- SAMPLE -- |
|
340 | -- SAMPLE -- | |
337 | sample : OUT Samples(ChannelCount-1 DOWNTO 0); |
|
341 | sample : OUT Samples(ChannelCount-1 DOWNTO 0); | |
338 | sample_val : OUT STD_LOGIC |
|
342 | sample_val : OUT STD_LOGIC | |
339 | ); |
|
343 | ); | |
340 | END COMPONENT; |
|
344 | END COMPONENT; | |
341 |
|
345 | |||
342 | COMPONENT top_ad_conv_RHF1401_withFilter |
|
346 | COMPONENT top_ad_conv_RHF1401_withFilter | |
343 | GENERIC ( |
|
347 | GENERIC ( | |
344 | ChanelCount : INTEGER; |
|
348 | ChanelCount : INTEGER; | |
345 | ncycle_cnv_high : INTEGER; |
|
349 | ncycle_cnv_high : INTEGER; | |
346 | ncycle_cnv : INTEGER); |
|
350 | ncycle_cnv : INTEGER); | |
347 | PORT ( |
|
351 | PORT ( | |
348 | cnv_clk : IN STD_LOGIC; |
|
352 | cnv_clk : IN STD_LOGIC; | |
349 | cnv_rstn : IN STD_LOGIC; |
|
353 | cnv_rstn : IN STD_LOGIC; | |
350 | cnv : OUT STD_LOGIC; |
|
354 | cnv : OUT STD_LOGIC; | |
351 | clk : IN STD_LOGIC; |
|
355 | clk : IN STD_LOGIC; | |
352 | rstn : IN STD_LOGIC; |
|
356 | rstn : IN STD_LOGIC; | |
353 | ADC_data : IN Samples14; |
|
357 | ADC_data : IN Samples14; | |
354 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
358 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
355 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
|
359 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); | |
356 | sample_val : OUT STD_LOGIC); |
|
360 | sample_val : OUT STD_LOGIC); | |
357 | END COMPONENT; |
|
361 | END COMPONENT; | |
358 |
|
362 | |||
359 |
|
363 | |||
360 | END lpp_ad_conv; |
|
364 | END lpp_ad_conv; | |
361 |
|
365 | |||
362 |
|
366 | |||
363 |
|
367 | |||
364 |
|
368 | |||
365 |
|
369 | |||
366 |
|
370 | |||
367 |
|
371 | |||
368 |
|
372 |
@@ -1,221 +1,221 | |||||
1 |
|
1 | |||
2 | LIBRARY IEEE; |
|
2 | LIBRARY IEEE; | |
3 | USE IEEE.STD_LOGIC_1164.ALL; |
|
3 | USE IEEE.STD_LOGIC_1164.ALL; | |
4 | USE IEEE.numeric_std.ALL; |
|
4 | USE IEEE.numeric_std.ALL; | |
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.general_purpose.SYNC_FF; |
|
7 | USE lpp.general_purpose.SYNC_FF; | |
8 |
|
8 | |||
9 | ENTITY top_ad_conv_RHF1401_withFilter IS |
|
9 | ENTITY top_ad_conv_RHF1401_withFilter IS | |
10 | GENERIC( |
|
10 | GENERIC( | |
11 | ChanelCount : INTEGER := 8; |
|
11 | ChanelCount : INTEGER := 8; | |
12 | ncycle_cnv_high : INTEGER := 13; |
|
12 | ncycle_cnv_high : INTEGER := 13; | |
13 | ncycle_cnv : INTEGER := 25); |
|
13 | ncycle_cnv : INTEGER := 25); | |
14 | PORT ( |
|
14 | PORT ( | |
15 | cnv_clk : IN STD_LOGIC; -- 24Mhz |
|
15 | cnv_clk : IN STD_LOGIC; -- 24Mhz | |
16 | cnv_rstn : IN STD_LOGIC; |
|
16 | cnv_rstn : IN STD_LOGIC; | |
17 |
|
17 | |||
18 | cnv : OUT STD_LOGIC; |
|
18 | cnv : OUT STD_LOGIC; | |
19 |
|
19 | |||
20 | clk : IN STD_LOGIC; -- 25MHz |
|
20 | clk : IN STD_LOGIC; -- 25MHz | |
21 | rstn : IN STD_LOGIC; |
|
21 | rstn : IN STD_LOGIC; | |
22 | ADC_data : IN Samples14; |
|
22 | ADC_data : IN Samples14; | |
23 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
23 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
24 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
|
24 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); | |
25 | sample_val : OUT STD_LOGIC |
|
25 | sample_val : OUT STD_LOGIC | |
26 | ); |
|
26 | ); | |
27 | END top_ad_conv_RHF1401_withFilter; |
|
27 | END top_ad_conv_RHF1401_withFilter; | |
28 |
|
28 | |||
29 | ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS |
|
29 | ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS | |
30 |
|
30 | |||
31 | SIGNAL cnv_cycle_counter : INTEGER; |
|
31 | SIGNAL cnv_cycle_counter : INTEGER; | |
32 | SIGNAL cnv_s : STD_LOGIC; |
|
32 | SIGNAL cnv_s : STD_LOGIC; | |
33 | SIGNAL cnv_sync : STD_LOGIC; |
|
33 | SIGNAL cnv_sync : STD_LOGIC; | |
34 | SIGNAL cnv_sync_pre : STD_LOGIC; |
|
34 | SIGNAL cnv_sync_pre : STD_LOGIC; | |
35 |
|
35 | |||
36 | SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
36 | SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
37 | SIGNAL enable_ADC : STD_LOGIC; |
|
37 | SIGNAL enable_ADC : STD_LOGIC; | |
38 |
|
38 | |||
39 |
|
39 | |||
40 | SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); |
|
40 | SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); | |
41 |
|
41 | |||
42 | SIGNAL channel_counter : INTEGER; |
|
42 | SIGNAL channel_counter : INTEGER; | |
43 | CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; |
|
43 | CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; | |
44 |
|
44 | |||
45 | SIGNAL ADC_data_selected : Samples14; |
|
45 | SIGNAL ADC_data_selected : Samples14; | |
46 |
SIGNAL ADC_data_result : Samples1 |
|
46 | SIGNAL ADC_data_result : Samples15; | |
47 |
|
47 | |||
48 | SIGNAL sample_counter : INTEGER; |
|
48 | SIGNAL sample_counter : INTEGER; | |
49 |
|
49 | |||
50 | BEGIN |
|
50 | BEGIN | |
51 |
|
51 | |||
52 |
|
52 | |||
53 | ----------------------------------------------------------------------------- |
|
53 | ----------------------------------------------------------------------------- | |
54 | -- CNV GEN |
|
54 | -- CNV GEN | |
55 | ----------------------------------------------------------------------------- |
|
55 | ----------------------------------------------------------------------------- | |
56 | PROCESS (cnv_clk, cnv_rstn) |
|
56 | PROCESS (cnv_clk, cnv_rstn) | |
57 | BEGIN -- PROCESS |
|
57 | BEGIN -- PROCESS | |
58 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
58 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |
59 | cnv_cycle_counter <= 0; |
|
59 | cnv_cycle_counter <= 0; | |
60 | cnv_s <= '0'; |
|
60 | cnv_s <= '0'; | |
61 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
61 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |
62 | IF cnv_cycle_counter < ncycle_cnv-1 THEN |
|
62 | IF cnv_cycle_counter < ncycle_cnv-1 THEN | |
63 | cnv_cycle_counter <= cnv_cycle_counter + 1; |
|
63 | cnv_cycle_counter <= cnv_cycle_counter + 1; | |
64 | IF cnv_cycle_counter < ncycle_cnv_high THEN |
|
64 | IF cnv_cycle_counter < ncycle_cnv_high THEN | |
65 | cnv_s <= '1'; |
|
65 | cnv_s <= '1'; | |
66 | ELSE |
|
66 | ELSE | |
67 | cnv_s <= '0'; |
|
67 | cnv_s <= '0'; | |
68 | END IF; |
|
68 | END IF; | |
69 | ELSE |
|
69 | ELSE | |
70 | cnv_s <= '1'; |
|
70 | cnv_s <= '1'; | |
71 | cnv_cycle_counter <= 0; |
|
71 | cnv_cycle_counter <= 0; | |
72 | END IF; |
|
72 | END IF; | |
73 | END IF; |
|
73 | END IF; | |
74 | END PROCESS; |
|
74 | END PROCESS; | |
75 |
|
75 | |||
76 | cnv <= cnv_s; |
|
76 | cnv <= cnv_s; | |
77 |
|
77 | |||
78 |
|
78 | |||
79 | ----------------------------------------------------------------------------- |
|
79 | ----------------------------------------------------------------------------- | |
80 | -- SYNC CNV |
|
80 | -- SYNC CNV | |
81 | ----------------------------------------------------------------------------- |
|
81 | ----------------------------------------------------------------------------- | |
82 |
|
82 | |||
83 | SYNC_FF_cnv : SYNC_FF |
|
83 | SYNC_FF_cnv : SYNC_FF | |
84 | GENERIC MAP ( |
|
84 | GENERIC MAP ( | |
85 | NB_FF_OF_SYNC => 2) |
|
85 | NB_FF_OF_SYNC => 2) | |
86 | PORT MAP ( |
|
86 | PORT MAP ( | |
87 | clk => clk, |
|
87 | clk => clk, | |
88 | rstn => rstn, |
|
88 | rstn => rstn, | |
89 | A => cnv_s, |
|
89 | A => cnv_s, | |
90 | A_sync => cnv_sync); |
|
90 | A_sync => cnv_sync); | |
91 |
|
91 | |||
92 |
|
92 | |||
93 | ----------------------------------------------------------------------------- |
|
93 | ----------------------------------------------------------------------------- | |
94 | -- DATA GEN Output Enable |
|
94 | -- DATA GEN Output Enable | |
95 | ----------------------------------------------------------------------------- |
|
95 | ----------------------------------------------------------------------------- | |
96 | PROCESS (clk, rstn) |
|
96 | PROCESS (clk, rstn) | |
97 | BEGIN -- PROCESS |
|
97 | BEGIN -- PROCESS | |
98 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
98 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
99 | ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1'); |
|
99 | ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1'); | |
100 | cnv_sync_pre <= '0'; |
|
100 | cnv_sync_pre <= '0'; | |
101 | enable_ADC <= '0'; |
|
101 | enable_ADC <= '0'; | |
102 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
102 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
103 | cnv_sync_pre <= cnv_sync; |
|
103 | cnv_sync_pre <= cnv_sync; | |
104 | IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN |
|
104 | IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN | |
105 | enable_ADC <= '1'; |
|
105 | enable_ADC <= '1'; | |
106 | ADC_nOE_reg(0) <= '0'; |
|
106 | ADC_nOE_reg(0) <= '0'; | |
107 | ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1'); |
|
107 | ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1'); | |
108 | ELSE |
|
108 | ELSE | |
109 | enable_ADC <= NOT enable_ADC; |
|
109 | enable_ADC <= NOT enable_ADC; | |
110 | IF enable_ADC = '0' THEN |
|
110 | IF enable_ADC = '0' THEN | |
111 | ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1'; |
|
111 | ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1'; | |
112 | END IF; |
|
112 | END IF; | |
113 | END IF; |
|
113 | END IF; | |
114 |
|
114 | |||
115 | END IF; |
|
115 | END IF; | |
116 | END PROCESS; |
|
116 | END PROCESS; | |
117 |
|
117 | |||
118 | ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg; |
|
118 | ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg; | |
119 |
|
119 | |||
120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
121 | -- ADC READ DATA |
|
121 | -- ADC READ DATA | |
122 | ----------------------------------------------------------------------------- |
|
122 | ----------------------------------------------------------------------------- | |
123 | PROCESS (clk, rstn) |
|
123 | PROCESS (clk, rstn) | |
124 | BEGIN -- PROCESS |
|
124 | BEGIN -- PROCESS | |
125 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
125 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
126 | channel_counter <= MAX_COUNTER; |
|
126 | channel_counter <= MAX_COUNTER; | |
127 | sample_reg(0) <= (OTHERS => '0'); |
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127 | sample_reg(0) <= (OTHERS => '0'); | |
128 | sample_reg(1) <= (OTHERS => '0'); |
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128 | sample_reg(1) <= (OTHERS => '0'); | |
129 | sample_reg(2) <= (OTHERS => '0'); |
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129 | sample_reg(2) <= (OTHERS => '0'); | |
130 | sample_reg(3) <= (OTHERS => '0'); |
|
130 | sample_reg(3) <= (OTHERS => '0'); | |
131 | sample_reg(4) <= (OTHERS => '0'); |
|
131 | sample_reg(4) <= (OTHERS => '0'); | |
132 | sample_reg(5) <= (OTHERS => '0'); |
|
132 | sample_reg(5) <= (OTHERS => '0'); | |
133 | sample_reg(6) <= (OTHERS => '0'); |
|
133 | sample_reg(6) <= (OTHERS => '0'); | |
134 | sample_reg(7) <= (OTHERS => '0'); |
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134 | sample_reg(7) <= (OTHERS => '0'); | |
135 |
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135 | |||
136 | sample_val <= '0'; |
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136 | sample_val <= '0'; | |
137 | sample_counter <= 0; |
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137 | sample_counter <= 0; | |
138 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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138 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
139 | IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN |
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139 | IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN | |
140 | channel_counter <= 0; |
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140 | channel_counter <= 0; | |
141 | ELSE |
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141 | ELSE | |
142 | IF channel_counter < MAX_COUNTER THEN |
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142 | IF channel_counter < MAX_COUNTER THEN | |
143 | channel_counter <= channel_counter + 1; |
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143 | channel_counter <= channel_counter + 1; | |
144 | END IF; |
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144 | END IF; | |
145 | END IF; |
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145 | END IF; | |
146 | sample_val <= '0'; |
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146 | sample_val <= '0'; | |
147 |
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147 | |||
148 | CASE channel_counter IS |
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148 | CASE channel_counter IS | |
149 | WHEN 0*2 => sample_reg(0) <= ADC_data_result; |
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149 | WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1); | |
150 | WHEN 1*2 => sample_reg(1) <= ADC_data_result; |
|
150 | WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1); | |
151 | WHEN 2*2 => sample_reg(2) <= ADC_data_result; |
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151 | WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1); | |
152 | WHEN 3*2 => sample_reg(3) <= ADC_data_result; |
|
152 | WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1); | |
153 | WHEN 4*2 => sample_reg(4) <= ADC_data_result; |
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153 | WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1); | |
154 | WHEN 5*2 => sample_reg(5) <= ADC_data_result; |
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154 | WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1); | |
155 | WHEN 6*2 => sample_reg(6) <= ADC_data_result; |
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155 | WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1); | |
156 | WHEN 7*2 => sample_reg(7) <= ADC_data_result; |
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156 | WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1); | |
157 | IF sample_counter = 9 THEN |
|
157 | IF sample_counter = 9 THEN | |
158 | sample_counter <= 0 ; |
|
158 | sample_counter <= 0 ; | |
159 | sample_val <= '1'; |
|
159 | sample_val <= '1'; | |
160 | ELSE |
|
160 | ELSE | |
161 | sample_counter <= sample_counter +1; |
|
161 | sample_counter <= sample_counter +1; | |
162 | END IF; |
|
162 | END IF; | |
163 |
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163 | |||
164 | WHEN OTHERS => NULL; |
|
164 | WHEN OTHERS => NULL; | |
165 | END CASE; |
|
165 | END CASE; | |
166 |
|
166 | |||
167 | END IF; |
|
167 | END IF; | |
168 | END PROCESS; |
|
168 | END PROCESS; | |
169 |
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169 | |||
170 |
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170 | |||
171 | WITH channel_counter SELECT |
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171 | WITH channel_counter SELECT | |
172 | ADC_data_selected <= sample_reg(0) WHEN 0*2, |
|
172 | ADC_data_selected <= sample_reg(0) WHEN 0*2, | |
173 | sample_reg(1) WHEN 1*2, |
|
173 | sample_reg(1) WHEN 1*2, | |
174 | sample_reg(2) WHEN 2*2, |
|
174 | sample_reg(2) WHEN 2*2, | |
175 | sample_reg(3) WHEN 3*2, |
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175 | sample_reg(3) WHEN 3*2, | |
176 | sample_reg(4) WHEN 4*2, |
|
176 | sample_reg(4) WHEN 4*2, | |
177 | sample_reg(5) WHEN 5*2, |
|
177 | sample_reg(5) WHEN 5*2, | |
178 | sample_reg(6) WHEN 6*2, |
|
178 | sample_reg(6) WHEN 6*2, | |
179 | sample_reg(7) WHEN OTHERS ; |
|
179 | sample_reg(7) WHEN OTHERS ; | |
180 |
|
180 | |||
181 |
|
181 | |||
182 |
ADC_data_result <= std_logic_vector( (signed(ADC_data_selected) + signed(ADC_data)) |
|
182 | ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) ); | |
183 |
|
183 | |||
184 | sample <= sample_reg; |
|
184 | sample <= sample_reg; | |
185 |
|
185 | |||
186 |
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186 | |||
187 |
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187 | |||
188 |
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188 | |||
189 | --RHF1401_drvr_1: RHF1401_drvr |
|
189 | --RHF1401_drvr_1: RHF1401_drvr | |
190 | -- GENERIC MAP ( |
|
190 | -- GENERIC MAP ( | |
191 | -- ChanelCount => ChanelCount) |
|
191 | -- ChanelCount => ChanelCount) | |
192 | -- PORT MAP ( |
|
192 | -- PORT MAP ( | |
193 | -- cnv_clk => cnv_sync, |
|
193 | -- cnv_clk => cnv_sync, | |
194 | -- clk => clk, |
|
194 | -- clk => clk, | |
195 | -- rstn => rstn, |
|
195 | -- rstn => rstn, | |
196 | -- ADC_data => ADC_data, |
|
196 | -- ADC_data => ADC_data, | |
197 | -- --ADC_smpclk => OPEN, |
|
197 | -- --ADC_smpclk => OPEN, | |
198 | -- ADC_nOE => ADC_nOE, |
|
198 | -- ADC_nOE => ADC_nOE, | |
199 | -- sample => sample, |
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199 | -- sample => sample, | |
200 | -- sample_val => sample_val); |
|
200 | -- sample_val => sample_val); | |
201 |
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201 | |||
202 |
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202 | |||
203 |
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203 | |||
204 |
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204 | |||
205 | END ar_top_ad_conv_RHF1401; |
|
205 | END ar_top_ad_conv_RHF1401; | |
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