##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

add filter (f2,f3)
pellion -
r520:4ecb2a443559 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,442
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
69 PORT (
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 PORT (
88 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 PORT (
110 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
127
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
152 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
165 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
184 SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
186 BEGIN
187
188 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
191 all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
201 END IF;
202 END IF;
203 END PROCESS;
204 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
206 all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
207 all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
208 sample_out_zero(I,J) <= '0';
209 END GENERATE all_bit;
210 END GENERATE all_channel_sample_out;
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 state_channel_selection <= IDLE;
216 CHANNEL_SEL <= '0';
217 sample_in_val <= '0';
218 sample_out1_val <= '0';
219 sample_out2_val <= '0';
220 sample_out1 <= sample_out_zero;
221 sample_out2 <= sample_out_zero;
222 channel_done <= "00";
223
224 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
226 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
229 sample_out1_val <= '0';
230 sample_out2_val <= '0';
231 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
240 END IF;
241 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
247 channel_done(0) <= '1';
248 END IF;
249 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
255 channel_done(1) <= '1';
256 END IF;
257 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
261 sample_out1_val <= '0';
262 sample_out2_val <= '0';
263 channel_done <= "00";
264
265 WHEN OTHERS => NULL;
266 END CASE;
267
268 END IF;
269 END PROCESS;
270
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
275
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
288 RAM_CTRLR_v2_1: RAM_CTRLR_v2
289 GENERIC MAP (
290 tech => tech,
291 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
293 PORT MAP (
294 clk => clk,
295 rstn => rstn,
296 ram_write => ram_write_1,
297 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
302 sample_out => ram_output_1);
303
304 RAM_CTRLR_v2_2: RAM_CTRLR_v2
305 GENERIC MAP (
306 tech => tech,
307 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
309 PORT MAP (
310 clk => clk,
311 rstn => rstn,
312 ram_write => ram_write_2,
313 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
318 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
320
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
328 rstn => rstn,
329 clk => clk,
330 virg_pos => virg_pos,
331 coefs => coefs,
332 --CTRL
333 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
335 --
336 ram_input => ram_input,
337 ram_output => ram_output,
338 --
339 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
343 --DATA
344 sample_in => sample_in_s,
345 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
347
348
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
354 PORT MAP (
355 rstn => rstn,
356 clk => clk,
357 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
361
362 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
365 ram_read => ram_read,
366 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
372
373 -----------------------------------------------------------------------------
374 -- SAMPLE IN
375 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
389 END IF;
390 END PROCESS;
391 END GENERATE loop_all_chanel;
392
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
395 END GENERATE loop_all_sample;
396
397 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
409 END PROCESS;
410
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
420 END IF;
421 END PROCESS;
422 END GENERATE chanel_HIGH;
423
424 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
435 END IF;
436 END PROCESS;
437 END GENERATE all_bit;
438 END GENERATE all_chanel;
439 END GENERATE chanel_more;
440
441 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
Show file before | Show file after | Hide comments
@@ -0,0 +1,213
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
27 USE lpp.general_purpose.ALL;
28
29
30
31 ENTITY IIR_CEL_CTRLR_v3_DATAFLOW IS
32 GENERIC(
33 Sample_SZ : INTEGER := 16;
34 Coef_SZ : INTEGER := 9;
35 Coef_Nb : INTEGER := 30;
36 Coef_sel_SZ : INTEGER := 5
37 );
38 PORT(
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- PARAMETER
42 virg_pos : IN INTEGER;
43 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
44 -- CONTROL
45 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
46 --
47 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 --
49 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
50 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
51
52 --
53 alu_sel_input : IN STD_LOGIC;
54 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
55 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
56 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
57 -- DATA
58 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
59 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
60 );
61 END IIR_CEL_CTRLR_v3_DATAFLOW;
62
63 ARCHITECTURE ar_IIR_CEL_CTRLR_v3_DATAFLOW OF IIR_CEL_CTRLR_v3_DATAFLOW IS
64
65 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
66 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
67 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
68 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
69
70 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
71 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
72
73 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
74
75 BEGIN
76
77 -----------------------------------------------------------------------------
78 -- INPUT
79 -----------------------------------------------------------------------------
80 PROCESS (clk, rstn)
81 BEGIN -- PROCESS
82 IF rstn = '0' THEN -- asynchronous reset (active low)
83 reg_sample_in <= (OTHERS => '0');
84 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
85 CASE in_sel_src IS
86 WHEN "00" => reg_sample_in <= reg_sample_in;
87 WHEN "01" => reg_sample_in <= sample_in;
88 WHEN "10" => reg_sample_in <= ram_output;
89 WHEN "11" => reg_sample_in <= alu_output;
90 WHEN OTHERS => NULL;
91 END CASE;
92 END IF;
93 END PROCESS;
94
95
96 -----------------------------------------------------------------------------
97 -- RAM + CTRL
98 -----------------------------------------------------------------------------
99
100 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
101 alu_output WHEN ram_sel_Wdata = "01" ELSE
102 ram_output;
103
104 -----------------------------------------------------------------------------
105 -- MAC_ACC
106 -----------------------------------------------------------------------------
107 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
108 -- Data In : mac_sample, mac_coef
109 -- Data Out: mac_output
110
111 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
112
113 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
114 coeff_in: IF I < Coef_Nb GENERATE
115 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
116 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
117 END GENERATE all_bit;
118 END GENERATE coeff_in;
119 coeff_null: IF I > (Coef_Nb -1) GENERATE
120 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
121 arrayCoeff(I,J) <= '0';
122 END GENERATE all_bit;
123 END GENERATE coeff_null;
124 END GENERATE coefftable;
125
126 Coeff_Mux : MUXN
127 GENERIC MAP (
128 Input_SZ => Coef_SZ,
129 NbStage => Coef_sel_SZ)
130 PORT MAP (
131 sel => alu_sel_coeff,
132 INPUT => arrayCoeff,
133 RES => alu_coef_s);
134
135
136 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
137 alu_coef(J) <= alu_coef_s(J);
138 END GENERATE all_bit;
139
140 -----------------------------------------------------------------------------
141 -- TODO : just for Synthesis test
142
143 --PROCESS (clk, rstn)
144 --BEGIN
145 -- IF rstn = '0' THEN
146 -- alu_coef <= (OTHERS => '0');
147 -- ELSIF clk'event AND clk = '1' THEN
148 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
149 -- alu_coef(J) <= alu_coef_s(J);
150 -- END LOOP all_bit;
151 -- END IF;
152 --END PROCESS;
153
154 -----------------------------------------------------------------------------
155
156
157 ALU_1: ALU
158 GENERIC MAP (
159 Arith_en => 1,
160 Input_SZ_1 => Sample_SZ,
161 Input_SZ_2 => Coef_SZ,
162 COMP_EN => 1)
163 PORT MAP (
164 clk => clk,
165 reset => rstn,
166 ctrl => alu_ctrl,
167 comp => alu_comp,
168 OP1 => alu_sample,
169 OP2 => alu_coef,
170 RES => alu_output_s);
171
172 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
173
174 sample_out <= alu_output;
175
176 END ar_IIR_CEL_CTRLR_v3_DATAFLOW;
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
Show file before | Show file after | Hide comments
@@ -1,443 +1,443
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 -- HK ---------------------------------------------------------------------
86 86 HK_smpclk : OUT STD_LOGIC;
87 87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
89 89 ---------------------------------------------------------------------------
90 90 TAG8 : OUT STD_LOGIC;
91 91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
92 92 );
93 93
94 94 END LFR_em;
95 95
96 96
97 97 ARCHITECTURE beh OF LFR_em IS
98 98 SIGNAL clk_50_s : STD_LOGIC := '0';
99 99 SIGNAL clk_25 : STD_LOGIC := '0';
100 100 SIGNAL clk_24 : STD_LOGIC := '0';
101 101 -----------------------------------------------------------------------------
102 102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 104
105 105 -- CONSTANTS
106 106 CONSTANT CFG_PADTECH : INTEGER := inferred;
107 107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
108 108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
109 109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
110 110
111 111 SIGNAL apbi_ext : apb_slv_in_type;
112 112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
113 113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
114 114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
115 115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
116 116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
117 117
118 118 -- Spacewire signals
119 119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 122 SIGNAL spw_rxtxclk : STD_ULOGIC;
123 123 SIGNAL spw_rxclkn : STD_ULOGIC;
124 124 SIGNAL spw_clk : STD_LOGIC;
125 125 SIGNAL swni : grspw_in_type;
126 126 SIGNAL swno : grspw_out_type;
127 127
128 128 --GPIO
129 129 SIGNAL gpioi : gpio_in_type;
130 130 SIGNAL gpioo : gpio_out_type;
131 131
132 132 -- AD Converter ADS7886
133 133 SIGNAL sample : Samples14v(8 DOWNTO 0);
134 134 SIGNAL sample_s : Samples(8 DOWNTO 0);
135 135 SIGNAL sample_val : STD_LOGIC;
136 136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
137 137
138 138 -----------------------------------------------------------------------------
139 139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 140
141 141 -----------------------------------------------------------------------------
142 142 SIGNAL rstn : STD_LOGIC;
143 143
144 144 SIGNAL LFR_soft_rstn : STD_LOGIC;
145 145 SIGNAL LFR_rstn : STD_LOGIC;
146 146
147 147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 148 -----------------------------------------------------------------------------
149 149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150
151 151 BEGIN -- beh
152 152
153 153 -----------------------------------------------------------------------------
154 154 -- CLK
155 155 -----------------------------------------------------------------------------
156 156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
157 157
158 158 PROCESS(clk100MHz)
159 159 BEGIN
160 160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
161 161 clk_50_s <= NOT clk_50_s;
162 162 END IF;
163 163 END PROCESS;
164 164
165 165 PROCESS(clk_50_s)
166 166 BEGIN
167 167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
168 168 clk_25 <= NOT clk_25;
169 169 END IF;
170 170 END PROCESS;
171 171
172 172 PROCESS(clk49_152MHz)
173 173 BEGIN
174 174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 175 clk_24 <= NOT clk_24;
176 176 END IF;
177 177 END PROCESS;
178 178
179 179 -----------------------------------------------------------------------------
180 180
181 181 PROCESS (clk_25, rstn)
182 182 BEGIN -- PROCESS
183 183 IF rstn = '0' THEN -- asynchronous reset (active low)
184 184 led(0) <= '0';
185 185 led(1) <= '0';
186 186 led(2) <= '0';
187 187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
188 188 led(0) <= '0';
189 189 led(1) <= '1';
190 190 led(2) <= '1';
191 191 END IF;
192 192 END PROCESS;
193 193
194 194 --
195 195 leon3_soc_1 : leon3_soc
196 196 GENERIC MAP (
197 197 fabtech => apa3e,
198 198 memtech => apa3e,
199 199 padtech => inferred,
200 200 clktech => inferred,
201 201 disas => 0,
202 202 dbguart => 0,
203 203 pclow => 2,
204 204 clk_freq => 25000,
205 205 NB_CPU => 1,
206 206 ENABLE_FPU => 1,
207 207 FPU_NETLIST => 0,
208 208 ENABLE_DSU => 1,
209 209 ENABLE_AHB_UART => 1,
210 210 ENABLE_APB_UART => 1,
211 211 ENABLE_IRQMP => 1,
212 212 ENABLE_GPT => 1,
213 213 NB_AHB_MASTER => NB_AHB_MASTER,
214 214 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 215 NB_APB_SLAVE => NB_APB_SLAVE,
216 216 ADDRESS_SIZE => 20,
217 217 USES_IAP_MEMCTRLR => 0)
218 218 PORT MAP (
219 219 clk => clk_25,
220 220 reset => rstn,
221 221 errorn => OPEN,
222 222
223 223 ahbrxd => TAG1,
224 224 ahbtxd => TAG3,
225 225 urxd1 => TAG2,
226 226 utxd1 => TAG4,
227 227
228 228 address => address,
229 229 data => data,
230 230 nSRAM_BE0 => nSRAM_BE0,
231 231 nSRAM_BE1 => nSRAM_BE1,
232 232 nSRAM_BE2 => nSRAM_BE2,
233 233 nSRAM_BE3 => nSRAM_BE3,
234 234 nSRAM_WE => nSRAM_WE,
235 235 nSRAM_CE => nSRAM_CE_s,
236 236 nSRAM_OE => nSRAM_OE,
237 237 nSRAM_READY => '0',
238 238 SRAM_MBE => OPEN,
239 239
240 240 apbi_ext => apbi_ext,
241 241 apbo_ext => apbo_ext,
242 242 ahbi_s_ext => ahbi_s_ext,
243 243 ahbo_s_ext => ahbo_s_ext,
244 244 ahbi_m_ext => ahbi_m_ext,
245 245 ahbo_m_ext => ahbo_m_ext);
246 246
247 247
248 248 nSRAM_CE <= nSRAM_CE_s(0);
249 249
250 250 -------------------------------------------------------------------------------
251 251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 252 -------------------------------------------------------------------------------
253 253 apb_lfr_management_1 : apb_lfr_management
254 254 GENERIC MAP (
255 255 pindex => 6,
256 256 paddr => 6,
257 257 pmask => 16#fff#,
258 258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
259 259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
260 260 PORT MAP (
261 261 clk25MHz => clk_25,
262 262 clk24_576MHz => clk_24, -- 49.152MHz/2
263 263 resetn => rstn,
264 264 grspw_tick => swno.tickout,
265 265 apbi => apbi_ext,
266 266 apbo => apbo_ext(6),
267 267
268 268 HK_sample => sample_s(8),
269 269 HK_val => sample_val,
270 270 HK_sel => HK_SEL,
271 271
272 272 coarse_time => coarse_time,
273 273 fine_time => fine_time,
274 274 LFR_soft_rstn => LFR_soft_rstn
275 275 );
276 276
277 277 -----------------------------------------------------------------------
278 278 --- SpaceWire --------------------------------------------------------
279 279 -----------------------------------------------------------------------
280 280
281 281 -- SPW_EN <= '1';
282 282
283 283 spw_clk <= clk_50_s;
284 284 spw_rxtxclk <= spw_clk;
285 285 spw_rxclkn <= NOT spw_rxtxclk;
286 286
287 287 -- PADS for SPW1
288 288 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
289 289 PORT MAP (spw1_din, dtmp(0));
290 290 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
291 291 PORT MAP (spw1_sin, stmp(0));
292 292 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
293 293 PORT MAP (spw1_dout, swno.d(0));
294 294 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
295 295 PORT MAP (spw1_sout, swno.s(0));
296 296 -- PADS FOR SPW2
297 297 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
298 298 PORT MAP (spw2_din, dtmp(1));
299 299 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
300 300 PORT MAP (spw2_sin, stmp(1));
301 301 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
302 302 PORT MAP (spw2_dout, swno.d(1));
303 303 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
304 304 PORT MAP (spw2_sout, swno.s(1));
305 305
306 306 -- GRSPW PHY
307 307 --spw1_input: if CFG_SPW_GRSPW = 1 generate
308 308 spw_inputloop : FOR j IN 0 TO 1 GENERATE
309 309 spw_phy0 : grspw_phy
310 310 GENERIC MAP(
311 311 tech => apa3e,
312 312 rxclkbuftype => 1,
313 313 scantest => 0)
314 314 PORT MAP(
315 315 rxrst => swno.rxrst,
316 316 di => dtmp(j),
317 317 si => stmp(j),
318 318 rxclko => spw_rxclk(j),
319 319 do => swni.d(j),
320 320 ndo => swni.nd(j*5+4 DOWNTO j*5),
321 321 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
322 322 END GENERATE spw_inputloop;
323 323
324 324 -- SPW core
325 325 sw0 : grspwm GENERIC MAP(
326 326 tech => apa3e,
327 327 hindex => 1,
328 328 pindex => 5,
329 329 paddr => 5,
330 330 pirq => 11,
331 331 sysfreq => 25000, -- CPU_FREQ
332 332 rmap => 1,
333 333 rmapcrc => 1,
334 334 fifosize1 => 16,
335 335 fifosize2 => 16,
336 336 rxclkbuftype => 1,
337 337 rxunaligned => 0,
338 338 rmapbufs => 4,
339 339 ft => 0,
340 340 netlist => 0,
341 341 ports => 2,
342 342 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
343 343 memtech => apa3e,
344 344 destkey => 2,
345 345 spwcore => 1
346 346 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
347 347 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
348 348 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
349 349 )
350 350 PORT MAP(rstn, clk_25, spw_rxclk(0),
351 351 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
352 352 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
353 353 swni, swno);
354 354
355 355 swni.tickin <= '0';
356 356 swni.rmapen <= '1';
357 357 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
358 358 swni.tickinraw <= '0';
359 359 swni.timein <= (OTHERS => '0');
360 360 swni.dcrstval <= (OTHERS => '0');
361 361 swni.timerrstval <= (OTHERS => '0');
362 362
363 363 -------------------------------------------------------------------------------
364 364 -- LFR ------------------------------------------------------------------------
365 365 -------------------------------------------------------------------------------
366 366 LFR_rstn <= LFR_soft_rstn AND rstn;
367 367
368 368 lpp_lfr_1 : lpp_lfr
369 369 GENERIC MAP (
370 370 Mem_use => use_RAM,
371 371 nb_data_by_buffer_size => 32,
372 372 --nb_word_by_buffer_size => 30,
373 373 nb_snapshot_param_size => 32,
374 374 delta_vector_size => 32,
375 375 delta_vector_size_f0_2 => 7, -- log2(96)
376 376 pindex => 15,
377 377 paddr => 15,
378 378 pmask => 16#fff#,
379 379 pirq_ms => 6,
380 380 pirq_wfp => 14,
381 381 hindex => 2,
382 top_lfr_version => X"010131") -- aa.bb.cc version
382 top_lfr_version => X"010135") -- aa.bb.cc version
383 383 -- AA : BOARD NUMBER
384 384 -- 0 => MINI_LFR
385 385 -- 1 => EM
386 386 PORT MAP (
387 387 clk => clk_25,
388 388 rstn => LFR_rstn,
389 389 sample_B => sample_s(2 DOWNTO 0),
390 390 sample_E => sample_s(7 DOWNTO 3),
391 391 sample_val => sample_val,
392 392 apbi => apbi_ext,
393 393 apbo => apbo_ext(15),
394 394 ahbi => ahbi_m_ext,
395 395 ahbo => ahbo_m_ext(2),
396 396 coarse_time => coarse_time,
397 397 fine_time => fine_time,
398 398 data_shaping_BW => bias_fail_sw,
399 399 debug_vector => OPEN,
400 400 debug_vector_ms => OPEN); --,
401 401 --observation_vector_0 => OPEN,
402 402 --observation_vector_1 => OPEN,
403 403 --observation_reg => observation_reg);
404 404
405 405
406 406 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
407 407 sample_s(I) <= sample(I) & '0' & '0';
408 408 END GENERATE all_sample;
409 409 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
410 410
411 411 -----------------------------------------------------------------------------
412 412 --
413 413 -----------------------------------------------------------------------------
414 414 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
415 415 GENERIC MAP (
416 416 ChanelCount => 9,
417 417 ncycle_cnv_high => 13,
418 418 ncycle_cnv => 25,
419 419 FILTER_ENABLED => 16#FF#)
420 420 PORT MAP (
421 421 cnv_clk => clk_24,
422 422 cnv_rstn => rstn,
423 423 cnv => ADC_smpclk_s,
424 424 clk => clk_25,
425 425 rstn => rstn,
426 426 ADC_data => ADC_data,
427 427 ADC_nOE => ADC_OEB_bar_CH_s,
428 428 sample => sample,
429 429 sample_val => sample_val);
430 430
431 431 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
432 432
433 433 ADC_smpclk <= ADC_smpclk_s;
434 434 HK_smpclk <= ADC_smpclk_s;
435 435
436 436 TAG8 <= ADC_smpclk_s;
437 437
438 438 -----------------------------------------------------------------------------
439 439 -- HK
440 440 -----------------------------------------------------------------------------
441 441 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
442 442
443 443 END beh;
Show file before | Show file after | Hide comments
@@ -1,733 +1,733
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 --
200 200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202 202
203 203 BEGIN -- beh
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- CLK
207 207 -----------------------------------------------------------------------------
208 208
209 209 --PROCESS(clk_50)
210 210 --BEGIN
211 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 212 -- clk_50_s <= NOT clk_50_s;
213 213 -- END IF;
214 214 --END PROCESS;
215 215
216 216 --PROCESS(clk_50_s)
217 217 --BEGIN
218 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 219 -- clk_25 <= NOT clk_25;
220 220 -- END IF;
221 221 --END PROCESS;
222 222
223 223 --PROCESS(clk_49)
224 224 --BEGIN
225 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 226 -- clk_24 <= NOT clk_24;
227 227 -- END IF;
228 228 --END PROCESS;
229 229
230 230 --PROCESS(clk_25)
231 231 --BEGIN
232 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 233 -- rstn_25 <= reset;
234 234 -- END IF;
235 235 --END PROCESS;
236 236
237 237 PROCESS (clk_50, reset)
238 238 BEGIN -- PROCESS
239 239 IF reset = '0' THEN -- asynchronous reset (active low)
240 240 clk_50_s <= '0';
241 241 rstn_50 <= '0';
242 242 rstn_50_d1 <= '0';
243 243 rstn_50_d2 <= '0';
244 244 rstn_50_d3 <= '0';
245 245
246 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 247 clk_50_s <= NOT clk_50_s;
248 248 rstn_50_d1 <= '1';
249 249 rstn_50_d2 <= rstn_50_d1;
250 250 rstn_50_d3 <= rstn_50_d2;
251 251 rstn_50 <= rstn_50_d3;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 PROCESS (clk_50_s, rstn_50)
256 256 BEGIN -- PROCESS
257 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 258 clk_25 <= '0';
259 259 rstn_25 <= '0';
260 260 rstn_25_d1 <= '0';
261 261 rstn_25_d2 <= '0';
262 262 rstn_25_d3 <= '0';
263 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 264 clk_25 <= NOT clk_25;
265 265 rstn_25_d1 <= '1';
266 266 rstn_25_d2 <= rstn_25_d1;
267 267 rstn_25_d3 <= rstn_25_d2;
268 268 rstn_25 <= rstn_25_d3;
269 269 END IF;
270 270 END PROCESS;
271 271
272 272 PROCESS (clk_49, reset)
273 273 BEGIN -- PROCESS
274 274 IF reset = '0' THEN -- asynchronous reset (active low)
275 275 clk_24 <= '0';
276 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 277 clk_24 <= NOT clk_24;
278 278 END IF;
279 279 END PROCESS;
280 280
281 281 -----------------------------------------------------------------------------
282 282
283 283 PROCESS (clk_25, rstn_25)
284 284 BEGIN -- PROCESS
285 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 286 LED0 <= '0';
287 287 LED1 <= '0';
288 288 LED2 <= '0';
289 289 --IO1 <= '0';
290 290 --IO2 <= '1';
291 291 --IO3 <= '0';
292 292 --IO4 <= '0';
293 293 --IO5 <= '0';
294 294 --IO6 <= '0';
295 295 --IO7 <= '0';
296 296 --IO8 <= '0';
297 297 --IO9 <= '0';
298 298 --IO10 <= '0';
299 299 --IO11 <= '0';
300 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 301 LED0 <= '0';
302 302 LED1 <= '1';
303 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 --IO1 <= '1';
305 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 306 --IO3 <= ADC_SDO(0);
307 307 --IO4 <= ADC_SDO(1);
308 308 --IO5 <= ADC_SDO(2);
309 309 --IO6 <= ADC_SDO(3);
310 310 --IO7 <= ADC_SDO(4);
311 311 --IO8 <= ADC_SDO(5);
312 312 --IO9 <= ADC_SDO(6);
313 313 --IO10 <= ADC_SDO(7);
314 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 PROCESS (clk_24, rstn_25)
319 319 BEGIN -- PROCESS
320 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 321 I00_s <= '0';
322 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 323 I00_s <= NOT I00_s;
324 324 END IF;
325 325 END PROCESS;
326 326 -- IO0 <= I00_s;
327 327
328 328 --UARTs
329 329 nCTS1 <= '1';
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 333 --EXT CONNECTOR
334 334
335 335 --SPACE WIRE
336 336
337 337 leon3_soc_1 : leon3_soc
338 338 GENERIC MAP (
339 339 fabtech => apa3e,
340 340 memtech => apa3e,
341 341 padtech => inferred,
342 342 clktech => inferred,
343 343 disas => 0,
344 344 dbguart => 0,
345 345 pclow => 2,
346 346 clk_freq => 25000,
347 347 NB_CPU => 1,
348 348 ENABLE_FPU => 1,
349 349 FPU_NETLIST => 0,
350 350 ENABLE_DSU => 1,
351 351 ENABLE_AHB_UART => 1,
352 352 ENABLE_APB_UART => 1,
353 353 ENABLE_IRQMP => 1,
354 354 ENABLE_GPT => 1,
355 355 NB_AHB_MASTER => NB_AHB_MASTER,
356 356 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 357 NB_APB_SLAVE => NB_APB_SLAVE,
358 358 ADDRESS_SIZE => 20,
359 359 USES_IAP_MEMCTRLR => 0)
360 360 PORT MAP (
361 361 clk => clk_25,
362 362 reset => rstn_25,
363 363 errorn => errorn,
364 364 ahbrxd => TXD1,
365 365 ahbtxd => RXD1,
366 366 urxd1 => TXD2,
367 367 utxd1 => RXD2,
368 368 address => SRAM_A,
369 369 data => SRAM_DQ,
370 370 nSRAM_BE0 => SRAM_nBE(0),
371 371 nSRAM_BE1 => SRAM_nBE(1),
372 372 nSRAM_BE2 => SRAM_nBE(2),
373 373 nSRAM_BE3 => SRAM_nBE(3),
374 374 nSRAM_WE => SRAM_nWE,
375 375 nSRAM_CE => SRAM_CE_s,
376 376 nSRAM_OE => SRAM_nOE,
377 377 nSRAM_READY => '0',
378 378 SRAM_MBE => OPEN,
379 379 apbi_ext => apbi_ext,
380 380 apbo_ext => apbo_ext,
381 381 ahbi_s_ext => ahbi_s_ext,
382 382 ahbo_s_ext => ahbo_s_ext,
383 383 ahbi_m_ext => ahbi_m_ext,
384 384 ahbo_m_ext => ahbo_m_ext);
385 385
386 386 SRAM_CE <= SRAM_CE_s(0);
387 387 -------------------------------------------------------------------------------
388 388 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
389 389 -------------------------------------------------------------------------------
390 390 apb_lfr_management_1 : apb_lfr_management
391 391 GENERIC MAP (
392 392 pindex => 6,
393 393 paddr => 6,
394 394 pmask => 16#fff#,
395 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 397 PORT MAP (
398 398 clk25MHz => clk_25,
399 399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 400 resetn => rstn_25,
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 404 HK_sample => sample_hk,
405 405 HK_val => sample_val,
406 406 HK_sel => HK_SEL,
407 407 coarse_time => coarse_time,
408 408 fine_time => fine_time,
409 409 LFR_soft_rstn => LFR_soft_rstn
410 410 );
411 411
412 412 -----------------------------------------------------------------------
413 413 --- SpaceWire --------------------------------------------------------
414 414 -----------------------------------------------------------------------
415 415
416 416 SPW_EN <= '1';
417 417
418 418 spw_clk <= clk_50_s;
419 419 spw_rxtxclk <= spw_clk;
420 420 spw_rxclkn <= NOT spw_rxtxclk;
421 421
422 422 -- PADS for SPW1
423 423 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
424 424 PORT MAP (SPW_NOM_DIN, dtmp(0));
425 425 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
426 426 PORT MAP (SPW_NOM_SIN, stmp(0));
427 427 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
428 428 PORT MAP (SPW_NOM_DOUT, swno.d(0));
429 429 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_NOM_SOUT, swno.s(0));
431 431 -- PADS FOR SPW2
432 432 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
433 433 PORT MAP (SPW_RED_SIN, dtmp(1));
434 434 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
435 435 PORT MAP (SPW_RED_DIN, stmp(1));
436 436 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
437 437 PORT MAP (SPW_RED_DOUT, swno.d(1));
438 438 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
439 439 PORT MAP (SPW_RED_SOUT, swno.s(1));
440 440
441 441 -- GRSPW PHY
442 442 --spw1_input: if CFG_SPW_GRSPW = 1 generate
443 443 spw_inputloop : FOR j IN 0 TO 1 GENERATE
444 444 spw_phy0 : grspw_phy
445 445 GENERIC MAP(
446 446 tech => apa3e,
447 447 rxclkbuftype => 1,
448 448 scantest => 0)
449 449 PORT MAP(
450 450 rxrst => swno.rxrst,
451 451 di => dtmp(j),
452 452 si => stmp(j),
453 453 rxclko => spw_rxclk(j),
454 454 do => swni.d(j),
455 455 ndo => swni.nd(j*5+4 DOWNTO j*5),
456 456 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
457 457 END GENERATE spw_inputloop;
458 458
459 459 swni.rmapnodeaddr <= (OTHERS => '0');
460 460
461 461 -- SPW core
462 462 sw0 : grspwm GENERIC MAP(
463 463 tech => apa3e,
464 464 hindex => 1,
465 465 pindex => 5,
466 466 paddr => 5,
467 467 pirq => 11,
468 468 sysfreq => 25000, -- CPU_FREQ
469 469 rmap => 1,
470 470 rmapcrc => 1,
471 471 fifosize1 => 16,
472 472 fifosize2 => 16,
473 473 rxclkbuftype => 1,
474 474 rxunaligned => 0,
475 475 rmapbufs => 4,
476 476 ft => 0,
477 477 netlist => 0,
478 478 ports => 2,
479 479 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
480 480 memtech => apa3e,
481 481 destkey => 2,
482 482 spwcore => 1
483 483 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
484 484 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
485 485 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
486 486 )
487 487 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
488 488 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
489 489 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
490 490 swni, swno);
491 491
492 492 swni.tickin <= '0';
493 493 swni.rmapen <= '1';
494 494 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
495 495 swni.tickinraw <= '0';
496 496 swni.timein <= (OTHERS => '0');
497 497 swni.dcrstval <= (OTHERS => '0');
498 498 swni.timerrstval <= (OTHERS => '0');
499 499
500 500 -------------------------------------------------------------------------------
501 501 -- LFR ------------------------------------------------------------------------
502 502 -------------------------------------------------------------------------------
503 503
504 504
505 505 LFR_rstn <= LFR_soft_rstn AND rstn_25;
506 506 --LFR_rstn <= rstn_25;
507 507
508 508 lpp_lfr_1 : lpp_lfr
509 509 GENERIC MAP (
510 510 Mem_use => use_RAM,
511 511 nb_data_by_buffer_size => 32,
512 512 nb_snapshot_param_size => 32,
513 513 delta_vector_size => 32,
514 514 delta_vector_size_f0_2 => 7, -- log2(96)
515 515 pindex => 15,
516 516 paddr => 15,
517 517 pmask => 16#fff#,
518 518 pirq_ms => 6,
519 519 pirq_wfp => 14,
520 520 hindex => 2,
521 521 top_lfr_version => X"000135") -- aa.bb.cc version
522 522 PORT MAP (
523 523 clk => clk_25,
524 524 rstn => LFR_rstn,
525 525 sample_B => sample_s(2 DOWNTO 0),
526 526 sample_E => sample_s(7 DOWNTO 3),
527 527 sample_val => sample_val,
528 528 apbi => apbi_ext,
529 529 apbo => apbo_ext(15),
530 530 ahbi => ahbi_m_ext,
531 531 ahbo => ahbo_m_ext(2),
532 532 coarse_time => coarse_time,
533 533 fine_time => fine_time,
534 534 data_shaping_BW => bias_fail_sw_sig,
535 535 debug_vector => lfr_debug_vector,
536 536 debug_vector_ms => lfr_debug_vector_ms
537 537 );
538 538
539 539 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
540 540 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
541 541 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
542 542 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
543 543 IO0 <= rstn_25;
544 544 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
545 545 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
546 546 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
547 547 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
548 548 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
549 549 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
550 550 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
551 551
552 552 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
553 553 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
554 554 END GENERATE all_sample;
555 555
556 556 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
557 557 GENERIC MAP(
558 558 ChannelCount => 8,
559 559 SampleNbBits => 14,
560 560 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
561 561 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
562 562 PORT MAP (
563 563 -- CONV
564 564 cnv_clk => clk_24,
565 565 cnv_rstn => rstn_25,
566 566 cnv => ADC_nCS_sig,
567 567 -- DATA
568 568 clk => clk_25,
569 569 rstn => rstn_25,
570 570 sck => ADC_CLK_sig,
571 571 sdo => ADC_SDO_sig,
572 572 -- SAMPLE
573 573 sample => sample,
574 574 sample_val => sample_val);
575 575
576 576 --IO10 <= ADC_SDO_sig(5);
577 577 --IO9 <= ADC_SDO_sig(4);
578 578 --IO8 <= ADC_SDO_sig(3);
579 579
580 580 ADC_nCS <= ADC_nCS_sig;
581 581 ADC_CLK <= ADC_CLK_sig;
582 582 ADC_SDO_sig <= ADC_SDO;
583 583
584 584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
585 "0010001000100010" WHEN HK_SEL = "10" ELSE
586 "0100010001000100" WHEN HK_SEL = "11" ELSE
585 "0010001000100010" WHEN HK_SEL = "01" ELSE
586 "0100010001000100" WHEN HK_SEL = "10" ELSE
587 587 (OTHERS => '0');
588 588
589 589
590 590 ----------------------------------------------------------------------
591 591 --- GPIO -----------------------------------------------------------
592 592 ----------------------------------------------------------------------
593 593
594 594 grgpio0 : grgpio
595 595 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
596 596 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
597 597
598 598 gpioi.sig_en <= (OTHERS => '0');
599 599 gpioi.sig_in <= (OTHERS => '0');
600 600 gpioi.din <= (OTHERS => '0');
601 601 --pio_pad_0 : iopad
602 602 -- GENERIC MAP (tech => CFG_PADTECH)
603 603 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
604 604 --pio_pad_1 : iopad
605 605 -- GENERIC MAP (tech => CFG_PADTECH)
606 606 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
607 607 --pio_pad_2 : iopad
608 608 -- GENERIC MAP (tech => CFG_PADTECH)
609 609 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
610 610 --pio_pad_3 : iopad
611 611 -- GENERIC MAP (tech => CFG_PADTECH)
612 612 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
613 613 --pio_pad_4 : iopad
614 614 -- GENERIC MAP (tech => CFG_PADTECH)
615 615 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
616 616 --pio_pad_5 : iopad
617 617 -- GENERIC MAP (tech => CFG_PADTECH)
618 618 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
619 619 --pio_pad_6 : iopad
620 620 -- GENERIC MAP (tech => CFG_PADTECH)
621 621 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
622 622 --pio_pad_7 : iopad
623 623 -- GENERIC MAP (tech => CFG_PADTECH)
624 624 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
625 625
626 626 PROCESS (clk_25, rstn_25)
627 627 BEGIN -- PROCESS
628 628 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
629 629 -- --IO0 <= '0';
630 630 -- IO1 <= '0';
631 631 -- IO2 <= '0';
632 632 -- IO3 <= '0';
633 633 -- IO4 <= '0';
634 634 -- IO5 <= '0';
635 635 -- IO6 <= '0';
636 636 -- IO7 <= '0';
637 637 IO8 <= '0';
638 638 IO9 <= '0';
639 639 IO10 <= '0';
640 640 IO11 <= '0';
641 641 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
642 642 CASE gpioo.dout(2 DOWNTO 0) IS
643 643 WHEN "011" =>
644 644 -- --IO0 <= observation_reg(0 );
645 645 -- IO1 <= observation_reg(1 );
646 646 -- IO2 <= observation_reg(2 );
647 647 -- IO3 <= observation_reg(3 );
648 648 -- IO4 <= observation_reg(4 );
649 649 -- IO5 <= observation_reg(5 );
650 650 -- IO6 <= observation_reg(6 );
651 651 -- IO7 <= observation_reg(7 );
652 652 IO8 <= observation_reg(8);
653 653 IO9 <= observation_reg(9);
654 654 IO10 <= observation_reg(10);
655 655 IO11 <= observation_reg(11);
656 656 WHEN "001" =>
657 657 -- --IO0 <= observation_reg(0 + 12);
658 658 -- IO1 <= observation_reg(1 + 12);
659 659 -- IO2 <= observation_reg(2 + 12);
660 660 -- IO3 <= observation_reg(3 + 12);
661 661 -- IO4 <= observation_reg(4 + 12);
662 662 -- IO5 <= observation_reg(5 + 12);
663 663 -- IO6 <= observation_reg(6 + 12);
664 664 -- IO7 <= observation_reg(7 + 12);
665 665 IO8 <= observation_reg(8 + 12);
666 666 IO9 <= observation_reg(9 + 12);
667 667 IO10 <= observation_reg(10 + 12);
668 668 IO11 <= observation_reg(11 + 12);
669 669 WHEN "010" =>
670 670 -- --IO0 <= observation_reg(0 + 12 + 12);
671 671 -- IO1 <= observation_reg(1 + 12 + 12);
672 672 -- IO2 <= observation_reg(2 + 12 + 12);
673 673 -- IO3 <= observation_reg(3 + 12 + 12);
674 674 -- IO4 <= observation_reg(4 + 12 + 12);
675 675 -- IO5 <= observation_reg(5 + 12 + 12);
676 676 -- IO6 <= observation_reg(6 + 12 + 12);
677 677 -- IO7 <= observation_reg(7 + 12 + 12);
678 678 IO8 <= '0';
679 679 IO9 <= '0';
680 680 IO10 <= '0';
681 681 IO11 <= '0';
682 682 WHEN "000" =>
683 683 -- --IO0 <= observation_vector_0(0 );
684 684 -- IO1 <= observation_vector_0(1 );
685 685 -- IO2 <= observation_vector_0(2 );
686 686 -- IO3 <= observation_vector_0(3 );
687 687 -- IO4 <= observation_vector_0(4 );
688 688 -- IO5 <= observation_vector_0(5 );
689 689 -- IO6 <= observation_vector_0(6 );
690 690 -- IO7 <= observation_vector_0(7 );
691 691 IO8 <= observation_vector_0(8);
692 692 IO9 <= observation_vector_0(9);
693 693 IO10 <= observation_vector_0(10);
694 694 IO11 <= observation_vector_0(11);
695 695 WHEN "100" =>
696 696 -- --IO0 <= observation_vector_1(0 );
697 697 -- IO1 <= observation_vector_1(1 );
698 698 -- IO2 <= observation_vector_1(2 );
699 699 -- IO3 <= observation_vector_1(3 );
700 700 -- IO4 <= observation_vector_1(4 );
701 701 -- IO5 <= observation_vector_1(5 );
702 702 -- IO6 <= observation_vector_1(6 );
703 703 -- IO7 <= observation_vector_1(7 );
704 704 IO8 <= observation_vector_1(8);
705 705 IO9 <= observation_vector_1(9);
706 706 IO10 <= observation_vector_1(10);
707 707 IO11 <= observation_vector_1(11);
708 708 WHEN OTHERS => NULL;
709 709 END CASE;
710 710
711 711 END IF;
712 712 END PROCESS;
713 713 -----------------------------------------------------------------------------
714 714 --
715 715 -----------------------------------------------------------------------------
716 716 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
717 717 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
718 718 apbo_ext(I) <= apb_none;
719 719 END GENERATE apbo_ext_not_used;
720 720 END GENERATE all_apbo_ext;
721 721
722 722
723 723 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
724 724 ahbo_s_ext(I) <= ahbs_none;
725 725 END GENERATE all_ahbo_ext;
726 726
727 727 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
728 728 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
729 729 ahbo_m_ext(I) <= ahbm_none;
730 730 END GENERATE ahbo_m_ext_not_used;
731 731 END GENERATE all_ahbo_m_ext;
732 732
733 733 END beh;
Show file before | Show file after | Hide comments
@@ -1,299 +1,326
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY ieee;
23 23 USE ieee.std_logic_1164.ALL;
24 24 LIBRARY grlib;
25 25 USE grlib.amba.ALL;
26 26 USE grlib.stdlib.ALL;
27 27 USE grlib.devices.ALL;
28 28
29 29
30 30
31 31
32 32 PACKAGE iir_filter IS
33 33
34 34
35 35 --===========================================================|
36 36 --================A L U C O N T R O L======================|
37 37 --===========================================================|
38 38 CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
39 39 CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
40 40 CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
41 41 CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
42 42 CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
43 43 CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
44 44
45 45 --____
46 46 --RAM |
47 47 --____|
48 48 CONSTANT use_RAM : INTEGER := 1;
49 49 CONSTANT use_CEL : INTEGER := 0;
50 50
51 51
52 52 --===========================================================|
53 53 --=============C O E F S ====================================|
54 54 --===========================================================|
55 55 -- create a specific type of data for coefs to avoid errors |
56 56 --===========================================================|
57 57
58 58 TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
59 59
60 60 TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
61 61
62 62 TYPE in_IIR_CEL_reg IS RECORD
63 63 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 65 END RECORD;
66 66
67 67 TYPE out_IIR_CEL_reg IS RECORD
68 68 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 END RECORD;
71 71
72 72
73 73 COMPONENT APB_IIR_CEL IS
74 74 GENERIC (
75 75 tech : INTEGER := 0;
76 76 pindex : INTEGER := 0;
77 77 paddr : INTEGER := 0;
78 78 pmask : INTEGER := 16#fff#;
79 79 pirq : INTEGER := 0;
80 80 abits : INTEGER := 8;
81 81 Sample_SZ : INTEGER := 16;
82 82 ChanelsCount : INTEGER := 6;
83 83 Coef_SZ : INTEGER := 9;
84 84 CoefCntPerCel : INTEGER := 6;
85 85 Cels_count : INTEGER := 5;
86 86 virgPos : INTEGER := 7;
87 87 Mem_use : INTEGER := use_RAM
88 88 );
89 89 PORT (
90 90 rst : IN STD_LOGIC;
91 91 clk : IN STD_LOGIC;
92 92 apbi : IN apb_slv_in_type;
93 93 apbo : OUT apb_slv_out_type;
94 94 sample_clk : IN STD_LOGIC;
95 95 sample_clk_out : OUT STD_LOGIC;
96 96 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
97 97 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
98 98 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
99 99 );
100 100 END COMPONENT;
101 101
102 102
103 103 COMPONENT Top_IIR IS
104 104 GENERIC(
105 105 Sample_SZ : INTEGER := 18;
106 106 ChanelsCount : INTEGER := 1;
107 107 Coef_SZ : INTEGER := 9;
108 108 CoefCntPerCel : INTEGER := 6;
109 109 Cels_count : INTEGER := 5);
110 110 PORT(
111 111 reset : IN STD_LOGIC;
112 112 clk : IN STD_LOGIC;
113 113 sample_clk : IN STD_LOGIC;
114 114 -- BP : in std_logic;
115 115 -- BPinput : in std_logic_vector(3 downto 0);
116 116 LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
117 117 INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
118 118 OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
119 119 );
120 120 END COMPONENT;
121 121
122 122 COMPONENT IIR_CEL_CTRLR_v2
123 123 GENERIC (
124 124 tech : INTEGER;
125 125 Mem_use : INTEGER;
126 126 Sample_SZ : INTEGER;
127 127 Coef_SZ : INTEGER;
128 128 Coef_Nb : INTEGER;
129 129 Coef_sel_SZ : INTEGER;
130 130 Cels_count : INTEGER;
131 131 ChanelsCount : INTEGER);
132 132 PORT (
133 133 rstn : IN STD_LOGIC;
134 134 clk : IN STD_LOGIC;
135 135 virg_pos : IN INTEGER;
136 136 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
137 137 sample_in_val : IN STD_LOGIC;
138 138 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
139 139 sample_out_val : OUT STD_LOGIC;
140 140 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
141 141 END COMPONENT;
142
143 COMPONENT IIR_CEL_CTRLR_v3
144 GENERIC (
145 tech : INTEGER;
146 Mem_use : INTEGER;
147 Sample_SZ : INTEGER;
148 Coef_SZ : INTEGER;
149 Coef_Nb : INTEGER;
150 Coef_sel_SZ : INTEGER;
151 Cels_count : INTEGER;
152 ChanelsCount : INTEGER);
153 PORT (
154 rstn : IN STD_LOGIC;
155 clk : IN STD_LOGIC;
156 virg_pos : IN INTEGER;
157 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
158 sample_in1_val : IN STD_LOGIC;
159 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
160 sample_in2_val : IN STD_LOGIC;
161 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
162 sample_out1_val : OUT STD_LOGIC;
163 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
164 sample_out2_val : OUT STD_LOGIC;
165 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
166 END COMPONENT;
142 167
143 168
169
170
144 171 --component FilterCTRLR is
145 172 --port(
146 173 -- reset : in std_logic;
147 174 -- clk : in std_logic;
148 175 -- sample_clk : in std_logic;
149 176 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
150 177 -- sample_in : in samplT;
151 178 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
152 179 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
153 180 --);
154 181 --end component;
155 182
156 183
157 184 --component FILTER_RAM_CTRLR is
158 185 --port(
159 186 -- reset : in std_logic;
160 187 -- clk : in std_logic;
161 188 -- run : in std_logic;
162 189 -- GO_0 : in std_logic;
163 190 -- B_A : in std_logic;
164 191 -- writeForce : in std_logic;
165 192 -- next_blk : in std_logic;
166 193 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
167 194 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
168 195 --);
169 196 --end component;
170 197
171 198
172 199 COMPONENT IIR_CEL_CTRLR IS
173 200 GENERIC(
174 201 tech : INTEGER := 0;
175 202 Sample_SZ : INTEGER := 16;
176 203 ChanelsCount : INTEGER := 1;
177 204 Coef_SZ : INTEGER := 9;
178 205 CoefCntPerCel : INTEGER := 3;
179 206 Cels_count : INTEGER := 5;
180 207 Mem_use : INTEGER := use_RAM
181 208 );
182 209 PORT(
183 210 reset : IN STD_LOGIC;
184 211 clk : IN STD_LOGIC;
185 212 sample_clk : IN STD_LOGIC;
186 213 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
187 214 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
188 215 virg_pos : IN INTEGER;
189 216 GOtest : OUT STD_LOGIC;
190 217 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
191 218 );
192 219 END COMPONENT;
193 220
194 221
195 222 COMPONENT RAM IS
196 223 GENERIC(
197 224 Input_SZ_1 : INTEGER := 8
198 225 );
199 226 PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
200 227 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
201 228 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
202 229 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC
203 230 ) ;
204 231 END COMPONENT;
205 232
206 233 COMPONENT RAM_CEL is
207 234 generic(DataSz : integer range 1 to 32 := 8;
208 235 abits : integer range 2 to 12 := 8);
209 236 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
210 237 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
211 238 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
212 239 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
213 240 ) ;
214 241 end COMPONENT;
215 242
216 243 COMPONENT RAM_CEL_N
217 244 GENERIC (
218 245 size : INTEGER);
219 246 PORT (
220 247 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
221 248 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
222 249 WEN, REN : IN STD_LOGIC;
223 250 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
224 251 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
225 252 RWCLK, RESET : IN STD_LOGIC);
226 253 END COMPONENT;
227 254
228 255 COMPONENT IIR_CEL_FILTER IS
229 256 GENERIC(
230 257 tech : INTEGER := 0;
231 258 Sample_SZ : INTEGER := 16;
232 259 ChanelsCount : INTEGER := 1;
233 260 Coef_SZ : INTEGER := 9;
234 261 CoefCntPerCel : INTEGER := 3;
235 262 Cels_count : INTEGER := 5;
236 263 Mem_use : INTEGER := use_RAM);
237 264 PORT(
238 265 reset : IN STD_LOGIC;
239 266 clk : IN STD_LOGIC;
240 267 sample_clk : IN STD_LOGIC;
241 268 regs_in : IN in_IIR_CEL_reg;
242 269 regs_out : IN out_IIR_CEL_reg;
243 270 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
244 271 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
245 272 GOtest : OUT STD_LOGIC;
246 273 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
247 274
248 275 );
249 276 END COMPONENT;
250 277
251 278
252 279 COMPONENT RAM_CTRLR2 IS
253 280 GENERIC(
254 281 tech : INTEGER := 0;
255 282 Input_SZ_1 : INTEGER := 16;
256 283 Mem_use : INTEGER := use_RAM
257 284 );
258 285 PORT(
259 286 reset : IN STD_LOGIC;
260 287 clk : IN STD_LOGIC;
261 288 WD_sel : IN STD_LOGIC;
262 289 Read : IN STD_LOGIC;
263 290 WADDR_sel : IN STD_LOGIC;
264 291 count : IN STD_LOGIC;
265 292 SVG_ADDR : IN STD_LOGIC;
266 293 Write : IN STD_LOGIC;
267 294 GO_0 : IN STD_LOGIC;
268 295 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
269 296 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
270 297 );
271 298 END COMPONENT;
272 299
273 300 COMPONENT APB_IIR_Filter IS
274 301 GENERIC (
275 302 tech : INTEGER := 0;
276 303 pindex : INTEGER := 0;
277 304 paddr : INTEGER := 0;
278 305 pmask : INTEGER := 16#fff#;
279 306 pirq : INTEGER := 0;
280 307 abits : INTEGER := 8;
281 308 Sample_SZ : INTEGER := 16;
282 309 ChanelsCount : INTEGER := 1;
283 310 Coef_SZ : INTEGER := 9;
284 311 CoefCntPerCel : INTEGER := 6;
285 312 Cels_count : INTEGER := 5;
286 313 virgPos : INTEGER := 3;
287 314 Mem_use : INTEGER := use_RAM
288 315 );
289 316 PORT (
290 317 rst : IN STD_LOGIC;
291 318 clk : IN STD_LOGIC;
292 319 apbi : IN apb_slv_in_type;
293 320 apbo : OUT apb_slv_out_type;
294 321 sample_clk_out : OUT STD_LOGIC;
295 322 GOtest : OUT STD_LOGIC;
296 323 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
297 324 );
298 325 END COMPONENT;
299 326 END;
Show file before | Show file after | Hide comments
@@ -1,8 +1,10
1 1 iir_filter.vhd
2 2 FILTERcfg.vhd
3 3 RAM.vhd
4 4 RAM_CEL.vhd
5 5 RAM_CTRLR_v2.vhd
6 6 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 8 IIR_CEL_CTRLR_v2.vhd
9 IIR_CEL_CTRLR_v3_DATAFLOW.vhd
10 IIR_CEL_CTRLR_v3.vhd
Show file before | Show file after | Hide comments
@@ -1,825 +1,825
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_lfr_pkg.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_lfr_apbreg IS
42 42 GENERIC (
43 43 nb_data_by_buffer_size : INTEGER := 11;
44 44 nb_snapshot_param_size : INTEGER := 11;
45 45 delta_vector_size : INTEGER := 20;
46 46 delta_vector_size_f0_2 : INTEGER := 3;
47 47
48 48 pindex : INTEGER := 4;
49 49 paddr : INTEGER := 4;
50 50 pmask : INTEGER := 16#fff#;
51 51 pirq_ms : INTEGER := 0;
52 52 pirq_wfp : INTEGER := 1;
53 53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 54 PORT (
55 55 -- AMBA AHB system signals
56 56 HCLK : IN STD_ULOGIC;
57 57 HRESETn : IN STD_ULOGIC;
58 58
59 59 -- AMBA APB Slave Interface
60 60 apbi : IN apb_slv_in_type;
61 61 apbo : OUT apb_slv_out_type;
62 62
63 63 ---------------------------------------------------------------------------
64 64 -- Spectral Matrix Reg
65 65 run_ms : OUT STD_LOGIC;
66 66 -- IN
67 67 ready_matrix_f0 : IN STD_LOGIC;
68 68 ready_matrix_f1 : IN STD_LOGIC;
69 69 ready_matrix_f2 : IN STD_LOGIC;
70 70
71 71 -- error_bad_component_error : IN STD_LOGIC;
72 error_buffer_full : IN STD_LOGIC; -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72 error_buffer_full : IN STD_LOGIC; -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74 74
75 75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76
77 77 -- OUT
78 78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 80 status_ready_matrix_f2 : OUT STD_LOGIC;
81 81
82 82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 83 --config_active_interruption_onError : OUT STD_LOGIC;
84 84
85 85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88
89 89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92 92
93 93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96 96
97 97 ---------------------------------------------------------------------------
98 98 ---------------------------------------------------------------------------
99 99 -- WaveForm picker Reg
100 100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104
105 105 -- OUT
106 106 data_shaping_BW : OUT STD_LOGIC;
107 107 data_shaping_SP0 : OUT STD_LOGIC;
108 108 data_shaping_SP1 : OUT STD_LOGIC;
109 109 data_shaping_R0 : OUT STD_LOGIC;
110 110 data_shaping_R1 : OUT STD_LOGIC;
111 111 data_shaping_R2 : OUT STD_LOGIC;
112 112
113 113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121 121
122 122 enable_f0 : OUT STD_LOGIC;
123 123 enable_f1 : OUT STD_LOGIC;
124 124 enable_f2 : OUT STD_LOGIC;
125 125 enable_f3 : OUT STD_LOGIC;
126 126
127 127 burst_f0 : OUT STD_LOGIC;
128 128 burst_f1 : OUT STD_LOGIC;
129 129 burst_f2 : OUT STD_LOGIC;
130 130
131 131 run : OUT STD_LOGIC;
132 132
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134
135 135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 141 ---------------------------------------------------------------------------
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
145 sample_f3_valid : IN STD_LOGIC;
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
145 sample_f3_valid : IN STD_LOGIC;
146 146 ---------------------------------------------------------------------------
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
148
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
148
149 149 );
150 150
151 151 END lpp_lfr_apbreg;
152 152
153 153 ARCHITECTURE beh OF lpp_lfr_apbreg IS
154 154
155 155 CONSTANT REVISION : INTEGER := 1;
156 156
157 157 CONSTANT pconfig : apb_config_type := (
158 158 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
159 159 1 => apb_iobar(paddr, pmask));
160 160
161 161 --CONSTANT pconfig : apb_config_type := (
162 162 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
163 163 -- 1 => apb_iobar(paddr, pmask));
164 164
165 165 TYPE lpp_SpectralMatrix_regs IS RECORD
166 166 config_active_interruption_onNewMatrix : STD_LOGIC;
167 167 config_active_interruption_onError : STD_LOGIC;
168 168 config_ms_run : STD_LOGIC;
169 169 status_ready_matrix_f0_0 : STD_LOGIC;
170 170 status_ready_matrix_f1_0 : STD_LOGIC;
171 171 status_ready_matrix_f2_0 : STD_LOGIC;
172 172 status_ready_matrix_f0_1 : STD_LOGIC;
173 173 status_ready_matrix_f1_1 : STD_LOGIC;
174 174 status_ready_matrix_f2_1 : STD_LOGIC;
175 175 -- status_error_bad_component_error : STD_LOGIC;
176 176 status_error_buffer_full : STD_LOGIC;
177 177 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
178 178
179 179 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 181 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 182 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 183 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 184 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 185
186 186 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
187 187
188 188 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 189 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 190 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 191 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 192 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193 193 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
194 194 END RECORD;
195 195 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
196 196
197 197 TYPE lpp_WaveformPicker_regs IS RECORD
198 198 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 199 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 data_shaping_BW : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 data_shaping_BW : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
213 213 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
215 enable_f0 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
222 run : STD_LOGIC;
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
215 enable_f0 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
222 run : STD_LOGIC;
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
226 226 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
229 229 END RECORD;
230 230 SIGNAL reg_wp : lpp_WaveformPicker_regs;
231 231
232 232 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
233 233
234 234 -----------------------------------------------------------------------------
235 235 -- IRQ
236 236 -----------------------------------------------------------------------------
237 237 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
238 238 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
239 239 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
240 240 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
241 241 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
242 242 SIGNAL ored_irq_wfp : STD_LOGIC;
243 243
244 244 -----------------------------------------------------------------------------
245 245 --
246 246 -----------------------------------------------------------------------------
247 247 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
248 248 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
250 250
251 251 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
252 252 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 253 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
254 254
255 255 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
256 256 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
257 257 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
258 258
259 259 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
260 260 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 261 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262 262
263 263 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
264 264 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 265 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
266 266
267 267 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
268 268 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 269 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
270 SIGNAL apbo_irq_ms : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
270 SIGNAL apbo_irq_ms : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
272 272 -----------------------------------------------------------------------------
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR(2*4-1 DOWNTO 0);
274 274
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
276
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
276
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
280 280
281 281 BEGIN -- beh
282 282
283 283 debug_vector(0) <= error_buffer_full;
284 284 debug_vector(1) <= reg_sp.status_error_buffer_full;
285 285 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
286 286 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
287 287 debug_vector(8) <= ready_matrix_f2;
288 288 debug_vector(9) <= reg0_ready_matrix_f2;
289 289 debug_vector(10) <= reg1_ready_matrix_f2;
290 290 debug_vector(11) <= HRESETn;
291
291
292 292 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
293 293 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
294 294 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
295 295
296 296 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
297 297 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
298 298
299 299
300 300 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
301 301 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
302 302 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
303 303
304 304
305 305 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
306 306 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
307 307 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
308 308 data_shaping_R0 <= reg_wp.data_shaping_R0;
309 309 data_shaping_R1 <= reg_wp.data_shaping_R1;
310 310 data_shaping_R2 <= reg_wp.data_shaping_R2;
311 311
312 312 delta_snapshot <= reg_wp.delta_snapshot;
313 313 delta_f0 <= reg_wp.delta_f0;
314 314 delta_f0_2 <= reg_wp.delta_f0_2;
315 315 delta_f1 <= reg_wp.delta_f1;
316 316 delta_f2 <= reg_wp.delta_f2;
317 317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
318 318 nb_snapshot_param <= reg_wp.nb_snapshot_param;
319 319
320 320 enable_f0 <= reg_wp.enable_f0;
321 321 enable_f1 <= reg_wp.enable_f1;
322 322 enable_f2 <= reg_wp.enable_f2;
323 323 enable_f3 <= reg_wp.enable_f3;
324 324
325 325 burst_f0 <= reg_wp.burst_f0;
326 326 burst_f1 <= reg_wp.burst_f1;
327 327 burst_f2 <= reg_wp.burst_f2;
328 328
329 329 run <= reg_wp.run;
330 330
331 331 --addr_data_f0 <= reg_wp.addr_data_f0;
332 332 --addr_data_f1 <= reg_wp.addr_data_f1;
333 333 --addr_data_f2 <= reg_wp.addr_data_f2;
334 334 --addr_data_f3 <= reg_wp.addr_data_f3;
335 335
336 336 start_date <= reg_wp.start_date;
337 337
338 length_matrix_f0 <= reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
338 length_matrix_f0 <= reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
341 341 wfp_length_buffer <= reg_wp.length_buffer;
342 342
343 343
344
344
345 345 PROCESS (HCLK, HRESETn)
346 346 BEGIN -- PROCESS
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
348 348 sample_f3_v_reg <= (OTHERS => '0');
349 349 sample_f3_e1_reg <= (OTHERS => '0');
350 350 sample_f3_e2_reg <= (OTHERS => '0');
351 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
351 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
352 352 IF sample_f3_valid = '1' THEN
353 353 sample_f3_v_reg <= sample_f3_v;
354 354 sample_f3_e1_reg <= sample_f3_e1;
355 355 sample_f3_e2_reg <= sample_f3_e2;
356 356 END IF;
357 357 END IF;
358 358 END PROCESS;
359
359
360 360
361 361 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
362 362 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
363 363 BEGIN -- PROCESS lpp_dma_top
364 364 IF HRESETn = '0' THEN -- asynchronous reset (active low)
365 365 reg_sp.config_active_interruption_onNewMatrix <= '0';
366 366 reg_sp.config_active_interruption_onError <= '0';
367 367 reg_sp.config_ms_run <= '0';
368 368 reg_sp.status_ready_matrix_f0_0 <= '0';
369 369 reg_sp.status_ready_matrix_f1_0 <= '0';
370 370 reg_sp.status_ready_matrix_f2_0 <= '0';
371 371 reg_sp.status_ready_matrix_f0_1 <= '0';
372 372 reg_sp.status_ready_matrix_f1_1 <= '0';
373 373 reg_sp.status_ready_matrix_f2_1 <= '0';
374 374 reg_sp.status_error_buffer_full <= '0';
375 375 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
376 376
377 377 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
378 378 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
379 379 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
380 380
381 381 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
382 382 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
383 383 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
384 384
385 385 reg_sp.length_matrix <= (OTHERS => '0');
386
386
387 387 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
388 388 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
389 389 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
390 390
391 391 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
392 392 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
393 393 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
394 394
395 395 prdata <= (OTHERS => '0');
396 396
397
398 apbo_irq_ms <= '0';
397
398 apbo_irq_ms <= '0';
399 399 apbo_irq_wfp <= '0';
400
400
401 401
402 402 -- status_full_ack <= (OTHERS => '0');
403 403
404 404 reg_wp.data_shaping_BW <= '0';
405 405 reg_wp.data_shaping_SP0 <= '0';
406 406 reg_wp.data_shaping_SP1 <= '0';
407 407 reg_wp.data_shaping_R0 <= '0';
408 408 reg_wp.data_shaping_R1 <= '0';
409 409 reg_wp.data_shaping_R2 <= '0';
410 410 reg_wp.enable_f0 <= '0';
411 411 reg_wp.enable_f1 <= '0';
412 412 reg_wp.enable_f2 <= '0';
413 413 reg_wp.enable_f3 <= '0';
414 414 reg_wp.burst_f0 <= '0';
415 415 reg_wp.burst_f1 <= '0';
416 416 reg_wp.burst_f2 <= '0';
417 417 reg_wp.run <= '0';
418 418 -- reg_wp.status_full <= (OTHERS => '0');
419 419 -- reg_wp.status_full_err <= (OTHERS => '0');
420 420 reg_wp.status_new_err <= (OTHERS => '0');
421 421 reg_wp.error_buffer_full <= (OTHERS => '0');
422 422 reg_wp.delta_snapshot <= (OTHERS => '0');
423 423 reg_wp.delta_f0 <= (OTHERS => '0');
424 424 reg_wp.delta_f0_2 <= (OTHERS => '0');
425 425 reg_wp.delta_f1 <= (OTHERS => '0');
426 426 reg_wp.delta_f2 <= (OTHERS => '0');
427 427 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
428 428 reg_wp.nb_snapshot_param <= (OTHERS => '0');
429 429 reg_wp.start_date <= (OTHERS => '1');
430
430
431 431 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
432 reg_wp.length_buffer <= (OTHERS => '0');
432 reg_wp.length_buffer <= (OTHERS => '0');
433 433
434 434 pirq_temp <= (OTHERS => '0');
435
435
436 436 reg_wp.addr_buffer_f <= (OTHERS => '0');
437
437
438 438 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
439 439
440 440 -- status_full_ack <= (OTHERS => '0');
441 441
442 442 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
443 443 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
444 444 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
445 445
446 446 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
447 447 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
448 448 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
449 449
450 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
450 all_status_ready_buffer_bit : FOR I IN 4*2-1 DOWNTO 0 LOOP
451 451 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
452 452 END LOOP all_status_ready_buffer_bit;
453 453
454 454
455 455 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
456 456 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
457 457 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
458 458 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
459 459
460 460
461 461
462 462 all_status : FOR I IN 3 DOWNTO 0 LOOP
463 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
464 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
463 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
464 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
465 465 END LOOP all_status;
466 466
467 467 paddr := "000000";
468 468 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
469 469 prdata <= (OTHERS => '0');
470 470 IF apbi.psel(pindex) = '1' THEN
471 471 -- APB DMA READ --
472 472 CASE paddr(7 DOWNTO 2) IS
473 473
474 474 WHEN ADDR_LFR_SM_CONFIG =>
475 475 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
476 476 prdata(1) <= reg_sp.config_active_interruption_onError;
477 477 prdata(2) <= reg_sp.config_ms_run;
478 478
479 479 WHEN ADDR_LFR_SM_STATUS =>
480 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
480 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
481 481 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
482 482 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
483 483 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
484 484 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
485 485 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
486 486 -- prdata(6) <= reg_sp.status_error_bad_component_error;
487 487 prdata(7) <= reg_sp.status_error_buffer_full;
488 488 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
489 489 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
490 490 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
491 491
492 492 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
493 493 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
494 494 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
495 495 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
496 496 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
497 497 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
498 498 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
499 499 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
500 500 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
501 501 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
502 502 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
503 503 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
504 504 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
505 505 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
506 506 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
507 507 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
508 508 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
509 509 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
510 510 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
511 ---------------------------------------------------------------------
512 WHEN ADDR_LFR_WP_DATASHAPING =>
511 ---------------------------------------------------------------------
512 WHEN ADDR_LFR_WP_DATASHAPING =>
513 513 prdata(0) <= reg_wp.data_shaping_BW;
514 514 prdata(1) <= reg_wp.data_shaping_SP0;
515 515 prdata(2) <= reg_wp.data_shaping_SP1;
516 516 prdata(3) <= reg_wp.data_shaping_R0;
517 517 prdata(4) <= reg_wp.data_shaping_R1;
518 518 prdata(5) <= reg_wp.data_shaping_R2;
519 519 WHEN ADDR_LFR_WP_CONTROL =>
520 520 prdata(0) <= reg_wp.enable_f0;
521 521 prdata(1) <= reg_wp.enable_f1;
522 522 prdata(2) <= reg_wp.enable_f2;
523 523 prdata(3) <= reg_wp.enable_f3;
524 524 prdata(4) <= reg_wp.burst_f0;
525 525 prdata(5) <= reg_wp.burst_f1;
526 526 prdata(6) <= reg_wp.burst_f2;
527 527 prdata(7) <= reg_wp.run;
528 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
529 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
530 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
531 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
532 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
533 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
534 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
535 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
536
528 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); --0
529 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
530 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); --1
531 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
532 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); --2
533 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
534 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); --3
535 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
536
537 537 WHEN ADDR_LFR_WP_STATUS =>
538 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
539 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
538 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
539 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
540 540 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
541 541
542 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
543 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
544 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
545 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
546 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
542 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
543 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
544 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
545 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
546 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
547 547 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
548 548 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
549 549 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
550 550
551 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
551 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
552 552 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
553 553 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
554 554 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
555
555
556 556 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
557 557 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
558 558 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
559 559 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
560
560
561 561 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
562 562 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
563 563 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
564 564 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
565
565
566 566 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
567 567 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
568 568 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
569 569 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
570 570
571 571 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
572
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
575 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
576 prdata(31 DOWNTO 16) <= (OTHERS => '0');
577 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
578 prdata(31 DOWNTO 16) <= (OTHERS => '0');
579 ---------------------------------------------------------------------
580 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
581 WHEN OTHERS => NULL;
572
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
575 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
576 prdata(31 DOWNTO 16) <= (OTHERS => '0');
577 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
578 prdata(31 DOWNTO 16) <= (OTHERS => '0');
579 ---------------------------------------------------------------------
580 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
581 WHEN OTHERS => NULL;
582 582
583 583 END CASE;
584 584 IF (apbi.pwrite AND apbi.penable) = '1' THEN
585 585 -- APB DMA WRITE --
586 586 CASE paddr(7 DOWNTO 2) IS
587 587 --
588 588 WHEN ADDR_LFR_SM_CONFIG =>
589 589 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
590 590 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
591 591 reg_sp.config_ms_run <= apbi.pwdata(2);
592
592
593 593 WHEN ADDR_LFR_SM_STATUS =>
594 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
595 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
596 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
597 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
598 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
599 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
600 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
601 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
602 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
594 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
595 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1)) AND reg_sp.status_ready_matrix_f0_1) OR reg1_ready_matrix_f0;
596 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2)) AND reg_sp.status_ready_matrix_f1_0) OR reg0_ready_matrix_f1;
597 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3)) AND reg_sp.status_ready_matrix_f1_1) OR reg1_ready_matrix_f1;
598 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4)) AND reg_sp.status_ready_matrix_f2_0) OR reg0_ready_matrix_f2;
599 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5)) AND reg_sp.status_ready_matrix_f2_1) OR reg1_ready_matrix_f2;
600 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7)) AND reg_sp.status_error_buffer_full) OR error_buffer_full;
601 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8)) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
602 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9)) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
603 603 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
604 604 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
605 605 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
606 606 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
607 607 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
608 608 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
609 609 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
610 610
611 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
612 ---------------------------------------------------------------------
611 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
612 ---------------------------------------------------------------------
613 613 WHEN ADDR_LFR_WP_DATASHAPING =>
614 614 reg_wp.data_shaping_BW <= apbi.pwdata(0);
615 615 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
616 616 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
617 617 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
618 618 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
619 619 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
620 WHEN ADDR_LFR_WP_CONTROL =>
620 WHEN ADDR_LFR_WP_CONTROL =>
621 621 reg_wp.enable_f0 <= apbi.pwdata(0);
622 622 reg_wp.enable_f1 <= apbi.pwdata(1);
623 623 reg_wp.enable_f2 <= apbi.pwdata(2);
624 624 reg_wp.enable_f3 <= apbi.pwdata(3);
625 625 reg_wp.burst_f0 <= apbi.pwdata(4);
626 626 reg_wp.burst_f1 <= apbi.pwdata(5);
627 627 reg_wp.burst_f2 <= apbi.pwdata(6);
628 628 reg_wp.run <= apbi.pwdata(7);
629 629 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
630 630 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
631 631 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
632 632 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
633 633 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
634 634 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
635 635 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
636 636 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
637 WHEN ADDR_LFR_WP_STATUS =>
638 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
639 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
637 WHEN ADDR_LFR_WP_STATUS =>
638 all_reg_wp_status_bit : FOR I IN 3 DOWNTO 0 LOOP
639 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2)) AND reg_wp.status_ready_buffer_f(I*2)) OR reg_ready_buffer_f(I*2);
640 640 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
641 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
642 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
641 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8)) AND reg_wp.error_buffer_full(I)) OR wfp_error_buffer_full(I);
642 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I);
643 643 END LOOP all_reg_wp_status_bit;
644 644
645 645 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
646 646 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
647 647 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
648 648 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
649 649 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
650 650 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
651 651 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
652 652 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
653
654 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
655 653
656 WHEN OTHERS => NULL;
654 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
655
656 WHEN OTHERS => NULL;
657 657 END CASE;
658 658 END IF;
659 659 END IF;
660 660 --apbo.pirq(pirq_ms) <=
661 pirq_temp( pirq_ms) <= apbo_irq_ms;
661 pirq_temp(pirq_ms) <= apbo_irq_ms;
662 662 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
663 663 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
664 ready_matrix_f1 OR
665 ready_matrix_f2)
666 )
667 OR
668 (reg_sp.config_active_interruption_onError AND (
664 ready_matrix_f1 OR
665 ready_matrix_f2)
666 )
667 OR
668 (reg_sp.config_active_interruption_onError AND (
669 669 -- error_bad_component_error OR
670 error_buffer_full
671 OR error_input_fifo_write(0)
672 OR error_input_fifo_write(1)
673 OR error_input_fifo_write(2))
674 ));
670 error_buffer_full
671 OR error_input_fifo_write(0)
672 OR error_input_fifo_write(1)
673 OR error_input_fifo_write(2))
674 ));
675 675 -- apbo.pirq(pirq_wfp)
676 apbo_irq_wfp<= ored_irq_wfp;
676 apbo_irq_wfp <= ored_irq_wfp;
677 677
678 678 END IF;
679 679 END PROCESS lpp_lfr_apbreg;
680 680
681 681 apbo.pirq <= pirq_temp;
682 682
683
683
684 684 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
685 685 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
686 686 -- apbo.pirq(I) <= apbo_irq_ms;
687 687 -- END GENERATE IRQ_is_PIRQ_MS;
688 688 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
689 689 -- apbo.pirq(I) <= apbo_irq_wfp;
690 690 -- END GENERATE IRQ_is_PIRQ_WFP;
691 691 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
692 692 -- apbo.pirq(I) <= '0';
693 693 -- END GENERATE IRQ_OTHERS;
694
694
695 695 --END GENERATE all_irq;
696
696
697 697
698
698
699 699 apbo.pindex <= pindex;
700 700 apbo.pconfig <= pconfig;
701 701 apbo.prdata <= prdata;
702 702
703 703 -----------------------------------------------------------------------------
704 704 -- IRQ
705 705 -----------------------------------------------------------------------------
706 706 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
707 707
708 708 PROCESS (HCLK, HRESETn)
709 709 BEGIN -- PROCESS
710 710 IF HRESETn = '0' THEN -- asynchronous reset (active low)
711 711 irq_wfp_reg <= (OTHERS => '0');
712 712 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
713 713 irq_wfp_reg <= irq_wfp_reg_s;
714 714 END IF;
715 715 END PROCESS;
716 716
717 717 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
718 718 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
719 719 END GENERATE all_irq_wfp;
720 720
721 721 irq_wfp_ZERO <= (OTHERS => '0');
722 722 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
723 723
724 724 run_ms <= reg_sp.config_ms_run;
725 725
726 726 -----------------------------------------------------------------------------
727 727 --
728 728 -----------------------------------------------------------------------------
729 729 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
730 730 PORT MAP (
731 731 clk => HCLK,
732 732 rstn => HRESETn,
733 733
734 run => '1',--reg_sp.config_ms_run,
735
734 run => '1', --reg_sp.config_ms_run,
735
736 736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
737 737 reg0_ready_matrix => reg0_ready_matrix_f0,
738 738 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
739 739 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
740 740
741 741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
742 742 reg1_ready_matrix => reg1_ready_matrix_f0,
743 743 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
744 744 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
745 745
746 746 ready_matrix => ready_matrix_f0,
747 747 status_ready_matrix => status_ready_matrix_f0,
748 748 addr_matrix => addr_matrix_f0,
749 749 matrix_time => matrix_time_f0);
750 750
751 751 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
752 752 PORT MAP (
753 753 clk => HCLK,
754 754 rstn => HRESETn,
755 755
756 run => '1',--reg_sp.config_ms_run,
756 run => '1', --reg_sp.config_ms_run,
757 757
758 758 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
759 759 reg0_ready_matrix => reg0_ready_matrix_f1,
760 760 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
761 761 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
762 762
763 763 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
764 764 reg1_ready_matrix => reg1_ready_matrix_f1,
765 765 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
766 766 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
767 767
768 768 ready_matrix => ready_matrix_f1,
769 769 status_ready_matrix => status_ready_matrix_f1,
770 770 addr_matrix => addr_matrix_f1,
771 771 matrix_time => matrix_time_f1);
772 772
773 773 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
774 774 PORT MAP (
775 775 clk => HCLK,
776 776 rstn => HRESETn,
777 777
778 run => '1',--reg_sp.config_ms_run,
778 run => '1', --reg_sp.config_ms_run,
779 779
780 780 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
781 781 reg0_ready_matrix => reg0_ready_matrix_f2,
782 782 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
783 783 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
784 784
785 785 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
786 786 reg1_ready_matrix => reg1_ready_matrix_f2,
787 787 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
788 788 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
789 789
790 790 ready_matrix => ready_matrix_f2,
791 791 status_ready_matrix => status_ready_matrix_f2,
792 792 addr_matrix => addr_matrix_f2,
793 793 matrix_time => matrix_time_f2);
794 794
795 795 -----------------------------------------------------------------------------
796 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
796 all_wfp_pointer : FOR I IN 3 DOWNTO 0 GENERATE
797 797 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
798 798 PORT MAP (
799 799 clk => HCLK,
800 800 rstn => HRESETn,
801 801
802 run => '1',--reg_wp.run,
802 run => '1', --reg_wp.run,
803 803
804 804 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
805 805 reg0_ready_matrix => reg_ready_buffer_f(2*I),
806 806 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
807 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
807 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
808 808
809 809 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
810 810 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
811 811 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
812 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
812 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
813 813
814 814 ready_matrix => wfp_ready_buffer(I),
815 815 status_ready_matrix => wfp_status_buffer_ready(I),
816 816 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
817 817 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
818 818 );
819
820 END GENERATE all_wfp_pointer;
819
820 END GENERATE all_wfp_pointer;
821 821 -----------------------------------------------------------------------------
822
822
823 823 END beh;
824 824
825 825 ------------------------------------------------------------------------------
General Comments 0
You need to be logged in to leave comments. Login now