@@ -1,21 +1,20 | |||
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1 | 1 | LIBRARY IEEE; |
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2 | 2 | USE IEEE.STD_LOGIC_1164.ALL; |
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3 | USE IEEE.std_logic_arith.ALL; | |
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4 | USE IEEE.std_logic_unsigned.ALL; | |
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3 | USE IEEE.NUMERIC_STD.ALL; | |
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5 | 4 | |
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6 | 5 | ENTITY general_counter IS |
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7 | 6 | |
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8 | 7 | GENERIC ( |
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9 | 8 | CYCLIC : STD_LOGIC := '1'; |
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10 | NB_BITS_COUNTER : INTEGER := 9 | |
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9 | NB_BITS_COUNTER : INTEGER := 9; | |
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10 | RST_VALUE : INTEGER := 0 | |
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11 | 11 | ); |
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12 | 12 | |
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13 | 13 | PORT ( |
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14 | 14 | clk : IN STD_LOGIC; |
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15 | 15 | rstn : IN STD_LOGIC; |
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16 | 16 | -- |
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17 |
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18 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); | |
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17 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); | |
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19 | 18 | -- |
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20 | 19 | set : IN STD_LOGIC; |
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21 | 20 | set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
@@ -26,20 +25,21 ENTITY general_counter IS | |||
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26 | 25 | END general_counter; |
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27 | 26 | |
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28 | 27 | ARCHITECTURE beh OF general_counter IS |
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29 | SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
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28 | CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER)); | |
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29 | SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
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30 | 30 | |
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31 | 31 | BEGIN -- beh |
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32 | 32 | |
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33 | 33 | PROCESS (clk, rstn) |
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34 | 34 | BEGIN -- PROCESS |
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35 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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36 | counter_s <= RST_VALUE; | |
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37 |
ELSIF clk' |
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35 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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36 | counter_s <= RST_VALUE_v; | |
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37 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
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38 | 38 | IF set = '1' THEN |
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39 | 39 | counter_s <= set_value; |
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40 | 40 | ELSIF add1 = '1' THEN |
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41 | 41 | IF counter_s < MAX_VALUE THEN |
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42 | counter_s <= counter_s + 1; | |
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42 | counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1)); | |
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43 | 43 | ELSE |
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44 | 44 | IF CYCLIC = '1' THEN |
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45 | 45 | counter_s <= (OTHERS => '0'); |
@@ -50,5 +50,5 BEGIN -- beh | |||
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50 | 50 | END PROCESS; |
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51 | 51 | |
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52 | 52 | counter <= counter_s; |
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53 | ||
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53 | ||
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54 | 54 | END beh; |
@@ -32,16 +32,16 USE IEEE.NUMERIC_STD.ALL; | |||
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32 | 32 | |
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33 | 33 | |
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34 | 34 | PACKAGE general_purpose IS |
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35 | ||
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35 | ||
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36 | 36 |
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37 | 37 | GENERIC ( |
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38 | 38 | CYCLIC : STD_LOGIC; |
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39 |
NB_BITS_COUNTER : INTEGER |
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39 | NB_BITS_COUNTER : INTEGER; | |
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40 | RST_VALUE : INTEGER); | |
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40 | 41 | PORT ( |
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41 | 42 | clk : IN STD_LOGIC; |
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42 | 43 | rstn : IN STD_LOGIC; |
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43 |
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44 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
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44 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
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45 | 45 | set : IN STD_LOGIC; |
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46 | 46 | set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
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47 | 47 | add1 : IN STD_LOGIC; |
@@ -48,11 +48,11 BEGIN -- beh | |||
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48 | 48 | counter_1 : general_counter |
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49 | 49 | GENERIC MAP ( |
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50 | 50 | CYCLIC => '1', |
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51 |
NB_BITS_COUNTER => 31 |
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51 | NB_BITS_COUNTER => 31, | |
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52 | RST_VALUE => 0) | |
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52 | 53 | PORT MAP ( |
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53 | 54 | clk => clk, |
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54 | 55 | rstn => rstn, |
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55 | RST_VALUE => (OTHERS => '0'), | |
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56 | 56 | MAX_VALUE => "111" & X"FFFFFFF" , |
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57 | 57 | set => set_TCU, |
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58 | 58 | set_value => set_TCU_value(30 DOWNTO 0), |
@@ -75,11 +75,12 BEGIN -- beh | |||
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75 | 75 | counter_2 : general_counter |
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76 | 76 | GENERIC MAP ( |
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77 | 77 | CYCLIC => '0', |
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78 |
NB_BITS_COUNTER => 6 |
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78 | NB_BITS_COUNTER => 6, | |
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79 | RST_VALUE => NB_SECOND_DESYNC | |
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80 | ) | |
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79 | 81 | PORT MAP ( |
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80 | 82 | clk => clk, |
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81 | 83 | rstn => rstn, |
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82 | RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), | |
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83 | 84 | MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), |
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84 | 85 | set => set_synchronized, |
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85 | 86 | set_value => set_synchronized_value, |
@@ -105,4 +106,4 BEGIN -- beh | |||
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105 | 106 | END IF; |
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106 | 107 | END PROCESS; |
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107 | 108 | |
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108 |
END beh; |
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109 | END beh; No newline at end of file |
@@ -43,11 +43,12 BEGIN -- beh | |||
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43 | 43 | counter_1 : general_counter |
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44 | 44 | GENERIC MAP ( |
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45 | 45 | CYCLIC => '1', |
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46 |
NB_BITS_COUNTER => 9 |
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46 | NB_BITS_COUNTER => 9, | |
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47 | RST_VALUE => 0 | |
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48 | ) | |
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47 | 49 | PORT MAP ( |
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48 | 50 | clk => clk, |
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49 | 51 | rstn => rstn, |
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50 | RST_VALUE => (OTHERS => '0'), | |
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51 | 52 | MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)), |
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52 | 53 | set => tick, |
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53 | 54 | set_value => (OTHERS => '0'), |
@@ -59,11 +60,12 BEGIN -- beh | |||
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59 | 60 | counter_2 : general_counter |
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60 | 61 | GENERIC MAP ( |
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61 | 62 | CYCLIC => '1', |
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62 |
NB_BITS_COUNTER => 16 |
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63 | NB_BITS_COUNTER => 16, | |
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64 | RST_VALUE => 0 | |
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65 | ) | |
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63 | 66 | PORT MAP ( |
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64 | 67 | clk => clk, |
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65 | 68 | rstn => rstn, |
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66 | RST_VALUE => (OTHERS => '0'), | |
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67 | 69 | MAX_VALUE => X"FFFF", |
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68 | 70 | set => tick, |
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69 | 71 | set_value => (OTHERS => '0'), |
@@ -90,4 +92,3 BEGIN -- beh | |||
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90 | 92 | END PROCESS; |
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91 | 93 | |
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92 | 94 | END beh; |
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93 |
@@ -44,7 +44,7 end RAM_READER; | |||
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44 | 44 | architecture Behavioral of RAM_READER is |
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45 | 45 | CONSTANT interleaved_sz : integer := dacresolution/(datawidth-dacresolution); |
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46 | 46 | |
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47 |
signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0) |
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47 | signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0);--:=(others=>'0'); | |
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48 | 48 | signal SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0'); |
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49 | 49 | signal INTERLEAVED_SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0'); |
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50 | 50 | signal SMP_CLK_R : STD_LOGIC; |
@@ -114,4 +114,4 begin | |||
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114 | 114 | end if; |
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115 | 115 | end process; |
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116 | 116 | |
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117 |
end Behavioral; |
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117 | end Behavioral; No newline at end of file |
@@ -47,7 +47,6 ARCHITECTURE behav OF SPI_DAC_DRIVER IS | |||
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47 | 47 | SIGNAL SMP_CLK_R : STD_LOGIC := '0'; |
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48 | 48 | SIGNAL shiftcnt : INTEGER := 0; |
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49 | 49 | SIGNAL shifting : STD_LOGIC := '0'; |
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50 | SIGNAL shifting_R : STD_LOGIC := '0'; | |
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51 | 50 | BEGIN |
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52 | 51 | |
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53 | 52 | |
@@ -64,11 +63,9 BEGIN | |||
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64 | 63 | PROCESS(clk, rstn) |
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65 | 64 | BEGIN |
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66 | 65 | IF rstn = '0' THEN |
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67 | -- shifting_R <= '0'; | |
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68 | 66 | SMP_CLK_R <= '0'; |
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69 | 67 | ELSIF clk'EVENT AND clk = '1' THEN |
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70 | 68 | SMP_CLK_R <= SMP_CLK; |
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71 | -- shifting_R <= shifting; | |
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72 | 69 | END IF; |
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73 | 70 | END PROCESS; |
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74 | 71 | |
@@ -104,4 +101,3 BEGIN | |||
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104 | 101 | |
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105 | 102 | END ARCHITECTURE behav; |
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106 | 103 | |
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107 |
@@ -43,7 +43,7 architecture Behavioral of dynamic_freq_ | |||
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43 | 43 | constant prescaller_reg_sz : integer := 2**PRESZ; |
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44 | 44 | constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1'); |
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45 | 45 | signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0'); |
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46 |
signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0) |
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46 | signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0'); | |
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47 | 47 | signal internal_clk : std_logic:='0'; |
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48 | 48 | signal internal_clk_reg : std_logic:='0'; |
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49 | 49 | signal clk_out_reg : std_logic:='0'; |
@@ -96,4 +96,4 elsif clk'event and clk = '1' then | |||
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96 | 96 | end if; |
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97 | 97 | end process; |
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98 | 98 | |
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99 |
end Behavioral; |
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99 | end Behavioral; No newline at end of file |
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