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Update : time counter into lfr_time_managment...
pellion -
r298:4de9ad150ab9 WaveFormPicker-0-0-E (MINI-LFR) JC
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@@ -6,6 +6,8 vcom -quiet -93 -work lpp ../../../grl
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8
8
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10
9 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
11 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
10
12
11 vcom -quiet -93 -work lpp testbench_package.vhd
13 vcom -quiet -93 -work lpp testbench_package.vhd
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@@ -44,7 +44,7 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
46
46
47 ENTITY testbenc h IS
47 ENTITY testbench IS
48 END;
48 END;
49
49
50 ARCHITECTURE behav OF testbench IS
50 ARCHITECTURE behav OF testbench IS
@@ -180,7 +180,13 ARCHITECTURE behav OF testbench IS
180
180
181 CONSTANT padtech : INTEGER := inferred;
181 CONSTANT padtech : INTEGER := inferred;
182 SIGNAL not_ramsn_0 : STD_LOGIC;
182 SIGNAL not_ramsn_0 : STD_LOGIC;
183
183
184 -----------------------------------------------------------------------------
185 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL read_buffer : STD_LOGIC;
187 -----------------------------------------------------------------------------
188 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
189 SIGNAL state_read_buffer_on_going : STD_LOGIC;
184
190
185 BEGIN
191 BEGIN
186
192
@@ -237,7 +243,7 BEGIN
237 pirq_ms => 6,
243 pirq_ms => 6,
238 pirq_wfp => 14,
244 pirq_wfp => 14,
239 hindex => 0,
245 hindex => 0,
240 top_lfr_version => X"00000001")
246 top_lfr_version => X"000001")
241 PORT MAP (
247 PORT MAP (
242 clk => clk25MHz,
248 clk => clk25MHz,
243 rstn => rstn,
249 rstn => rstn,
@@ -257,7 +263,7 BEGIN
257 ahb0 : ahbctrl -- AHB arbiter/multiplexer
263 ahb0 : ahbctrl -- AHB arbiter/multiplexer
258 GENERIC MAP (defmast => 0, split => 0,
264 GENERIC MAP (defmast => 0, split => 0,
259 rrobin => 1, ioaddr => 16#FFF#,
265 rrobin => 1, ioaddr => 16#FFF#,
260 ioen => 0, nahbm => 1, nahbs => 1)
266 ioen => 0, nahbm => 2, nahbs => 1)
261 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
267 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
262
268
263 --- AHB RAM ----------------------------------------------------------
269 --- AHB RAM ----------------------------------------------------------
@@ -347,6 +353,7 BEGIN
347 BLE_b => nSRAM_BE2,
353 BLE_b => nSRAM_BE2,
348 A => address,
354 A => address,
349 DQ => data(31 DOWNTO 16));
355 DQ => data(31 DOWNTO 16));
356
350
357
351
358
352 -----------------------------------------------------------------------------
359 -----------------------------------------------------------------------------
@@ -381,17 +388,16 BEGIN
381 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
388 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
382 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
389 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
383
390
384 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
391 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000080");--"00000020"
385 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
392 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019"
386 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
393 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
387 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
394 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
388 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
395 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000060");--"00000001"
389
396
390 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
397 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
391 --
398 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
392 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
399 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
393 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
400 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000c2");
394 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
395
401
396
402
397 WAIT UNTIL clk25MHz = '1';
403 WAIT UNTIL clk25MHz = '1';
@@ -405,23 +411,40 BEGIN
405 WAIT UNTIL clk25MHz = '1';
411 WAIT UNTIL clk25MHz = '1';
406 WAIT FOR 1 us;
412 WAIT FOR 1 us;
407 coarse_time <= X"00000001";
413 coarse_time <= X"00000001";
414
415 WAIT UNTIL clk25MHz = '1';
416
417 read_buffer <= '0';
418 while_loop: WHILE run_test_waveform_picker = '1' LOOP
419 WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1';
420 APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status);
421 IF status(2 DOWNTO 0) = "111" THEN
422 APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000");
423 read_buffer <= '1';
424 END IF;
425 WAIT UNTIL clk25MHz = '1';
426 read_buffer <= '0';
427 END LOOP while_loop;
428
429
408 ---------------------------------------------------------------------------
430 ---------------------------------------------------------------------------
409 -- RUN STEP
431 -- RUN STEP
410 WAIT FOR 200 ms;
432 WAIT FOR 20000 ms;
411 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
412 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
413 WAIT FOR 10 us;
414 WAIT UNTIL clk25MHz = '1';
415 WAIT UNTIL clk25MHz = '1';
416 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
417 WAIT UNTIL clk25MHz = '1';
418 coarse_time <= X"00000010";
419 WAIT FOR 100 ms;
420 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
421 WAIT FOR 10 us;
422 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
423 WAIT FOR 200 ms;
424 REPORT "*** END simulation ***" SEVERITY failure;
433 REPORT "*** END simulation ***" SEVERITY failure;
434 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
435 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
436 --WAIT FOR 10 us;
437 --WAIT UNTIL clk25MHz = '1';
438 --WAIT UNTIL clk25MHz = '1';
439 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
440 --WAIT UNTIL clk25MHz = '1';
441 --coarse_time <= X"00000010";
442 --WAIT FOR 100 ms;
443 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
444 --WAIT FOR 10 us;
445 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
446 --WAIT FOR 200 ms;
447 --REPORT "*** END simulation ***" SEVERITY failure;
425
448
426
449
427 WAIT;
450 WAIT;
@@ -435,9 +458,37 BEGIN
435 PROCESS (clk25MHz, rstn)
458 PROCESS (clk25MHz, rstn)
436 BEGIN -- PROCESS
459 BEGIN -- PROCESS
437 IF rstn = '0' THEN -- asynchronous reset (active low)
460 IF rstn = '0' THEN -- asynchronous reset (active low)
438
461 state_read_buffer_on_going <= '0';
439 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
462 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
463 IF read_buffer = '1' THEN
464 state_read_buffer_on_going <= '1';
465
466 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000", time_mem_f0(31 DOWNTO 0));
467 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000", time_mem_f1(31 DOWNTO 0));
468 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000", time_mem_f2(31 DOWNTO 0));
469 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000", time_mem_f3(31 DOWNTO 0));
470
471 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000004", time_mem_f0(63 DOWNTO 32));
472 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020004", time_mem_f1(63 DOWNTO 32));
473 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040004", time_mem_f2(63 DOWNTO 32));
474 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060004", time_mem_f3(63 DOWNTO 32));
475
476 current_data <= 8;
477 ELSE
478 IF state_read_buffer_on_going = '1' THEN
479 -- READ ALL DATA in memory
480 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40000000" + current_data, data_mem_f0);
481 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40020000" + current_data, data_mem_f1);
482 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40040000" + current_data, data_mem_f2);
483 AHB_READ(clk, hindex, ahbmi, ahbmo, X"40060000" + current_data, data_mem_f3);
484 IF current_data < LIMIT_DATA THEN
440
485
486 current_data <= current_data + 4;
487 ELSE
488 state_read_buffer_on_going <= '0';
489 END IF;
490 END IF;
491 END IF;
441 END IF;
492 END IF;
442 END PROCESS;
493 END PROCESS;
443 -----------------------------------------------------------------------------
494 -----------------------------------------------------------------------------
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@@ -14,7 +14,6 USE grlib.stdlib.ALL;
14
14
15 PACKAGE testbench_package IS
15 PACKAGE testbench_package IS
16
16
17
18 PROCEDURE APB_WRITE (
17 PROCEDURE APB_WRITE (
19 SIGNAL clk : IN STD_LOGIC;
18 SIGNAL clk : IN STD_LOGIC;
20 CONSTANT pindex : IN INTEGER;
19 CONSTANT pindex : IN INTEGER;
@@ -23,12 +22,29 PACKAGE testbench_package IS
23 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
24 );
23 );
25
24
25 PROCEDURE APB_READ (
26 SIGNAL clk : IN STD_LOGIC;
27 CONSTANT pindex : IN INTEGER;
28 SIGNAL apbi : OUT apb_slv_in_type;
29 SIGNAL apbo : IN apb_slv_out_type;
30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
32 );
33
34 PROCEDURE AHB_READ (
35 SIGNAL clk : IN STD_LOGIC;
36 CONSTANT hindex : IN INTEGER
37 SIGNAL ahbmi : OUT ahb_slv_in_type;
38 SIGNAL ahbmo : IN ahb_slv_out_type;
39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
41 );
42
26 END testbench_package;
43 END testbench_package;
27
44
28 PACKAGE BODY testbench_package IS
45 PACKAGE BODY testbench_package IS
29
46
30 PROCEDURE APB_WRITE (
47 PROCEDURE APB_WRITE (
31
32 SIGNAL clk : IN STD_LOGIC;
48 SIGNAL clk : IN STD_LOGIC;
33 CONSTANT pindex : IN INTEGER;
49 CONSTANT pindex : IN INTEGER;
34 SIGNAL apbi : OUT apb_slv_in_type;
50 SIGNAL apbi : OUT apb_slv_in_type;
@@ -50,4 +66,40 PACKAGE BODY testbench_package IS
50
66
51 END APB_WRITE;
67 END APB_WRITE;
52
68
69 PROCEDURE APB_READ (
70 SIGNAL clk : IN STD_LOGIC;
71 CONSTANT pindex : IN INTEGER;
72 SIGNAL apbi : OUT apb_slv_in_type;
73 SIGNAL apbo : IN apb_slv_out_type;
74 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
76 ) IS
77 BEGIN
78 apbi.psel(pindex) <= '1';
79 apbi.pwrite <= '0';
80 apbi.penable <= '1';
81 apbi.paddr <= paddr;
82 WAIT UNTIL clk = '1';
83 apbi.psel(pindex) <= '0';
84 apbi.pwrite <= '0';
85 apbi.penable <= '0';
86 apbi.paddr <= (OTHERS => '0');
87 WAIT UNTIL clk = '1';
88 prdata <= apbo.prdata;
89 END APB_READ;
90
91 PROCEDURE AHB_READ (
92 SIGNAL clk : IN STD_LOGIC;
93 CONSTANT hindex : IN INTEGER
94 SIGNAL ahbmi : OUT ahb_slv_in_type;
95 SIGNAL ahbmo : IN ahb_slv_out_type;
96 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
98 ) IS
99 BEGIN
100
101 END AHB_READ;
102
103
104
53 END testbench_package;
105 END testbench_package;
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@@ -171,6 +171,7 ARCHITECTURE beh OF MINI_LFR_top IS
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174
175
175 BEGIN -- beh
176 BEGIN -- beh
176
177
@@ -221,7 +222,7 BEGIN -- beh
221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 LED0 <= '0';
223 LED0 <= '0';
223 LED1 <= '1';
224 LED1 <= '1';
224 LED2 <= BP0;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 --IO1 <= '1';
226 --IO1 <= '1';
226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
@@ -232,7 +233,7 BEGIN -- beh
232 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
233 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
234 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= ;
236 END IF;
237 END IF;
237 END PROCESS;
238 END PROCESS;
238
239
@@ -424,7 +425,7 BEGIN -- beh
424 pirq_ms => 6,
425 pirq_ms => 6,
425 pirq_wfp => 14,
426 pirq_wfp => 14,
426 hindex => 2,
427 hindex => 2,
427 top_lfr_version => X"00000C") -- aa.bb.cc version
428 top_lfr_version => X"00000E") -- aa.bb.cc version
428 PORT MAP (
429 PORT MAP (
429 clk => clk_25,
430 clk => clk_25,
430 rstn => reset,
431 rstn => reset,
@@ -437,7 +438,8 BEGIN -- beh
437 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
438 coarse_time => coarse_time,
439 coarse_time => coarse_time,
439 fine_time => fine_time,
440 fine_time => fine_time,
440 data_shaping_BW => bias_fail_sw_sig);
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
441
443
442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
443 GENERIC MAP(
445 GENERIC MAP(
@@ -459,9 +461,9 BEGIN -- beh
459 sample => sample,
461 sample => sample,
460 sample_val => sample_val);
462 sample_val => sample_val);
461
463
462 IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
463 IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
464 IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
465
467
466 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
467 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
@@ -475,29 +477,104 BEGIN -- beh
475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
477
479
478 pio_pad_0 : iopad
480 --pio_pad_0 : iopad
479 GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
481 pio_pad_1 : iopad
483 --pio_pad_1 : iopad
482 GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
484 pio_pad_2 : iopad
486 --pio_pad_2 : iopad
485 GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
487 pio_pad_3 : iopad
489 --pio_pad_3 : iopad
488 GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
490 pio_pad_4 : iopad
492 --pio_pad_4 : iopad
491 GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
493 pio_pad_5 : iopad
495 --pio_pad_5 : iopad
494 GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
496 pio_pad_6 : iopad
498 --pio_pad_6 : iopad
497 GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
499 pio_pad_7 : iopad
501 --pio_pad_7 : iopad
500 GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
502
504
503 END beh;
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
562 IO0 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
575 END CASE;
576
577 END IF;
578 END PROCESS;
579
580 END beh; No newline at end of file
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@@ -57,7 +57,7 BEGIN
57
57
58 lpp_counter_1 : lpp_counter
58 lpp_counter_1 : lpp_counter
59 GENERIC MAP (
59 GENERIC MAP (
60 nb_wait_period => 750,
60 nb_wait_period => nb_wait_pediod,
61 nb_bit_of_data => 16)
61 nb_bit_of_data => 16)
62 PORT MAP (
62 PORT MAP (
63 clk => clk,
63 clk => clk,
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@@ -41,4 +41,6 PACKAGE apb_devices_list IS
41 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
41 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
42 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
42 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
43
43
44 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
45
44 END;
46 END;
Show file before | Show file after | Hide comments
@@ -60,46 +60,48 ENTITY lpp_lfr IS
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
63
65
64 --debug
66 --debug
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
73
75
74 -- debug FIFO_IN
76 ---- debug FIFO_IN
75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
83
85
84 --debug FIFO OUT
86 ----debug FIFO OUT
85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
93
95
94 --debug DMA IN
96 ----debug DMA IN
95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
103 );
105 );
104 END lpp_lfr;
106 END lpp_lfr;
105
107
@@ -474,39 +476,41 BEGIN
474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
476 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
475 data_f3_data_out_ren => data_f3_data_out_ren,
477 data_f3_data_out_ren => data_f3_data_out_ren,
476
478
477 -- debug SNAPSHOT_OUT
479 -------------------------------------------------------------------------
478 debug_f0_data => debug_f0_data,
480 observation_reg => observation_reg
479 debug_f0_data_valid => debug_f0_data_valid ,
481 ---- debug SNAPSHOT_OUT
480 debug_f1_data => debug_f1_data ,
482 --debug_f0_data => debug_f0_data,
481 debug_f1_data_valid => debug_f1_data_valid,
483 --debug_f0_data_valid => debug_f0_data_valid ,
482 debug_f2_data => debug_f2_data ,
484 --debug_f1_data => debug_f1_data ,
483 debug_f2_data_valid => debug_f2_data_valid ,
485 --debug_f1_data_valid => debug_f1_data_valid,
484 debug_f3_data => debug_f3_data ,
486 --debug_f2_data => debug_f2_data ,
485 debug_f3_data_valid => debug_f3_data_valid,
487 --debug_f2_data_valid => debug_f2_data_valid ,
488 --debug_f3_data => debug_f3_data ,
489 --debug_f3_data_valid => debug_f3_data_valid,
486
490
487 -- debug FIFO_IN
491 ---- debug FIFO_IN
488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
492 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
493 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
494 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
495 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
496 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
497 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
498 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
499 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
496
500
497 );
501 );
498
502
499
503
500 -----------------------------------------------------------------------------
504 -----------------------------------------------------------------------------
501 -- DEBUG -- WFP OUT
505 -- DEBUG -- WFP OUT
502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
506 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
503 debug_f0_data_fifo_out <= data_f0_data_out;
507 --debug_f0_data_fifo_out <= data_f0_data_out;
504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
508 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
505 debug_f1_data_fifo_out <= data_f1_data_out;
509 --debug_f1_data_fifo_out <= data_f1_data_out;
506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
510 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
507 debug_f2_data_fifo_out <= data_f2_data_out;
511 --debug_f2_data_fifo_out <= data_f2_data_out;
508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
512 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
509 debug_f3_data_fifo_out <= data_f3_data_out;
513 --debug_f3_data_fifo_out <= data_f3_data_out;
510 -----------------------------------------------------------------------------
514 -----------------------------------------------------------------------------
511
515
512
516
@@ -630,14 +634,14 BEGIN
630
634
631 -----------------------------------------------------------------------------
635 -----------------------------------------------------------------------------
632 -- DEBUG -- DMA IN
636 -- DEBUG -- DMA IN
633 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
637 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
634 debug_f0_data_dma_in <= dma_data;
638 --debug_f0_data_dma_in <= dma_data;
635 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
639 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
636 debug_f1_data_dma_in <= dma_data;
640 --debug_f1_data_dma_in <= dma_data;
637 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
641 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
638 debug_f2_data_dma_in <= dma_data;
642 --debug_f2_data_dma_in <= dma_data;
639 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
643 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
640 debug_f3_data_dma_in <= dma_data;
644 --debug_f3_data_dma_in <= dma_data;
641 -----------------------------------------------------------------------------
645 -----------------------------------------------------------------------------
642
646
643 -----------------------------------------------------------------------------
647 -----------------------------------------------------------------------------
Show file before | Show file after | Hide comments
@@ -100,46 +100,47 PACKAGE lpp_lfr_pkg IS
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 data_shaping_BW : OUT STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC;
103 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103
104
104 --debug
105 ----debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 --debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 --debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 --debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC;
113 --debug_f3_data_valid : OUT STD_LOGIC;
113
114
114 -- debug FIFO_IN
115 ---- debug FIFO_IN
115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123
124
124 --debug FIFO OUT
125 ----debug FIFO OUT
125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133
134
134 --debug DMA IN
135 ----debug DMA IN
135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 );
144 );
144 END COMPONENT;
145 END COMPONENT;
145
146
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This diff has been collapsed as it changes many lines, (1020 lines changed) Show them Hide them
@@ -1,495 +1,525
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
40
40
41 GENERIC (
41 GENERIC (
42 tech : INTEGER := inferred;
42 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
43 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
44 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
47 delta_vector_size : INTEGER := 20;
47 delta_vector_size : INTEGER := 20;
48 delta_vector_size_f0_2 : INTEGER := 3);
48 delta_vector_size_f0_2 : INTEGER := 3);
49
49
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53
53
54 ---- AMBA AHB Master Interface
54 ---- AMBA AHB Master Interface
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57
57
58 --config
58 --config
59 reg_run : IN STD_LOGIC;
59 reg_run : IN STD_LOGIC;
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
66
67 enable_f0 : IN STD_LOGIC;
67 enable_f0 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
71
71
72 burst_f0 : IN STD_LOGIC;
72 burst_f0 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
75
75
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 -- INPUT
84 -- INPUT
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
87
88 --f0
88 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
90 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
92 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
94 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
96 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
98 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
100 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
102 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104
104
105 ---------------------------------------------------------------------------
105 ---------------------------------------------------------------------------
106 -- OUTPUT
106 -- OUTPUT
107 --f0
107 --f0
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
110 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
113 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
116 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
119 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
122 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
125 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
128 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
131
131
132 --debug SNAPSHOT OUT
132 ---------------------------------------------------------------------------
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 --
134 debug_f0_data_valid : OUT STD_LOGIC;
134 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135
136 debug_f1_data_valid : OUT STD_LOGIC;
136
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 ----debug SNAPSHOT OUT
138 debug_f2_data_valid : OUT STD_LOGIC;
138 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 --debug_f0_data_valid : OUT STD_LOGIC;
140 debug_f3_data_valid : OUT STD_LOGIC;
140 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141
141 --debug_f1_data_valid : OUT STD_LOGIC;
142 --debug FIFO IN
142 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
143 --debug_f2_data_valid : OUT STD_LOGIC;
144 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
144 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
145 --debug_f3_data_valid : OUT STD_LOGIC;
146 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
146
147 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 ----debug FIFO IN
148 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
148 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
150 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
150 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151
151 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
152 );
152 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153
153 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
154 END lpp_waveform;
154 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
156 ARCHITECTURE beh OF lpp_waveform IS
156
157 SIGNAL start_snapshot_f0 : STD_LOGIC;
157 );
158 SIGNAL start_snapshot_f1 : STD_LOGIC;
158
159 SIGNAL start_snapshot_f2 : STD_LOGIC;
159 END lpp_waveform;
160
160
161 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
161 ARCHITECTURE beh OF lpp_waveform IS
162 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
162 SIGNAL start_snapshot_f0 : STD_LOGIC;
163 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
163 SIGNAL start_snapshot_f1 : STD_LOGIC;
164 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
164 SIGNAL start_snapshot_f2 : STD_LOGIC;
165
165
166 SIGNAL data_f0_out_valid : STD_LOGIC;
166 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
167 SIGNAL data_f1_out_valid : STD_LOGIC;
167 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
168 SIGNAL data_f2_out_valid : STD_LOGIC;
168 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 SIGNAL data_f3_out_valid : STD_LOGIC;
169 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
170
171 --
171 SIGNAL data_f0_out_valid : STD_LOGIC;
172 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL data_f1_out_valid : STD_LOGIC;
173 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL data_f2_out_valid : STD_LOGIC;
174 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 SIGNAL data_f3_out_valid : STD_LOGIC;
175 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
176 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 --
177 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 --
185 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 --
190 --
191 SIGNAL run : STD_LOGIC;
191 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 --
192 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
193 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
194 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
195 --
196 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
196 SIGNAL run : STD_LOGIC;
197 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
197 --
198 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
198 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
199 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
199 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
200 --
200 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
201
201 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
202 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
202 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
203 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
203 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
204 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 --
206
206
207 BEGIN -- beh
207 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
208
208 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
209 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 GENERIC MAP (
210 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 delta_vector_size => delta_vector_size,
211
212 delta_vector_size_f0_2 => delta_vector_size_f0_2
212 --
213 )
213
214 PORT MAP (
214 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 clk => clk,
215 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 rstn => rstn,
216
217 reg_run => reg_run,
217 BEGIN -- beh
218 reg_start_date => reg_start_date,
218
219 reg_delta_snapshot => reg_delta_snapshot,
219 -----------------------------------------------------------------------------
220 reg_delta_f0 => reg_delta_f0,
220 -- DEBUG
221 reg_delta_f0_2 => reg_delta_f0_2,
221 -----------------------------------------------------------------------------
222 reg_delta_f1 => reg_delta_f1,
222 PROCESS (clk, rstn)
223 reg_delta_f2 => reg_delta_f2,
223 BEGIN -- PROCESS
224 coarse_time => coarse_time(30 DOWNTO 0),
224 IF rstn = '0' THEN -- asynchronous reset (active low)
225 data_f0_valid => data_f0_in_valid,
225 observation_reg <= (OTHERS => '0');
226 data_f2_valid => data_f2_in_valid,
226 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
227 start_snapshot_f0 => start_snapshot_f0,
227 observation_reg <= observation_reg_s;
228 start_snapshot_f1 => start_snapshot_f1,
228 END IF;
229 start_snapshot_f2 => start_snapshot_f2,
229 END PROCESS;
230 wfp_on => run);
230 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
231
231 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
232 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
232 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
233 GENERIC MAP (
233 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
234 data_size => data_size,
234 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
235 nb_snapshot_param_size => nb_snapshot_param_size)
235 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
236 PORT MAP (
236 -----------------------------------------------------------------------------
237 clk => clk,
237
238 rstn => rstn,
238 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
239 run => run,
239 GENERIC MAP (
240 enable => enable_f0,
240 delta_vector_size => delta_vector_size,
241 burst_enable => burst_f0,
241 delta_vector_size_f0_2 => delta_vector_size_f0_2
242 nb_snapshot_param => nb_snapshot_param,
242 )
243 start_snapshot => start_snapshot_f0,
243 PORT MAP (
244 data_in => data_f0_in,
244 clk => clk,
245 data_in_valid => data_f0_in_valid,
245 rstn => rstn,
246 data_out => data_f0_out,
246 reg_run => reg_run,
247 data_out_valid => data_f0_out_valid);
247 reg_start_date => reg_start_date,
248
248 reg_delta_snapshot => reg_delta_snapshot,
249 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
249 reg_delta_f0 => reg_delta_f0,
250
250 reg_delta_f0_2 => reg_delta_f0_2,
251 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
251 reg_delta_f1 => reg_delta_f1,
252 GENERIC MAP (
252 reg_delta_f2 => reg_delta_f2,
253 data_size => data_size,
253 coarse_time => coarse_time(30 DOWNTO 0),
254 nb_snapshot_param_size => nb_snapshot_param_size+1)
254 data_f0_valid => data_f0_in_valid,
255 PORT MAP (
255 data_f2_valid => data_f2_in_valid,
256 clk => clk,
256 start_snapshot_f0 => start_snapshot_f0,
257 rstn => rstn,
257 start_snapshot_f1 => start_snapshot_f1,
258 run => run,
258 start_snapshot_f2 => start_snapshot_f2,
259 enable => enable_f1,
259 wfp_on => run);
260 burst_enable => burst_f1,
260
261 nb_snapshot_param => nb_snapshot_param_more_one,
261 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
262 start_snapshot => start_snapshot_f1,
262 GENERIC MAP (
263 data_in => data_f1_in,
263 data_size => data_size,
264 data_in_valid => data_f1_in_valid,
264 nb_snapshot_param_size => nb_snapshot_param_size)
265 data_out => data_f1_out,
265 PORT MAP (
266 data_out_valid => data_f1_out_valid);
266 clk => clk,
267
267 rstn => rstn,
268 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
268 run => run,
269 GENERIC MAP (
269 enable => enable_f0,
270 data_size => data_size,
270 burst_enable => burst_f0,
271 nb_snapshot_param_size => nb_snapshot_param_size+1)
271 nb_snapshot_param => nb_snapshot_param,
272 PORT MAP (
272 start_snapshot => start_snapshot_f0,
273 clk => clk,
273 data_in => data_f0_in,
274 rstn => rstn,
274 data_in_valid => data_f0_in_valid,
275 run => run,
275 data_out => data_f0_out,
276 enable => enable_f2,
276 data_out_valid => data_f0_out_valid);
277 burst_enable => burst_f2,
277
278 nb_snapshot_param => nb_snapshot_param_more_one,
278 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
279 start_snapshot => start_snapshot_f2,
279
280 data_in => data_f2_in,
280 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
281 data_in_valid => data_f2_in_valid,
281 GENERIC MAP (
282 data_out => data_f2_out,
282 data_size => data_size,
283 data_out_valid => data_f2_out_valid);
283 nb_snapshot_param_size => nb_snapshot_param_size+1)
284
284 PORT MAP (
285 lpp_waveform_burst_f3 : lpp_waveform_burst
285 clk => clk,
286 GENERIC MAP (
286 rstn => rstn,
287 data_size => data_size)
287 run => run,
288 PORT MAP (
288 enable => enable_f1,
289 clk => clk,
289 burst_enable => burst_f1,
290 rstn => rstn,
290 nb_snapshot_param => nb_snapshot_param_more_one,
291 run => run,
291 start_snapshot => start_snapshot_f1,
292 enable => enable_f3,
292 data_in => data_f1_in,
293 data_in => data_f3_in,
293 data_in_valid => data_f1_in_valid,
294 data_in_valid => data_f3_in_valid,
294 data_out => data_f1_out,
295 data_out => data_f3_out,
295 data_out_valid => data_f1_out_valid);
296 data_out_valid => data_f3_out_valid);
296
297
297 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
298 -----------------------------------------------------------------------------
298 GENERIC MAP (
299 -- DEBUG -- SNAPSHOT OUT
299 data_size => data_size,
300 debug_f0_data_valid <= data_f0_out_valid;
300 nb_snapshot_param_size => nb_snapshot_param_size+1)
301 debug_f0_data <= data_f0_out;
301 PORT MAP (
302 debug_f1_data_valid <= data_f1_out_valid;
302 clk => clk,
303 debug_f1_data <= data_f1_out;
303 rstn => rstn,
304 debug_f2_data_valid <= data_f2_out_valid;
304 run => run,
305 debug_f2_data <= data_f2_out;
305 enable => enable_f2,
306 debug_f3_data_valid <= data_f3_out_valid;
306 burst_enable => burst_f2,
307 debug_f3_data <= data_f3_out;
307 nb_snapshot_param => nb_snapshot_param_more_one,
308 -----------------------------------------------------------------------------
308 start_snapshot => start_snapshot_f2,
309
309 data_in => data_f2_in,
310 PROCESS (clk, rstn)
310 data_in_valid => data_f2_in_valid,
311 BEGIN -- PROCESS
311 data_out => data_f2_out,
312 IF rstn = '0' THEN -- asynchronous reset (active low)
312 data_out_valid => data_f2_out_valid);
313 time_reg1 <= (OTHERS => '0');
313
314 time_reg2 <= (OTHERS => '0');
314 lpp_waveform_burst_f3 : lpp_waveform_burst
315 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
315 GENERIC MAP (
316 time_reg1 <= fine_time & coarse_time;
316 data_size => data_size)
317 time_reg2 <= time_reg1;
317 PORT MAP (
318 END IF;
318 clk => clk,
319 END PROCESS;
319 rstn => rstn,
320
320 run => run,
321 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
321 enable => enable_f3,
322 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
322 data_in => data_f3_in,
323 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
323 data_in_valid => data_f3_in_valid,
324 PORT MAP (
324 data_out => data_f3_out,
325 HCLK => clk,
325 data_out_valid => data_f3_out_valid);
326 HRESETn => rstn,
326
327 run => run,
327 -----------------------------------------------------------------------------
328 valid_in => valid_in(I),
328 -- DEBUG -- SNAPSHOT OUT
329 ack_in => valid_ack(I),
329 --debug_f0_data_valid <= data_f0_out_valid;
330 time_in => time_reg2, -- Todo
330 --debug_f0_data <= data_f0_out;
331 valid_out => valid_out(I),
331 --debug_f1_data_valid <= data_f1_out_valid;
332 time_out => time_out(I), -- Todo
332 --debug_f1_data <= data_f1_out;
333 error => status_new_err(I));
333 --debug_f2_data_valid <= data_f2_out_valid;
334 END GENERATE all_input_valid;
334 --debug_f2_data <= data_f2_out;
335
335 --debug_f3_data_valid <= data_f3_out_valid;
336 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
336 --debug_f3_data <= data_f3_out;
337 data_out(0, I) <= data_f0_out(I);
337 -----------------------------------------------------------------------------
338 data_out(1, I) <= data_f1_out(I);
338
339 data_out(2, I) <= data_f2_out(I);
339 PROCESS (clk, rstn)
340 data_out(3, I) <= data_f3_out(I);
340 BEGIN -- PROCESS
341 END GENERATE all_bit_of_data_out;
341 IF rstn = '0' THEN -- asynchronous reset (active low)
342
342 time_reg1 <= (OTHERS => '0');
343 -----------------------------------------------------------------------------
343 time_reg2 <= (OTHERS => '0');
344 -- TODO : debug
344 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
345 -----------------------------------------------------------------------------
345 time_reg1 <= fine_time & coarse_time;
346 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
346 time_reg2 <= time_reg1;
347 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
347 END IF;
348 time_out_2(J, I) <= time_out(J)(I);
348 END PROCESS;
349 END GENERATE all_sample_of_time_out;
349
350 END GENERATE all_bit_of_time_out;
350 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
351
351 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
352 -- DEBUG --
352 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
353 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
353 PORT MAP (
354 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
354 HCLK => clk,
355 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
355 HRESETn => rstn,
356 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
356 run => run,
357
357 valid_in => valid_in(I),
358 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
358 ack_in => valid_ack(I),
359 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
359 time_in => time_reg2, -- Todo
360 -- time_out_2(J, I) <= time_out_debug(J)(I);
360 valid_out => valid_out(I),
361 -- END GENERATE all_sample_of_time_out;
361 time_out => time_out(I), -- Todo
362 --END GENERATE all_bit_of_time_out;
362 error => status_new_err(I));
363 -- DEBUG --
363 END GENERATE all_input_valid;
364
364
365 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
365 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
366 GENERIC MAP (tech => tech,
366 data_out(0, I) <= data_f0_out(I);
367 nb_data_by_buffer_size => nb_data_by_buffer_size)
367 data_out(1, I) <= data_f1_out(I);
368 PORT MAP (
368 data_out(2, I) <= data_f2_out(I);
369 clk => clk,
369 data_out(3, I) <= data_f3_out(I);
370 rstn => rstn,
370 END GENERATE all_bit_of_data_out;
371 run => run,
371
372 nb_data_by_buffer => nb_data_by_buffer,
372 -----------------------------------------------------------------------------
373 data_in_valid => valid_out,
373 -- TODO : debug
374 data_in_ack => valid_ack,
374 -----------------------------------------------------------------------------
375 data_in => data_out,
375 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
376 time_in => time_out_2,
376 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
377
377 time_out_2(J, I) <= time_out(J)(I);
378 data_out => wdata,
378 END GENERATE all_sample_of_time_out;
379 data_out_wen => data_wen,
379 END GENERATE all_bit_of_time_out;
380 full_almost => full_almost,
380
381 full => full);
381 -- DEBUG --
382
382 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
383 -----------------------------------------------------------------------------
383 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
384 -- DEBUG -- SNAPSHOT IN
384 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
385 debug_f0_data_fifo_in_valid <= NOT data_wen(0);
385 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
386 debug_f0_data_fifo_in <= wdata;
386
387 debug_f1_data_fifo_in_valid <= NOT data_wen(1);
387 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
388 debug_f1_data_fifo_in <= wdata;
388 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
389 debug_f2_data_fifo_in_valid <= NOT data_wen(2);
389 -- time_out_2(J, I) <= time_out_debug(J)(I);
390 debug_f2_data_fifo_in <= wdata;
390 -- END GENERATE all_sample_of_time_out;
391 debug_f3_data_fifo_in_valid <= NOT data_wen(3);
391 --END GENERATE all_bit_of_time_out;
392 debug_f3_data_fifo_in <= wdata;
392 -- DEBUG --
393 -----------------------------------------------------------------------------
393
394
394 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
395 lpp_waveform_fifo_1 : lpp_waveform_fifo
395 GENERIC MAP (tech => tech,
396 GENERIC MAP (tech => tech)
396 nb_data_by_buffer_size => nb_data_by_buffer_size)
397 PORT MAP (
397 PORT MAP (
398 clk => clk,
398 clk => clk,
399 rstn => rstn,
399 rstn => rstn,
400 run => run,
400 run => run,
401
401 nb_data_by_buffer => nb_data_by_buffer,
402 empty => s_empty,
402 data_in_valid => valid_out,
403 empty_almost => s_empty_almost,
403 data_in_ack => valid_ack,
404 data_ren => s_data_ren,
404 data_in => data_out,
405 rdata => s_rdata,
405 time_in => time_out_2,
406
406
407
407 data_out => wdata,
408 full_almost => full_almost,
408 data_out_wen => data_wen,
409 full => full,
409 full_almost => full_almost,
410 data_wen => data_wen,
410 full => full);
411 wdata => wdata);
411
412
412 -----------------------------------------------------------------------------
413 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
413 -- DEBUG -- SNAPSHOT IN
414 GENERIC MAP (tech => tech)
414 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
415 PORT MAP (
415 --debug_f0_data_fifo_in <= wdata;
416 clk => clk,
416 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
417 rstn => rstn,
417 --debug_f1_data_fifo_in <= wdata;
418 run => run,
418 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
419 o_empty_almost => empty_almost,
419 --debug_f2_data_fifo_in <= wdata;
420 o_empty => empty,
420 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
421
421 --debug_f3_data_fifo_in <= wdata;s
422 o_data_ren => data_ren,
422 -----------------------------------------------------------------------------
423 o_rdata_0 => data_f0_data_out,
423
424 o_rdata_1 => data_f1_data_out,
424 lpp_waveform_fifo_1 : lpp_waveform_fifo
425 o_rdata_2 => data_f2_data_out,
425 GENERIC MAP (tech => tech)
426 o_rdata_3 => data_f3_data_out,
426 PORT MAP (
427
427 clk => clk,
428 i_empty_almost => s_empty_almost,
428 rstn => rstn,
429 i_empty => s_empty,
429 run => run,
430 i_data_ren => s_data_ren,
430
431 i_rdata => s_rdata);
431 empty => s_empty,
432
432 empty_almost => s_empty_almost,
433
433 data_ren => s_data_ren,
434 --data_f0_data_out <= rdata;
434 rdata => s_rdata,
435 --data_f1_data_out <= rdata;
435
436 --data_f2_data_out <= rdata;
436
437 --data_f3_data_out <= rdata;
437 full_almost => full_almost,
438
438 full => full,
439 data_ren <= data_f3_data_out_ren &
439 data_wen => data_wen,
440 data_f2_data_out_ren &
440 wdata => wdata);
441 data_f1_data_out_ren &
441
442 data_f0_data_out_ren;
442 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
443
443 GENERIC MAP (tech => tech)
444 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
444 PORT MAP (
445 GENERIC MAP (
445 clk => clk,
446 nb_data_by_buffer_size => nb_word_by_buffer_size)
446 rstn => rstn,
447 PORT MAP (
447 run => run,
448 clk => clk,
448 o_empty_almost => empty_almost,
449 rstn => rstn,
449 o_empty => empty,
450 run => run,
450
451
451 o_data_ren => data_ren,
452 -------------------------------------------------------------------------
452 o_rdata_0 => data_f0_data_out,
453 -- CONFIG
453 o_rdata_1 => data_f1_data_out,
454 -------------------------------------------------------------------------
454 o_rdata_2 => data_f2_data_out,
455 nb_data_by_buffer => nb_word_by_buffer,
455 o_rdata_3 => data_f3_data_out,
456
456
457 addr_data_f0 => addr_data_f0,
457 i_empty_almost => s_empty_almost,
458 addr_data_f1 => addr_data_f1,
458 i_empty => s_empty,
459 addr_data_f2 => addr_data_f2,
459 i_data_ren => s_data_ren,
460 addr_data_f3 => addr_data_f3,
460 i_rdata => s_rdata);
461 -------------------------------------------------------------------------
461
462 -- CTRL
462
463 -------------------------------------------------------------------------
463 --data_f0_data_out <= rdata;
464 -- IN
464 --data_f1_data_out <= rdata;
465 empty => empty,
465 --data_f2_data_out <= rdata;
466 empty_almost => empty_almost,
466 --data_f3_data_out <= rdata;
467 data_ren => data_ren,
467
468
468 data_ren <= data_f3_data_out_ren &
469 -------------------------------------------------------------------------
469 data_f2_data_out_ren &
470 -- STATUS
470 data_f1_data_out_ren &
471 -------------------------------------------------------------------------
471 data_f0_data_out_ren;
472 status_full => status_full,
472
473 status_full_ack => status_full_ack,
473 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
474 status_full_err => status_full_err,
474 GENERIC MAP (
475
475 nb_data_by_buffer_size => nb_word_by_buffer_size)
476 -------------------------------------------------------------------------
476 PORT MAP (
477 -- ADDR DATA OUT
477 clk => clk,
478 -------------------------------------------------------------------------
478 rstn => rstn,
479 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
479 run => run,
480 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
480
481 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
481 -------------------------------------------------------------------------
482 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
482 -- CONFIG
483
483 -------------------------------------------------------------------------
484 data_f0_data_out_valid => data_f0_data_out_valid,
484 nb_data_by_buffer => nb_word_by_buffer,
485 data_f1_data_out_valid => data_f1_data_out_valid,
485
486 data_f2_data_out_valid => data_f2_data_out_valid,
486 addr_data_f0 => addr_data_f0,
487 data_f3_data_out_valid => data_f3_data_out_valid,
487 addr_data_f1 => addr_data_f1,
488
488 addr_data_f2 => addr_data_f2,
489 data_f0_addr_out => data_f0_addr_out,
489 addr_data_f3 => addr_data_f3,
490 data_f1_addr_out => data_f1_addr_out,
490 -------------------------------------------------------------------------
491 data_f2_addr_out => data_f2_addr_out,
491 -- CTRL
492 data_f3_addr_out => data_f3_addr_out
492 -------------------------------------------------------------------------
493 );
493 -- IN
494
494 empty => empty,
495 END beh;
495 empty_almost => empty_almost,
496 data_ren => data_ren,
497
498 -------------------------------------------------------------------------
499 -- STATUS
500 -------------------------------------------------------------------------
501 status_full => status_full_s,
502 status_full_ack => status_full_ack,
503 status_full_err => status_full_err,
504
505 -------------------------------------------------------------------------
506 -- ADDR DATA OUT
507 -------------------------------------------------------------------------
508 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
509 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
510 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
511 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
512
513 data_f0_data_out_valid => data_f0_data_out_valid,
514 data_f1_data_out_valid => data_f1_data_out_valid,
515 data_f2_data_out_valid => data_f2_data_out_valid,
516 data_f3_data_out_valid => data_f3_data_out_valid,
517
518 data_f0_addr_out => data_f0_addr_out,
519 data_f1_addr_out => data_f1_addr_out,
520 data_f2_addr_out => data_f2_addr_out,
521 data_f3_addr_out => data_f3_addr_out
522 );
523 status_full <= status_full_s;
524
525 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -169,24 +169,25 PACKAGE lpp_waveform_pkg IS
169 data_f3_data_out_ren : IN STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
170
170
171 --debug
171 --debug
172 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
173 debug_f0_data_valid : OUT STD_LOGIC;
173 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 --debug_f0_data_valid : OUT STD_LOGIC;
175 debug_f1_data_valid : OUT STD_LOGIC;
175 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 --debug_f1_data_valid : OUT STD_LOGIC;
177 debug_f2_data_valid : OUT STD_LOGIC;
177 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
178 --debug_f2_data_valid : OUT STD_LOGIC;
179 debug_f3_data_valid : OUT STD_LOGIC;
179 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
180 --debug_f3_data_valid : OUT STD_LOGIC;
180
181
181 --debug FIFO IN
182 ----debug FIFO IN
182 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
184 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
184 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
186 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
186 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
188 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
188 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
190 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
190 );
191 );
191 END COMPONENT;
192 END COMPONENT;
192
193
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