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MINI-LFR 0.1.23 => LFR-EM 1.1.23
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r396:4bab7e93fe00 (LFR-EM) WFP_MS_1-1-23 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL sample_val : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
140 SIGNAL rstn : STD_LOGIC;
141 BEGIN -- beh
141 BEGIN -- beh
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- CLK
144 -- CLK
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
147
147
148 PROCESS(clk100MHz)
148 PROCESS(clk100MHz)
149 BEGIN
149 BEGIN
150 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
151 clk_50_s <= NOT clk_50_s;
151 clk_50_s <= NOT clk_50_s;
152 END IF;
152 END IF;
153 END PROCESS;
153 END PROCESS;
154
154
155 PROCESS(clk_50_s)
155 PROCESS(clk_50_s)
156 BEGIN
156 BEGIN
157 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
158 clk_25 <= NOT clk_25;
158 clk_25 <= NOT clk_25;
159 END IF;
159 END IF;
160 END PROCESS;
160 END PROCESS;
161
161
162 PROCESS(clk49_152MHz)
162 PROCESS(clk49_152MHz)
163 BEGIN
163 BEGIN
164 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
165 clk_24 <= NOT clk_24;
165 clk_24 <= NOT clk_24;
166 END IF;
166 END IF;
167 END PROCESS;
167 END PROCESS;
168
168
169 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
170
170
171 PROCESS (clk_25, rstn)
171 PROCESS (clk_25, rstn)
172 BEGIN -- PROCESS
172 BEGIN -- PROCESS
173 IF rstn = '0' THEN -- asynchronous reset (active low)
173 IF rstn = '0' THEN -- asynchronous reset (active low)
174 led(0) <= '0';
174 led(0) <= '0';
175 led(1) <= '0';
175 led(1) <= '0';
176 led(2) <= '0';
176 led(2) <= '0';
177 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
178 led(0) <= '0';
178 led(0) <= '0';
179 led(1) <= '1';
179 led(1) <= '1';
180 led(2) <= '1';
180 led(2) <= '1';
181 END IF;
181 END IF;
182 END PROCESS;
182 END PROCESS;
183
183
184 --
184 --
185 leon3_soc_1 : leon3_soc
185 leon3_soc_1 : leon3_soc
186 GENERIC MAP (
186 GENERIC MAP (
187 fabtech => apa3e,
187 fabtech => apa3e,
188 memtech => apa3e,
188 memtech => apa3e,
189 padtech => inferred,
189 padtech => inferred,
190 clktech => inferred,
190 clktech => inferred,
191 disas => 0,
191 disas => 0,
192 dbguart => 0,
192 dbguart => 0,
193 pclow => 2,
193 pclow => 2,
194 clk_freq => 25000,
194 clk_freq => 25000,
195 NB_CPU => 1,
195 NB_CPU => 1,
196 ENABLE_FPU => 1,
196 ENABLE_FPU => 1,
197 FPU_NETLIST => 0,
197 FPU_NETLIST => 0,
198 ENABLE_DSU => 1,
198 ENABLE_DSU => 1,
199 ENABLE_AHB_UART => 1,
199 ENABLE_AHB_UART => 1,
200 ENABLE_APB_UART => 1,
200 ENABLE_APB_UART => 1,
201 ENABLE_IRQMP => 1,
201 ENABLE_IRQMP => 1,
202 ENABLE_GPT => 1,
202 ENABLE_GPT => 1,
203 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_MASTER => NB_AHB_MASTER,
204 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_AHB_SLAVE => NB_AHB_SLAVE,
205 NB_APB_SLAVE => NB_APB_SLAVE)
205 NB_APB_SLAVE => NB_APB_SLAVE)
206 PORT MAP (
206 PORT MAP (
207 clk => clk_25,
207 clk => clk_25,
208 reset => rstn,
208 reset => rstn,
209 errorn => OPEN,
209 errorn => OPEN,
210
210
211 ahbrxd => TAG1,
211 ahbrxd => TAG1,
212 ahbtxd => TAG3,
212 ahbtxd => TAG3,
213 urxd1 => TAG2,
213 urxd1 => TAG2,
214 utxd1 => TAG4,
214 utxd1 => TAG4,
215
215
216 address => address,
216 address => address,
217 data => data,
217 data => data,
218 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE0 => nSRAM_BE0,
219 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE1 => nSRAM_BE1,
220 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE2 => nSRAM_BE2,
221 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_BE3 => nSRAM_BE3,
222 nSRAM_WE => nSRAM_WE,
222 nSRAM_WE => nSRAM_WE,
223 nSRAM_CE => nSRAM_CE,
223 nSRAM_CE => nSRAM_CE,
224 nSRAM_OE => nSRAM_OE,
224 nSRAM_OE => nSRAM_OE,
225
225
226 apbi_ext => apbi_ext,
226 apbi_ext => apbi_ext,
227 apbo_ext => apbo_ext,
227 apbo_ext => apbo_ext,
228 ahbi_s_ext => ahbi_s_ext,
228 ahbi_s_ext => ahbi_s_ext,
229 ahbo_s_ext => ahbo_s_ext,
229 ahbo_s_ext => ahbo_s_ext,
230 ahbi_m_ext => ahbi_m_ext,
230 ahbi_m_ext => ahbi_m_ext,
231 ahbo_m_ext => ahbo_m_ext);
231 ahbo_m_ext => ahbo_m_ext);
232
232
233
233
234 -------------------------------------------------------------------------------
234 -------------------------------------------------------------------------------
235 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
236 -------------------------------------------------------------------------------
236 -------------------------------------------------------------------------------
237 apb_lfr_time_management_1 : apb_lfr_time_management
237 apb_lfr_time_management_1 : apb_lfr_time_management
238 GENERIC MAP (
238 GENERIC MAP (
239 pindex => 6,
239 pindex => 6,
240 paddr => 6,
240 paddr => 6,
241 pmask => 16#fff#,
241 pmask => 16#fff#,
242 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
243 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
244 PORT MAP (
244 PORT MAP (
245 clk25MHz => clk_25,
245 clk25MHz => clk_25,
246 clk24_576MHz => clk_24, -- 49.152MHz/2
246 clk24_576MHz => clk_24, -- 49.152MHz/2
247 resetn => rstn,
247 resetn => rstn,
248 grspw_tick => swno.tickout,
248 grspw_tick => swno.tickout,
249 apbi => apbi_ext,
249 apbi => apbi_ext,
250 apbo => apbo_ext(6),
250 apbo => apbo_ext(6),
251 coarse_time => coarse_time,
251 coarse_time => coarse_time,
252 fine_time => fine_time);
252 fine_time => fine_time);
253
253
254 -----------------------------------------------------------------------
254 -----------------------------------------------------------------------
255 --- SpaceWire --------------------------------------------------------
255 --- SpaceWire --------------------------------------------------------
256 -----------------------------------------------------------------------
256 -----------------------------------------------------------------------
257
257
258 -- SPW_EN <= '1';
258 -- SPW_EN <= '1';
259
259
260 spw_clk <= clk_50_s;
260 spw_clk <= clk_50_s;
261 spw_rxtxclk <= spw_clk;
261 spw_rxtxclk <= spw_clk;
262 spw_rxclkn <= NOT spw_rxtxclk;
262 spw_rxclkn <= NOT spw_rxtxclk;
263
263
264 -- PADS for SPW1
264 -- PADS for SPW1
265 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
266 PORT MAP (spw1_din, dtmp(0));
266 PORT MAP (spw1_din, dtmp(0));
267 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
268 PORT MAP (spw1_sin, stmp(0));
268 PORT MAP (spw1_sin, stmp(0));
269 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
270 PORT MAP (spw1_dout, swno.d(0));
270 PORT MAP (spw1_dout, swno.d(0));
271 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
272 PORT MAP (spw1_sout, swno.s(0));
272 PORT MAP (spw1_sout, swno.s(0));
273 -- PADS FOR SPW2
273 -- PADS FOR SPW2
274 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
275 PORT MAP (spw2_sin, dtmp(1));
275 PORT MAP (spw2_sin, dtmp(1));
276 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
277 PORT MAP (spw2_din, stmp(1));
277 PORT MAP (spw2_din, stmp(1));
278 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
279 PORT MAP (spw2_dout, swno.d(1));
279 PORT MAP (spw2_dout, swno.d(1));
280 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
281 PORT MAP (spw2_sout, swno.s(1));
281 PORT MAP (spw2_sout, swno.s(1));
282
282
283 -- GRSPW PHY
283 -- GRSPW PHY
284 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 --spw1_input: if CFG_SPW_GRSPW = 1 generate
285 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_inputloop : FOR j IN 0 TO 1 GENERATE
286 spw_phy0 : grspw_phy
286 spw_phy0 : grspw_phy
287 GENERIC MAP(
287 GENERIC MAP(
288 tech => apa3e,
288 tech => apa3e,
289 rxclkbuftype => 1,
289 rxclkbuftype => 1,
290 scantest => 0)
290 scantest => 0)
291 PORT MAP(
291 PORT MAP(
292 rxrst => swno.rxrst,
292 rxrst => swno.rxrst,
293 di => dtmp(j),
293 di => dtmp(j),
294 si => stmp(j),
294 si => stmp(j),
295 rxclko => spw_rxclk(j),
295 rxclko => spw_rxclk(j),
296 do => swni.d(j),
296 do => swni.d(j),
297 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 ndo => swni.nd(j*5+4 DOWNTO j*5),
298 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
299 END GENERATE spw_inputloop;
299 END GENERATE spw_inputloop;
300
300
301 -- SPW core
301 -- SPW core
302 sw0 : grspwm GENERIC MAP(
302 sw0 : grspwm GENERIC MAP(
303 tech => apa3e,
303 tech => apa3e,
304 hindex => 1,
304 hindex => 1,
305 pindex => 5,
305 pindex => 5,
306 paddr => 5,
306 paddr => 5,
307 pirq => 11,
307 pirq => 11,
308 sysfreq => 25000, -- CPU_FREQ
308 sysfreq => 25000, -- CPU_FREQ
309 rmap => 1,
309 rmap => 1,
310 rmapcrc => 1,
310 rmapcrc => 1,
311 fifosize1 => 16,
311 fifosize1 => 16,
312 fifosize2 => 16,
312 fifosize2 => 16,
313 rxclkbuftype => 1,
313 rxclkbuftype => 1,
314 rxunaligned => 0,
314 rxunaligned => 0,
315 rmapbufs => 4,
315 rmapbufs => 4,
316 ft => 0,
316 ft => 0,
317 netlist => 0,
317 netlist => 0,
318 ports => 2,
318 ports => 2,
319 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
320 memtech => apa3e,
320 memtech => apa3e,
321 destkey => 2,
321 destkey => 2,
322 spwcore => 1
322 spwcore => 1
323 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
324 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
325 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
326 )
326 )
327 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 PORT MAP(rstn, clk_25, spw_rxclk(0),
328 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
329 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
330 swni, swno);
330 swni, swno);
331
331
332 swni.tickin <= '0';
332 swni.tickin <= '0';
333 swni.rmapen <= '1';
333 swni.rmapen <= '1';
334 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
335 swni.tickinraw <= '0';
335 swni.tickinraw <= '0';
336 swni.timein <= (OTHERS => '0');
336 swni.timein <= (OTHERS => '0');
337 swni.dcrstval <= (OTHERS => '0');
337 swni.dcrstval <= (OTHERS => '0');
338 swni.timerrstval <= (OTHERS => '0');
338 swni.timerrstval <= (OTHERS => '0');
339
339
340 -------------------------------------------------------------------------------
340 -------------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
343 lpp_lfr_1 : lpp_lfr
343 lpp_lfr_1 : lpp_lfr
344 GENERIC MAP (
344 GENERIC MAP (
345 Mem_use => use_RAM,
345 Mem_use => use_RAM,
346 nb_data_by_buffer_size => 32,
346 nb_data_by_buffer_size => 32,
347 nb_word_by_buffer_size => 30,
347 nb_word_by_buffer_size => 30,
348 nb_snapshot_param_size => 32,
348 nb_snapshot_param_size => 32,
349 delta_vector_size => 32,
349 delta_vector_size => 32,
350 delta_vector_size_f0_2 => 7, -- log2(96)
350 delta_vector_size_f0_2 => 7, -- log2(96)
351 pindex => 15,
351 pindex => 15,
352 paddr => 15,
352 paddr => 15,
353 pmask => 16#fff#,
353 pmask => 16#fff#,
354 pirq_ms => 6,
354 pirq_ms => 6,
355 pirq_wfp => 14,
355 pirq_wfp => 14,
356 hindex => 2,
356 hindex => 2,
357 top_lfr_version => X"010110") -- aa.bb.cc version
357 top_lfr_version => X"010117") -- aa.bb.cc version
358 -- AA : BOARD NUMBER
358 -- AA : BOARD NUMBER
359 -- 0 => MINI_LFR
359 -- 0 => MINI_LFR
360 -- 1 => EM
360 -- 1 => EM
361 PORT MAP (
361 PORT MAP (
362 clk => clk_25,
362 clk => clk_25,
363 rstn => rstn,
363 rstn => rstn,
364 sample_B => sample_s(2 DOWNTO 0),
364 sample_B => sample_s(2 DOWNTO 0),
365 sample_E => sample_s(7 DOWNTO 3),
365 sample_E => sample_s(7 DOWNTO 3),
366 sample_val => sample_val,
366 sample_val => sample_val,
367 apbi => apbi_ext,
367 apbi => apbi_ext,
368 apbo => apbo_ext(15),
368 apbo => apbo_ext(15),
369 ahbi => ahbi_m_ext,
369 ahbi => ahbi_m_ext,
370 ahbo => ahbo_m_ext(2),
370 ahbo => ahbo_m_ext(2),
371 coarse_time => coarse_time,
371 coarse_time => coarse_time,
372 fine_time => fine_time,
372 fine_time => fine_time,
373 data_shaping_BW => bias_fail_sw,
373 data_shaping_BW => bias_fail_sw,
374 observation_reg => observation_reg);
374 observation_reg => observation_reg);
375
375
376
376
377 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
377 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
378 sample_s(I) <= sample(I) & '0' & '0';
378 sample_s(I) <= sample(I) & '0' & '0';
379 END GENERATE all_sample;
379 END GENERATE all_sample;
380
380
381 -----------------------------------------------------------------------------
381 -----------------------------------------------------------------------------
382 --
382 --
383 -----------------------------------------------------------------------------
383 -----------------------------------------------------------------------------
384 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
384 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
385 GENERIC MAP (
385 GENERIC MAP (
386 ChanelCount => 8,
386 ChanelCount => 8,
387 ncycle_cnv_high => 40, -- TODO : 79
387 ncycle_cnv_high => 40, -- TODO : 79
388 ncycle_cnv => 250) -- TODO : 500
388 ncycle_cnv => 250) -- TODO : 500
389 PORT MAP (
389 PORT MAP (
390 cnv_clk => clk_24, -- TODO : 49.152
390 cnv_clk => clk_24, -- TODO : 49.152
391 cnv_rstn => rstn, -- ok
391 cnv_rstn => rstn, -- ok
392 cnv => ADC_smpclk, -- ok
392 cnv => ADC_smpclk, -- ok
393 clk => clk_25, -- ok
393 clk => clk_25, -- ok
394 rstn => rstn, -- ok
394 rstn => rstn, -- ok
395 ADC_data => ADC_data, -- ok
395 ADC_data => ADC_data, -- ok
396 ADC_nOE => ADC_OEB_bar_CH, -- ok
396 ADC_nOE => ADC_OEB_bar_CH, -- ok
397 sample => sample, -- ok
397 sample => sample, -- ok
398 sample_val => sample_val); -- ok
398 sample_val => sample_val); -- ok
399
399
400 TAG8 <= ADC_smpclk;
400 TAG8 <= ADC_smpclk;
401
401
402 END beh;
402 END beh;
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