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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity ReadFifo_GEN is
27 port(
28 clk,raz : in std_logic; --! Horloge et Reset du composant
29 SYNC : in std_logic;
30 Readn : out std_logic
31 );
32 end entity;
33
34
35 architecture ar_ReadFifo_GEN of ReadFifo_GEN is
36
37 type etat is (eX,e0);
38 signal ect : etat;
39
40 signal SYNC_reg : std_logic;
41
42 begin
43 process(clk,raz)
44 begin
45 if(raz='0')then
46 ect <= eX;
47 Readn <= '1';
48
49 elsif(clk'event and clk='1')then
50 SYNC_reg <= SYNC;
51
52 case ect is
53 when eX =>
54 if (SYNC_reg='0' and SYNC='1') then
55 Readn <= '0';
56 ect <= e0;
57 end if;
58
59 when e0 =>
60 Readn <= '1';
61 ect <= eX;
62
63 end case;
64 end if;
65 end process;
66
67 end architecture; No newline at end of file
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@@ -0,0 +1,53
1 -- Bridge.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity Bridge is
7 port(
8 clk : in std_logic;
9 raz : in std_logic;
10 EmptyUp : in std_logic;
11 FullDwn : in std_logic;
12 WriteDwn : out std_logic;
13 ReadUp : out std_logic
14 );
15 end entity;
16
17
18 architecture ar_Bridge of Bridge is
19
20 type etat is (e0,e1);
21 signal ect : etat;
22
23 begin
24
25 process(clk,raz)
26 begin
27 if(raz='0')then
28 WriteDwn <= '1';
29 ReadUp <= '1';
30 ect <= e0;
31
32 elsif(clk'event and clk='1')then
33
34 case ect is
35
36 when e0 =>
37 WriteDwn <= '1';
38 if(EmptyUp='0' and FullDwn='0')then
39 ReadUp <= '0';
40 ect <= e1;
41 end if;
42
43 when e1 =>
44 ReadUp <= '1';
45 WriteDwn <= '0';
46 ect <= e0;
47
48 end case;
49
50 end if;
51 end process;
52
53 end architecture; No newline at end of file
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@@ -1,43 +1,43
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #include "lpp_apb_functions.h"
22 #include "lpp_apb_functions.h"
23 #include "apb_fifo_Driver.h"
23 #include "apb_fifo_Driver.h"
24 #include <stdio.h>
24 #include <stdio.h>
25
25
26
26
27 FIFO_Device* openFIFO(int count)
27 FIFO_Device* openFIFO(int count)
28 {
28 {
29 FIFO_Device* fifo0;
29 FIFO_Device* fifo0;
30 fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count);
30 fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count);
31 return fifo0;
31 return fifo0;
32 }
32 }
33
33
34
34
35 int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count)
35 int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count)
36 {
36 {
37 int i=0;
37 int i=0;
38 //int poub;
38 //int poub;
39 //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]);
39 //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]);
40 while(i<count)
40 while(i<=count)
41 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS
41 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS
42 {
42 {
43 //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);
43 //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);
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@@ -38,13 +38,16 entity APB_DAC is
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8);
41 abits : integer := 8;
42 cpt_serial : integer := 6);
42 port (
43 port (
43 clk : in std_logic; --! Horloge du composant
44 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 DataIN : in std_logic_vector(15 downto 0);
47 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
49 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
50 Readn : out std_logic;
48 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
51 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
49 SCLK : out std_logic; --! Horloge systeme du convertisseur
52 SCLK : out std_logic; --! Horloge systeme du convertisseur
50 DATA : out std_logic --! Donn�e num�rique s�rialis�
53 DATA : out std_logic --! Donn�e num�rique s�rialis�
@@ -63,11 +66,11 constant pconfig : apb_config_type := (
63 1 => apb_iobar(paddr, pmask));
66 1 => apb_iobar(paddr, pmask));
64
67
65 signal enable : std_logic;
68 signal enable : std_logic;
66 signal flag_sd : std_logic;
69 signal Ready : std_logic;
67
70
68 type DAC_ctrlr_Reg is record
71 type DAC_ctrlr_Reg is record
69 DAC_Cfg : std_logic_vector(1 downto 0);
72 DAC_Cfg : std_logic_vector(1 downto 0);
70 DAC_Data : std_logic_vector(15 downto 0);
73 -- DAC_Data : std_logic_vector(15 downto 0);
71 end record;
74 end record;
72
75
73 signal Rec : DAC_ctrlr_Reg;
76 signal Rec : DAC_ctrlr_Reg;
@@ -76,16 +79,18 signal Rdata : std_logic_vector(31 d
76 begin
79 begin
77
80
78 enable <= Rec.DAC_Cfg(0);
81 enable <= Rec.DAC_Cfg(0);
79 Rec.DAC_Cfg(1) <= flag_sd;
82 Rec.DAC_Cfg(1) <= Ready;
80
83
81 CONV0 : DacDriver
84 CONV0 : DacDriver
82 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
85 generic map (cpt_serial)
86 port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Ready,Data);
87 -- port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
83
88
84
89
85 process(rst,clk)
90 process(rst,clk)
86 begin
91 begin
87 if(rst='0')then
92 if(rst='0')then
88 Rec.DAC_Data <= (others => '0');
93 -- Rec.DAC_Data <= (others => '0');
89
94
90 elsif(clk'event and clk='1')then
95 elsif(clk'event and clk='1')then
91
96
@@ -95,8 +100,8 Rec.DAC_Cfg(1) <= flag_sd;
95 case apbi.paddr(abits-1 downto 2) is
100 case apbi.paddr(abits-1 downto 2) is
96 when "000000" =>
101 when "000000" =>
97 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
102 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
98 when "000001" =>
103 -- when "000001" =>
99 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
104 -- Rec.DAC_Data <= apbi.pwdata(15 downto 0);
100 when others =>
105 when others =>
101 null;
106 null;
102 end case;
107 end case;
@@ -108,9 +113,9 Rec.DAC_Cfg(1) <= flag_sd;
108 when "000000" =>
113 when "000000" =>
109 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
114 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
110 Rdata(1 downto 0) <= Rec.DAC_Cfg;
115 Rdata(1 downto 0) <= Rec.DAC_Cfg;
111 when "000001" =>
116 -- when "000001" =>
112 Rdata(31 downto 16) <= X"FD18";
117 -- Rdata(31 downto 16) <= X"FD18";
113 Rdata(15 downto 0) <= Rec.DAC_Data;
118 -- Rdata(15 downto 0) <= Rec.DAC_Data;
114 when others =>
119 when others =>
115 Rdata <= (others => '0');
120 Rdata <= (others => '0');
116 end case;
121 end case;
@@ -122,4 +127,4 Rec.DAC_Cfg(1) <= flag_sd;
122
127
123 apbo.prdata <= Rdata when apbi.penable = '1';
128 apbo.prdata <= Rdata when apbi.penable = '1';
124 Cal_EN <= enable;
129 Cal_EN <= enable;
125 end architecture;
130 end architecture; No newline at end of file
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@@ -22,20 +22,21
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.Convertisseur_config.all;
26 use lpp.lpp_cna.all;
25 use lpp.lpp_cna.all;
27
26
28 --! Programme du Convertisseur Num�rique/Analogique
27 --! Programme du Convertisseur Num�rique/Analogique
29
28
30 entity DacDriver is
29 entity DacDriver is
30 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
31 port(
31 port(
32 clk : in std_logic; --! Horloge du composant
32 clk : in std_logic; --! Horloge du composant
33 rst : in std_logic; --! Reset general du composant
33 rst : in std_logic; --! Reset general du composant
34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
35 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 SCLK : out std_logic; --! Horloge systeme du convertisseur
37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
38 Readn : out std_logic;
39 Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
39 Data : out std_logic --! Donn�e num�rique s�rialis�
40 Data : out std_logic --! Donn�e num�rique s�rialis�
40 );
41 );
41 end entity;
42 end entity;
@@ -46,22 +47,24 end entity;
46 architecture ar_DacDriver of DacDriver is
47 architecture ar_DacDriver of DacDriver is
47
48
48 signal s_SCLK : std_logic;
49 signal s_SCLK : std_logic;
49 signal OKAI_send : std_logic;
50 signal Send : std_logic;
50
51
51 begin
52 begin
52
53
53 SystemCLK : Systeme_Clock
54 SystemCLK : Systeme_Clock
54 generic map (nb_serial)
55 generic map (cpt_serial)
55 port map (clk,rst,s_SCLK);
56 port map (clk,rst,s_SCLK);
56
57
57
58
58 Signal_sync : Gene_SYNC
59 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
60 port map (s_SCLK,rst,enable,Send,SYNC);
60
61
61
62
62 Serial : serialize
63 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
64 port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
64
65
66 RenGEN : ReadFifo_GEN
67 port map (clk,rst,Send,Readn);
65
68
66 SCLK <= s_SCLK;
69 SCLK <= s_SCLK;
67
70
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@@ -29,7 +29,7 entity Gene_SYNC is
29 port(
29 port(
30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
32 OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
32 Send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
33 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
33 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
34 );
34 );
35 end Gene_SYNC;
35 end Gene_SYNC;
@@ -46,7 +46,7 begin
46 if(raz='0')then
46 if(raz='0')then
47 SYNC <= '0';
47 SYNC <= '0';
48 count <= 14;
48 count <= 14;
49 OKAI_send <= '0';
49 Send <= '0';
50
50
51 elsif(SCLK' event and SCLK='1')then
51 elsif(SCLK' event and SCLK='1')then
52 if(enable='1')then
52 if(enable='1')then
@@ -57,10 +57,10 begin
57 elsif(count=16)then
57 elsif(count=16)then
58 count <= 0;
58 count <= 0;
59 SYNC <= '0';
59 SYNC <= '0';
60 OKAI_send <= '1';
60 Send <= '1';
61 else
61 else
62 count <= count+1;
62 count <= count+1;
63 OKAI_send <= '0';
63 Send <= '0';
64 end if;
64 end if;
65
65
66 end if;
66 end if;
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@@ -1,96 +1,108
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_cna is
32 package lpp_cna is
33
33
34 component APB_DAC is
34 component APB_DAC is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8);
40 abits : integer := 8;
41 port (
41 cpt_serial : integer := 6);
42 clk : in std_logic;
42 port (
43 rst : in std_logic;
43 clk : in std_logic;
44 apbi : in apb_slv_in_type;
44 rst : in std_logic;
45 apbo : out apb_slv_out_type;
45 apbi : in apb_slv_in_type;
46 Cal_EN : out std_logic;
46 apbo : out apb_slv_out_type;
47 SYNC : out std_logic;
47 DataIN : in std_logic_vector(15 downto 0);
48 SCLK : out std_logic;
48 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
49 DATA : out std_logic
49 Readn : out std_logic;
50 );
50 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
51 end component;
51 SCLK : out std_logic; --! Horloge systeme du convertisseur
52
52 DATA : out std_logic
53
53 );
54 component DacDriver is
54 end component;
55 port(
55
56 clk : in std_logic;
56
57 rst : in std_logic;
57 component DacDriver is
58 enable : in std_logic;
58 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
59 Data_C : in std_logic_vector(15 downto 0);
59 port(
60 SYNC : out std_logic;
60 clk : in std_logic;
61 SCLK : out std_logic;
61 rst : in std_logic;
62 flag_sd : out std_logic;
62 enable : in std_logic;
63 Data : out std_logic
63 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
64 );
64 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
65 end component;
65 SCLK : out std_logic; --! Horloge systeme du convertisseur
66
66 Readn : out std_logic;
67
67 Ready : out std_logic;
68 component Systeme_Clock is
68 Data : out std_logic
69 generic(N :integer := 695);
69 );
70 port(
70 end component;
71 clk, raz : in std_logic ;
71
72 clock : out std_logic);
72
73 end component;
73 component Systeme_Clock is
74
74 generic(N :integer := 695);
75
75 port(
76 component Gene_SYNC is
76 clk, raz : in std_logic ;
77 port(
77 sclk : out std_logic);
78 clk,raz : in std_logic;
78 end component;
79 send : in std_logic;
79
80 Sysclk : in std_logic;
80
81 OKAI_send : out std_logic;
81 component Gene_SYNC is
82 SYNC : out std_logic);
82 port(
83 end component;
83 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
84
84 enable : in std_logic; --! Autorise ou non l'utilisation du composant
85
85 Send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
86 component Serialize is
86 SYNC : out std_logic); --! Signal de synchronisation du convertisseur g�n�r�
87 port(
87 end component;
88 clk,raz : in std_logic;
88
89 sclk : in std_logic;
89
90 vectin : in std_logic_vector(15 downto 0);
90 component Serialize is
91 send : in std_logic;
91 port(
92 sended : out std_logic;
92 clk,raz : in std_logic;
93 Data : out std_logic);
93 sclk : in std_logic;
94 end component;
94 vectin : in std_logic_vector(15 downto 0);
95
95 send : in std_logic;
96 end;
96 sended : out std_logic;
97 Data : out std_logic);
98 end component;
99
100 component ReadFifo_GEN is
101 port(
102 clk,raz : in std_logic; --! Horloge et Reset du composant
103 SYNC : in std_logic;
104 Readn : out std_logic
105 );
106 end component;
107
108 end; No newline at end of file
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@@ -158,6 +158,17 port(
158 );
158 );
159 end component;
159 end component;
160
160
161 component Bridge is
162 port(
163 clk : in std_logic;
164 raz : in std_logic;
165 EmptyUp : in std_logic;
166 FullDwn : in std_logic;
167 WriteDwn : out std_logic;
168 ReadUp : out std_logic
169 );
170 end component;
171
161 component ssram_plugin is
172 component ssram_plugin is
162 generic (tech : integer := 0);
173 generic (tech : integer := 0);
163 port
174 port
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