@@ -310,11 +310,11 BEGIN -- beh | |||
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310 | 310 | pindex => 6, |
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311 | 311 | paddr => 6, |
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312 | 312 | pmask => 16#fff#, |
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313 | pirq => 12, | |
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314 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 | |
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313 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
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314 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
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315 | 315 | PORT MAP ( |
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316 | 316 | clk25MHz => clk_25, |
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317 |
clk |
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317 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
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318 | 318 | resetn => reset, |
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319 | 319 | grspw_tick => swno.tickout, |
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320 | 320 | apbi => apbi_ext, |
@@ -425,7 +425,7 BEGIN -- beh | |||
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425 | 425 | pirq_ms => 6, |
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426 | 426 | pirq_wfp => 14, |
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427 | 427 | hindex => 2, |
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428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000106") -- aa.bb.cc version | |
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429 | 429 | PORT MAP ( |
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430 | 430 | clk => clk_25, |
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431 | 431 | rstn => reset, |
@@ -577,4 +577,4 BEGIN -- beh | |||
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577 | 577 | END IF; |
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578 | 578 | END PROCESS; |
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579 | 579 | |
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580 |
END beh; |
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580 | END beh; No newline at end of file |
@@ -142,7 +142,7 vcom_lpp: | |||
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142 | 142 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
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143 | 143 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
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144 | 144 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
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145 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/counter.vhd | |
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145 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
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146 | 146 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
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147 | 147 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
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148 | 148 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
@@ -3,7 +3,7 USE IEEE.STD_LOGIC_1164.ALL; | |||
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3 | 3 | USE IEEE.std_logic_arith.ALL; |
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4 | 4 | USE IEEE.std_logic_unsigned.ALL; |
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5 | 5 | |
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6 | ENTITY counter IS | |
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6 | ENTITY general_counter IS | |
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7 | 7 | |
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8 | 8 | GENERIC ( |
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9 | 9 | CYCLIC : STD_LOGIC := '1'; |
@@ -23,9 +23,9 ENTITY counter IS | |||
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23 | 23 | counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) |
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24 | 24 | ); |
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25 | 25 | |
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26 | END counter; | |
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26 | END general_counter; | |
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27 | 27 | |
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28 | ARCHITECTURE beh OF counter IS | |
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28 | ARCHITECTURE beh OF general_counter IS | |
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29 | 29 | SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
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30 | 30 | |
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31 | 31 | BEGIN -- beh |
@@ -33,7 +33,7 USE IEEE.NUMERIC_STD.ALL; | |||
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33 | 33 | |
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34 | 34 | PACKAGE general_purpose IS |
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35 | 35 | |
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36 | COMPONENT counter | |
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36 | COMPONENT general_counter | |
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37 | 37 | GENERIC ( |
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38 | 38 | CYCLIC : STD_LOGIC; |
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39 | 39 | NB_BITS_COUNTER : INTEGER); |
@@ -22,4 +22,4 lpp_front_detection.vhd | |||
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22 | 22 | lpp_front_positive_detection.vhd |
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23 | 23 | SYNC_VALID_BIT.vhd |
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24 | 24 | RR_Arbiter_4.vhd |
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25 | counter.vhd | |
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25 | general_counter.vhd |
@@ -38,7 +38,7 ARCHITECTURE beh OF coarse_time_counter | |||
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38 | 38 | --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 |
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39 | 39 | BEGIN -- beh |
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40 | 40 | |
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41 | counter_1 : counter | |
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41 | counter_1 : general_counter | |
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42 | 42 | GENERIC MAP ( |
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43 | 43 | CYCLIC => '1', |
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44 | 44 | NB_BITS_COUNTER => 31) |
@@ -55,7 +55,7 BEGIN -- beh | |||
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55 | 55 | |
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56 | 56 | add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; |
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57 | 57 | |
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58 | counter_2 : counter | |
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58 | counter_2 : general_counter | |
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59 | 59 | GENERIC MAP ( |
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60 | 60 | CYCLIC => '0', |
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61 | 61 | NB_BITS_COUNTER => 6) |
@@ -40,7 +40,7 BEGIN -- beh | |||
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40 | 40 | |
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41 | 41 | |
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42 | 42 | |
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43 | counter_1 : counter | |
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43 | counter_1 : general_counter | |
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44 | 44 | GENERIC MAP ( |
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45 | 45 | CYCLIC => '1', |
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46 | 46 | NB_BITS_COUNTER => 9) |
@@ -56,7 +56,7 BEGIN -- beh | |||
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56 | 56 | |
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57 | 57 | new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0'; |
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58 | 58 | |
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59 | counter_2 : counter | |
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59 | counter_2 : general_counter | |
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60 | 60 | GENERIC MAP ( |
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61 | 61 | CYCLIC => '1', |
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62 | 62 | NB_BITS_COUNTER => 16) |
@@ -115,8 +115,7 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs | |||
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115 | 115 | WRITE_FINE_TIME, |
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116 | 116 | TRASH_FIFO, |
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117 | 117 | SEND_DATA, |
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118 |
WAIT_DATA_ACK |
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119 | CHECK_LENGTH | |
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118 | WAIT_DATA_ACK | |
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120 | 119 | ); |
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121 | 120 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; |
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122 | 121 | |
@@ -149,6 +148,9 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs | |||
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149 | 148 | ----------------------------------------------------------------------------- |
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150 | 149 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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151 | 150 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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151 | ||
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152 | ----------------------------------------------------------------------------- | |
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153 | SIGNAL log_empty_fifo : STD_LOGIC; | |
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152 | 154 | |
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153 | 155 | BEGIN |
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154 | 156 | |
@@ -199,6 +201,8 BEGIN | |||
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199 | 201 | |
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200 | 202 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
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201 | 203 | |
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204 | log_empty_fifo <= '0'; | |
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205 | ||
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202 | 206 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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203 | 207 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); |
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204 | 208 | |
@@ -227,6 +231,7 BEGIN | |||
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227 | 231 | component_type_pre <= component_type; |
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228 | 232 | state <= CHECK_COMPONENT_TYPE; |
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229 | 233 | END IF; |
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234 | log_empty_fifo <= '0'; | |
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230 | 235 | |
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231 | 236 | WHEN CHECK_COMPONENT_TYPE => |
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232 | 237 | debug_reg_s(2 DOWNTO 0) <= "001"; |
@@ -330,7 +335,7 BEGIN | |||
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330 | 335 | header_ack <= '0'; |
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331 | 336 | debug_reg_s(2 DOWNTO 0) <= "101"; |
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332 | 337 | |
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333 | IF fifo_empty = '1' THEN | |
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338 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
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334 | 339 | state <= IDLE; |
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335 | 340 | IF component_type = "1110" THEN --"1110" -- JC |
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336 | 341 | CASE matrix_type IS |
@@ -349,6 +354,8 BEGIN | |||
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349 | 354 | END IF; |
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350 | 355 | |
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351 | 356 | WHEN WAIT_DATA_ACK => |
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357 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |
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358 | ||
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352 | 359 |
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353 | 360 | |
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354 | 361 | component_send <= '0'; |
@@ -357,13 +364,14 BEGIN | |||
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357 | 364 | state <= SEND_DATA; |
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358 | 365 | ELSIF component_send_ko = '1' THEN |
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359 | 366 | error_anticipating_empty_fifo <= '0'; |
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360 |
state |
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367 | state <= TRASH_FIFO; | |
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361 | 368 | END IF; |
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362 | 369 | |
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363 | WHEN CHECK_LENGTH => | |
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364 | component_send <= '0'; | |
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365 | debug_reg_s(2 DOWNTO 0) <= "111"; | |
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366 | state <= IDLE; | |
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370 | ||
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371 | --WHEN CHECK_LENGTH => | |
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372 | -- component_send <= '0'; | |
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373 | -- debug_reg_s(2 DOWNTO 0) <= "111"; | |
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374 | -- state <= IDLE; | |
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367 | 375 | |
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368 | 376 | WHEN OTHERS => NULL; |
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369 | 377 | END CASE; |
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