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MINI LFR - WFP&MS - 0.1.6...
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r330:420e00cb22ab (MINI-LFR) WFP_MS-0-1-6 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
175
175
176 BEGIN -- beh
176 BEGIN -- beh
177
177
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179 -- CLK
179 -- CLK
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181
181
182 PROCESS(clk_50)
182 PROCESS(clk_50)
183 BEGIN
183 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
186 END IF;
186 END IF;
187 END PROCESS;
187 END PROCESS;
188
188
189 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
190 BEGIN
190 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 PROCESS(clk_49)
196 PROCESS(clk_49)
197 BEGIN
197 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
200 END IF;
200 END IF;
201 END PROCESS;
201 END PROCESS;
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
208 LED0 <= '0';
209 LED1 <= '0';
209 LED1 <= '0';
210 LED2 <= '0';
210 LED2 <= '0';
211 --IO1 <= '0';
211 --IO1 <= '0';
212 --IO2 <= '1';
212 --IO2 <= '1';
213 --IO3 <= '0';
213 --IO3 <= '0';
214 --IO4 <= '0';
214 --IO4 <= '0';
215 --IO5 <= '0';
215 --IO5 <= '0';
216 --IO6 <= '0';
216 --IO6 <= '0';
217 --IO7 <= '0';
217 --IO7 <= '0';
218 --IO8 <= '0';
218 --IO8 <= '0';
219 --IO9 <= '0';
219 --IO9 <= '0';
220 --IO10 <= '0';
220 --IO10 <= '0';
221 --IO11 <= '0';
221 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
223 LED0 <= '0';
224 LED1 <= '1';
224 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
226 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
241 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
243 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s ;
245 I00_s <= NOT I00_s ;
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
249
249
250 --UARTs
250 --UARTs
251 nCTS1 <= '1';
251 nCTS1 <= '1';
252 nCTS2 <= '1';
252 nCTS2 <= '1';
253 nDCD2 <= '1';
253 nDCD2 <= '1';
254
254
255 --EXT CONNECTOR
255 --EXT CONNECTOR
256
256
257 --SPACE WIRE
257 --SPACE WIRE
258
258
259 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
260 GENERIC MAP (
261 fabtech => apa3e,
261 fabtech => apa3e,
262 memtech => apa3e,
262 memtech => apa3e,
263 padtech => inferred,
263 padtech => inferred,
264 clktech => inferred,
264 clktech => inferred,
265 disas => 0,
265 disas => 0,
266 dbguart => 0,
266 dbguart => 0,
267 pclow => 2,
267 pclow => 2,
268 clk_freq => 25000,
268 clk_freq => 25000,
269 NB_CPU => 1,
269 NB_CPU => 1,
270 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
280 PORT MAP (
281 clk => clk_25,
281 clk => clk_25,
282 reset => reset,
282 reset => reset,
283 errorn => errorn,
283 errorn => errorn,
284 ahbrxd => TXD1,
284 ahbrxd => TXD1,
285 ahbtxd => RXD1,
285 ahbtxd => RXD1,
286 urxd1 => TXD2,
286 urxd1 => TXD2,
287 utxd1 => RXD2,
287 utxd1 => RXD2,
288 address => SRAM_A,
288 address => SRAM_A,
289 data => SRAM_DQ,
289 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
297
297
298 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
304
304
305 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
309 GENERIC MAP (
310 pindex => 6,
310 pindex => 6,
311 paddr => 6,
311 paddr => 6,
312 pmask => 16#fff#,
312 pmask => 16#fff#,
313 pirq => 12,
313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 PORT MAP (
315 PORT MAP (
316 clk25MHz => clk_25,
316 clk25MHz => clk_25,
317 clk49_152MHz => clk_24, -- 49.152MHz/2
317 clk24_576MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
318 resetn => reset,
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
322 coarse_time => coarse_time,
323 fine_time => fine_time);
323 fine_time => fine_time);
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 SPW_EN <= '1';
329 SPW_EN <= '1';
330
330
331 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334
334
335 -- PADS for SPW1
335 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
344 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
353
354 -- GRSPW PHY
354 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
358 GENERIC MAP(
358 GENERIC MAP(
359 tech => apa3e,
359 tech => apa3e,
360 rxclkbuftype => 1,
360 rxclkbuftype => 1,
361 scantest => 0)
361 scantest => 0)
362 PORT MAP(
362 PORT MAP(
363 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
364 di => dtmp(j),
364 di => dtmp(j),
365 si => stmp(j),
365 si => stmp(j),
366 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
367 do => swni.d(j),
367 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
371
371
372 -- SPW core
372 -- SPW core
373 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
374 tech => apa3e,
375 hindex => 1,
375 hindex => 1,
376 pindex => 5,
376 pindex => 5,
377 paddr => 5,
377 paddr => 5,
378 pirq => 11,
378 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
380 rmap => 1,
381 rmapcrc => 1,
381 rmapcrc => 1,
382 fifosize1 => 16,
382 fifosize1 => 16,
383 fifosize2 => 16,
383 fifosize2 => 16,
384 rxclkbuftype => 1,
384 rxclkbuftype => 1,
385 rxunaligned => 0,
385 rxunaligned => 0,
386 rmapbufs => 4,
386 rmapbufs => 4,
387 ft => 0,
387 ft => 0,
388 netlist => 0,
388 netlist => 0,
389 ports => 2,
389 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
391 memtech => apa3e,
392 destkey => 2,
392 destkey => 2,
393 spwcore => 1
393 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
397 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
401 swni, swno);
402
402
403 swni.tickin <= '0';
403 swni.tickin <= '0';
404 swni.rmapen <= '1';
404 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410
410
411 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
415 GENERIC MAP (
416 Mem_use => use_RAM,
416 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"000105") -- aa.bb.cc version
428 top_lfr_version => X"000106") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
434 sample_val => sample_val,
434 sample_val => sample_val,
435 apbi => apbi_ext,
435 apbi => apbi_ext,
436 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
439 coarse_time => coarse_time,
440 fine_time => fine_time,
440 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
442 observation_reg => observation_reg);
443
443
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
445 GENERIC MAP(
446 ChannelCount => 8,
446 ChannelCount => 8,
447 SampleNbBits => 14,
447 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
450 PORT MAP (
451 -- CONV
451 -- CONV
452 cnv_clk => clk_24,
452 cnv_clk => clk_24,
453 cnv_rstn => reset,
453 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
455 -- DATA
455 -- DATA
456 clk => clk_25,
456 clk => clk_25,
457 rstn => reset,
457 rstn => reset,
458 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
460 -- SAMPLE
460 -- SAMPLE
461 sample => sample,
461 sample => sample,
462 sample_val => sample_val);
462 sample_val => sample_val);
463
463
464 --IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
467
467
468 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
471
471
472 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
475
475
476 grgpio0 : grgpio
476 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
479
480 --pio_pad_0 : iopad
480 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
483 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
486 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
489 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
492 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
495 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
498 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
501 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
504
505 PROCESS (clk_25, reset)
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
508 IO0 <= '0';
509 IO1 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
557 IO8 <= '0';
558 IO9 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
561 WHEN "11" =>
562 IO0 <= '0';
562 IO0 <= '0';
563 IO1 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
574 WHEN OTHERS => NULL;
575 END CASE;
575 END CASE;
576
576
577 END IF;
577 END IF;
578 END PROCESS;
578 END PROCESS;
579
579
580 END beh;
580 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,151 +1,151
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3
3
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=TB
5 TOP=TB
6
6
7 ##VHDLSYNFILES= TB.vhd
7 ##VHDLSYNFILES= TB.vhd
8
8
9 ##LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
9 ##LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
10 ## tmtc openchip hynix ihp gleichmann micron usbhc
10 ## tmtc openchip hynix ihp gleichmann micron usbhc
11
11
12 ##DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
12 ##DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
13 ## pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
13 ## pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
14 ## ./amba_lcd_16x2_ctrlr \
14 ## ./amba_lcd_16x2_ctrlr \
15 ## ./general_purpose/lpp_AMR \
15 ## ./general_purpose/lpp_AMR \
16 ## ./general_purpose/lpp_balise \
16 ## ./general_purpose/lpp_balise \
17 ## ./general_purpose/lpp_delay \
17 ## ./general_purpose/lpp_delay \
18 ## ./dsp/lpp_fft \
18 ## ./dsp/lpp_fft \
19 ## ./lpp_bootloader \
19 ## ./lpp_bootloader \
20 ## ./lpp_cna \
20 ## ./lpp_cna \
21 ## ./lpp_demux \
21 ## ./lpp_demux \
22 ## ./lpp_matrix \
22 ## ./lpp_matrix \
23 ## ./lpp_uart \
23 ## ./lpp_uart \
24 ## ./lpp_usb \
24 ## ./lpp_usb \
25 ## ./lpp_Header \
25 ## ./lpp_Header \
26
26
27 ##FILESKIP =lpp_lfr_ms.vhd \x
27 ##FILESKIP =lpp_lfr_ms.vhd \x
28 ## i2cmst.vhd \
28 ## i2cmst.vhd \
29 ## APB_MULTI_DIODE.vhd \
29 ## APB_MULTI_DIODE.vhd \
30 ## APB_SIMPLE_DIODE.vhd \
30 ## APB_SIMPLE_DIODE.vhd \
31 ## Top_MatrixSpec.vhd \
31 ## Top_MatrixSpec.vhd \
32 ## APB_FFT.vhd
32 ## APB_FFT.vhd
33
33
34 ##include $(GRLIB)/bin/Makefile
34 ##include $(GRLIB)/bin/Makefile
35 ##include $(GRLIB)/software/leon3/Makefile
35 ##include $(GRLIB)/software/leon3/Makefile
36
36
37 CMD_VLIB=vlib
37 CMD_VLIB=vlib
38 CMD_VMAP=vmap
38 CMD_VMAP=vmap
39 CMD_VCOM=@vcom -quiet -93 -work
39 CMD_VCOM=@vcom -quiet -93 -work
40
40
41 ################## project specific targets ##########################
41 ################## project specific targets ##########################
42
42
43 all:
43 all:
44 @echo "make vsim"
44 @echo "make vsim"
45 @echo "make libs"
45 @echo "make libs"
46 @echo "make clean"
46 @echo "make clean"
47 @echo "make vcom_grlib vcom_lpp vcom_tb"
47 @echo "make vcom_grlib vcom_lpp vcom_tb"
48
48
49 run:
49 run:
50 @vsim work.TB -do run.do
50 @vsim work.TB -do run.do
51
51
52 vsim: libs vcom run
52 vsim: libs vcom run
53
53
54 libs:
54 libs:
55 @$(CMD_VLIB) modelsim
55 @$(CMD_VLIB) modelsim
56 @$(CMD_VMAP) modelsim modelsim
56 @$(CMD_VMAP) modelsim modelsim
57 @$(CMD_VLIB) modelsim/grlib
57 @$(CMD_VLIB) modelsim/grlib
58 @$(CMD_VMAP) grlib modelsim/grlib
58 @$(CMD_VMAP) grlib modelsim/grlib
59 @$(CMD_VLIB) modelsim/work
59 @$(CMD_VLIB) modelsim/work
60 @$(CMD_VMAP) work modelsim/work
60 @$(CMD_VMAP) work modelsim/work
61 @$(CMD_VLIB) modelsim/lpp
61 @$(CMD_VLIB) modelsim/lpp
62 @$(CMD_VMAP) lpp modelsim/lpp
62 @$(CMD_VMAP) lpp modelsim/lpp
63 @echo "libs done"
63 @echo "libs done"
64
64
65
65
66 clean:
66 clean:
67 @rm -Rf modelsim
67 @rm -Rf modelsim
68 @rm -Rf modelsim.ini
68 @rm -Rf modelsim.ini
69 @rm -Rf *~
69 @rm -Rf *~
70 @rm -Rf transcript
70 @rm -Rf transcript
71 @rm -Rf wlft*
71 @rm -Rf wlft*
72 @rm -Rf *.wlf
72 @rm -Rf *.wlf
73 @rm -Rf vish_stacktrace.vstf
73 @rm -Rf vish_stacktrace.vstf
74 @rm -Rf libs.do
74 @rm -Rf libs.do
75
75
76 vcom: vcom_grlib vcom_lpp vcom_tb
76 vcom: vcom_grlib vcom_lpp vcom_tb
77
77
78 vcom_tb:
78 vcom_tb:
79 $(CMD_VCOM) work TB.vhd
79 $(CMD_VCOM) work TB.vhd
80 @echo "vcom work done"
80 @echo "vcom work done"
81
81
82 vcom_grlib:
82 vcom_grlib:
83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
101 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
101 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
102 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
102 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
103 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
103 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
104 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
104 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
105 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
105 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
106 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
106 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
107 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
107 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
108 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
108 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
109 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
109 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
110 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
110 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
111 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
111 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
112 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
112 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
113 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
113 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
114 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
114 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
115 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
115 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
116 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
116 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
117 @echo "vcom grlib done"
117 @echo "vcom grlib done"
118
118
119 vcom_lpp:
119 vcom_lpp:
120 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
120 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
121 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
121 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
122 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
122 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
123 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
123 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
124 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
124 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
125 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
125 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
126 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
126 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
127 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
127 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
128 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
128 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
129 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
129 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
130 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
130 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
131 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
131 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
132 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
132 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
133 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
133 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
134 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
134 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
135 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
135 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
136 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
136 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
137 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
137 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
138 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
138 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
139 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
139 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
140 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
140 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
141 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
141 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
142 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
142 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
143 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
143 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
144 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
144 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
145 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/counter.vhd
145 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
146 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
146 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
147 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
147 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
148 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
148 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
149 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
149 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
150 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
150 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
151 @echo "vcom lpp done"
151 @echo "vcom lpp done"
Show file before | Show file after | Hide comments
@@ -1,54 +1,54
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.std_logic_arith.ALL;
3 USE IEEE.std_logic_arith.ALL;
4 USE IEEE.std_logic_unsigned.ALL;
4 USE IEEE.std_logic_unsigned.ALL;
5
5
6 ENTITY counter IS
6 ENTITY general_counter IS
7
7
8 GENERIC (
8 GENERIC (
9 CYCLIC : STD_LOGIC := '1';
9 CYCLIC : STD_LOGIC := '1';
10 NB_BITS_COUNTER : INTEGER := 9
10 NB_BITS_COUNTER : INTEGER := 9
11 );
11 );
12
12
13 PORT (
13 PORT (
14 clk : IN STD_LOGIC;
14 clk : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
15 rstn : IN STD_LOGIC;
16 --
16 --
17 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0');
17 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0');
18 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
18 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
19 --
19 --
20 set : IN STD_LOGIC;
20 set : IN STD_LOGIC;
21 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
21 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
22 add1 : IN STD_LOGIC;
22 add1 : IN STD_LOGIC;
23 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
23 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
24 );
24 );
25
25
26 END counter;
26 END general_counter;
27
27
28 ARCHITECTURE beh OF counter IS
28 ARCHITECTURE beh OF general_counter IS
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
30
30
31 BEGIN -- beh
31 BEGIN -- beh
32
32
33 PROCESS (clk, rstn)
33 PROCESS (clk, rstn)
34 BEGIN -- PROCESS
34 BEGIN -- PROCESS
35 IF rstn = '0' THEN -- asynchronous reset (active low)
35 IF rstn = '0' THEN -- asynchronous reset (active low)
36 counter_s <= RST_VALUE;
36 counter_s <= RST_VALUE;
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
38 IF set = '1' THEN
38 IF set = '1' THEN
39 counter_s <= set_value;
39 counter_s <= set_value;
40 ELSIF add1 = '1' THEN
40 ELSIF add1 = '1' THEN
41 IF counter_s < MAX_VALUE THEN
41 IF counter_s < MAX_VALUE THEN
42 counter_s <= counter_s + 1;
42 counter_s <= counter_s + 1;
43 ELSE
43 ELSE
44 IF CYCLIC = '1' THEN
44 IF CYCLIC = '1' THEN
45 counter_s <= (OTHERS => '0');
45 counter_s <= (OTHERS => '0');
46 END IF;
46 END IF;
47 END IF;
47 END IF;
48 END IF;
48 END IF;
49 END IF;
49 END IF;
50 END PROCESS;
50 END PROCESS;
51
51
52 counter <= counter_s;
52 counter <= counter_s;
53
53
54 END beh;
54 END beh;
Show file before | Show file after | Hide comments
@@ -1,395 +1,395
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
31
31
32
32
33
33
34 PACKAGE general_purpose IS
34 PACKAGE general_purpose IS
35
35
36 COMPONENT counter
36 COMPONENT general_counter
37 GENERIC (
37 GENERIC (
38 CYCLIC : STD_LOGIC;
38 CYCLIC : STD_LOGIC;
39 NB_BITS_COUNTER : INTEGER);
39 NB_BITS_COUNTER : INTEGER);
40 PORT (
40 PORT (
41 clk : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
43 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
45 set : IN STD_LOGIC;
45 set : IN STD_LOGIC;
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 add1 : IN STD_LOGIC;
47 add1 : IN STD_LOGIC;
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
49 END COMPONENT;
49 END COMPONENT;
50
50
51 COMPONENT Clk_divider IS
51 COMPONENT Clk_divider IS
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
53 TargetFreq_Hz : INTEGER := 50000);
53 TargetFreq_Hz : INTEGER := 50000);
54 PORT (clk : IN STD_LOGIC;
54 PORT (clk : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
56 clk_divided : OUT STD_LOGIC);
56 clk_divided : OUT STD_LOGIC);
57 END COMPONENT;
57 END COMPONENT;
58
58
59
59
60 COMPONENT Clk_divider2 IS
60 COMPONENT Clk_divider2 IS
61 generic(N : integer := 16);
61 generic(N : integer := 16);
62 port(
62 port(
63 clk_in : in std_logic;
63 clk_in : in std_logic;
64 clk_out : out std_logic);
64 clk_out : out std_logic);
65 END COMPONENT;
65 END COMPONENT;
66
66
67 COMPONENT Adder IS
67 COMPONENT Adder IS
68 GENERIC(
68 GENERIC(
69 Input_SZ_A : INTEGER := 16;
69 Input_SZ_A : INTEGER := 16;
70 Input_SZ_B : INTEGER := 16
70 Input_SZ_B : INTEGER := 16
71
71
72 );
72 );
73 PORT(
73 PORT(
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 reset : IN STD_LOGIC;
75 reset : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
77 load : IN STD_LOGIC;
77 load : IN STD_LOGIC;
78 add : IN STD_LOGIC;
78 add : IN STD_LOGIC;
79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
82 );
82 );
83 END COMPONENT;
83 END COMPONENT;
84
84
85 COMPONENT Adder_V0 is
85 COMPONENT Adder_V0 is
86 generic(
86 generic(
87 Input_SZ_A : integer := 16;
87 Input_SZ_A : integer := 16;
88 Input_SZ_B : integer := 16
88 Input_SZ_B : integer := 16
89
89
90 );
90 );
91 port(
91 port(
92 clk : in std_logic;
92 clk : in std_logic;
93 reset : in std_logic;
93 reset : in std_logic;
94 clr : in std_logic;
94 clr : in std_logic;
95 add : in std_logic;
95 add : in std_logic;
96 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
96 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
97 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
97 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
98 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
98 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
99 );
99 );
100 end COMPONENT;
100 end COMPONENT;
101
101
102 COMPONENT ADDRcntr IS
102 COMPONENT ADDRcntr IS
103 PORT(
103 PORT(
104 clk : IN STD_LOGIC;
104 clk : IN STD_LOGIC;
105 reset : IN STD_LOGIC;
105 reset : IN STD_LOGIC;
106 count : IN STD_LOGIC;
106 count : IN STD_LOGIC;
107 clr : IN STD_LOGIC;
107 clr : IN STD_LOGIC;
108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
109 );
109 );
110 END COMPONENT;
110 END COMPONENT;
111
111
112 COMPONENT ALU IS
112 COMPONENT ALU IS
113 GENERIC(
113 GENERIC(
114 Arith_en : INTEGER := 1;
114 Arith_en : INTEGER := 1;
115 Logic_en : INTEGER := 1;
115 Logic_en : INTEGER := 1;
116 Input_SZ_1 : INTEGER := 16;
116 Input_SZ_1 : INTEGER := 16;
117 Input_SZ_2 : INTEGER := 9;
117 Input_SZ_2 : INTEGER := 9;
118 COMP_EN : INTEGER := 0 -- 1 => No Comp
118 COMP_EN : INTEGER := 0 -- 1 => No Comp
119
119
120 );
120 );
121 PORT(
121 PORT(
122 clk : IN STD_LOGIC;
122 clk : IN STD_LOGIC;
123 reset : IN STD_LOGIC;
123 reset : IN STD_LOGIC;
124 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
124 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
125 comp : IN STD_LOGIC_VECTOR(1 downto 0);
125 comp : IN STD_LOGIC_VECTOR(1 downto 0);
126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
129 );
129 );
130 END COMPONENT;
130 END COMPONENT;
131
131
132 COMPONENT ALU_V0 IS
132 COMPONENT ALU_V0 IS
133 GENERIC(
133 GENERIC(
134 Arith_en : INTEGER := 1;
134 Arith_en : INTEGER := 1;
135 Logic_en : INTEGER := 1;
135 Logic_en : INTEGER := 1;
136 Input_SZ_1 : INTEGER := 16;
136 Input_SZ_1 : INTEGER := 16;
137 Input_SZ_2 : INTEGER := 9
137 Input_SZ_2 : INTEGER := 9
138
138
139 );
139 );
140 PORT(
140 PORT(
141 clk : IN STD_LOGIC;
141 clk : IN STD_LOGIC;
142 reset : IN STD_LOGIC;
142 reset : IN STD_LOGIC;
143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
147 );
147 );
148 END COMPONENT;
148 END COMPONENT;
149
149
150 COMPONENT MAC_V0 is
150 COMPONENT MAC_V0 is
151 generic(
151 generic(
152 Input_SZ_A : integer := 8;
152 Input_SZ_A : integer := 8;
153 Input_SZ_B : integer := 8
153 Input_SZ_B : integer := 8
154
154
155 );
155 );
156 port(
156 port(
157 clk : in std_logic;
157 clk : in std_logic;
158 reset : in std_logic;
158 reset : in std_logic;
159 clr_MAC : in std_logic;
159 clr_MAC : in std_logic;
160 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
160 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
161 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
161 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
162 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
162 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
163 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
163 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
164 );
164 );
165 end COMPONENT;
165 end COMPONENT;
166
166
167 ---------------------------------------------------------
167 ---------------------------------------------------------
168 -------- // SΓ©lection grace a l'entrΓ©e "ctrl" \\ --------
168 -------- // SΓ©lection grace a l'entrΓ©e "ctrl" \\ --------
169 ---------------------------------------------------------
169 ---------------------------------------------------------
170 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
170 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
171 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
171 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
172 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
172 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
173 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
173 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
174 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
174 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
175
175
176
176
177 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
177 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
178 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
178 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
179 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
179 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
180 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
180 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
181 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
181 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
182 ---------------------------------------------------------
182 ---------------------------------------------------------
183
183
184 COMPONENT MAC IS
184 COMPONENT MAC IS
185 GENERIC(
185 GENERIC(
186 Input_SZ_A : INTEGER := 8;
186 Input_SZ_A : INTEGER := 8;
187 Input_SZ_B : INTEGER := 8;
187 Input_SZ_B : INTEGER := 8;
188 COMP_EN : INTEGER := 0 -- 1 => No Comp
188 COMP_EN : INTEGER := 0 -- 1 => No Comp
189 );
189 );
190 PORT(
190 PORT(
191 clk : IN STD_LOGIC;
191 clk : IN STD_LOGIC;
192 reset : IN STD_LOGIC;
192 reset : IN STD_LOGIC;
193 clr_MAC : IN STD_LOGIC;
193 clr_MAC : IN STD_LOGIC;
194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
199 );
199 );
200 END COMPONENT;
200 END COMPONENT;
201
201
202 COMPONENT TwoComplementer is
202 COMPONENT TwoComplementer is
203 generic(
203 generic(
204 Input_SZ : integer := 16);
204 Input_SZ : integer := 16);
205 port(
205 port(
206 clk : in std_logic; --! Horloge du composant
206 clk : in std_logic; --! Horloge du composant
207 reset : in std_logic; --! Reset general du composant
207 reset : in std_logic; --! Reset general du composant
208 clr : in std_logic; --! Un reset spΓ©cifique au programme
208 clr : in std_logic; --! Un reset spΓ©cifique au programme
209 TwoComp : in std_logic; --! Autorise l'utilisation du complΓ©ment
209 TwoComp : in std_logic; --! Autorise l'utilisation du complΓ©ment
210 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpΓ©rande d'entrΓ©e
210 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpΓ©rande d'entrΓ©e
211 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RΓ©sultat, opΓ©rande complΓ©mentΓ© ou non
211 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RΓ©sultat, opΓ©rande complΓ©mentΓ© ou non
212 );
212 );
213 end COMPONENT;
213 end COMPONENT;
214
214
215 COMPONENT MAC_CONTROLER IS
215 COMPONENT MAC_CONTROLER IS
216 PORT(
216 PORT(
217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
218 MULT : OUT STD_LOGIC;
218 MULT : OUT STD_LOGIC;
219 ADD : OUT STD_LOGIC;
219 ADD : OUT STD_LOGIC;
220 LOAD_ADDER : out std_logic;
220 LOAD_ADDER : out std_logic;
221 MACMUX_sel : OUT STD_LOGIC;
221 MACMUX_sel : OUT STD_LOGIC;
222 MACMUX2_sel : OUT STD_LOGIC
222 MACMUX2_sel : OUT STD_LOGIC
223 );
223 );
224 END COMPONENT;
224 END COMPONENT;
225
225
226 COMPONENT MAC_MUX IS
226 COMPONENT MAC_MUX IS
227 GENERIC(
227 GENERIC(
228 Input_SZ_A : INTEGER := 16;
228 Input_SZ_A : INTEGER := 16;
229 Input_SZ_B : INTEGER := 16
229 Input_SZ_B : INTEGER := 16
230
230
231 );
231 );
232 PORT(
232 PORT(
233 sel : IN STD_LOGIC;
233 sel : IN STD_LOGIC;
234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
240 );
240 );
241 END COMPONENT;
241 END COMPONENT;
242
242
243
243
244 COMPONENT MAC_MUX2 IS
244 COMPONENT MAC_MUX2 IS
245 GENERIC(Input_SZ : INTEGER := 16);
245 GENERIC(Input_SZ : INTEGER := 16);
246 PORT(
246 PORT(
247 sel : IN STD_LOGIC;
247 sel : IN STD_LOGIC;
248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
251 );
251 );
252 END COMPONENT;
252 END COMPONENT;
253
253
254
254
255 COMPONENT MAC_REG IS
255 COMPONENT MAC_REG IS
256 GENERIC(size : INTEGER := 16);
256 GENERIC(size : INTEGER := 16);
257 PORT(
257 PORT(
258 reset : IN STD_LOGIC;
258 reset : IN STD_LOGIC;
259 clk : IN STD_LOGIC;
259 clk : IN STD_LOGIC;
260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
262 );
262 );
263 END COMPONENT;
263 END COMPONENT;
264
264
265
265
266 COMPONENT MUX2 IS
266 COMPONENT MUX2 IS
267 GENERIC(Input_SZ : INTEGER := 16);
267 GENERIC(Input_SZ : INTEGER := 16);
268 PORT(
268 PORT(
269 sel : IN STD_LOGIC;
269 sel : IN STD_LOGIC;
270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
273 );
273 );
274 END COMPONENT;
274 END COMPONENT;
275
275
276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
278
278
279 COMPONENT MUXN
279 COMPONENT MUXN
280 GENERIC (
280 GENERIC (
281 Input_SZ : INTEGER;
281 Input_SZ : INTEGER;
282 NbStage : INTEGER);
282 NbStage : INTEGER);
283 PORT (
283 PORT (
284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
288 END COMPONENT;
288 END COMPONENT;
289
289
290
290
291
291
292 COMPONENT Multiplier IS
292 COMPONENT Multiplier IS
293 GENERIC(
293 GENERIC(
294 Input_SZ_A : INTEGER := 16;
294 Input_SZ_A : INTEGER := 16;
295 Input_SZ_B : INTEGER := 16
295 Input_SZ_B : INTEGER := 16
296
296
297 );
297 );
298 PORT(
298 PORT(
299 clk : IN STD_LOGIC;
299 clk : IN STD_LOGIC;
300 reset : IN STD_LOGIC;
300 reset : IN STD_LOGIC;
301 mult : IN STD_LOGIC;
301 mult : IN STD_LOGIC;
302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
305 );
305 );
306 END COMPONENT;
306 END COMPONENT;
307
307
308 COMPONENT REG IS
308 COMPONENT REG IS
309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
310 PORT(
310 PORT(
311 reset : IN STD_LOGIC;
311 reset : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
315 );
315 );
316 END COMPONENT;
316 END COMPONENT;
317
317
318
318
319
319
320 COMPONENT RShifter IS
320 COMPONENT RShifter IS
321 GENERIC(
321 GENERIC(
322 Input_SZ : INTEGER := 16;
322 Input_SZ : INTEGER := 16;
323 shift_SZ : INTEGER := 4
323 shift_SZ : INTEGER := 4
324 );
324 );
325 PORT(
325 PORT(
326 clk : IN STD_LOGIC;
326 clk : IN STD_LOGIC;
327 reset : IN STD_LOGIC;
327 reset : IN STD_LOGIC;
328 shift : IN STD_LOGIC;
328 shift : IN STD_LOGIC;
329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
332 );
332 );
333 END COMPONENT;
333 END COMPONENT;
334
334
335 COMPONENT SYNC_FF
335 COMPONENT SYNC_FF
336 GENERIC (
336 GENERIC (
337 NB_FF_OF_SYNC : INTEGER);
337 NB_FF_OF_SYNC : INTEGER);
338 PORT (
338 PORT (
339 clk : IN STD_LOGIC;
339 clk : IN STD_LOGIC;
340 rstn : IN STD_LOGIC;
340 rstn : IN STD_LOGIC;
341 A : IN STD_LOGIC;
341 A : IN STD_LOGIC;
342 A_sync : OUT STD_LOGIC);
342 A_sync : OUT STD_LOGIC);
343 END COMPONENT;
343 END COMPONENT;
344
344
345 COMPONENT lpp_front_to_level
345 COMPONENT lpp_front_to_level
346 PORT (
346 PORT (
347 clk : IN STD_LOGIC;
347 clk : IN STD_LOGIC;
348 rstn : IN STD_LOGIC;
348 rstn : IN STD_LOGIC;
349 sin : IN STD_LOGIC;
349 sin : IN STD_LOGIC;
350 sout : OUT STD_LOGIC);
350 sout : OUT STD_LOGIC);
351 END COMPONENT;
351 END COMPONENT;
352
352
353 COMPONENT lpp_front_detection
353 COMPONENT lpp_front_detection
354 PORT (
354 PORT (
355 clk : IN STD_LOGIC;
355 clk : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
357 sin : IN STD_LOGIC;
357 sin : IN STD_LOGIC;
358 sout : OUT STD_LOGIC);
358 sout : OUT STD_LOGIC);
359 END COMPONENT;
359 END COMPONENT;
360
360
361 COMPONENT lpp_front_positive_detection
361 COMPONENT lpp_front_positive_detection
362 PORT (
362 PORT (
363 clk : IN STD_LOGIC;
363 clk : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
365 sin : IN STD_LOGIC;
365 sin : IN STD_LOGIC;
366 sout : OUT STD_LOGIC);
366 sout : OUT STD_LOGIC);
367 END COMPONENT;
367 END COMPONENT;
368
368
369 COMPONENT SYNC_VALID_BIT
369 COMPONENT SYNC_VALID_BIT
370 GENERIC (
370 GENERIC (
371 NB_FF_OF_SYNC : INTEGER);
371 NB_FF_OF_SYNC : INTEGER);
372 PORT (
372 PORT (
373 clk_in : IN STD_LOGIC;
373 clk_in : IN STD_LOGIC;
374 clk_out : IN STD_LOGIC;
374 clk_out : IN STD_LOGIC;
375 rstn : IN STD_LOGIC;
375 rstn : IN STD_LOGIC;
376 sin : IN STD_LOGIC;
376 sin : IN STD_LOGIC;
377 sout : OUT STD_LOGIC);
377 sout : OUT STD_LOGIC);
378 END COMPONENT;
378 END COMPONENT;
379
379
380 COMPONENT RR_Arbiter_4
380 COMPONENT RR_Arbiter_4
381 PORT (
381 PORT (
382 clk : IN STD_LOGIC;
382 clk : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
384 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
384 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
385 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
385 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
386 END COMPONENT;
386 END COMPONENT;
387
387
388 COMPONENT Clock_Divider is
388 COMPONENT Clock_Divider is
389 generic(N :integer := 10);
389 generic(N :integer := 10);
390 port(
390 port(
391 clk, rst : in std_logic;
391 clk, rst : in std_logic;
392 sclk : out std_logic);
392 sclk : out std_logic);
393 end COMPONENT;
393 end COMPONENT;
394
394
395 END;
395 END;
Show file before | Show file after | Hide comments
@@ -1,25 +1,25
1 general_purpose.vhd
1 general_purpose.vhd
2 ADDRcntr.vhd
2 ADDRcntr.vhd
3 ALU.vhd
3 ALU.vhd
4 Adder.vhd
4 Adder.vhd
5 Clk_Divider2.vhd
5 Clk_Divider2.vhd
6 Clk_divider.vhd
6 Clk_divider.vhd
7 MAC.vhd
7 MAC.vhd
8 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
9 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
10 MAC_MUX2.vhd
11 MAC_REG.vhd
11 MAC_REG.vhd
12 MUX2.vhd
12 MUX2.vhd
13 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
14 Multiplier.vhd
15 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
16 SYNC_FF.vhd
17 Shifter.vhd
17 Shifter.vhd
18 TwoComplementer.vhd
18 TwoComplementer.vhd
19 Clock_Divider.vhd
19 Clock_Divider.vhd
20 lpp_front_to_level.vhd
20 lpp_front_to_level.vhd
21 lpp_front_detection.vhd
21 lpp_front_detection.vhd
22 lpp_front_positive_detection.vhd
22 lpp_front_positive_detection.vhd
23 SYNC_VALID_BIT.vhd
23 SYNC_VALID_BIT.vhd
24 RR_Arbiter_4.vhd
24 RR_Arbiter_4.vhd
25 counter.vhd
25 general_counter.vhd
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@@ -1,91 +1,91
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
6 USE lpp.general_purpose.ALL;
7
7
8 ENTITY coarse_time_counter IS
8 ENTITY coarse_time_counter IS
9 GENERIC (
9 GENERIC (
10 NB_SECOND_DESYNC : INTEGER := 60);
10 NB_SECOND_DESYNC : INTEGER := 60);
11
11
12 PORT (
12 PORT (
13 clk : IN STD_LOGIC;
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15
15
16 tick : IN STD_LOGIC;
16 tick : IN STD_LOGIC;
17 set_TCU : IN STD_LOGIC;
17 set_TCU : IN STD_LOGIC;
18 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
18 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19 CT_add1 : IN STD_LOGIC;
19 CT_add1 : IN STD_LOGIC;
20 fsm_desync : IN STD_LOGIC;
20 fsm_desync : IN STD_LOGIC;
21 FT_max : IN STD_LOGIC;
21 FT_max : IN STD_LOGIC;
22
22
23 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
23 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
24 coarse_time_new : OUT STD_LOGIC
24 coarse_time_new : OUT STD_LOGIC
25
25
26 );
26 );
27
27
28 END coarse_time_counter;
28 END coarse_time_counter;
29
29
30 ARCHITECTURE beh OF coarse_time_counter IS
30 ARCHITECTURE beh OF coarse_time_counter IS
31
31
32 SIGNAL add1_bit31 : STD_LOGIC;
32 SIGNAL add1_bit31 : STD_LOGIC;
33 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
33 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
34 SIGNAL coarse_time_new_counter : STD_LOGIC;
34 SIGNAL coarse_time_new_counter : STD_LOGIC;
35 SIGNAL coarse_time_31 : STD_LOGIC;
35 SIGNAL coarse_time_31 : STD_LOGIC;
36 SIGNAL coarse_time_31_reg : STD_LOGIC;
36 SIGNAL coarse_time_31_reg : STD_LOGIC;
37
37
38 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
38 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
39 BEGIN -- beh
39 BEGIN -- beh
40
40
41 counter_1 : counter
41 counter_1 : general_counter
42 GENERIC MAP (
42 GENERIC MAP (
43 CYCLIC => '1',
43 CYCLIC => '1',
44 NB_BITS_COUNTER => 31)
44 NB_BITS_COUNTER => 31)
45 PORT MAP (
45 PORT MAP (
46 clk => clk,
46 clk => clk,
47 rstn => rstn,
47 rstn => rstn,
48 RST_VALUE => (OTHERS => '0'),
48 RST_VALUE => (OTHERS => '0'),
49 MAX_VALUE => "111" & X"FFFFFFF" ,
49 MAX_VALUE => "111" & X"FFFFFFF" ,
50 set => set_TCU,
50 set => set_TCU,
51 set_value => set_TCU_value,
51 set_value => set_TCU_value,
52 add1 => CT_add1,
52 add1 => CT_add1,
53 counter => coarse_time(30 DOWNTO 0));
53 counter => coarse_time(30 DOWNTO 0));
54
54
55
55
56 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
56 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
57
57
58 counter_2 : counter
58 counter_2 : general_counter
59 GENERIC MAP (
59 GENERIC MAP (
60 CYCLIC => '0',
60 CYCLIC => '0',
61 NB_BITS_COUNTER => 6)
61 NB_BITS_COUNTER => 6)
62 PORT MAP (
62 PORT MAP (
63 clk => clk,
63 clk => clk,
64 rstn => rstn,
64 rstn => rstn,
65 RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
65 RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
66 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
66 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
67 set => tick,
67 set => tick,
68 set_value => (OTHERS => '0'),
68 set_value => (OTHERS => '0'),
69 add1 => add1_bit31,
69 add1 => add1_bit31,
70 counter => nb_second_counter);
70 counter => nb_second_counter);
71
71
72 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
72 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
73 coarse_time(31) <= coarse_time_31;
73 coarse_time(31) <= coarse_time_31;
74 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
74 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
75
75
76 PROCESS (clk, rstn)
76 PROCESS (clk, rstn)
77 BEGIN -- PROCESS
77 BEGIN -- PROCESS
78 IF rstn = '0' THEN -- asynchronous reset (active low)
78 IF rstn = '0' THEN -- asynchronous reset (active low)
79 coarse_time_new_counter <= '0';
79 coarse_time_new_counter <= '0';
80 coarse_time_31_reg <= '0';
80 coarse_time_31_reg <= '0';
81 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
81 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
82 coarse_time_31_reg <= coarse_time_31;
82 coarse_time_31_reg <= coarse_time_31;
83 IF set_TCU = '1' OR CT_add1 = '1' THEN
83 IF set_TCU = '1' OR CT_add1 = '1' THEN
84 coarse_time_new_counter <= '1';
84 coarse_time_new_counter <= '1';
85 ELSE
85 ELSE
86 coarse_time_new_counter <= '0';
86 coarse_time_new_counter <= '0';
87 END IF;
87 END IF;
88 END IF;
88 END IF;
89 END PROCESS;
89 END PROCESS;
90
90
91 END beh;
91 END beh;
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@@ -1,93 +1,93
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.general_purpose.ALL;
6 USE lpp.general_purpose.ALL;
7
7
8 ENTITY fine_time_counter IS
8 ENTITY fine_time_counter IS
9
9
10 GENERIC (
10 GENERIC (
11 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
11 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
12 FIRST_DIVISION : INTEGER := 374
12 FIRST_DIVISION : INTEGER := 374
13 );
13 );
14
14
15 PORT (
15 PORT (
16 clk : IN STD_LOGIC;
16 clk : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
17 rstn : IN STD_LOGIC;
18 --
18 --
19 tick : IN STD_LOGIC;
19 tick : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
20 fsm_transition : IN STD_LOGIC;
21
21
22 FT_max : OUT STD_LOGIC;
22 FT_max : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
23 FT_half : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
24 FT_wait : OUT STD_LOGIC;
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
25 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
26 fine_time_new : OUT STD_LOGIC
26 fine_time_new : OUT STD_LOGIC
27 );
27 );
28
28
29 END fine_time_counter;
29 END fine_time_counter;
30
30
31 ARCHITECTURE beh OF fine_time_counter IS
31 ARCHITECTURE beh OF fine_time_counter IS
32
32
33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
33 SIGNAL new_ft_counter : STD_LOGIC_VECTOR(8 DOWNTO 0);
34 SIGNAL new_ft : STD_LOGIC;
34 SIGNAL new_ft : STD_LOGIC;
35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
35 SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
36
36
37 -- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
37 -- CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
38
38
39 BEGIN -- beh
39 BEGIN -- beh
40
40
41
41
42
42
43 counter_1 : counter
43 counter_1 : general_counter
44 GENERIC MAP (
44 GENERIC MAP (
45 CYCLIC => '1',
45 CYCLIC => '1',
46 NB_BITS_COUNTER => 9)
46 NB_BITS_COUNTER => 9)
47 PORT MAP (
47 PORT MAP (
48 clk => clk,
48 clk => clk,
49 rstn => rstn,
49 rstn => rstn,
50 RST_VALUE => (OTHERS => '0'),
50 RST_VALUE => (OTHERS => '0'),
51 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
51 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
52 set => tick,
52 set => tick,
53 set_value => (OTHERS => '0'),
53 set_value => (OTHERS => '0'),
54 add1 => '1',
54 add1 => '1',
55 counter => new_ft_counter);
55 counter => new_ft_counter);
56
56
57 new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
57 new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
58
58
59 counter_2 : counter
59 counter_2 : general_counter
60 GENERIC MAP (
60 GENERIC MAP (
61 CYCLIC => '1',
61 CYCLIC => '1',
62 NB_BITS_COUNTER => 16)
62 NB_BITS_COUNTER => 16)
63 PORT MAP (
63 PORT MAP (
64 clk => clk,
64 clk => clk,
65 rstn => rstn,
65 rstn => rstn,
66 RST_VALUE => (OTHERS => '0'),
66 RST_VALUE => (OTHERS => '0'),
67 MAX_VALUE => X"FFFF",
67 MAX_VALUE => X"FFFF",
68 set => tick,
68 set => tick,
69 set_value => (OTHERS => '0'),
69 set_value => (OTHERS => '0'),
70 add1 => new_ft,
70 add1 => new_ft,
71 counter => fine_time_counter);
71 counter => fine_time_counter);
72
72
73 FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
73 FT_max <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
74 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
74 FT_half <= '1' WHEN fine_time_counter > X"7FFF" ELSE '0';
75 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
75 FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME ELSE '0';
76
76
77 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
77 fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
78
78
79 PROCESS (clk, rstn)
79 PROCESS (clk, rstn)
80 BEGIN -- PROCESS
80 BEGIN -- PROCESS
81 IF rstn = '0' THEN -- asynchronous reset (active low)
81 IF rstn = '0' THEN -- asynchronous reset (active low)
82 fine_time_new <= '0';
82 fine_time_new <= '0';
83 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
83 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
84 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
84 IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
85 fine_time_new <= '1';
85 fine_time_new <= '1';
86 ELSE
86 ELSE
87 fine_time_new <= '0';
87 fine_time_new <= '0';
88 END IF;
88 END IF;
89 END IF;
89 END IF;
90 END PROCESS;
90 END PROCESS;
91
91
92 END beh;
92 END beh;
93
93
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@@ -1,386 +1,394
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 LIBRARY techmap;
39 LIBRARY techmap;
40 USE techmap.gencomp.ALL;
40 USE techmap.gencomp.ALL;
41
41
42
42
43 ENTITY lpp_lfr_ms_fsmdma IS
43 ENTITY lpp_lfr_ms_fsmdma IS
44 PORT (
44 PORT (
45 -- AMBA AHB system signals
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
48
49 --TIME
49 --TIME
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51
51
52 -- fifo interface
52 -- fifo interface
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 fifo_empty : IN STD_LOGIC;
54 fifo_empty : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
56
56
57 -- header
57 -- header
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 header_val : IN STD_LOGIC;
59 header_val : IN STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
61
61
62 -- DMA
62 -- DMA
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_valid : OUT STD_LOGIC;
65 dma_valid : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
69
69
70 -- Reg out
70 -- Reg out
71 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_0 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78
78
79 -- Reg In
79 -- Reg In
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
86
86
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93
93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
98
98
99 );
99 );
100 END;
100 END;
101
101
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -- SIGNAL DMAIn : DMA_In_Type;
104 -- SIGNAL DMAIn : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 TYPE state_DMAWriteBurst IS (IDLE,
112 TYPE state_DMAWriteBurst IS (IDLE,
113 CHECK_COMPONENT_TYPE,
113 CHECK_COMPONENT_TYPE,
114 WRITE_COARSE_TIME,
114 WRITE_COARSE_TIME,
115 WRITE_FINE_TIME,
115 WRITE_FINE_TIME,
116 TRASH_FIFO,
116 TRASH_FIFO,
117 SEND_DATA,
117 SEND_DATA,
118 WAIT_DATA_ACK,
118 WAIT_DATA_ACK
119 CHECK_LENGTH
120 );
119 );
121 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
120 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
122
121
123 -- SIGNAL nbSend : INTEGER;
122 -- SIGNAL nbSend : INTEGER;
124 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
123 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
124 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL header_check_ok : STD_LOGIC;
126 SIGNAL header_check_ok : STD_LOGIC;
128 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL send_matrix : STD_LOGIC;
128 SIGNAL send_matrix : STD_LOGIC;
130 -- SIGNAL request : STD_LOGIC;
129 -- SIGNAL request : STD_LOGIC;
131 -- SIGNAL remaining_data_request : INTEGER;
130 -- SIGNAL remaining_data_request : INTEGER;
132 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
135 SIGNAL header_select : STD_LOGIC;
134 SIGNAL header_select : STD_LOGIC;
136
135
137 SIGNAL header_send : STD_LOGIC;
136 SIGNAL header_send : STD_LOGIC;
138 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL header_send_ok : STD_LOGIC;
138 SIGNAL header_send_ok : STD_LOGIC;
140 SIGNAL header_send_ko : STD_LOGIC;
139 SIGNAL header_send_ko : STD_LOGIC;
141
140
142 SIGNAL component_send : STD_LOGIC;
141 SIGNAL component_send : STD_LOGIC;
143 SIGNAL component_send_ok : STD_LOGIC;
142 SIGNAL component_send_ok : STD_LOGIC;
144 SIGNAL component_send_ko : STD_LOGIC;
143 SIGNAL component_send_ko : STD_LOGIC;
145 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
146 SIGNAL fifo_ren_trash : STD_LOGIC;
145 SIGNAL fifo_ren_trash : STD_LOGIC;
147 SIGNAL component_fifo_ren : STD_LOGIC;
146 SIGNAL component_fifo_ren : STD_LOGIC;
148
147
149 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
150 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
152
151
152 -----------------------------------------------------------------------------
153 SIGNAL log_empty_fifo : STD_LOGIC;
154
153 BEGIN
155 BEGIN
154
156
155 debug_reg <= debug_reg_s;
157 debug_reg <= debug_reg_s;
156
158
157
159
158 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
160 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
159 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
161 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
160 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
162 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
161 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
163 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
162 '0';
164 '0';
163
165
164 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
166 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
165 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
167 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
166 '1' WHEN component_type = component_type_pre + "0001" ELSE
168 '1' WHEN component_type = component_type_pre + "0001" ELSE
167 '0';
169 '0';
168
170
169 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
171 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
170 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
172 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
171 addr_matrix_f1 WHEN matrix_type = "10" ELSE
173 addr_matrix_f1 WHEN matrix_type = "10" ELSE
172 addr_matrix_f2 WHEN matrix_type = "11" ELSE
174 addr_matrix_f2 WHEN matrix_type = "11" ELSE
173 (OTHERS => '0');
175 (OTHERS => '0');
174
176
175 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
176 -- DMA control
178 -- DMA control
177 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
178 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
180 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
179 BEGIN -- PROCESS DMAWriteBurst_p
181 BEGIN -- PROCESS DMAWriteBurst_p
180 IF HRESETn = '0' THEN -- asynchronous reset (active low)
182 IF HRESETn = '0' THEN -- asynchronous reset (active low)
181 matrix_type <= (OTHERS => '0');
183 matrix_type <= (OTHERS => '0');
182 component_type <= (OTHERS => '0');
184 component_type <= (OTHERS => '0');
183 state <= IDLE;
185 state <= IDLE;
184 header_ack <= '0';
186 header_ack <= '0';
185 ready_matrix_f0_0 <= '0';
187 ready_matrix_f0_0 <= '0';
186 ready_matrix_f0_1 <= '0';
188 ready_matrix_f0_1 <= '0';
187 ready_matrix_f1 <= '0';
189 ready_matrix_f1 <= '0';
188 ready_matrix_f2 <= '0';
190 ready_matrix_f2 <= '0';
189 error_anticipating_empty_fifo <= '0';
191 error_anticipating_empty_fifo <= '0';
190 error_bad_component_error <= '0';
192 error_bad_component_error <= '0';
191 component_type_pre <= "0000";
193 component_type_pre <= "0000";
192 fifo_ren_trash <= '1';
194 fifo_ren_trash <= '1';
193 component_send <= '0';
195 component_send <= '0';
194 address <= (OTHERS => '0');
196 address <= (OTHERS => '0');
195 header_select <= '0';
197 header_select <= '0';
196 header_send <= '0';
198 header_send <= '0';
197 header_data <= (OTHERS => '0');
199 header_data <= (OTHERS => '0');
198 fine_time_reg <= (OTHERS => '0');
200 fine_time_reg <= (OTHERS => '0');
199
201
200 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
202 debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
201
203
204 log_empty_fifo <= '0';
205
202 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
206 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
203 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
207 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
204
208
205 CASE state IS
209 CASE state IS
206 WHEN IDLE =>
210 WHEN IDLE =>
207 debug_reg_s(2 DOWNTO 0) <= "000";
211 debug_reg_s(2 DOWNTO 0) <= "000";
208
212
209 matrix_type <= header(1 DOWNTO 0);
213 matrix_type <= header(1 DOWNTO 0);
210 --component_type <= header(5 DOWNTO 2);
214 --component_type <= header(5 DOWNTO 2);
211
215
212 ready_matrix_f0_0 <= '0';
216 ready_matrix_f0_0 <= '0';
213 ready_matrix_f0_1 <= '0';
217 ready_matrix_f0_1 <= '0';
214 ready_matrix_f1 <= '0';
218 ready_matrix_f1 <= '0';
215 ready_matrix_f2 <= '0';
219 ready_matrix_f2 <= '0';
216 error_bad_component_error <= '0';
220 error_bad_component_error <= '0';
217 header_select <= '1';
221 header_select <= '1';
218 IF header_val = '1' THEN
222 IF header_val = '1' THEN
219 header_ack <= '1';
223 header_ack <= '1';
220 END IF;
224 END IF;
221 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
225 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
222 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
226 debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0);
223 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
227 debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2);
224
228
225 matrix_type <= header(1 DOWNTO 0);
229 matrix_type <= header(1 DOWNTO 0);
226 component_type <= header(5 DOWNTO 2);
230 component_type <= header(5 DOWNTO 2);
227 component_type_pre <= component_type;
231 component_type_pre <= component_type;
228 state <= CHECK_COMPONENT_TYPE;
232 state <= CHECK_COMPONENT_TYPE;
229 END IF;
233 END IF;
234 log_empty_fifo <= '0';
230
235
231 WHEN CHECK_COMPONENT_TYPE =>
236 WHEN CHECK_COMPONENT_TYPE =>
232 debug_reg_s(2 DOWNTO 0) <= "001";
237 debug_reg_s(2 DOWNTO 0) <= "001";
233 header_ack <= '0';
238 header_ack <= '0';
234
239
235 IF header_check_ok = '1' THEN
240 IF header_check_ok = '1' THEN
236 header_send <= '0';
241 header_send <= '0';
237 --
242 --
238 IF component_type = "0000" THEN
243 IF component_type = "0000" THEN
239 address <= address_matrix;
244 address <= address_matrix;
240 CASE matrix_type IS
245 CASE matrix_type IS
241 WHEN "00" => matrix_time_f0_0 <= data_time;
246 WHEN "00" => matrix_time_f0_0 <= data_time;
242 WHEN "01" => matrix_time_f0_1 <= data_time;
247 WHEN "01" => matrix_time_f0_1 <= data_time;
243 WHEN "10" => matrix_time_f1 <= data_time;
248 WHEN "10" => matrix_time_f1 <= data_time;
244 WHEN "11" => matrix_time_f2 <= data_time ;
249 WHEN "11" => matrix_time_f2 <= data_time ;
245 WHEN OTHERS => NULL;
250 WHEN OTHERS => NULL;
246 END CASE;
251 END CASE;
247
252
248 header_data <= data_time(31 DOWNTO 0);
253 header_data <= data_time(31 DOWNTO 0);
249 fine_time_reg <= data_time(47 DOWNTO 32);
254 fine_time_reg <= data_time(47 DOWNTO 32);
250 --state <= WRITE_COARSE_TIME;
255 --state <= WRITE_COARSE_TIME;
251 --header_send <= '1';
256 --header_send <= '1';
252 state <= SEND_DATA;
257 state <= SEND_DATA;
253 header_send <= '0';
258 header_send <= '0';
254 component_send <= '1';
259 component_send <= '1';
255 header_select <= '0';
260 header_select <= '0';
256 ELSE
261 ELSE
257 state <= SEND_DATA;
262 state <= SEND_DATA;
258 END IF;
263 END IF;
259 --
264 --
260 ELSE
265 ELSE
261 error_bad_component_error <= '1';
266 error_bad_component_error <= '1';
262 component_type_pre <= "0000";
267 component_type_pre <= "0000";
263 state <= TRASH_FIFO;
268 state <= TRASH_FIFO;
264 END IF;
269 END IF;
265
270
266 --WHEN WRITE_COARSE_TIME =>
271 --WHEN WRITE_COARSE_TIME =>
267 -- debug_reg_s(2 DOWNTO 0) <= "010";
272 -- debug_reg_s(2 DOWNTO 0) <= "010";
268
273
269 -- header_ack <= '0';
274 -- header_ack <= '0';
270
275
271 -- IF dma_ren = '0' THEN
276 -- IF dma_ren = '0' THEN
272 -- header_send <= '0';
277 -- header_send <= '0';
273 -- ELSE
278 -- ELSE
274 -- header_send <= header_send;
279 -- header_send <= header_send;
275 -- END IF;
280 -- END IF;
276
281
277
282
278 -- IF header_send_ko = '1' THEN
283 -- IF header_send_ko = '1' THEN
279 -- header_send <= '0';
284 -- header_send <= '0';
280 -- state <= TRASH_FIFO;
285 -- state <= TRASH_FIFO;
281 -- error_anticipating_empty_fifo <= '1';
286 -- error_anticipating_empty_fifo <= '1';
282 -- -- TODO : error sending header
287 -- -- TODO : error sending header
283 -- ELSIF header_send_ok = '1' THEN
288 -- ELSIF header_send_ok = '1' THEN
284 -- header_send <= '1';
289 -- header_send <= '1';
285 -- header_select <= '1';
290 -- header_select <= '1';
286 -- header_data(15 DOWNTO 0) <= fine_time_reg;
291 -- header_data(15 DOWNTO 0) <= fine_time_reg;
287 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
292 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
288 -- state <= WRITE_FINE_TIME;
293 -- state <= WRITE_FINE_TIME;
289 -- address <= address + 4;
294 -- address <= address + 4;
290 -- END IF;
295 -- END IF;
291
296
292
297
293 --WHEN WRITE_FINE_TIME =>
298 --WHEN WRITE_FINE_TIME =>
294 -- debug_reg_s(2 DOWNTO 0) <= "011";
299 -- debug_reg_s(2 DOWNTO 0) <= "011";
295
300
296 -- header_ack <= '0';
301 -- header_ack <= '0';
297
302
298 -- IF dma_ren = '0' THEN
303 -- IF dma_ren = '0' THEN
299 -- header_send <= '0';
304 -- header_send <= '0';
300 -- ELSE
305 -- ELSE
301 -- header_send <= header_send;
306 -- header_send <= header_send;
302 -- END IF;
307 -- END IF;
303
308
304 -- IF header_send_ko = '1' THEN
309 -- IF header_send_ko = '1' THEN
305 -- header_send <= '0';
310 -- header_send <= '0';
306 -- state <= TRASH_FIFO;
311 -- state <= TRASH_FIFO;
307 -- error_anticipating_empty_fifo <= '1';
312 -- error_anticipating_empty_fifo <= '1';
308 -- -- TODO : error sending header
313 -- -- TODO : error sending header
309 -- ELSIF header_send_ok = '1' THEN
314 -- ELSIF header_send_ok = '1' THEN
310 -- header_send <= '0';
315 -- header_send <= '0';
311 -- header_select <= '0';
316 -- header_select <= '0';
312 -- state <= SEND_DATA;
317 -- state <= SEND_DATA;
313 -- address <= address + 4;
318 -- address <= address + 4;
314 -- END IF;
319 -- END IF;
315
320
316 WHEN TRASH_FIFO =>
321 WHEN TRASH_FIFO =>
317 debug_reg_s(2 DOWNTO 0) <= "100";
322 debug_reg_s(2 DOWNTO 0) <= "100";
318
323
319 header_ack <= '0';
324 header_ack <= '0';
320 error_bad_component_error <= '0';
325 error_bad_component_error <= '0';
321 error_anticipating_empty_fifo <= '0';
326 error_anticipating_empty_fifo <= '0';
322 IF fifo_empty = '1' THEN
327 IF fifo_empty = '1' THEN
323 state <= IDLE;
328 state <= IDLE;
324 fifo_ren_trash <= '1';
329 fifo_ren_trash <= '1';
325 ELSE
330 ELSE
326 fifo_ren_trash <= '0';
331 fifo_ren_trash <= '0';
327 END IF;
332 END IF;
328
333
329 WHEN SEND_DATA =>
334 WHEN SEND_DATA =>
330 header_ack <= '0';
335 header_ack <= '0';
331 debug_reg_s(2 DOWNTO 0) <= "101";
336 debug_reg_s(2 DOWNTO 0) <= "101";
332
337
333 IF fifo_empty = '1' THEN
338 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
334 state <= IDLE;
339 state <= IDLE;
335 IF component_type = "1110" THEN --"1110" -- JC
340 IF component_type = "1110" THEN --"1110" -- JC
336 CASE matrix_type IS
341 CASE matrix_type IS
337 WHEN "00" => ready_matrix_f0_0 <= '1';
342 WHEN "00" => ready_matrix_f0_0 <= '1';
338 WHEN "01" => ready_matrix_f0_1 <= '1';
343 WHEN "01" => ready_matrix_f0_1 <= '1';
339 WHEN "10" => ready_matrix_f1 <= '1';
344 WHEN "10" => ready_matrix_f1 <= '1';
340 WHEN "11" => ready_matrix_f2 <= '1';
345 WHEN "11" => ready_matrix_f2 <= '1';
341 WHEN OTHERS => NULL;
346 WHEN OTHERS => NULL;
342 END CASE;
347 END CASE;
343
348
344 END IF;
349 END IF;
345 ELSE
350 ELSE
346 component_send <= '1';
351 component_send <= '1';
347 address <= address;
352 address <= address;
348 state <= WAIT_DATA_ACK;
353 state <= WAIT_DATA_ACK;
349 END IF;
354 END IF;
350
355
351 WHEN WAIT_DATA_ACK =>
356 WHEN WAIT_DATA_ACK =>
357 log_empty_fifo <= fifo_empty OR log_empty_fifo;
358
352 debug_reg_s(2 DOWNTO 0) <= "110";
359 debug_reg_s(2 DOWNTO 0) <= "110";
353
360
354 component_send <= '0';
361 component_send <= '0';
355 IF component_send_ok = '1' THEN
362 IF component_send_ok = '1' THEN
356 address <= address + 64;
363 address <= address + 64;
357 state <= SEND_DATA;
364 state <= SEND_DATA;
358 ELSIF component_send_ko = '1' THEN
365 ELSIF component_send_ko = '1' THEN
359 error_anticipating_empty_fifo <= '0';
366 error_anticipating_empty_fifo <= '0';
360 state <= TRASH_FIFO;
367 state <= TRASH_FIFO;
361 END IF;
368 END IF;
362
369
363 WHEN CHECK_LENGTH =>
370
364 component_send <= '0';
371 --WHEN CHECK_LENGTH =>
365 debug_reg_s(2 DOWNTO 0) <= "111";
372 -- component_send <= '0';
366 state <= IDLE;
373 -- debug_reg_s(2 DOWNTO 0) <= "111";
374 -- state <= IDLE;
367
375
368 WHEN OTHERS => NULL;
376 WHEN OTHERS => NULL;
369 END CASE;
377 END CASE;
370
378
371 END IF;
379 END IF;
372 END PROCESS DMAWriteFSM_p;
380 END PROCESS DMAWriteFSM_p;
373
381
374 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
382 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
375 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
383 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
376 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
384 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
377 dma_addr <= address;
385 dma_addr <= address;
378 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
386 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
379
387
380 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
388 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
381 component_send_ko <= '0';
389 component_send_ko <= '0';
382
390
383 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
391 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
384 header_send_ko <= '0';
392 header_send_ko <= '0';
385
393
386 END Behavioral;
394 END Behavioral;
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