@@ -0,0 +1,342 | |||||
|
1 | LIBRARY ieee; | |||
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
3 | USE ieee.numeric_std.ALL; | |||
|
4 | ||||
|
5 | LIBRARY lpp; | |||
|
6 | USE lpp.lpp_ad_conv.ALL; | |||
|
7 | USE lpp.iir_filter.ALL; | |||
|
8 | USE lpp.FILTERcfg.ALL; | |||
|
9 | USE lpp.lpp_memory.ALL; | |||
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
11 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
|
12 | USE lpp.lpp_lfr_pkg.ALL; | |||
|
13 | ||||
|
14 | LIBRARY techmap; | |||
|
15 | USE techmap.gencomp.ALL; | |||
|
16 | ||||
|
17 | LIBRARY grlib; | |||
|
18 | USE grlib.amba.ALL; | |||
|
19 | USE grlib.stdlib.ALL; | |||
|
20 | USE grlib.devices.ALL; | |||
|
21 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
22 | ||||
|
23 | ENTITY lpp_lfr IS | |||
|
24 | GENERIC ( | |||
|
25 | Mem_use : INTEGER := use_RAM; | |||
|
26 | nb_burst_available_size : INTEGER := 11; | |||
|
27 | nb_snapshot_param_size : INTEGER := 11; | |||
|
28 | delta_snapshot_size : INTEGER := 16; | |||
|
29 | delta_f2_f0_size : INTEGER := 10; | |||
|
30 | delta_f2_f1_size : INTEGER := 10; | |||
|
31 | ||||
|
32 | pindex : INTEGER := 4; | |||
|
33 | paddr : INTEGER := 4; | |||
|
34 | pmask : INTEGER := 16#fff#; | |||
|
35 | pirq_ms : INTEGER := 0; | |||
|
36 | pirq_wfp : INTEGER := 1; | |||
|
37 | ||||
|
38 | hindex_wfp : INTEGER := 2; | |||
|
39 | hindex_ms : INTEGER := 3 | |||
|
40 | ||||
|
41 | ); | |||
|
42 | PORT ( | |||
|
43 | clk : IN STD_LOGIC; | |||
|
44 | rstn : IN STD_LOGIC; | |||
|
45 | -- | |||
|
46 | sample_B : IN Samples14v(2 DOWNTO 0); | |||
|
47 | sample_E : IN Samples14v(4 DOWNTO 0); | |||
|
48 | sample_val : IN STD_LOGIC; | |||
|
49 | -- | |||
|
50 | apbi : IN apb_slv_in_type; | |||
|
51 | apbo : OUT apb_slv_out_type; | |||
|
52 | -- | |||
|
53 | ahbi_wfp : IN AHB_Mst_In_Type; | |||
|
54 | ahbo_wfp : OUT AHB_Mst_Out_Type; | |||
|
55 | -- | |||
|
56 | ahbi_ms : IN AHB_Mst_In_Type; | |||
|
57 | ahbo_ms : OUT AHB_Mst_Out_Type; | |||
|
58 | -- | |||
|
59 | coarse_time_0 : IN STD_LOGIC; | |||
|
60 | -- | |||
|
61 | data_shaping_BW : OUT STD_LOGIC | |||
|
62 | ); | |||
|
63 | END lpp_lfr; | |||
|
64 | ||||
|
65 | ARCHITECTURE beh OF lpp_lfr IS | |||
|
66 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |||
|
67 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |||
|
68 | -- | |||
|
69 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |||
|
70 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |||
|
71 | SIGNAL data_shaping_R0 : STD_LOGIC; | |||
|
72 | SIGNAL data_shaping_R1 : STD_LOGIC; | |||
|
73 | -- | |||
|
74 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
75 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
76 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
77 | -- | |||
|
78 | SIGNAL sample_f0_val : STD_LOGIC; | |||
|
79 | SIGNAL sample_f1_val : STD_LOGIC; | |||
|
80 | SIGNAL sample_f2_val : STD_LOGIC; | |||
|
81 | SIGNAL sample_f3_val : STD_LOGIC; | |||
|
82 | -- | |||
|
83 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
84 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
85 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
86 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
87 | -- | |||
|
88 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
89 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
90 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
91 | ||||
|
92 | -- SM | |||
|
93 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |||
|
94 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |||
|
95 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |||
|
96 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |||
|
97 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |||
|
98 | SIGNAL error_bad_component_error : STD_LOGIC; | |||
|
99 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
100 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |||
|
101 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |||
|
102 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |||
|
103 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |||
|
104 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |||
|
105 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |||
|
106 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |||
|
107 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |||
|
108 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
109 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
110 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
111 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
112 | ||||
|
113 | -- WFP | |||
|
114 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
115 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
116 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
117 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
118 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
119 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
120 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
121 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
122 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
123 | SIGNAL enable_f0 : STD_LOGIC; | |||
|
124 | SIGNAL enable_f1 : STD_LOGIC; | |||
|
125 | SIGNAL enable_f2 : STD_LOGIC; | |||
|
126 | SIGNAL enable_f3 : STD_LOGIC; | |||
|
127 | SIGNAL burst_f0 : STD_LOGIC; | |||
|
128 | SIGNAL burst_f1 : STD_LOGIC; | |||
|
129 | SIGNAL burst_f2 : STD_LOGIC; | |||
|
130 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
131 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
132 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
133 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
134 | ||||
|
135 | -- | |||
|
136 | SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0); | |||
|
137 | SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |||
|
138 | SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |||
|
139 | SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |||
|
140 | SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; | |||
|
141 | ||||
|
142 | SIGNAL val_f0_wfp : STD_LOGIC; | |||
|
143 | SIGNAL val_f1_wfp : STD_LOGIC; | |||
|
144 | SIGNAL val_f2_wfp : STD_LOGIC; | |||
|
145 | SIGNAL val_f3_wfp : STD_LOGIC; | |||
|
146 | BEGIN | |||
|
147 | ||||
|
148 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |||
|
149 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |||
|
150 | ||||
|
151 | all_channel: FOR i IN 7 DOWNTO 0 GENERATE | |||
|
152 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |||
|
153 | END GENERATE all_channel; | |||
|
154 | ||||
|
155 | ----------------------------------------------------------------------------- | |||
|
156 | lpp_lfr_filter_1 : lpp_lfr_filter | |||
|
157 | GENERIC MAP ( | |||
|
158 | Mem_use => Mem_use) | |||
|
159 | PORT MAP ( | |||
|
160 | sample => sample_s, | |||
|
161 | sample_val => sample_val, | |||
|
162 | clk => clk, | |||
|
163 | rstn => rstn, | |||
|
164 | data_shaping_SP0 => data_shaping_SP0, | |||
|
165 | data_shaping_SP1 => data_shaping_SP1, | |||
|
166 | data_shaping_R0 => data_shaping_R0, | |||
|
167 | data_shaping_R1 => data_shaping_R1, | |||
|
168 | sample_f0_val => sample_f0_val, | |||
|
169 | sample_f1_val => sample_f1_val, | |||
|
170 | sample_f2_val => sample_f2_val, | |||
|
171 | sample_f3_val => sample_f3_val, | |||
|
172 | sample_f0_wdata => sample_f0_data, | |||
|
173 | sample_f1_wdata => sample_f1_data, | |||
|
174 | sample_f2_wdata => sample_f2_data, | |||
|
175 | sample_f3_wdata => sample_f3_data); | |||
|
176 | ||||
|
177 | ----------------------------------------------------------------------------- | |||
|
178 | lpp_top_apbreg_1 : lpp_lfr_apbreg | |||
|
179 | GENERIC MAP ( | |||
|
180 | nb_burst_available_size => nb_burst_available_size, | |||
|
181 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
182 | delta_snapshot_size => delta_snapshot_size, | |||
|
183 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
184 | delta_f2_f1_size => delta_f2_f1_size, | |||
|
185 | pindex => pindex, | |||
|
186 | paddr => paddr, | |||
|
187 | pmask => pmask, | |||
|
188 | pirq_ms => pirq_ms, | |||
|
189 | pirq_wfp => pirq_wfp) | |||
|
190 | PORT MAP ( | |||
|
191 | HCLK => clk, | |||
|
192 | HRESETn => rstn, | |||
|
193 | apbi => apbi, | |||
|
194 | apbo => apbo, | |||
|
195 | ||||
|
196 | ready_matrix_f0_0 => ready_matrix_f0_0, | |||
|
197 | ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
198 | ready_matrix_f1 => ready_matrix_f1, | |||
|
199 | ready_matrix_f2 => ready_matrix_f2, | |||
|
200 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
|
201 | error_bad_component_error => error_bad_component_error, | |||
|
202 | debug_reg => debug_reg, | |||
|
203 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
|
204 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
|
205 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
206 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
207 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
|
208 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
209 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
210 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
211 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
212 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
213 | addr_matrix_f1 => addr_matrix_f1, | |||
|
214 | addr_matrix_f2 => addr_matrix_f2, | |||
|
215 | ||||
|
216 | status_full => status_full, | |||
|
217 | status_full_ack => status_full_ack, | |||
|
218 | status_full_err => status_full_err, | |||
|
219 | status_new_err => status_new_err, | |||
|
220 | data_shaping_BW => data_shaping_BW, | |||
|
221 | data_shaping_SP0 => data_shaping_SP0, | |||
|
222 | data_shaping_SP1 => data_shaping_SP1, | |||
|
223 | data_shaping_R0 => data_shaping_R0, | |||
|
224 | data_shaping_R1 => data_shaping_R1, | |||
|
225 | delta_snapshot => delta_snapshot, | |||
|
226 | delta_f2_f1 => delta_f2_f1, | |||
|
227 | delta_f2_f0 => delta_f2_f0, | |||
|
228 | nb_burst_available => nb_burst_available, | |||
|
229 | nb_snapshot_param => nb_snapshot_param, | |||
|
230 | enable_f0 => enable_f0, | |||
|
231 | enable_f1 => enable_f1, | |||
|
232 | enable_f2 => enable_f2, | |||
|
233 | enable_f3 => enable_f3, | |||
|
234 | burst_f0 => burst_f0, | |||
|
235 | burst_f1 => burst_f1, | |||
|
236 | burst_f2 => burst_f2, | |||
|
237 | addr_data_f0 => addr_data_f0, | |||
|
238 | addr_data_f1 => addr_data_f1, | |||
|
239 | addr_data_f2 => addr_data_f2, | |||
|
240 | addr_data_f3 => addr_data_f3); | |||
|
241 | ||||
|
242 | ----------------------------------------------------------------------------- | |||
|
243 | lpp_waveform_1: lpp_waveform | |||
|
244 | GENERIC MAP ( | |||
|
245 | hindex => hindex_wfp, | |||
|
246 | tech => inferred, | |||
|
247 | data_size => 160, | |||
|
248 | nb_burst_available_size => nb_burst_available_size, | |||
|
249 | nb_snapshot_param_size => nb_snapshot_param_size, | |||
|
250 | delta_snapshot_size => delta_snapshot_size, | |||
|
251 | delta_f2_f0_size => delta_f2_f0_size, | |||
|
252 | delta_f2_f1_size => delta_f2_f1_size) | |||
|
253 | PORT MAP ( | |||
|
254 | clk => clk, | |||
|
255 | rstn => rstn, | |||
|
256 | AHB_Master_In => ahbi_wfp, | |||
|
257 | AHB_Master_Out => ahbo_wfp, | |||
|
258 | coarse_time_0 => coarse_time_0, | |||
|
259 | ||||
|
260 | delta_snapshot => delta_snapshot, | |||
|
261 | delta_f2_f1 => delta_f2_f1, | |||
|
262 | delta_f2_f0 => delta_f2_f0, | |||
|
263 | enable_f0 => enable_f0, | |||
|
264 | enable_f1 => enable_f1, | |||
|
265 | enable_f2 => enable_f2, | |||
|
266 | enable_f3 => enable_f3, | |||
|
267 | burst_f0 => burst_f0, | |||
|
268 | burst_f1 => burst_f1, | |||
|
269 | burst_f2 => burst_f2, | |||
|
270 | nb_burst_available => nb_burst_available, | |||
|
271 | nb_snapshot_param => nb_snapshot_param, | |||
|
272 | status_full => status_full, | |||
|
273 | status_full_ack => status_full_ack, | |||
|
274 | status_full_err => status_full_err, | |||
|
275 | status_new_err => status_new_err, | |||
|
276 | addr_data_f0 => addr_data_f0, | |||
|
277 | addr_data_f1 => addr_data_f1, | |||
|
278 | addr_data_f2 => addr_data_f2, | |||
|
279 | addr_data_f3 => addr_data_f3, | |||
|
280 | ||||
|
281 | data_f0_in => data_f0_wfp, | |||
|
282 | data_f1_in => data_f1_wfp, | |||
|
283 | data_f2_in => data_f2_wfp, | |||
|
284 | data_f3_in => data_f3_wfp, | |||
|
285 | data_f0_in_valid => sample_f0_val, | |||
|
286 | data_f1_in_valid => sample_f1_val, | |||
|
287 | data_f2_in_valid => sample_f2_val, | |||
|
288 | data_f3_in_valid => sample_f3_val); | |||
|
289 | ||||
|
290 | data_f0_wfp <= sample_f0_data & time_info; | |||
|
291 | data_f1_wfp <= sample_f1_data & time_info; | |||
|
292 | data_f2_wfp <= sample_f2_data & time_info; | |||
|
293 | data_f3_wfp <= sample_f3_data & time_info; | |||
|
294 | ||||
|
295 | ----------------------------------------------------------------------------- | |||
|
296 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |||
|
297 | NOT(sample_f0_val) & NOT(sample_f0_val) ; | |||
|
298 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |||
|
299 | NOT(sample_f1_val) & NOT(sample_f1_val) ; | |||
|
300 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |||
|
301 | NOT(sample_f3_val) & NOT(sample_f3_val) ; | |||
|
302 | ||||
|
303 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |||
|
304 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |||
|
305 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |||
|
306 | ----------------------------------------------------------------------------- | |||
|
307 | lpp_lfr_ms_1: lpp_lfr_ms | |||
|
308 | GENERIC MAP ( | |||
|
309 | hindex => hindex_ms) | |||
|
310 | PORT MAP ( | |||
|
311 | clk => clk, | |||
|
312 | rstn => rstn, | |||
|
313 | sample_f0_wen => sample_f0_wen, | |||
|
314 | sample_f0_wdata => sample_f0_wdata, | |||
|
315 | sample_f1_wen => sample_f1_wen, | |||
|
316 | sample_f1_wdata => sample_f1_wdata, | |||
|
317 | sample_f3_wen => sample_f3_wen, | |||
|
318 | sample_f3_wdata => sample_f3_wdata, | |||
|
319 | AHB_Master_In => ahbi_ms, | |||
|
320 | AHB_Master_Out => ahbo_ms, | |||
|
321 | ||||
|
322 | ready_matrix_f0_0 => ready_matrix_f0_0, | |||
|
323 | ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
324 | ready_matrix_f1 => ready_matrix_f1, | |||
|
325 | ready_matrix_f2 => ready_matrix_f2, | |||
|
326 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
|
327 | error_bad_component_error => error_bad_component_error, | |||
|
328 | debug_reg => debug_reg, | |||
|
329 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
|
330 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
|
331 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
332 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
333 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
|
334 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
335 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
336 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
337 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
338 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
339 | addr_matrix_f1 => addr_matrix_f1, | |||
|
340 | addr_matrix_f2 => addr_matrix_f2); | |||
|
341 | ||||
|
342 | END beh; No newline at end of file |
@@ -0,0 +1,407 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
22 | ---------------------------------------------------------------------------- | |||
|
23 | LIBRARY ieee; | |||
|
24 | USE ieee.std_logic_1164.ALL; | |||
|
25 | USE ieee.numeric_std.ALL; | |||
|
26 | LIBRARY grlib; | |||
|
27 | USE grlib.amba.ALL; | |||
|
28 | USE grlib.stdlib.ALL; | |||
|
29 | USE grlib.devices.ALL; | |||
|
30 | LIBRARY lpp; | |||
|
31 | USE lpp.lpp_amba.ALL; | |||
|
32 | USE lpp.apb_devices_list.ALL; | |||
|
33 | USE lpp.lpp_memory.ALL; | |||
|
34 | LIBRARY techmap; | |||
|
35 | USE techmap.gencomp.ALL; | |||
|
36 | ||||
|
37 | ENTITY lpp_lfr_apbreg IS | |||
|
38 | GENERIC ( | |||
|
39 | nb_burst_available_size : INTEGER := 11; | |||
|
40 | nb_snapshot_param_size : INTEGER := 11; | |||
|
41 | delta_snapshot_size : INTEGER := 16; | |||
|
42 | delta_f2_f0_size : INTEGER := 10; | |||
|
43 | delta_f2_f1_size : INTEGER := 10; | |||
|
44 | ||||
|
45 | pindex : INTEGER := 4; | |||
|
46 | paddr : INTEGER := 4; | |||
|
47 | pmask : INTEGER := 16#fff#; | |||
|
48 | pirq_ms : INTEGER := 0; | |||
|
49 | pirq_wfp : INTEGER := 1); | |||
|
50 | PORT ( | |||
|
51 | -- AMBA AHB system signals | |||
|
52 | HCLK : IN STD_ULOGIC; | |||
|
53 | HRESETn : IN STD_ULOGIC; | |||
|
54 | ||||
|
55 | -- AMBA APB Slave Interface | |||
|
56 | apbi : IN apb_slv_in_type; | |||
|
57 | apbo : OUT apb_slv_out_type; | |||
|
58 | ||||
|
59 | --------------------------------------------------------------------------- | |||
|
60 | -- Spectral Matrix Reg | |||
|
61 | -- IN | |||
|
62 | ready_matrix_f0_0 : IN STD_LOGIC; | |||
|
63 | ready_matrix_f0_1 : IN STD_LOGIC; | |||
|
64 | ready_matrix_f1 : IN STD_LOGIC; | |||
|
65 | ready_matrix_f2 : IN STD_LOGIC; | |||
|
66 | error_anticipating_empty_fifo : IN STD_LOGIC; | |||
|
67 | error_bad_component_error : IN STD_LOGIC; | |||
|
68 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
69 | ||||
|
70 | -- OUT | |||
|
71 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |||
|
72 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |||
|
73 | status_ready_matrix_f1 : OUT STD_LOGIC; | |||
|
74 | status_ready_matrix_f2 : OUT STD_LOGIC; | |||
|
75 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
|
76 | status_error_bad_component_error : OUT STD_LOGIC; | |||
|
77 | ||||
|
78 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |||
|
79 | config_active_interruption_onError : OUT STD_LOGIC; | |||
|
80 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
81 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
82 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
83 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
84 | --------------------------------------------------------------------------- | |||
|
85 | --------------------------------------------------------------------------- | |||
|
86 | -- WaveForm picker Reg | |||
|
87 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
88 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
89 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
90 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
91 | ||||
|
92 | -- OUT | |||
|
93 | data_shaping_BW : OUT STD_LOGIC; | |||
|
94 | data_shaping_SP0 : OUT STD_LOGIC; | |||
|
95 | data_shaping_SP1 : OUT STD_LOGIC; | |||
|
96 | data_shaping_R0 : OUT STD_LOGIC; | |||
|
97 | data_shaping_R1 : OUT STD_LOGIC; | |||
|
98 | ||||
|
99 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
100 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
101 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
102 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
103 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
104 | ||||
|
105 | enable_f0 : OUT STD_LOGIC; | |||
|
106 | enable_f1 : OUT STD_LOGIC; | |||
|
107 | enable_f2 : OUT STD_LOGIC; | |||
|
108 | enable_f3 : OUT STD_LOGIC; | |||
|
109 | ||||
|
110 | burst_f0 : OUT STD_LOGIC; | |||
|
111 | burst_f1 : OUT STD_LOGIC; | |||
|
112 | burst_f2 : OUT STD_LOGIC; | |||
|
113 | ||||
|
114 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
115 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
116 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
117 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
118 | ||||
|
119 | --------------------------------------------------------------------------- | |||
|
120 | ); | |||
|
121 | ||||
|
122 | END lpp_lfr_apbreg; | |||
|
123 | ||||
|
124 | ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
125 | ||||
|
126 | CONSTANT REVISION : INTEGER := 1; | |||
|
127 | ||||
|
128 | CONSTANT pconfig : apb_config_type := ( | |||
|
129 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq_wfp), | |||
|
130 | 1 => apb_iobar(paddr, pmask)); | |||
|
131 | ||||
|
132 | TYPE lpp_SpectralMatrix_regs IS RECORD | |||
|
133 | config_active_interruption_onNewMatrix : STD_LOGIC; | |||
|
134 | config_active_interruption_onError : STD_LOGIC; | |||
|
135 | status_ready_matrix_f0_0 : STD_LOGIC; | |||
|
136 | status_ready_matrix_f0_1 : STD_LOGIC; | |||
|
137 | status_ready_matrix_f1 : STD_LOGIC; | |||
|
138 | status_ready_matrix_f2 : STD_LOGIC; | |||
|
139 | status_error_anticipating_empty_fifo : STD_LOGIC; | |||
|
140 | status_error_bad_component_error : STD_LOGIC; | |||
|
141 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
142 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
143 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
144 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
145 | END RECORD; | |||
|
146 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; | |||
|
147 | ||||
|
148 | TYPE lpp_WaveformPicker_regs IS RECORD | |||
|
149 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
150 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
151 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
152 | data_shaping_BW : STD_LOGIC; | |||
|
153 | data_shaping_SP0 : STD_LOGIC; | |||
|
154 | data_shaping_SP1 : STD_LOGIC; | |||
|
155 | data_shaping_R0 : STD_LOGIC; | |||
|
156 | data_shaping_R1 : STD_LOGIC; | |||
|
157 | delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
158 | delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
159 | delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
160 | nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
161 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
162 | enable_f0 : STD_LOGIC; | |||
|
163 | enable_f1 : STD_LOGIC; | |||
|
164 | enable_f2 : STD_LOGIC; | |||
|
165 | enable_f3 : STD_LOGIC; | |||
|
166 | burst_f0 : STD_LOGIC; | |||
|
167 | burst_f1 : STD_LOGIC; | |||
|
168 | burst_f2 : STD_LOGIC; | |||
|
169 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
170 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
171 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
172 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
173 | END RECORD; | |||
|
174 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |||
|
175 | ||||
|
176 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
177 | ||||
|
178 | BEGIN -- beh | |||
|
179 | ||||
|
180 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; | |||
|
181 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |||
|
182 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |||
|
183 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |||
|
184 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |||
|
185 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |||
|
186 | ||||
|
187 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; | |||
|
188 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; | |||
|
189 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; | |||
|
190 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |||
|
191 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; | |||
|
192 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; | |||
|
193 | ||||
|
194 | ||||
|
195 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; | |||
|
196 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; | |||
|
197 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; | |||
|
198 | data_shaping_R0 <= reg_wp.data_shaping_R0; | |||
|
199 | data_shaping_R1 <= reg_wp.data_shaping_R1; | |||
|
200 | ||||
|
201 | delta_snapshot <= reg_wp.delta_snapshot; | |||
|
202 | delta_f2_f1 <= reg_wp.delta_f2_f1; | |||
|
203 | delta_f2_f0 <= reg_wp.delta_f2_f0; | |||
|
204 | nb_burst_available <= reg_wp.nb_burst_available; | |||
|
205 | nb_snapshot_param <= reg_wp.nb_snapshot_param; | |||
|
206 | ||||
|
207 | enable_f0 <= reg_wp.enable_f0; | |||
|
208 | enable_f1 <= reg_wp.enable_f1; | |||
|
209 | enable_f2 <= reg_wp.enable_f2; | |||
|
210 | enable_f3 <= reg_wp.enable_f3; | |||
|
211 | ||||
|
212 | burst_f0 <= reg_wp.burst_f0; | |||
|
213 | burst_f1 <= reg_wp.burst_f1; | |||
|
214 | burst_f2 <= reg_wp.burst_f2; | |||
|
215 | ||||
|
216 | addr_data_f0 <= reg_wp.addr_data_f0; | |||
|
217 | addr_data_f1 <= reg_wp.addr_data_f1; | |||
|
218 | addr_data_f2 <= reg_wp.addr_data_f2; | |||
|
219 | addr_data_f3 <= reg_wp.addr_data_f3; | |||
|
220 | ||||
|
221 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |||
|
222 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |||
|
223 | BEGIN -- PROCESS lpp_dma_top | |||
|
224 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
225 | reg_sp.config_active_interruption_onNewMatrix <= '0'; | |||
|
226 | reg_sp.config_active_interruption_onError <= '0'; | |||
|
227 | reg_sp.status_ready_matrix_f0_0 <= '0'; | |||
|
228 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |||
|
229 | reg_sp.status_ready_matrix_f1 <= '0'; | |||
|
230 | reg_sp.status_ready_matrix_f2 <= '0'; | |||
|
231 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |||
|
232 | reg_sp.status_error_bad_component_error <= '0'; | |||
|
233 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); | |||
|
234 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |||
|
235 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); | |||
|
236 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); | |||
|
237 | prdata <= (OTHERS => '0'); | |||
|
238 | ||||
|
239 | apbo.pirq <= (OTHERS => '0'); | |||
|
240 | ||||
|
241 | status_full_ack <= (OTHERS => '0'); | |||
|
242 | ||||
|
243 | reg_wp.data_shaping_BW <= '0'; | |||
|
244 | reg_wp.data_shaping_SP0 <= '0'; | |||
|
245 | reg_wp.data_shaping_SP1 <= '0'; | |||
|
246 | reg_wp.data_shaping_R0 <= '0'; | |||
|
247 | reg_wp.data_shaping_R1 <= '0'; | |||
|
248 | reg_wp.enable_f0 <= '0'; | |||
|
249 | reg_wp.enable_f1 <= '0'; | |||
|
250 | reg_wp.enable_f2 <= '0'; | |||
|
251 | reg_wp.enable_f3 <= '0'; | |||
|
252 | reg_wp.burst_f0 <= '0'; | |||
|
253 | reg_wp.burst_f1 <= '0'; | |||
|
254 | reg_wp.burst_f2 <= '0'; | |||
|
255 | reg_wp.addr_data_f0 <= (OTHERS => '0'); | |||
|
256 | reg_wp.addr_data_f1 <= (OTHERS => '0'); | |||
|
257 | reg_wp.addr_data_f2 <= (OTHERS => '0'); | |||
|
258 | reg_wp.addr_data_f3 <= (OTHERS => '0'); | |||
|
259 | reg_wp.status_full <= (OTHERS => '0'); | |||
|
260 | reg_wp.status_full_err <= (OTHERS => '0'); | |||
|
261 | reg_wp.status_new_err <= (OTHERS => '0'); | |||
|
262 | reg_wp.delta_snapshot <= (OTHERS => '0'); | |||
|
263 | reg_wp.delta_f2_f1 <= (OTHERS => '0'); | |||
|
264 | reg_wp.delta_f2_f0 <= (OTHERS => '0'); | |||
|
265 | reg_wp.nb_burst_available <= (OTHERS => '0'); | |||
|
266 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |||
|
267 | ||||
|
268 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |||
|
269 | status_full_ack <= (OTHERS => '0'); | |||
|
270 | ||||
|
271 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; | |||
|
272 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |||
|
273 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; | |||
|
274 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; | |||
|
275 | ||||
|
276 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |||
|
277 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; | |||
|
278 | ||||
|
279 | reg_wp.status_full <= reg_wp.status_full OR status_full; | |||
|
280 | reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; | |||
|
281 | reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; | |||
|
282 | ||||
|
283 | paddr := "000000"; | |||
|
284 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |||
|
285 | prdata <= (OTHERS => '0'); | |||
|
286 | IF apbi.psel(pindex) = '1' THEN | |||
|
287 | -- APB DMA READ -- | |||
|
288 | CASE paddr(7 DOWNTO 2) IS | |||
|
289 | -- | |||
|
290 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; | |||
|
291 | prdata(1) <= reg_sp.config_active_interruption_onError; | |||
|
292 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |||
|
293 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |||
|
294 | prdata(2) <= reg_sp.status_ready_matrix_f1; | |||
|
295 | prdata(3) <= reg_sp.status_ready_matrix_f2; | |||
|
296 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |||
|
297 | prdata(5) <= reg_sp.status_error_bad_component_error; | |||
|
298 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; | |||
|
299 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |||
|
300 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; | |||
|
301 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; | |||
|
302 | WHEN "000110" => prdata <= debug_reg; | |||
|
303 | -- | |||
|
304 | WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; | |||
|
305 | prdata(1) <= reg_wp.data_shaping_SP0; | |||
|
306 | prdata(2) <= reg_wp.data_shaping_SP1; | |||
|
307 | prdata(3) <= reg_wp.data_shaping_R0; | |||
|
308 | prdata(4) <= reg_wp.data_shaping_R1; | |||
|
309 | WHEN "001001" => prdata(0) <= reg_wp.enable_f0; | |||
|
310 | prdata(1) <= reg_wp.enable_f1; | |||
|
311 | prdata(2) <= reg_wp.enable_f2; | |||
|
312 | prdata(3) <= reg_wp.enable_f3; | |||
|
313 | prdata(4) <= reg_wp.burst_f0; | |||
|
314 | prdata(5) <= reg_wp.burst_f1; | |||
|
315 | prdata(6) <= reg_wp.burst_f2; | |||
|
316 | WHEN "001010" => prdata <= reg_wp.addr_data_f0; | |||
|
317 | WHEN "001011" => prdata <= reg_wp.addr_data_f1; | |||
|
318 | WHEN "001100" => prdata <= reg_wp.addr_data_f2; | |||
|
319 | WHEN "001101" => prdata <= reg_wp.addr_data_f3; | |||
|
320 | WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; | |||
|
321 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; | |||
|
322 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; | |||
|
323 | WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |||
|
324 | WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1; | |||
|
325 | WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0; | |||
|
326 | WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available; | |||
|
327 | WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |||
|
328 | -- | |||
|
329 | WHEN OTHERS => NULL; | |||
|
330 | END CASE; | |||
|
331 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |||
|
332 | -- APB DMA WRITE -- | |||
|
333 | CASE paddr(7 DOWNTO 2) IS | |||
|
334 | -- | |||
|
335 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |||
|
336 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |||
|
337 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |||
|
338 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |||
|
339 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); | |||
|
340 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); | |||
|
341 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |||
|
342 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); | |||
|
343 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |||
|
344 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |||
|
345 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; | |||
|
346 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; | |||
|
347 | -- | |||
|
348 | WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); | |||
|
349 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |||
|
350 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); | |||
|
351 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |||
|
352 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |||
|
353 | WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); | |||
|
354 | reg_wp.enable_f1 <= apbi.pwdata(1); | |||
|
355 | reg_wp.enable_f2 <= apbi.pwdata(2); | |||
|
356 | reg_wp.enable_f3 <= apbi.pwdata(3); | |||
|
357 | reg_wp.burst_f0 <= apbi.pwdata(4); | |||
|
358 | reg_wp.burst_f1 <= apbi.pwdata(5); | |||
|
359 | reg_wp.burst_f2 <= apbi.pwdata(6); | |||
|
360 | WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; | |||
|
361 | WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; | |||
|
362 | WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; | |||
|
363 | WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; | |||
|
364 | WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); | |||
|
365 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); | |||
|
366 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); | |||
|
367 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); | |||
|
368 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); | |||
|
369 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); | |||
|
370 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); | |||
|
371 | WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); | |||
|
372 | WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); | |||
|
373 | WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); | |||
|
374 | WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0); | |||
|
375 | WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
376 | -- | |||
|
377 | WHEN OTHERS => NULL; | |||
|
378 | END CASE; | |||
|
379 | END IF; | |||
|
380 | END IF; | |||
|
381 | ||||
|
382 | apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR | |||
|
383 | ready_matrix_f0_1 OR | |||
|
384 | ready_matrix_f1 OR | |||
|
385 | ready_matrix_f2) | |||
|
386 | ) | |||
|
387 | OR | |||
|
388 | (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR | |||
|
389 | error_bad_component_error) | |||
|
390 | ); | |||
|
391 | ||||
|
392 | apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR | |||
|
393 | status_full(1) OR status_full_err(1) OR status_new_err(1) OR | |||
|
394 | status_full(2) OR status_full_err(2) OR status_new_err(2) OR | |||
|
395 | status_full(3) OR status_full_err(3) OR status_new_err(3) | |||
|
396 | ); | |||
|
397 | ||||
|
398 | ||||
|
399 | END IF; | |||
|
400 | END PROCESS lpp_lfr_apbreg; | |||
|
401 | ||||
|
402 | apbo.pindex <= pindex; | |||
|
403 | apbo.pconfig <= pconfig; | |||
|
404 | apbo.prdata <= prdata; | |||
|
405 | ||||
|
406 | ||||
|
407 | END beh; |
@@ -0,0 +1,385 | |||||
|
1 | LIBRARY ieee; | |||
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
3 | USE ieee.numeric_std.ALL; | |||
|
4 | ||||
|
5 | LIBRARY lpp; | |||
|
6 | USE lpp.lpp_ad_conv.ALL; | |||
|
7 | USE lpp.iir_filter.ALL; | |||
|
8 | USE lpp.FILTERcfg.ALL; | |||
|
9 | USE lpp.lpp_memory.ALL; | |||
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
11 | ||||
|
12 | LIBRARY techmap; | |||
|
13 | USE techmap.gencomp.ALL; | |||
|
14 | ||||
|
15 | LIBRARY grlib; | |||
|
16 | USE grlib.amba.ALL; | |||
|
17 | USE grlib.stdlib.ALL; | |||
|
18 | USE grlib.devices.ALL; | |||
|
19 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
20 | ||||
|
21 | ENTITY lpp_lfr_filter IS | |||
|
22 | GENERIC( | |||
|
23 | Mem_use : INTEGER := use_RAM | |||
|
24 | ); | |||
|
25 | PORT ( | |||
|
26 | sample : IN Samples(7 DOWNTO 0); | |||
|
27 | sample_val : IN STD_LOGIC; | |||
|
28 | -- | |||
|
29 | clk : IN STD_LOGIC; | |||
|
30 | rstn : IN STD_LOGIC; | |||
|
31 | -- | |||
|
32 | data_shaping_SP0 : IN STD_LOGIC; | |||
|
33 | data_shaping_SP1 : IN STD_LOGIC; | |||
|
34 | data_shaping_R0 : IN STD_LOGIC; | |||
|
35 | data_shaping_R1 : IN STD_LOGIC; | |||
|
36 | -- | |||
|
37 | sample_f0_val : OUT STD_LOGIC; | |||
|
38 | sample_f1_val : OUT STD_LOGIC; | |||
|
39 | sample_f2_val : OUT STD_LOGIC; | |||
|
40 | sample_f3_val : OUT STD_LOGIC; | |||
|
41 | -- | |||
|
42 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
43 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
44 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
45 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0) | |||
|
46 | ); | |||
|
47 | END lpp_lfr_filter; | |||
|
48 | ||||
|
49 | ARCHITECTURE tb OF lpp_lfr_filter IS | |||
|
50 | ||||
|
51 | COMPONENT Downsampling | |||
|
52 | GENERIC ( | |||
|
53 | ChanelCount : INTEGER; | |||
|
54 | SampleSize : INTEGER; | |||
|
55 | DivideParam : INTEGER); | |||
|
56 | PORT ( | |||
|
57 | clk : IN STD_LOGIC; | |||
|
58 | rstn : IN STD_LOGIC; | |||
|
59 | sample_in_val : IN STD_LOGIC; | |||
|
60 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |||
|
61 | sample_out_val : OUT STD_LOGIC; | |||
|
62 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |||
|
63 | END COMPONENT; | |||
|
64 | ||||
|
65 | ----------------------------------------------------------------------------- | |||
|
66 | CONSTANT ChanelCount : INTEGER := 8; | |||
|
67 | ||||
|
68 | ----------------------------------------------------------------------------- | |||
|
69 | SIGNAL sample_val_delay : STD_LOGIC; | |||
|
70 | ----------------------------------------------------------------------------- | |||
|
71 | CONSTANT Coef_SZ : INTEGER := 9; | |||
|
72 | CONSTANT CoefCntPerCel : INTEGER := 6; | |||
|
73 | CONSTANT CoefPerCel : INTEGER := 5; | |||
|
74 | CONSTANT Cels_count : INTEGER := 5; | |||
|
75 | ||||
|
76 | SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); | |||
|
77 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |||
|
78 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
79 | SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
80 | -- | |||
|
81 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |||
|
82 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
83 | ----------------------------------------------------------------------------- | |||
|
84 | SIGNAL sample_data_shaping_out_val : STD_LOGIC; | |||
|
85 | SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
86 | SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
87 | SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
88 | SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
89 | SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
90 | SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); | |||
|
91 | ----------------------------------------------------------------------------- | |||
|
92 | SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; | |||
|
93 | SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
|
94 | ----------------------------------------------------------------------------- | |||
|
95 | -- SIGNAL sample_f0_val : STD_LOGIC; | |||
|
96 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
|
97 | SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
|
98 | -- | |||
|
99 | -- SIGNAL sample_f1_val : STD_LOGIC; | |||
|
100 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); | |||
|
101 | SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
|
102 | -- | |||
|
103 | -- SIGNAL sample_f2_val : STD_LOGIC; | |||
|
104 | SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
|
105 | -- | |||
|
106 | -- SIGNAL sample_f3_val : STD_LOGIC; | |||
|
107 | SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); | |||
|
108 | ||||
|
109 | ----------------------------------------------------------------------------- | |||
|
110 | SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
|
111 | SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
|
112 | SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
|
113 | SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); | |||
|
114 | ----------------------------------------------------------------------------- | |||
|
115 | ||||
|
116 | SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
117 | SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
118 | SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
119 | SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
120 | ||||
|
121 | SIGNAL sample_f0_val_s : STD_LOGIC; | |||
|
122 | SIGNAL sample_f1_val_s : STD_LOGIC; | |||
|
123 | BEGIN | |||
|
124 | ||||
|
125 | ----------------------------------------------------------------------------- | |||
|
126 | PROCESS (clk, rstn) | |||
|
127 | BEGIN -- PROCESS | |||
|
128 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
129 | sample_val_delay <= '0'; | |||
|
130 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
131 | sample_val_delay <= sample_val; | |||
|
132 | END IF; | |||
|
133 | END PROCESS; | |||
|
134 | ||||
|
135 | ----------------------------------------------------------------------------- | |||
|
136 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |||
|
137 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |||
|
138 | sample_filter_in(i, j) <= sample(i)(j); | |||
|
139 | END GENERATE; | |||
|
140 | ||||
|
141 | sample_filter_in(i, 16) <= sample(i)(15); | |||
|
142 | sample_filter_in(i, 17) <= sample(i)(15); | |||
|
143 | END GENERATE; | |||
|
144 | ||||
|
145 | coefs_v2 <= CoefsInitValCst_v2; | |||
|
146 | ||||
|
147 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |||
|
148 | GENERIC MAP ( | |||
|
149 | tech => 0, | |||
|
150 | Mem_use => Mem_use, -- use_RAM | |||
|
151 | Sample_SZ => 18, | |||
|
152 | Coef_SZ => Coef_SZ, | |||
|
153 | Coef_Nb => 25, | |||
|
154 | Coef_sel_SZ => 5, | |||
|
155 | Cels_count => Cels_count, | |||
|
156 | ChanelsCount => ChanelCount) | |||
|
157 | PORT MAP ( | |||
|
158 | rstn => rstn, | |||
|
159 | clk => clk, | |||
|
160 | virg_pos => 7, | |||
|
161 | coefs => coefs_v2, | |||
|
162 | sample_in_val => sample_val_delay, | |||
|
163 | sample_in => sample_filter_in, | |||
|
164 | sample_out_val => sample_filter_v2_out_val, | |||
|
165 | sample_out => sample_filter_v2_out); | |||
|
166 | ||||
|
167 | ----------------------------------------------------------------------------- | |||
|
168 | -- DATA_SHAPING | |||
|
169 | ----------------------------------------------------------------------------- | |||
|
170 | all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE | |||
|
171 | sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I); | |||
|
172 | sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I); | |||
|
173 | sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I); | |||
|
174 | END GENERATE all_data_shaping_in_loop; | |||
|
175 | ||||
|
176 | sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; | |||
|
177 | sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; | |||
|
178 | ||||
|
179 | PROCESS (clk, rstn) | |||
|
180 | BEGIN -- PROCESS | |||
|
181 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
182 | sample_data_shaping_out_val <= '0'; | |||
|
183 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
184 | sample_data_shaping_out_val <= sample_filter_v2_out_val; | |||
|
185 | END IF; | |||
|
186 | END PROCESS; | |||
|
187 | ||||
|
188 | SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE | |||
|
189 | PROCESS (clk, rstn) | |||
|
190 | BEGIN | |||
|
191 | IF rstn = '0' THEN | |||
|
192 | sample_data_shaping_out(0, j) <= '0'; | |||
|
193 | sample_data_shaping_out(1, j) <= '0'; | |||
|
194 | sample_data_shaping_out(2, j) <= '0'; | |||
|
195 | sample_data_shaping_out(3, j) <= '0'; | |||
|
196 | sample_data_shaping_out(4, j) <= '0'; | |||
|
197 | sample_data_shaping_out(5, j) <= '0'; | |||
|
198 | sample_data_shaping_out(6, j) <= '0'; | |||
|
199 | sample_data_shaping_out(7, j) <= '0'; | |||
|
200 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
201 | sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j); | |||
|
202 | IF data_shaping_SP0 = '1' THEN | |||
|
203 | sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j); | |||
|
204 | ELSE | |||
|
205 | sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j); | |||
|
206 | END IF; | |||
|
207 | IF data_shaping_SP1 = '1' THEN | |||
|
208 | sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j); | |||
|
209 | ELSE | |||
|
210 | sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j); | |||
|
211 | END IF; | |||
|
212 | sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j); | |||
|
213 | sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j); | |||
|
214 | sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j); | |||
|
215 | sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j); | |||
|
216 | sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j); | |||
|
217 | END IF; | |||
|
218 | END PROCESS; | |||
|
219 | END GENERATE; | |||
|
220 | ||||
|
221 | sample_filter_v2_out_val_s <= sample_data_shaping_out_val; | |||
|
222 | ChanelLoopOut : FOR i IN 0 TO 7 GENERATE | |||
|
223 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |||
|
224 | sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j); | |||
|
225 | END GENERATE; | |||
|
226 | END GENERATE; | |||
|
227 | ----------------------------------------------------------------------------- | |||
|
228 | -- F0 -- @24.576 kHz | |||
|
229 | ----------------------------------------------------------------------------- | |||
|
230 | Downsampling_f0 : Downsampling | |||
|
231 | GENERIC MAP ( | |||
|
232 | ChanelCount => 8, | |||
|
233 | SampleSize => 16, | |||
|
234 | DivideParam => 4) | |||
|
235 | PORT MAP ( | |||
|
236 | clk => clk, | |||
|
237 | rstn => rstn, | |||
|
238 | sample_in_val => sample_filter_v2_out_val_s, | |||
|
239 | sample_in => sample_filter_v2_out_s, | |||
|
240 | sample_out_val => sample_f0_val_s, | |||
|
241 | sample_out => sample_f0); | |||
|
242 | ||||
|
243 | sample_f0_val <= sample_f0_val_s; | |||
|
244 | ||||
|
245 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
246 | sample_f0_wdata_s(I) <= sample_f0(0, I); -- V | |||
|
247 | sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 | |||
|
248 | sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 | |||
|
249 | sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 | |||
|
250 | sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 | |||
|
251 | sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 | |||
|
252 | END GENERATE all_bit_sample_f0; | |||
|
253 | ||||
|
254 | --sample_f0_wen <= NOT(sample_f0_val) & | |||
|
255 | -- NOT(sample_f0_val) & | |||
|
256 | -- NOT(sample_f0_val) & | |||
|
257 | -- NOT(sample_f0_val) & | |||
|
258 | -- NOT(sample_f0_val) & | |||
|
259 | -- NOT(sample_f0_val); | |||
|
260 | ||||
|
261 | ----------------------------------------------------------------------------- | |||
|
262 | -- F1 -- @4096 Hz | |||
|
263 | ----------------------------------------------------------------------------- | |||
|
264 | Downsampling_f1 : Downsampling | |||
|
265 | GENERIC MAP ( | |||
|
266 | ChanelCount => 8, | |||
|
267 | SampleSize => 16, | |||
|
268 | DivideParam => 6) | |||
|
269 | PORT MAP ( | |||
|
270 | clk => clk, | |||
|
271 | rstn => rstn, | |||
|
272 | sample_in_val => sample_f0_val_s , | |||
|
273 | sample_in => sample_f0, | |||
|
274 | sample_out_val => sample_f1_val_s, | |||
|
275 | sample_out => sample_f1); | |||
|
276 | ||||
|
277 | sample_f1_val <= sample_f1_val_s; | |||
|
278 | ||||
|
279 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
280 | sample_f1_wdata_s(I) <= sample_f1(0, I); -- V | |||
|
281 | sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 | |||
|
282 | sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 | |||
|
283 | sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 | |||
|
284 | sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 | |||
|
285 | sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 | |||
|
286 | END GENERATE all_bit_sample_f1; | |||
|
287 | ||||
|
288 | --sample_f1_wen <= NOT(sample_f1_val) & | |||
|
289 | -- NOT(sample_f1_val) & | |||
|
290 | -- NOT(sample_f1_val) & | |||
|
291 | -- NOT(sample_f1_val) & | |||
|
292 | -- NOT(sample_f1_val) & | |||
|
293 | -- NOT(sample_f1_val); | |||
|
294 | ||||
|
295 | ----------------------------------------------------------------------------- | |||
|
296 | -- F2 -- @256 Hz | |||
|
297 | ----------------------------------------------------------------------------- | |||
|
298 | all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
299 | sample_f0_s(0, I) <= sample_f0(0, I); -- V | |||
|
300 | sample_f0_s(1, I) <= sample_f0(1, I); -- E1 | |||
|
301 | sample_f0_s(2, I) <= sample_f0(2, I); -- E2 | |||
|
302 | sample_f0_s(3, I) <= sample_f0(5, I); -- B1 | |||
|
303 | sample_f0_s(4, I) <= sample_f0(6, I); -- B2 | |||
|
304 | sample_f0_s(5, I) <= sample_f0(7, I); -- B3 | |||
|
305 | END GENERATE all_bit_sample_f0_s; | |||
|
306 | ||||
|
307 | Downsampling_f2 : Downsampling | |||
|
308 | GENERIC MAP ( | |||
|
309 | ChanelCount => 6, | |||
|
310 | SampleSize => 16, | |||
|
311 | DivideParam => 96) | |||
|
312 | PORT MAP ( | |||
|
313 | clk => clk, | |||
|
314 | rstn => rstn, | |||
|
315 | sample_in_val => sample_f0_val_s , | |||
|
316 | sample_in => sample_f0_s, | |||
|
317 | sample_out_val => sample_f2_val, | |||
|
318 | sample_out => sample_f2); | |||
|
319 | ||||
|
320 | --sample_f2_wen <= NOT(sample_f2_val) & | |||
|
321 | -- NOT(sample_f2_val) & | |||
|
322 | -- NOT(sample_f2_val) & | |||
|
323 | -- NOT(sample_f2_val) & | |||
|
324 | -- NOT(sample_f2_val) & | |||
|
325 | -- NOT(sample_f2_val); | |||
|
326 | ||||
|
327 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
328 | sample_f2_wdata_s(I) <= sample_f2(0, I); | |||
|
329 | sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); | |||
|
330 | sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); | |||
|
331 | sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); | |||
|
332 | sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); | |||
|
333 | sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); | |||
|
334 | END GENERATE all_bit_sample_f2; | |||
|
335 | ||||
|
336 | ----------------------------------------------------------------------------- | |||
|
337 | -- F3 -- @16 Hz | |||
|
338 | ----------------------------------------------------------------------------- | |||
|
339 | all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
340 | sample_f1_s(0, I) <= sample_f1(0, I); -- V | |||
|
341 | sample_f1_s(1, I) <= sample_f1(1, I); -- E1 | |||
|
342 | sample_f1_s(2, I) <= sample_f1(2, I); -- E2 | |||
|
343 | sample_f1_s(3, I) <= sample_f1(5, I); -- B1 | |||
|
344 | sample_f1_s(4, I) <= sample_f1(6, I); -- B2 | |||
|
345 | sample_f1_s(5, I) <= sample_f1(7, I); -- B3 | |||
|
346 | END GENERATE all_bit_sample_f1_s; | |||
|
347 | ||||
|
348 | Downsampling_f3 : Downsampling | |||
|
349 | GENERIC MAP ( | |||
|
350 | ChanelCount => 6, | |||
|
351 | SampleSize => 16, | |||
|
352 | DivideParam => 256) | |||
|
353 | PORT MAP ( | |||
|
354 | clk => clk, | |||
|
355 | rstn => rstn, | |||
|
356 | sample_in_val => sample_f1_val_s , | |||
|
357 | sample_in => sample_f1_s, | |||
|
358 | sample_out_val => sample_f3_val, | |||
|
359 | sample_out => sample_f3); | |||
|
360 | ||||
|
361 | --sample_f3_wen <= (NOT sample_f3_val) & | |||
|
362 | -- (NOT sample_f3_val) & | |||
|
363 | -- (NOT sample_f3_val) & | |||
|
364 | -- (NOT sample_f3_val) & | |||
|
365 | -- (NOT sample_f3_val) & | |||
|
366 | -- (NOT sample_f3_val); | |||
|
367 | ||||
|
368 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
369 | sample_f3_wdata_s(I) <= sample_f3(0, I); | |||
|
370 | sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); | |||
|
371 | sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); | |||
|
372 | sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); | |||
|
373 | sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); | |||
|
374 | sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); | |||
|
375 | END GENERATE all_bit_sample_f3; | |||
|
376 | ||||
|
377 | ----------------------------------------------------------------------------- | |||
|
378 | -- | |||
|
379 | ----------------------------------------------------------------------------- | |||
|
380 | sample_f0_wdata <= sample_f0_wdata_s; | |||
|
381 | sample_f1_wdata <= sample_f1_wdata_s; | |||
|
382 | sample_f2_wdata <= sample_f2_wdata_s; | |||
|
383 | sample_f3_wdata <= sample_f3_wdata_s; | |||
|
384 | ||||
|
385 | END tb; No newline at end of file |
@@ -0,0 +1,346 | |||||
|
1 | LIBRARY ieee; | |||
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
3 | ||||
|
4 | LIBRARY lpp; | |||
|
5 | USE lpp.lpp_amba.ALL; | |||
|
6 | USE lpp.lpp_memory.ALL; | |||
|
7 | USE lpp.lpp_uart.ALL; | |||
|
8 | USE lpp.lpp_matrix.ALL; | |||
|
9 | USE lpp.lpp_delay.ALL; | |||
|
10 | USE lpp.lpp_fft.ALL; | |||
|
11 | USE lpp.fft_components.ALL; | |||
|
12 | USE lpp.lpp_ad_conv.ALL; | |||
|
13 | USE lpp.iir_filter.ALL; | |||
|
14 | USE lpp.general_purpose.ALL; | |||
|
15 | USE lpp.Filtercfg.ALL; | |||
|
16 | USE lpp.lpp_demux.ALL; | |||
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
|
18 | USE lpp.lpp_dma_pkg.ALL; | |||
|
19 | USE lpp.lpp_Header.ALL; | |||
|
20 | ||||
|
21 | LIBRARY grlib; | |||
|
22 | USE grlib.amba.ALL; | |||
|
23 | USE grlib.stdlib.ALL; | |||
|
24 | USE grlib.devices.ALL; | |||
|
25 | USE GRLIB.DMA2AHB_Package.ALL; | |||
|
26 | ||||
|
27 | ||||
|
28 | ENTITY lpp_lfr_ms IS | |||
|
29 | GENERIC ( | |||
|
30 | hindex : INTEGER := 2 | |||
|
31 | ); | |||
|
32 | PORT ( | |||
|
33 | clk : IN STD_LOGIC; | |||
|
34 | rstn : IN STD_LOGIC; | |||
|
35 | ||||
|
36 | --------------------------------------------------------------------------- | |||
|
37 | -- DATA INPUT | |||
|
38 | --------------------------------------------------------------------------- | |||
|
39 | -- | |||
|
40 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
41 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
42 | -- | |||
|
43 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
44 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
45 | -- | |||
|
46 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
47 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
48 | ||||
|
49 | --------------------------------------------------------------------------- | |||
|
50 | -- DMA | |||
|
51 | --------------------------------------------------------------------------- | |||
|
52 | ||||
|
53 | -- AMBA AHB Master Interface | |||
|
54 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
56 | ||||
|
57 | -- Reg out | |||
|
58 | ready_matrix_f0_0 : OUT STD_LOGIC; | |||
|
59 | ready_matrix_f0_1 : OUT STD_LOGIC; | |||
|
60 | ready_matrix_f1 : OUT STD_LOGIC; | |||
|
61 | ready_matrix_f2 : OUT STD_LOGIC; | |||
|
62 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
|
63 | error_bad_component_error : OUT STD_LOGIC; | |||
|
64 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
65 | ||||
|
66 | -- Reg In | |||
|
67 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |||
|
68 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |||
|
69 | status_ready_matrix_f1 :IN STD_LOGIC; | |||
|
70 | status_ready_matrix_f2 :IN STD_LOGIC; | |||
|
71 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |||
|
72 | status_error_bad_component_error :IN STD_LOGIC; | |||
|
73 | ||||
|
74 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |||
|
75 | config_active_interruption_onError : IN STD_LOGIC; | |||
|
76 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
77 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
78 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
79 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |||
|
80 | ); | |||
|
81 | END; | |||
|
82 | ||||
|
83 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
84 | ----------------------------------------------------------------------------- | |||
|
85 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
86 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
87 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
88 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |||
|
89 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |||
|
90 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |||
|
91 | ||||
|
92 | ----------------------------------------------------------------------------- | |||
|
93 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); | |||
|
94 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
95 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |||
|
96 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
97 | ||||
|
98 | ----------------------------------------------------------------------------- | |||
|
99 | SIGNAL FFT_Load : STD_LOGIC; | |||
|
100 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
101 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
102 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
103 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |||
|
104 | ||||
|
105 | ----------------------------------------------------------------------------- | |||
|
106 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
107 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); | |||
|
108 | ||||
|
109 | ----------------------------------------------------------------------------- | |||
|
110 | SIGNAL SM_FlagError : STD_LOGIC; | |||
|
111 | SIGNAL SM_Pong : STD_LOGIC; | |||
|
112 | SIGNAL SM_Wen : STD_LOGIC; | |||
|
113 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
114 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
115 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
116 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
117 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
|
118 | ||||
|
119 | ----------------------------------------------------------------------------- | |||
|
120 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
121 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
122 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); | |||
|
123 | ||||
|
124 | ----------------------------------------------------------------------------- | |||
|
125 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
126 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
127 | SIGNAL Head_Empty : STD_LOGIC; | |||
|
128 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
129 | SIGNAL Head_Valid : STD_LOGIC; | |||
|
130 | SIGNAL Head_Val : STD_LOGIC; | |||
|
131 | ||||
|
132 | ----------------------------------------------------------------------------- | |||
|
133 | SIGNAL DMA_Read : STD_LOGIC; | |||
|
134 | SIGNAL DMA_ack : STD_LOGIC; | |||
|
135 | ||||
|
136 | BEGIN | |||
|
137 | ||||
|
138 | ----------------------------------------------------------------------------- | |||
|
139 | Memf0: lppFIFOxN | |||
|
140 | GENERIC MAP ( | |||
|
141 | tech => 0, Mem_use => use_RAM, Data_sz => 16, | |||
|
142 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |||
|
143 | PORT MAP ( | |||
|
144 | rst => rstn, wclk => clk, rclk => clk, | |||
|
145 | ReUse => (OTHERS => '0'), | |||
|
146 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |||
|
147 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |||
|
148 | full => OPEN, empty => FifoF0_Empty); | |||
|
149 | ||||
|
150 | Memf1: lppFIFOxN | |||
|
151 | GENERIC MAP ( | |||
|
152 | tech => 0, Mem_use => use_RAM, Data_sz => 16, | |||
|
153 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |||
|
154 | PORT MAP ( | |||
|
155 | rst => rstn, wclk => clk, rclk => clk, | |||
|
156 | ReUse => (OTHERS => '0'), | |||
|
157 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |||
|
158 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |||
|
159 | full => OPEN, empty => FifoF1_Empty); | |||
|
160 | ||||
|
161 | ||||
|
162 | Memf2: lppFIFOxN | |||
|
163 | GENERIC MAP ( | |||
|
164 | tech => 0, Mem_use => use_RAM, Data_sz => 16, | |||
|
165 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |||
|
166 | PORT MAP ( | |||
|
167 | rst => rstn, wclk => clk, rclk => clk, | |||
|
168 | ReUse => (OTHERS => '0'), | |||
|
169 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |||
|
170 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |||
|
171 | full => OPEN, empty => FifoF3_Empty); | |||
|
172 | ----------------------------------------------------------------------------- | |||
|
173 | ||||
|
174 | ||||
|
175 | ----------------------------------------------------------------------------- | |||
|
176 | DMUX0 : DEMUX | |||
|
177 | GENERIC MAP ( | |||
|
178 | Data_sz => 16) | |||
|
179 | PORT MAP ( | |||
|
180 | clk => clk, | |||
|
181 | rstn => rstn, | |||
|
182 | Read => FFT_Read, | |||
|
183 | Load => FFT_Load, | |||
|
184 | EmptyF0 => FifoF0_Empty, | |||
|
185 | EmptyF1 => FifoF1_Empty, | |||
|
186 | EmptyF2 => FifoF3_Empty, | |||
|
187 | DataF0 => FifoF0_Data, | |||
|
188 | DataF1 => FifoF1_Data, | |||
|
189 | DataF2 => FifoF3_Data, | |||
|
190 | WorkFreq => DMUX_WorkFreq, | |||
|
191 | Read_DEMUX => DMUX_Read, | |||
|
192 | Empty => DMUX_Empty, | |||
|
193 | Data => DMUX_Data); | |||
|
194 | ----------------------------------------------------------------------------- | |||
|
195 | ||||
|
196 | ||||
|
197 | ----------------------------------------------------------------------------- | |||
|
198 | FFT0: FFT | |||
|
199 | GENERIC MAP ( | |||
|
200 | Data_sz => 16, | |||
|
201 | NbData => 256) | |||
|
202 | PORT MAP ( | |||
|
203 | clkm => clk, | |||
|
204 | rstn => rstn, | |||
|
205 | FifoIN_Empty => DMUX_Empty, | |||
|
206 | FifoIN_Data => DMUX_Data, | |||
|
207 | FifoOUT_Full => FifoINT_Full, | |||
|
208 | Load => FFT_Load, | |||
|
209 | Read => FFT_Read, | |||
|
210 | Write => FFT_Write, | |||
|
211 | ReUse => FFT_ReUse, | |||
|
212 | Data => FFT_Data); | |||
|
213 | ----------------------------------------------------------------------------- | |||
|
214 | ||||
|
215 | ||||
|
216 | ----------------------------------------------------------------------------- | |||
|
217 | MemInt : lppFIFOxN | |||
|
218 | GENERIC MAP ( | |||
|
219 | tech => 0, | |||
|
220 | Mem_use => use_RAM, | |||
|
221 | Data_sz => 16, | |||
|
222 | Addr_sz => 8, | |||
|
223 | FifoCnt => 5, | |||
|
224 | Enable_ReUse => '1') | |||
|
225 | PORT MAP ( | |||
|
226 | rst => rstn, | |||
|
227 | wclk => clk, | |||
|
228 | rclk => clk, | |||
|
229 | ReUse => SM_ReUse, | |||
|
230 | wen => FFT_Write, | |||
|
231 | ren => SM_Read, | |||
|
232 | wdata => FFT_Data, | |||
|
233 | rdata => FifoINT_Data, | |||
|
234 | full => FifoINT_Full, | |||
|
235 | empty => OPEN); | |||
|
236 | ----------------------------------------------------------------------------- | |||
|
237 | ||||
|
238 | ----------------------------------------------------------------------------- | |||
|
239 | SM0 : MatriceSpectrale | |||
|
240 | GENERIC MAP ( | |||
|
241 | Input_SZ => 16, | |||
|
242 | Result_SZ => 32) | |||
|
243 | PORT MAP ( | |||
|
244 | clkm => clk, | |||
|
245 | rstn => rstn, | |||
|
246 | FifoIN_Full => FifoINT_Full, | |||
|
247 | SetReUse => FFT_ReUse, | |||
|
248 | Valid => Head_Valid, | |||
|
249 | Data_IN => FifoINT_Data, | |||
|
250 | ACQ => DMA_ack, | |||
|
251 | SM_Write => SM_Wen, | |||
|
252 | FlagError => SM_FlagError, | |||
|
253 | Pong => SM_Pong, | |||
|
254 | Statu => SM_Param, | |||
|
255 | Write => SM_Write, | |||
|
256 | Read => SM_Read, | |||
|
257 | ReUse => SM_ReUse, | |||
|
258 | Data_OUT => SM_Data); | |||
|
259 | ----------------------------------------------------------------------------- | |||
|
260 | ||||
|
261 | ----------------------------------------------------------------------------- | |||
|
262 | MemOut : lppFIFOxN | |||
|
263 | GENERIC MAP ( | |||
|
264 | tech => 0, | |||
|
265 | Mem_use => use_RAM, | |||
|
266 | Data_sz => 32, | |||
|
267 | Addr_sz => 8, | |||
|
268 | FifoCnt => 2, | |||
|
269 | Enable_ReUse => '0') | |||
|
270 | PORT MAP ( | |||
|
271 | rst => rstn, | |||
|
272 | wclk => clk, | |||
|
273 | rclk => clk, | |||
|
274 | ReUse => (OTHERS => '0'), | |||
|
275 | wen => SM_Write, | |||
|
276 | ren => Head_Read, | |||
|
277 | wdata => SM_Data, | |||
|
278 | rdata => FifoOUT_Data, | |||
|
279 | full => FifoOUT_Full, | |||
|
280 | empty => FifoOUT_Empty); | |||
|
281 | ----------------------------------------------------------------------------- | |||
|
282 | ||||
|
283 | ----------------------------------------------------------------------------- | |||
|
284 | Head0 : HeaderBuilder | |||
|
285 | GENERIC MAP ( | |||
|
286 | Data_sz => 32) | |||
|
287 | PORT MAP ( | |||
|
288 | clkm => clk, | |||
|
289 | rstn => rstn, | |||
|
290 | pong => SM_Pong, | |||
|
291 | Statu => SM_Param, | |||
|
292 | Matrix_Type => DMUX_WorkFreq, | |||
|
293 | Matrix_Write => SM_Wen, | |||
|
294 | Valid => Head_Valid, | |||
|
295 | dataIN => FifoOUT_Data, | |||
|
296 | emptyIN => FifoOUT_Empty, | |||
|
297 | RenOUT => Head_Read, | |||
|
298 | dataOUT => Head_Data, | |||
|
299 | emptyOUT => Head_Empty, | |||
|
300 | RenIN => DMA_Read, | |||
|
301 | header => Head_Header, | |||
|
302 | header_val => Head_Val, | |||
|
303 | header_ack => DMA_ack ); | |||
|
304 | ----------------------------------------------------------------------------- | |||
|
305 | ||||
|
306 | ----------------------------------------------------------------------------- | |||
|
307 | lpp_dma_ip_1: lpp_dma_ip | |||
|
308 | GENERIC MAP ( | |||
|
309 | tech => 0, | |||
|
310 | hindex => hindex) | |||
|
311 | PORT MAP ( | |||
|
312 | HCLK => clk, | |||
|
313 | HRESETn => rstn, | |||
|
314 | AHB_Master_In => AHB_Master_In, | |||
|
315 | AHB_Master_Out => AHB_Master_Out, | |||
|
316 | ||||
|
317 | fifo_data => Head_Data, | |||
|
318 | fifo_empty => Head_Empty, | |||
|
319 | fifo_ren => DMA_Read, | |||
|
320 | ||||
|
321 | header => Head_Header, | |||
|
322 | header_val => Head_Val, | |||
|
323 | header_ack => DMA_ack, | |||
|
324 | ||||
|
325 | ready_matrix_f0_0 => ready_matrix_f0_0, | |||
|
326 | ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
327 | ready_matrix_f1 => ready_matrix_f1, | |||
|
328 | ready_matrix_f2 => ready_matrix_f2, | |||
|
329 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
|
330 | error_bad_component_error => error_bad_component_error, | |||
|
331 | debug_reg => debug_reg, | |||
|
332 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
|
333 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
|
334 | status_ready_matrix_f1 => status_ready_matrix_f1, | |||
|
335 | status_ready_matrix_f2 => status_ready_matrix_f2, | |||
|
336 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
|
337 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
338 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
339 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
340 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
341 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
342 | addr_matrix_f1 => addr_matrix_f1, | |||
|
343 | addr_matrix_f2 => addr_matrix_f2); | |||
|
344 | ----------------------------------------------------------------------------- | |||
|
345 | ||||
|
346 | END Behavioral; No newline at end of file |
@@ -0,0 +1,168 | |||||
|
1 | LIBRARY ieee; | |||
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
3 | ||||
|
4 | LIBRARY grlib; | |||
|
5 | USE grlib.amba.ALL; | |||
|
6 | ||||
|
7 | LIBRARY lpp; | |||
|
8 | USE lpp.lpp_ad_conv.ALL; | |||
|
9 | USE lpp.iir_filter.ALL; | |||
|
10 | USE lpp.FILTERcfg.ALL; | |||
|
11 | USE lpp.lpp_memory.ALL; | |||
|
12 | LIBRARY techmap; | |||
|
13 | USE techmap.gencomp.ALL; | |||
|
14 | ||||
|
15 | PACKAGE lpp_lfr_pkg IS | |||
|
16 | ||||
|
17 | COMPONENT lpp_lfr_ms | |||
|
18 | GENERIC ( | |||
|
19 | hindex : INTEGER); | |||
|
20 | PORT ( | |||
|
21 | clk : IN STD_LOGIC; | |||
|
22 | rstn : IN STD_LOGIC; | |||
|
23 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
24 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
25 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
26 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
27 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
28 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
29 | AHB_Master_In : IN AHB_Mst_In_Type; | |||
|
30 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |||
|
31 | ready_matrix_f0_0 : OUT STD_LOGIC; | |||
|
32 | ready_matrix_f0_1 : OUT STD_LOGIC; | |||
|
33 | ready_matrix_f1 : OUT STD_LOGIC; | |||
|
34 | ready_matrix_f2 : OUT STD_LOGIC; | |||
|
35 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
|
36 | error_bad_component_error : OUT STD_LOGIC; | |||
|
37 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
38 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |||
|
39 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |||
|
40 | status_ready_matrix_f1 : IN STD_LOGIC; | |||
|
41 | status_ready_matrix_f2 : IN STD_LOGIC; | |||
|
42 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |||
|
43 | status_error_bad_component_error : IN STD_LOGIC; | |||
|
44 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |||
|
45 | config_active_interruption_onError : IN STD_LOGIC; | |||
|
46 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
47 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
48 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
49 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
50 | END COMPONENT; | |||
|
51 | ||||
|
52 | COMPONENT lpp_lfr_filter | |||
|
53 | GENERIC ( | |||
|
54 | Mem_use : INTEGER); | |||
|
55 | PORT ( | |||
|
56 | sample : IN Samples(7 DOWNTO 0); | |||
|
57 | sample_val : IN STD_LOGIC; | |||
|
58 | clk : IN STD_LOGIC; | |||
|
59 | rstn : IN STD_LOGIC; | |||
|
60 | data_shaping_SP0 : IN STD_LOGIC; | |||
|
61 | data_shaping_SP1 : IN STD_LOGIC; | |||
|
62 | data_shaping_R0 : IN STD_LOGIC; | |||
|
63 | data_shaping_R1 : IN STD_LOGIC; | |||
|
64 | sample_f0_val : OUT STD_LOGIC; | |||
|
65 | sample_f1_val : OUT STD_LOGIC; | |||
|
66 | sample_f2_val : OUT STD_LOGIC; | |||
|
67 | sample_f3_val : OUT STD_LOGIC; | |||
|
68 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
69 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
70 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |||
|
71 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); | |||
|
72 | END COMPONENT; | |||
|
73 | ||||
|
74 | COMPONENT lpp_lfr | |||
|
75 | GENERIC ( | |||
|
76 | Mem_use : INTEGER; | |||
|
77 | nb_burst_available_size : INTEGER; | |||
|
78 | nb_snapshot_param_size : INTEGER; | |||
|
79 | delta_snapshot_size : INTEGER; | |||
|
80 | delta_f2_f0_size : INTEGER; | |||
|
81 | delta_f2_f1_size : INTEGER; | |||
|
82 | pindex : INTEGER; | |||
|
83 | paddr : INTEGER; | |||
|
84 | pmask : INTEGER; | |||
|
85 | pirq_ms : INTEGER; | |||
|
86 | pirq_wfp : INTEGER; | |||
|
87 | hindex_wfp : INTEGER; | |||
|
88 | hindex_ms : INTEGER); | |||
|
89 | PORT ( | |||
|
90 | clk : IN STD_LOGIC; | |||
|
91 | rstn : IN STD_LOGIC; | |||
|
92 | sample_B : IN Samples14v(2 DOWNTO 0); | |||
|
93 | sample_E : IN Samples14v(4 DOWNTO 0); | |||
|
94 | sample_val : IN STD_LOGIC; | |||
|
95 | apbi : IN apb_slv_in_type; | |||
|
96 | apbo : OUT apb_slv_out_type; | |||
|
97 | ahbi_wfp : IN AHB_Mst_In_Type; | |||
|
98 | ahbo_wfp : OUT AHB_Mst_Out_Type; | |||
|
99 | ahbi_ms : IN AHB_Mst_In_Type; | |||
|
100 | ahbo_ms : OUT AHB_Mst_Out_Type; | |||
|
101 | coarse_time_0 : IN STD_LOGIC; | |||
|
102 | data_shaping_BW : OUT STD_LOGIC); | |||
|
103 | END COMPONENT; | |||
|
104 | ||||
|
105 | COMPONENT lpp_lfr_apbreg | |||
|
106 | GENERIC ( | |||
|
107 | nb_burst_available_size : INTEGER; | |||
|
108 | nb_snapshot_param_size : INTEGER; | |||
|
109 | delta_snapshot_size : INTEGER; | |||
|
110 | delta_f2_f0_size : INTEGER; | |||
|
111 | delta_f2_f1_size : INTEGER; | |||
|
112 | pindex : INTEGER; | |||
|
113 | paddr : INTEGER; | |||
|
114 | pmask : INTEGER; | |||
|
115 | pirq_ms : INTEGER; | |||
|
116 | pirq_wfp : INTEGER); | |||
|
117 | PORT ( | |||
|
118 | HCLK : IN STD_ULOGIC; | |||
|
119 | HRESETn : IN STD_ULOGIC; | |||
|
120 | apbi : IN apb_slv_in_type; | |||
|
121 | apbo : OUT apb_slv_out_type; | |||
|
122 | ready_matrix_f0_0 : IN STD_LOGIC; | |||
|
123 | ready_matrix_f0_1 : IN STD_LOGIC; | |||
|
124 | ready_matrix_f1 : IN STD_LOGIC; | |||
|
125 | ready_matrix_f2 : IN STD_LOGIC; | |||
|
126 | error_anticipating_empty_fifo : IN STD_LOGIC; | |||
|
127 | error_bad_component_error : IN STD_LOGIC; | |||
|
128 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
129 | status_ready_matrix_f0_0 : OUT STD_LOGIC; | |||
|
130 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |||
|
131 | status_ready_matrix_f1 : OUT STD_LOGIC; | |||
|
132 | status_ready_matrix_f2 : OUT STD_LOGIC; | |||
|
133 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
|
134 | status_error_bad_component_error : OUT STD_LOGIC; | |||
|
135 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; | |||
|
136 | config_active_interruption_onError : OUT STD_LOGIC; | |||
|
137 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
138 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
139 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
140 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
141 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
142 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
143 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
144 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
145 | data_shaping_BW : OUT STD_LOGIC; | |||
|
146 | data_shaping_SP0 : OUT STD_LOGIC; | |||
|
147 | data_shaping_SP1 : OUT STD_LOGIC; | |||
|
148 | data_shaping_R0 : OUT STD_LOGIC; | |||
|
149 | data_shaping_R1 : OUT STD_LOGIC; | |||
|
150 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); | |||
|
151 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); | |||
|
152 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); | |||
|
153 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); | |||
|
154 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |||
|
155 | enable_f0 : OUT STD_LOGIC; | |||
|
156 | enable_f1 : OUT STD_LOGIC; | |||
|
157 | enable_f2 : OUT STD_LOGIC; | |||
|
158 | enable_f3 : OUT STD_LOGIC; | |||
|
159 | burst_f0 : OUT STD_LOGIC; | |||
|
160 | burst_f1 : OUT STD_LOGIC; | |||
|
161 | burst_f2 : OUT STD_LOGIC; | |||
|
162 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
163 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
164 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
165 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
166 | END COMPONENT; | |||
|
167 | ||||
|
168 | END lpp_lfr_pkg; |
@@ -1,365 +1,365 | |||||
1 |
|
1 | |||
2 | ------------------------------------------------------------------------------ |
|
2 | ------------------------------------------------------------------------------ | |
3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
5 | -- |
|
5 | -- | |
6 | -- This program is free software; you can redistribute it and/or modify |
|
6 | -- This program is free software; you can redistribute it and/or modify | |
7 | -- it under the terms of the GNU General Public License as published by |
|
7 | -- it under the terms of the GNU General Public License as published by | |
8 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |
9 | -- (at your option) any later version. |
|
9 | -- (at your option) any later version. | |
10 | -- |
|
10 | -- | |
11 | -- This program is distributed in the hope that it will be useful, |
|
11 | -- This program is distributed in the hope that it will be useful, | |
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | -- GNU General Public License for more details. |
|
14 | -- GNU General Public License for more details. | |
15 | -- |
|
15 | -- | |
16 | -- You should have received a copy of the GNU General Public License |
|
16 | -- You should have received a copy of the GNU General Public License | |
17 | -- along with this program; if not, write to the Free Software |
|
17 | -- along with this program; if not, write to the Free Software | |
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | ------------------------------------------------------------------------------- |
|
19 | ------------------------------------------------------------------------------- | |
20 | -- Author : Jean-christophe Pellion |
|
20 | -- Author : Jean-christophe Pellion | |
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
22 | -- jean-christophe.pellion@easii-ic.com |
|
22 | -- jean-christophe.pellion@easii-ic.com | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 1.0 - initial version |
|
24 | -- 1.0 - initial version | |
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) |
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |
26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
27 | LIBRARY ieee; |
|
27 | LIBRARY ieee; | |
28 | USE ieee.std_logic_1164.ALL; |
|
28 | USE ieee.std_logic_1164.ALL; | |
29 | USE ieee.numeric_std.ALL; |
|
29 | USE ieee.numeric_std.ALL; | |
30 | LIBRARY grlib; |
|
30 | LIBRARY grlib; | |
31 | USE grlib.amba.ALL; |
|
31 | USE grlib.amba.ALL; | |
32 | USE grlib.stdlib.ALL; |
|
32 | USE grlib.stdlib.ALL; | |
33 | USE grlib.devices.ALL; |
|
33 | USE grlib.devices.ALL; | |
34 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | USE GRLIB.DMA2AHB_Package.ALL; | |
35 | --USE GRLIB.DMA2AHB_TestPackage.ALL; |
|
35 | --USE GRLIB.DMA2AHB_TestPackage.ALL; | |
36 | LIBRARY lpp; |
|
36 | LIBRARY lpp; | |
37 | USE lpp.lpp_amba.ALL; |
|
37 | USE lpp.lpp_amba.ALL; | |
38 | USE lpp.apb_devices_list.ALL; |
|
38 | USE lpp.apb_devices_list.ALL; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_dma_pkg.ALL; |
|
40 | USE lpp.lpp_dma_pkg.ALL; | |
41 | LIBRARY techmap; |
|
41 | LIBRARY techmap; | |
42 | USE techmap.gencomp.ALL; |
|
42 | USE techmap.gencomp.ALL; | |
43 |
|
43 | |||
44 |
|
44 | |||
45 | ENTITY lpp_dma_ip IS |
|
45 | ENTITY lpp_dma_ip IS | |
46 | GENERIC ( |
|
46 | GENERIC ( | |
47 | tech : INTEGER := inferred; |
|
47 | tech : INTEGER := inferred; | |
48 | hindex : INTEGER := 2 |
|
48 | hindex : INTEGER := 2 | |
49 | ); |
|
49 | ); | |
50 | PORT ( |
|
50 | PORT ( | |
51 | -- AMBA AHB system signals |
|
51 | -- AMBA AHB system signals | |
52 | HCLK : IN STD_ULOGIC; |
|
52 | HCLK : IN STD_ULOGIC; | |
53 | HRESETn : IN STD_ULOGIC; |
|
53 | HRESETn : IN STD_ULOGIC; | |
54 |
|
54 | |||
55 | -- AMBA AHB Master Interface |
|
55 | -- AMBA AHB Master Interface | |
56 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
56 | AHB_Master_In : IN AHB_Mst_In_Type; | |
57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
57 | AHB_Master_Out : OUT AHB_Mst_Out_Type; | |
58 |
|
58 | |||
59 | -- fifo interface |
|
59 | -- fifo interface | |
60 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
61 | fifo_empty : IN STD_LOGIC; |
|
61 | fifo_empty : IN STD_LOGIC; | |
62 | fifo_ren : OUT STD_LOGIC; |
|
62 | fifo_ren : OUT STD_LOGIC; | |
63 |
|
63 | |||
64 | -- header |
|
64 | -- header | |
65 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
66 | header_val : IN STD_LOGIC; |
|
66 | header_val : IN STD_LOGIC; | |
67 | header_ack : OUT STD_LOGIC; |
|
67 | header_ack : OUT STD_LOGIC; | |
68 |
|
68 | |||
69 | -- Reg out |
|
69 | -- Reg out | |
70 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
70 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
71 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
71 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
72 | ready_matrix_f1 : OUT STD_LOGIC; |
|
72 | ready_matrix_f1 : OUT STD_LOGIC; | |
73 | ready_matrix_f2 : OUT STD_LOGIC; |
|
73 | ready_matrix_f2 : OUT STD_LOGIC; | |
74 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
74 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |
75 | error_bad_component_error : OUT STD_LOGIC; |
|
75 | error_bad_component_error : OUT STD_LOGIC; | |
76 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
77 |
|
77 | |||
78 | -- Reg In |
|
78 | -- Reg In | |
79 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
|
79 | status_ready_matrix_f0_0 :IN STD_LOGIC; | |
80 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
|
80 | status_ready_matrix_f0_1 :IN STD_LOGIC; | |
81 | status_ready_matrix_f1 :IN STD_LOGIC; |
|
81 | status_ready_matrix_f1 :IN STD_LOGIC; | |
82 | status_ready_matrix_f2 :IN STD_LOGIC; |
|
82 | status_ready_matrix_f2 :IN STD_LOGIC; | |
83 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
|
83 | status_error_anticipating_empty_fifo :IN STD_LOGIC; | |
84 | status_error_bad_component_error :IN STD_LOGIC; |
|
84 | status_error_bad_component_error :IN STD_LOGIC; | |
85 |
|
85 | |||
86 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
86 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |
87 | config_active_interruption_onError : IN STD_LOGIC; |
|
87 | config_active_interruption_onError : IN STD_LOGIC; | |
88 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
89 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
91 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
92 | ); |
|
92 | ); | |
93 | END; |
|
93 | END; | |
94 |
|
94 | |||
95 | ARCHITECTURE Behavioral OF lpp_dma_ip IS |
|
95 | ARCHITECTURE Behavioral OF lpp_dma_ip IS | |
96 | ----------------------------------------------------------------------------- |
|
96 | ----------------------------------------------------------------------------- | |
97 | SIGNAL DMAIn : DMA_In_Type; |
|
97 | SIGNAL DMAIn : DMA_In_Type; | |
98 | SIGNAL header_dmai : DMA_In_Type; |
|
98 | SIGNAL header_dmai : DMA_In_Type; | |
99 | SIGNAL component_dmai : DMA_In_Type; |
|
99 | SIGNAL component_dmai : DMA_In_Type; | |
100 | SIGNAL DMAOut : DMA_OUt_Type; |
|
100 | SIGNAL DMAOut : DMA_OUt_Type; | |
101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
102 |
|
102 | |||
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | ----------------------------------------------------------------------------- |
|
104 | ----------------------------------------------------------------------------- | |
105 | TYPE state_DMAWriteBurst IS (IDLE, |
|
105 | TYPE state_DMAWriteBurst IS (IDLE, | |
106 | CHECK_COMPONENT_TYPE, |
|
106 | CHECK_COMPONENT_TYPE, | |
107 | TRASH_FIFO, |
|
107 | TRASH_FIFO, | |
108 | WAIT_HEADER_ACK, |
|
108 | WAIT_HEADER_ACK, | |
109 | SEND_DATA, |
|
109 | SEND_DATA, | |
110 | WAIT_DATA_ACK, |
|
110 | WAIT_DATA_ACK, | |
111 | CHECK_LENGTH |
|
111 | CHECK_LENGTH | |
112 | ); |
|
112 | ); | |
113 | SIGNAL state : state_DMAWriteBurst := IDLE; |
|
113 | SIGNAL state : state_DMAWriteBurst := IDLE; | |
114 |
|
114 | |||
115 | SIGNAL nbSend : INTEGER; |
|
115 | SIGNAL nbSend : INTEGER; | |
116 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
116 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
117 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
117 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
118 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
118 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
119 | SIGNAL header_check_ok : STD_LOGIC; |
|
119 | SIGNAL header_check_ok : STD_LOGIC; | |
120 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL send_matrix : STD_LOGIC; |
|
121 | SIGNAL send_matrix : STD_LOGIC; | |
122 | SIGNAL request : STD_LOGIC; |
|
122 | SIGNAL request : STD_LOGIC; | |
123 | SIGNAL remaining_data_request : INTEGER; |
|
123 | SIGNAL remaining_data_request : INTEGER; | |
124 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
124 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
125 | ----------------------------------------------------------------------------- |
|
125 | ----------------------------------------------------------------------------- | |
126 | ----------------------------------------------------------------------------- |
|
126 | ----------------------------------------------------------------------------- | |
127 | SIGNAL header_select : STD_LOGIC; |
|
127 | SIGNAL header_select : STD_LOGIC; | |
128 |
|
128 | |||
129 | SIGNAL header_send : STD_LOGIC; |
|
129 | SIGNAL header_send : STD_LOGIC; | |
130 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
131 | SIGNAL header_send_ok : STD_LOGIC; |
|
131 | SIGNAL header_send_ok : STD_LOGIC; | |
132 | SIGNAL header_send_ko : STD_LOGIC; |
|
132 | SIGNAL header_send_ko : STD_LOGIC; | |
133 |
|
133 | |||
134 | SIGNAL component_send : STD_LOGIC; |
|
134 | SIGNAL component_send : STD_LOGIC; | |
135 | SIGNAL component_send_ok : STD_LOGIC; |
|
135 | SIGNAL component_send_ok : STD_LOGIC; | |
136 | SIGNAL component_send_ko : STD_LOGIC; |
|
136 | SIGNAL component_send_ko : STD_LOGIC; | |
137 | ----------------------------------------------------------------------------- |
|
137 | ----------------------------------------------------------------------------- | |
138 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
138 | SIGNAL fifo_ren_trash : STD_LOGIC; | |
139 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
139 | SIGNAL component_fifo_ren : STD_LOGIC; | |
140 |
|
140 | |||
141 | ----------------------------------------------------------------------------- |
|
141 | ----------------------------------------------------------------------------- | |
142 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
143 |
|
143 | |||
144 | BEGIN |
|
144 | BEGIN | |
145 |
|
145 | |||
146 | ----------------------------------------------------------------------------- |
|
146 | ----------------------------------------------------------------------------- | |
147 | -- DMA to AHB interface |
|
147 | -- DMA to AHB interface | |
148 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
149 |
|
149 | |||
150 | DMA2AHB_1 : DMA2AHB |
|
150 | DMA2AHB_1 : DMA2AHB | |
151 | GENERIC MAP ( |
|
151 | GENERIC MAP ( | |
152 | hindex => hindex, |
|
152 | hindex => hindex, | |
153 | vendorid => VENDOR_LPP, |
|
153 | vendorid => VENDOR_LPP, | |
154 |
deviceid => |
|
154 | deviceid => 11, | |
155 | version => 0, |
|
155 | version => 0, | |
156 | syncrst => 1, |
|
156 | syncrst => 1, | |
157 | boundary => 1) -- FIX 11/01/2013 |
|
157 | boundary => 1) -- FIX 11/01/2013 | |
158 | PORT MAP ( |
|
158 | PORT MAP ( | |
159 | HCLK => HCLK, |
|
159 | HCLK => HCLK, | |
160 | HRESETn => HRESETn, |
|
160 | HRESETn => HRESETn, | |
161 | DMAIn => DMAIn, |
|
161 | DMAIn => DMAIn, | |
162 | DMAOut => DMAOut, |
|
162 | DMAOut => DMAOut, | |
163 | AHBIn => AHB_Master_In, |
|
163 | AHBIn => AHB_Master_In, | |
164 | AHBOut => AHB_Master_Out); |
|
164 | AHBOut => AHB_Master_Out); | |
165 |
|
165 | |||
166 | debug_reg <= debug_reg_s; |
|
166 | debug_reg <= debug_reg_s; | |
167 |
|
167 | |||
168 | debug_info: PROCESS (HCLK, HRESETn) |
|
168 | debug_info: PROCESS (HCLK, HRESETn) | |
169 | BEGIN -- PROCESS debug_info |
|
169 | BEGIN -- PROCESS debug_info | |
170 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
170 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
171 | debug_reg_s <= (OTHERS => '0'); |
|
171 | debug_reg_s <= (OTHERS => '0'); | |
172 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge |
|
172 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |
173 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); |
|
173 | debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry ); | |
174 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; |
|
174 | debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ; | |
175 | IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF; |
|
175 | IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF; | |
176 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); |
|
176 | debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko); | |
177 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); |
|
177 | debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok); | |
178 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); |
|
178 | debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko); | |
179 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); |
|
179 | debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok); | |
180 |
|
180 | |||
181 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); |
|
181 | debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1'); | |
182 | END IF; |
|
182 | END IF; | |
183 | END PROCESS debug_info; |
|
183 | END PROCESS debug_info; | |
184 |
|
184 | |||
185 |
|
185 | |||
186 |
|
186 | |||
187 |
|
187 | |||
188 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
|
188 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE | |
189 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
189 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
190 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
190 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE | |
191 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
191 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE | |
192 | '0'; |
|
192 | '0'; | |
193 |
|
193 | |||
194 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
194 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" | |
195 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE |
|
195 | '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE | |
196 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
196 | '1' WHEN component_type = component_type_pre + "0001" ELSE | |
197 | '0'; |
|
197 | '0'; | |
198 |
|
198 | |||
199 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
199 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE | |
200 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
200 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
201 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
201 | addr_matrix_f1 WHEN matrix_type = "10" ELSE | |
202 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
202 | addr_matrix_f2 WHEN matrix_type = "11" ELSE | |
203 | (OTHERS => '0'); |
|
203 | (OTHERS => '0'); | |
204 |
|
204 | |||
205 | ----------------------------------------------------------------------------- |
|
205 | ----------------------------------------------------------------------------- | |
206 | -- DMA control |
|
206 | -- DMA control | |
207 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
208 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
208 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) | |
209 | BEGIN -- PROCESS DMAWriteBurst_p |
|
209 | BEGIN -- PROCESS DMAWriteBurst_p | |
210 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
210 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
211 | matrix_type <= (others => '0'); |
|
211 | matrix_type <= (others => '0'); | |
212 | component_type <= (others => '0'); |
|
212 | component_type <= (others => '0'); | |
213 | state <= IDLE; |
|
213 | state <= IDLE; | |
214 | header_ack <= '0'; |
|
214 | header_ack <= '0'; | |
215 | ready_matrix_f0_0 <= '0'; |
|
215 | ready_matrix_f0_0 <= '0'; | |
216 | ready_matrix_f0_1 <= '0'; |
|
216 | ready_matrix_f0_1 <= '0'; | |
217 | ready_matrix_f1 <= '0'; |
|
217 | ready_matrix_f1 <= '0'; | |
218 | ready_matrix_f2 <= '0'; |
|
218 | ready_matrix_f2 <= '0'; | |
219 | error_anticipating_empty_fifo <= '0'; |
|
219 | error_anticipating_empty_fifo <= '0'; | |
220 | error_bad_component_error <= '0'; |
|
220 | error_bad_component_error <= '0'; | |
221 | component_type_pre <= "0000"; |
|
221 | component_type_pre <= "0000"; | |
222 | fifo_ren_trash <= '1'; |
|
222 | fifo_ren_trash <= '1'; | |
223 | component_send <= '0'; |
|
223 | component_send <= '0'; | |
224 | address <= (OTHERS => '0'); |
|
224 | address <= (OTHERS => '0'); | |
225 | header_select <= '0'; |
|
225 | header_select <= '0'; | |
226 | header_send <= '0'; |
|
226 | header_send <= '0'; | |
227 | header_data <= (OTHERS => '0'); |
|
227 | header_data <= (OTHERS => '0'); | |
228 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
228 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
229 |
|
229 | |||
230 | CASE state IS |
|
230 | CASE state IS | |
231 | WHEN IDLE => |
|
231 | WHEN IDLE => | |
232 | matrix_type <= header(1 DOWNTO 0); |
|
232 | matrix_type <= header(1 DOWNTO 0); | |
233 | --component_type <= header(5 DOWNTO 2); |
|
233 | --component_type <= header(5 DOWNTO 2); | |
234 |
|
234 | |||
235 | ready_matrix_f0_0 <= '0'; |
|
235 | ready_matrix_f0_0 <= '0'; | |
236 | ready_matrix_f0_1 <= '0'; |
|
236 | ready_matrix_f0_1 <= '0'; | |
237 | ready_matrix_f1 <= '0'; |
|
237 | ready_matrix_f1 <= '0'; | |
238 | ready_matrix_f2 <= '0'; |
|
238 | ready_matrix_f2 <= '0'; | |
239 | error_bad_component_error <= '0'; |
|
239 | error_bad_component_error <= '0'; | |
240 | header_select <= '1'; |
|
240 | header_select <= '1'; | |
241 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
241 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
242 | matrix_type <= header(1 DOWNTO 0); |
|
242 | matrix_type <= header(1 DOWNTO 0); | |
243 | component_type <= header(5 DOWNTO 2); |
|
243 | component_type <= header(5 DOWNTO 2); | |
244 | component_type_pre <= component_type; |
|
244 | component_type_pre <= component_type; | |
245 | state <= CHECK_COMPONENT_TYPE; |
|
245 | state <= CHECK_COMPONENT_TYPE; | |
246 | END IF; |
|
246 | END IF; | |
247 |
|
247 | |||
248 | WHEN CHECK_COMPONENT_TYPE => |
|
248 | WHEN CHECK_COMPONENT_TYPE => | |
249 | IF header_check_ok = '1' THEN |
|
249 | IF header_check_ok = '1' THEN | |
250 | header_ack <= '1'; |
|
250 | header_ack <= '1'; | |
251 | -- |
|
251 | -- | |
252 | header_send <= '1'; |
|
252 | header_send <= '1'; | |
253 | IF component_type = "0000" THEN |
|
253 | IF component_type = "0000" THEN | |
254 | address <= address_matrix; |
|
254 | address <= address_matrix; | |
255 | END IF; |
|
255 | END IF; | |
256 | header_data <= header; |
|
256 | header_data <= header; | |
257 | -- |
|
257 | -- | |
258 | state <= WAIT_HEADER_ACK; |
|
258 | state <= WAIT_HEADER_ACK; | |
259 | ELSE |
|
259 | ELSE | |
260 | error_bad_component_error <= '1'; |
|
260 | error_bad_component_error <= '1'; | |
261 | component_type_pre <= "0000"; |
|
261 | component_type_pre <= "0000"; | |
262 | header_ack <= '1'; |
|
262 | header_ack <= '1'; | |
263 | state <= TRASH_FIFO; |
|
263 | state <= TRASH_FIFO; | |
264 | END IF; |
|
264 | END IF; | |
265 |
|
265 | |||
266 |
|
266 | |||
267 | WHEN TRASH_FIFO => |
|
267 | WHEN TRASH_FIFO => | |
268 | header_ack <= '0'; |
|
268 | header_ack <= '0'; | |
269 | error_bad_component_error <= '0'; |
|
269 | error_bad_component_error <= '0'; | |
270 | error_anticipating_empty_fifo <= '0'; |
|
270 | error_anticipating_empty_fifo <= '0'; | |
271 | IF fifo_empty = '1' THEN |
|
271 | IF fifo_empty = '1' THEN | |
272 | state <= IDLE; |
|
272 | state <= IDLE; | |
273 | fifo_ren_trash <= '1'; |
|
273 | fifo_ren_trash <= '1'; | |
274 | ELSE |
|
274 | ELSE | |
275 | fifo_ren_trash <= '0'; |
|
275 | fifo_ren_trash <= '0'; | |
276 | END IF; |
|
276 | END IF; | |
277 |
|
277 | |||
278 | WHEN WAIT_HEADER_ACK => |
|
278 | WHEN WAIT_HEADER_ACK => | |
279 | header_ack <= '0'; |
|
279 | header_ack <= '0'; | |
280 | header_send <= '0'; |
|
280 | header_send <= '0'; | |
281 | IF header_send_ko = '1' THEN |
|
281 | IF header_send_ko = '1' THEN | |
282 | state <= TRASH_FIFO; |
|
282 | state <= TRASH_FIFO; | |
283 | error_anticipating_empty_fifo <= '1'; |
|
283 | error_anticipating_empty_fifo <= '1'; | |
284 | -- TODO : error sending header |
|
284 | -- TODO : error sending header | |
285 | ELSIF header_send_ok = '1' THEN |
|
285 | ELSIF header_send_ok = '1' THEN | |
286 | header_select <= '0'; |
|
286 | header_select <= '0'; | |
287 | state <= SEND_DATA; |
|
287 | state <= SEND_DATA; | |
288 | address <= address + 4; |
|
288 | address <= address + 4; | |
289 | END IF; |
|
289 | END IF; | |
290 |
|
290 | |||
291 | WHEN SEND_DATA => |
|
291 | WHEN SEND_DATA => | |
292 | IF fifo_empty = '1' THEN |
|
292 | IF fifo_empty = '1' THEN | |
293 | state <= IDLE; |
|
293 | state <= IDLE; | |
294 | IF component_type = "1110" THEN --"1110" -- JC |
|
294 | IF component_type = "1110" THEN --"1110" -- JC | |
295 | CASE matrix_type IS |
|
295 | CASE matrix_type IS | |
296 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
296 | WHEN "00" => ready_matrix_f0_0 <= '1'; | |
297 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
297 | WHEN "01" => ready_matrix_f0_1 <= '1'; | |
298 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
298 | WHEN "10" => ready_matrix_f1 <= '1'; | |
299 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
299 | WHEN "11" => ready_matrix_f2 <= '1'; | |
300 | WHEN OTHERS => NULL; |
|
300 | WHEN OTHERS => NULL; | |
301 | END CASE; |
|
301 | END CASE; | |
302 |
|
302 | |||
303 | END IF; |
|
303 | END IF; | |
304 | ELSE |
|
304 | ELSE | |
305 | component_send <= '1'; |
|
305 | component_send <= '1'; | |
306 | address <= address; |
|
306 | address <= address; | |
307 | state <= WAIT_DATA_ACK; |
|
307 | state <= WAIT_DATA_ACK; | |
308 | END IF; |
|
308 | END IF; | |
309 |
|
309 | |||
310 | WHEN WAIT_DATA_ACK => |
|
310 | WHEN WAIT_DATA_ACK => | |
311 | component_send <= '0'; |
|
311 | component_send <= '0'; | |
312 | IF component_send_ok = '1' THEN |
|
312 | IF component_send_ok = '1' THEN | |
313 | address <= address + 64; |
|
313 | address <= address + 64; | |
314 | state <= SEND_DATA; |
|
314 | state <= SEND_DATA; | |
315 | ELSIF component_send_ko = '1' THEN |
|
315 | ELSIF component_send_ko = '1' THEN | |
316 | error_anticipating_empty_fifo <= '0'; |
|
316 | error_anticipating_empty_fifo <= '0'; | |
317 | state <= TRASH_FIFO; |
|
317 | state <= TRASH_FIFO; | |
318 | END IF; |
|
318 | END IF; | |
319 |
|
319 | |||
320 | WHEN CHECK_LENGTH => |
|
320 | WHEN CHECK_LENGTH => | |
321 | state <= IDLE; |
|
321 | state <= IDLE; | |
322 | WHEN OTHERS => NULL; |
|
322 | WHEN OTHERS => NULL; | |
323 | END CASE; |
|
323 | END CASE; | |
324 |
|
324 | |||
325 | END IF; |
|
325 | END IF; | |
326 | END PROCESS DMAWriteFSM_p; |
|
326 | END PROCESS DMAWriteFSM_p; | |
327 |
|
327 | |||
328 | ----------------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------------- | |
329 | -- SEND 1 word by DMA |
|
329 | -- SEND 1 word by DMA | |
330 | ----------------------------------------------------------------------------- |
|
330 | ----------------------------------------------------------------------------- | |
331 | lpp_dma_send_1word_1 : lpp_dma_send_1word |
|
331 | lpp_dma_send_1word_1 : lpp_dma_send_1word | |
332 | PORT MAP ( |
|
332 | PORT MAP ( | |
333 | HCLK => HCLK, |
|
333 | HCLK => HCLK, | |
334 | HRESETn => HRESETn, |
|
334 | HRESETn => HRESETn, | |
335 | DMAIn => header_dmai, |
|
335 | DMAIn => header_dmai, | |
336 | DMAOut => DMAOut, |
|
336 | DMAOut => DMAOut, | |
337 |
|
337 | |||
338 | send => header_send, |
|
338 | send => header_send, | |
339 | address => address, |
|
339 | address => address, | |
340 | data => header_data, |
|
340 | data => header_data, | |
341 | send_ok => header_send_ok, |
|
341 | send_ok => header_send_ok, | |
342 | send_ko => header_send_ko |
|
342 | send_ko => header_send_ko | |
343 | ); |
|
343 | ); | |
344 |
|
344 | |||
345 | ----------------------------------------------------------------------------- |
|
345 | ----------------------------------------------------------------------------- | |
346 | -- SEND 16 word by DMA (in burst mode) |
|
346 | -- SEND 16 word by DMA (in burst mode) | |
347 | ----------------------------------------------------------------------------- |
|
347 | ----------------------------------------------------------------------------- | |
348 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
|
348 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
349 | PORT MAP ( |
|
349 | PORT MAP ( | |
350 | HCLK => HCLK, |
|
350 | HCLK => HCLK, | |
351 | HRESETn => HRESETn, |
|
351 | HRESETn => HRESETn, | |
352 | DMAIn => component_dmai, |
|
352 | DMAIn => component_dmai, | |
353 | DMAOut => DMAOut, |
|
353 | DMAOut => DMAOut, | |
354 |
|
354 | |||
355 | send => component_send, |
|
355 | send => component_send, | |
356 | address => address, |
|
356 | address => address, | |
357 | data => fifo_data, |
|
357 | data => fifo_data, | |
358 | ren => component_fifo_ren, |
|
358 | ren => component_fifo_ren, | |
359 | send_ok => component_send_ok, |
|
359 | send_ok => component_send_ok, | |
360 | send_ko => component_send_ko); |
|
360 | send_ko => component_send_ko); | |
361 |
|
361 | |||
362 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; |
|
362 | DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; | |
363 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; |
|
363 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; | |
364 |
|
364 | |||
365 | END Behavioral; No newline at end of file |
|
365 | END Behavioral; |
@@ -1,304 +1,304 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | LIBRARY lpp; |
|
3 | LIBRARY lpp; | |
4 | USE lpp.lpp_ad_conv.ALL; |
|
4 | USE lpp.lpp_ad_conv.ALL; | |
5 | USE lpp.iir_filter.ALL; |
|
5 | USE lpp.iir_filter.ALL; | |
6 | USE lpp.FILTERcfg.ALL; |
|
6 | USE lpp.FILTERcfg.ALL; | |
7 | USE lpp.lpp_memory.ALL; |
|
7 | USE lpp.lpp_memory.ALL; | |
8 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
8 | USE lpp.lpp_top_lfr_pkg.ALL; | |
9 | LIBRARY techmap; |
|
9 | LIBRARY techmap; | |
10 | USE techmap.gencomp.ALL; |
|
10 | USE techmap.gencomp.ALL; | |
11 |
|
11 | |||
12 | ENTITY lpp_top_acq IS |
|
12 | ENTITY lpp_top_acq IS | |
13 | GENERIC( |
|
13 | GENERIC( | |
14 | tech : INTEGER := 0; |
|
14 | tech : INTEGER := 0; | |
15 | Mem_use : integer := use_RAM |
|
15 | Mem_use : integer := use_RAM | |
16 | ); |
|
16 | ); | |
17 | PORT ( |
|
17 | PORT ( | |
18 | -- ADS7886 |
|
18 | -- ADS7886 | |
19 | cnv_run : IN STD_LOGIC; |
|
19 | cnv_run : IN STD_LOGIC; | |
20 | cnv : OUT STD_LOGIC; |
|
20 | cnv : OUT STD_LOGIC; | |
21 | sck : OUT STD_LOGIC; |
|
21 | sck : OUT STD_LOGIC; | |
22 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
22 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
23 | -- |
|
23 | -- | |
24 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
|
24 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
25 | cnv_rstn : IN STD_LOGIC; |
|
25 | cnv_rstn : IN STD_LOGIC; | |
26 | -- |
|
26 | -- | |
27 | clk : IN STD_LOGIC; -- 25 MHz |
|
27 | clk : IN STD_LOGIC; -- 25 MHz | |
28 | rstn : IN STD_LOGIC; |
|
28 | rstn : IN STD_LOGIC; | |
29 | -- |
|
29 | -- | |
30 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
31 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
32 | -- |
|
32 | -- | |
33 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
34 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
35 | -- |
|
35 | -- | |
36 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
37 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
38 | -- |
|
38 | -- | |
39 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
39 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
40 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
|
40 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |
41 | ); |
|
41 | ); | |
42 | END lpp_top_acq; |
|
42 | END lpp_top_acq; | |
43 |
|
43 | |||
44 | ARCHITECTURE tb OF lpp_top_acq IS |
|
44 | ARCHITECTURE tb OF lpp_top_acq IS | |
45 |
|
45 | |||
46 | COMPONENT Downsampling |
|
46 | COMPONENT Downsampling | |
47 | GENERIC ( |
|
47 | GENERIC ( | |
48 | ChanelCount : INTEGER; |
|
48 | ChanelCount : INTEGER; | |
49 | SampleSize : INTEGER; |
|
49 | SampleSize : INTEGER; | |
50 | DivideParam : INTEGER); |
|
50 | DivideParam : INTEGER); | |
51 | PORT ( |
|
51 | PORT ( | |
52 | clk : IN STD_LOGIC; |
|
52 | clk : IN STD_LOGIC; | |
53 | rstn : IN STD_LOGIC; |
|
53 | rstn : IN STD_LOGIC; | |
54 | sample_in_val : IN STD_LOGIC; |
|
54 | sample_in_val : IN STD_LOGIC; | |
55 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); |
|
55 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |
56 | sample_out_val : OUT STD_LOGIC; |
|
56 | sample_out_val : OUT STD_LOGIC; | |
57 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); |
|
57 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |
58 | END COMPONENT; |
|
58 | END COMPONENT; | |
59 |
|
59 | |||
60 | ----------------------------------------------------------------------------- |
|
60 | ----------------------------------------------------------------------------- | |
61 | CONSTANT ChanelCount : INTEGER := 8; |
|
61 | CONSTANT ChanelCount : INTEGER := 8; | |
62 | CONSTANT ncycle_cnv_high : INTEGER := 79; |
|
62 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |
63 | CONSTANT ncycle_cnv : INTEGER := 500; |
|
63 | CONSTANT ncycle_cnv : INTEGER := 500; | |
64 |
|
64 | |||
65 | ----------------------------------------------------------------------------- |
|
65 | ----------------------------------------------------------------------------- | |
66 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); |
|
66 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |
67 | SIGNAL sample_val : STD_LOGIC; |
|
67 | SIGNAL sample_val : STD_LOGIC; | |
68 | SIGNAL sample_val_delay : STD_LOGIC; |
|
68 | SIGNAL sample_val_delay : STD_LOGIC; | |
69 | ----------------------------------------------------------------------------- |
|
69 | ----------------------------------------------------------------------------- | |
70 | CONSTANT Coef_SZ : INTEGER := 9; |
|
70 | CONSTANT Coef_SZ : INTEGER := 9; | |
71 | CONSTANT CoefCntPerCel : INTEGER := 6; |
|
71 | CONSTANT CoefCntPerCel : INTEGER := 6; | |
72 | CONSTANT CoefPerCel : INTEGER := 5; |
|
72 | CONSTANT CoefPerCel : INTEGER := 5; | |
73 | CONSTANT Cels_count : INTEGER := 5; |
|
73 | CONSTANT Cels_count : INTEGER := 5; | |
74 |
|
74 | |||
75 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); |
|
75 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |
76 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
76 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
77 | -- |
|
77 | -- | |
78 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; |
|
78 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |
79 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
79 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
80 | -- |
|
80 | -- | |
81 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; |
|
81 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |
82 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
82 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
83 | ----------------------------------------------------------------------------- |
|
83 | ----------------------------------------------------------------------------- | |
84 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
84 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
85 | SIGNAL sample_downsampling_out_val : STD_LOGIC; |
|
85 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |
86 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
86 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
87 | -- |
|
87 | -- | |
88 | SIGNAL sample_f0_val : STD_LOGIC; |
|
88 | SIGNAL sample_f0_val : STD_LOGIC; | |
89 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
89 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
90 | ----------------------------------------------------------------------------- |
|
90 | ----------------------------------------------------------------------------- | |
91 | SIGNAL sample_f1_val : STD_LOGIC; |
|
91 | SIGNAL sample_f1_val : STD_LOGIC; | |
92 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
92 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
93 | -- |
|
93 | -- | |
94 | SIGNAL sample_f2_val : STD_LOGIC; |
|
94 | SIGNAL sample_f2_val : STD_LOGIC; | |
95 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
95 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
96 | -- |
|
96 | -- | |
97 | SIGNAL sample_f3_val : STD_LOGIC; |
|
97 | SIGNAL sample_f3_val : STD_LOGIC; | |
98 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); |
|
98 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |
99 |
|
99 | |||
100 | BEGIN |
|
100 | BEGIN | |
101 |
|
101 | |||
102 | -- component instantiation |
|
102 | -- component instantiation | |
103 | ----------------------------------------------------------------------------- |
|
103 | ----------------------------------------------------------------------------- | |
104 | DIGITAL_acquisition : AD7688_drvr |
|
104 | DIGITAL_acquisition : AD7688_drvr | |
105 | GENERIC MAP ( |
|
105 | GENERIC MAP ( | |
106 | ChanelCount => ChanelCount, |
|
106 | ChanelCount => ChanelCount, | |
107 | ncycle_cnv_high => ncycle_cnv_high, |
|
107 | ncycle_cnv_high => ncycle_cnv_high, | |
108 | ncycle_cnv => ncycle_cnv) |
|
108 | ncycle_cnv => ncycle_cnv) | |
109 | PORT MAP ( |
|
109 | PORT MAP ( | |
110 | cnv_clk => cnv_clk, -- |
|
110 | cnv_clk => cnv_clk, -- | |
111 | cnv_rstn => cnv_rstn, -- |
|
111 | cnv_rstn => cnv_rstn, -- | |
112 | cnv_run => cnv_run, -- |
|
112 | cnv_run => cnv_run, -- | |
113 | cnv => cnv, -- |
|
113 | cnv => cnv, -- | |
114 | clk => clk, -- |
|
114 | clk => clk, -- | |
115 | rstn => rstn, -- |
|
115 | rstn => rstn, -- | |
116 | sck => sck, -- |
|
116 | sck => sck, -- | |
117 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
|
117 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |
118 | sample => sample, |
|
118 | sample => sample, | |
119 | sample_val => sample_val); |
|
119 | sample_val => sample_val); | |
120 |
|
120 | |||
121 | ----------------------------------------------------------------------------- |
|
121 | ----------------------------------------------------------------------------- | |
122 |
|
122 | |||
123 | PROCESS (clk, rstn) |
|
123 | PROCESS (clk, rstn) | |
124 | BEGIN -- PROCESS |
|
124 | BEGIN -- PROCESS | |
125 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
125 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
126 | sample_val_delay <= '0'; |
|
126 | sample_val_delay <= '0'; | |
127 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
127 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
128 | sample_val_delay <= sample_val; |
|
128 | sample_val_delay <= sample_val; | |
129 | END IF; |
|
129 | END IF; | |
130 | END PROCESS; |
|
130 | END PROCESS; | |
131 |
|
131 | |||
132 | ----------------------------------------------------------------------------- |
|
132 | ----------------------------------------------------------------------------- | |
133 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE |
|
133 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |
134 | SampleLoop : FOR j IN 0 TO 15 GENERATE |
|
134 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |
135 | sample_filter_in(i, j) <= sample(i)(j); |
|
135 | sample_filter_in(i, j) <= sample(i)(j); | |
136 | END GENERATE; |
|
136 | END GENERATE; | |
137 |
|
137 | |||
138 | sample_filter_in(i, 16) <= sample(i)(15); |
|
138 | sample_filter_in(i, 16) <= sample(i)(15); | |
139 | sample_filter_in(i, 17) <= sample(i)(15); |
|
139 | sample_filter_in(i, 17) <= sample(i)(15); | |
140 | END GENERATE; |
|
140 | END GENERATE; | |
141 |
|
141 | |||
142 | coefs_v2 <= CoefsInitValCst_v2; |
|
142 | coefs_v2 <= CoefsInitValCst_v2; | |
143 |
|
143 | |||
144 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 |
|
144 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
145 | GENERIC MAP ( |
|
145 | GENERIC MAP ( | |
146 | tech => 0, |
|
146 | tech => 0, | |
147 | Mem_use => Mem_use, |
|
147 | Mem_use => Mem_use, | |
148 | Sample_SZ => 18, |
|
148 | Sample_SZ => 18, | |
149 | Coef_SZ => Coef_SZ, |
|
149 | Coef_SZ => Coef_SZ, | |
150 | Coef_Nb => 25, -- TODO |
|
150 | Coef_Nb => 25, -- TODO | |
151 | Coef_sel_SZ => 5, -- TODO |
|
151 | Coef_sel_SZ => 5, -- TODO | |
152 | Cels_count => Cels_count, |
|
152 | Cels_count => Cels_count, | |
153 | ChanelsCount => ChanelCount) |
|
153 | ChanelsCount => ChanelCount) | |
154 | PORT MAP ( |
|
154 | PORT MAP ( | |
155 | rstn => rstn, |
|
155 | rstn => rstn, | |
156 | clk => clk, |
|
156 | clk => clk, | |
157 | virg_pos => 7, |
|
157 | virg_pos => 7, | |
158 | coefs => coefs_v2, |
|
158 | coefs => coefs_v2, | |
159 | sample_in_val => sample_val_delay, |
|
159 | sample_in_val => sample_val_delay, | |
160 | sample_in => sample_filter_in, |
|
160 | sample_in => sample_filter_in, | |
161 | sample_out_val => sample_filter_v2_out_val, |
|
161 | sample_out_val => sample_filter_v2_out_val, | |
162 | sample_out => sample_filter_v2_out); |
|
162 | sample_out => sample_filter_v2_out); | |
163 |
|
163 | |||
164 | ----------------------------------------------------------------------------- |
|
164 | ----------------------------------------------------------------------------- | |
165 | PROCESS (clk, rstn) |
|
165 | PROCESS (clk, rstn) | |
166 | BEGIN -- PROCESS |
|
166 | BEGIN -- PROCESS | |
167 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
167 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
168 | sample_filter_v2_out_r_val <= '0'; |
|
168 | sample_filter_v2_out_r_val <= '0'; | |
169 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
|
169 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |
170 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP |
|
170 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |
171 | sample_filter_v2_out_r(I, J) <= '0'; |
|
171 | sample_filter_v2_out_r(I, J) <= '0'; | |
172 | END LOOP rst_all_bits; |
|
172 | END LOOP rst_all_bits; | |
173 | END LOOP rst_all_chanel; |
|
173 | END LOOP rst_all_chanel; | |
174 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
174 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
175 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; |
|
175 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |
176 | IF sample_filter_v2_out_val = '1' THEN |
|
176 | IF sample_filter_v2_out_val = '1' THEN | |
177 | sample_filter_v2_out_r <= sample_filter_v2_out; |
|
177 | sample_filter_v2_out_r <= sample_filter_v2_out; | |
178 | END IF; |
|
178 | END IF; | |
179 | END IF; |
|
179 | END IF; | |
180 | END PROCESS; |
|
180 | END PROCESS; | |
181 |
|
181 | |||
182 | ----------------------------------------------------------------------------- |
|
182 | ----------------------------------------------------------------------------- | |
183 | -- F0 -- @24.576 kHz |
|
183 | -- F0 -- @24.576 kHz | |
184 | ----------------------------------------------------------------------------- |
|
184 | ----------------------------------------------------------------------------- | |
185 | Downsampling_f0 : Downsampling |
|
185 | Downsampling_f0 : Downsampling | |
186 | GENERIC MAP ( |
|
186 | GENERIC MAP ( | |
187 | ChanelCount => ChanelCount, |
|
187 | ChanelCount => ChanelCount, | |
188 | SampleSize => 18, |
|
188 | SampleSize => 18, | |
189 | DivideParam => 4) |
|
189 | DivideParam => 4) | |
190 | PORT MAP ( |
|
190 | PORT MAP ( | |
191 | clk => clk, |
|
191 | clk => clk, | |
192 | rstn => rstn, |
|
192 | rstn => rstn, | |
193 | sample_in_val => sample_filter_v2_out_val , |
|
193 | sample_in_val => sample_filter_v2_out_val , | |
194 | sample_in => sample_filter_v2_out, |
|
194 | sample_in => sample_filter_v2_out, | |
195 | sample_out_val => sample_f0_val, |
|
195 | sample_out_val => sample_f0_val, | |
196 | sample_out => sample_f0); |
|
196 | sample_out => sample_f0); | |
197 |
|
197 | |||
198 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE |
|
198 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |
199 | sample_f0_wdata(I) <= sample_f0(0, I); |
|
199 | sample_f0_wdata(I) <= sample_f0(0, I); | |
200 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); |
|
200 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |
201 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); |
|
201 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |
202 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); |
|
202 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | |
203 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); |
|
203 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |
204 | END GENERATE all_bit_sample_f0; |
|
204 | END GENERATE all_bit_sample_f0; | |
205 |
|
205 | |||
206 | sample_f0_wen <= NOT(sample_f0_val) & |
|
206 | sample_f0_wen <= NOT(sample_f0_val) & | |
207 | NOT(sample_f0_val) & |
|
207 | NOT(sample_f0_val) & | |
208 | NOT(sample_f0_val) & |
|
208 | NOT(sample_f0_val) & | |
209 | NOT(sample_f0_val) & |
|
209 | NOT(sample_f0_val) & | |
210 | NOT(sample_f0_val); |
|
210 | NOT(sample_f0_val); | |
211 |
|
211 | |||
212 | ----------------------------------------------------------------------------- |
|
212 | ----------------------------------------------------------------------------- | |
213 | -- F1 -- @4096 Hz |
|
213 | -- F1 -- @4096 Hz | |
214 | ----------------------------------------------------------------------------- |
|
214 | ----------------------------------------------------------------------------- | |
215 | Downsampling_f1 : Downsampling |
|
215 | Downsampling_f1 : Downsampling | |
216 | GENERIC MAP ( |
|
216 | GENERIC MAP ( | |
217 | ChanelCount => ChanelCount, |
|
217 | ChanelCount => ChanelCount, | |
218 | SampleSize => 18, |
|
218 | SampleSize => 18, | |
219 | DivideParam => 6) |
|
219 | DivideParam => 6) | |
220 | PORT MAP ( |
|
220 | PORT MAP ( | |
221 | clk => clk, |
|
221 | clk => clk, | |
222 | rstn => rstn, |
|
222 | rstn => rstn, | |
223 | sample_in_val => sample_f0_val , |
|
223 | sample_in_val => sample_f0_val , | |
224 | sample_in => sample_f0, |
|
224 | sample_in => sample_f0, | |
225 | sample_out_val => sample_f1_val, |
|
225 | sample_out_val => sample_f1_val, | |
226 | sample_out => sample_f1); |
|
226 | sample_out => sample_f1); | |
227 |
|
227 | |||
228 | sample_f1_wen <= NOT(sample_f1_val) & |
|
228 | sample_f1_wen <= NOT(sample_f1_val) & | |
229 | NOT(sample_f1_val) & |
|
229 | NOT(sample_f1_val) & | |
230 | NOT(sample_f1_val) & |
|
230 | NOT(sample_f1_val) & | |
231 | NOT(sample_f1_val) & |
|
231 | NOT(sample_f1_val) & | |
232 | NOT(sample_f1_val); |
|
232 | NOT(sample_f1_val); | |
233 |
|
233 | |||
234 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE |
|
234 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |
235 | sample_f1_wdata(I) <= sample_f1(0, I); |
|
235 | sample_f1_wdata(I) <= sample_f1(0, I); | |
236 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); |
|
236 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |
237 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); |
|
237 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |
238 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); |
|
238 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |
239 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); |
|
239 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | |
240 | END GENERATE all_bit_sample_f1; |
|
240 | END GENERATE all_bit_sample_f1; | |
241 |
|
241 | |||
242 | ----------------------------------------------------------------------------- |
|
242 | ----------------------------------------------------------------------------- | |
243 | -- F2 -- @16 Hz |
|
243 | -- F2 -- @16 Hz | |
244 | ----------------------------------------------------------------------------- |
|
244 | ----------------------------------------------------------------------------- | |
245 | Downsampling_f2 : Downsampling |
|
245 | Downsampling_f2 : Downsampling | |
246 | GENERIC MAP ( |
|
246 | GENERIC MAP ( | |
247 | ChanelCount => ChanelCount, |
|
247 | ChanelCount => ChanelCount, | |
248 | SampleSize => 18, |
|
248 | SampleSize => 18, | |
249 | DivideParam => 96) |
|
249 | DivideParam => 96) | |
250 | PORT MAP ( |
|
250 | PORT MAP ( | |
251 | clk => clk, |
|
251 | clk => clk, | |
252 | rstn => rstn, |
|
252 | rstn => rstn, | |
253 | sample_in_val => sample_f1_val , |
|
253 | sample_in_val => sample_f1_val , | |
254 | sample_in => sample_f1, |
|
254 | sample_in => sample_f1, | |
255 | sample_out_val => sample_f2_val, |
|
255 | sample_out_val => sample_f2_val, | |
256 | sample_out => sample_f2); |
|
256 | sample_out => sample_f2); | |
257 |
|
257 | |||
258 | sample_f2_wen <= NOT(sample_f2_val) & |
|
258 | sample_f2_wen <= NOT(sample_f2_val) & | |
259 | NOT(sample_f2_val) & |
|
259 | NOT(sample_f2_val) & | |
260 | NOT(sample_f2_val) & |
|
260 | NOT(sample_f2_val) & | |
261 | NOT(sample_f2_val) & |
|
261 | NOT(sample_f2_val) & | |
262 | NOT(sample_f2_val); |
|
262 | NOT(sample_f2_val); | |
263 |
|
263 | |||
264 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE |
|
264 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |
265 | sample_f2_wdata(I) <= sample_f2(0, I); |
|
265 | sample_f2_wdata(I) <= sample_f2(0, I); | |
266 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); |
|
266 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |
267 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); |
|
267 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |
268 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); |
|
268 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |
269 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); |
|
269 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |
270 | END GENERATE all_bit_sample_f2; |
|
270 | END GENERATE all_bit_sample_f2; | |
271 |
|
271 | |||
272 | ----------------------------------------------------------------------------- |
|
272 | ----------------------------------------------------------------------------- | |
273 | -- F3 -- @256 Hz |
|
273 | -- F3 -- @256 Hz | |
274 | ----------------------------------------------------------------------------- |
|
274 | ----------------------------------------------------------------------------- | |
275 | Downsampling_f3 : Downsampling |
|
275 | Downsampling_f3 : Downsampling | |
276 | GENERIC MAP ( |
|
276 | GENERIC MAP ( | |
277 | ChanelCount => ChanelCount, |
|
277 | ChanelCount => ChanelCount, | |
278 | SampleSize => 18, |
|
278 | SampleSize => 18, | |
279 | DivideParam => 256) |
|
279 | DivideParam => 256) | |
280 | PORT MAP ( |
|
280 | PORT MAP ( | |
281 | clk => clk, |
|
281 | clk => clk, | |
282 | rstn => rstn, |
|
282 | rstn => rstn, | |
283 | sample_in_val => sample_f0_val , |
|
283 | sample_in_val => sample_f0_val , | |
284 | sample_in => sample_f0, |
|
284 | sample_in => sample_f0, | |
285 | sample_out_val => sample_f3_val, |
|
285 | sample_out_val => sample_f3_val, | |
286 | sample_out => sample_f3); |
|
286 | sample_out => sample_f3); | |
287 |
|
287 | |||
288 | sample_f3_wen <= (NOT sample_f3_val) & |
|
288 | sample_f3_wen <= (NOT sample_f3_val) & | |
289 | (NOT sample_f3_val) & |
|
289 | (NOT sample_f3_val) & | |
290 | (NOT sample_f3_val) & |
|
290 | (NOT sample_f3_val) & | |
291 | (NOT sample_f3_val) & |
|
291 | (NOT sample_f3_val) & | |
292 | (NOT sample_f3_val); |
|
292 | (NOT sample_f3_val); | |
293 |
|
293 | |||
294 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE |
|
294 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |
295 | sample_f3_wdata(I) <= sample_f3(0, I); |
|
295 | sample_f3_wdata(I) <= sample_f3(0, I); | |
296 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); |
|
296 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |
297 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); |
|
297 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |
298 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); |
|
298 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |
299 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); |
|
299 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |
300 | END GENERATE all_bit_sample_f3; |
|
300 | END GENERATE all_bit_sample_f3; | |
301 |
|
301 | |||
302 |
|
302 | |||
303 |
|
303 | |||
304 | END tb; |
|
304 | END tb; |
@@ -1,8 +1,13 | |||||
1 | lpp_top_lfr_pkg.vhd |
|
1 | lpp_top_lfr_pkg.vhd | |
|
2 | lpp_lfr_pkg.vhd | |||
2 | lpp_top_apbreg.vhd |
|
3 | lpp_top_apbreg.vhd | |
3 | lpp_top_acq.vhd |
|
4 | lpp_top_acq.vhd | |
4 | lpp_top_lfr_wf_picker.vhd |
|
5 | lpp_top_lfr_wf_picker.vhd | |
5 | lpp_top_lfr_wf_picker_ip.vhd |
|
6 | lpp_top_lfr_wf_picker_ip.vhd | |
6 | lpp_top_lfr_wf_picker_ip_whitout_filter.vhd |
|
7 | lpp_top_lfr_wf_picker_ip_whitout_filter.vhd | |
7 | top_lfr_wf_picker.vhd |
|
8 | top_lfr_wf_picker.vhd | |
|
9 | lpp_lfr_apbreg.vhd | |||
8 | top_wf_picker.vhd |
|
10 | top_wf_picker.vhd | |
|
11 | lpp_lfr_filter.vhd | |||
|
12 | lpp_lfr_ms.vhd | |||
|
13 | lpp_lfr.vhd |
General Comments 0
You need to be logged in to leave comments.
Login now