diff --git a/lib/lpp/lpp_dma/lpp_dma_ip.vhd b/lib/lpp/lpp_dma/lpp_dma_ip.vhd --- a/lib/lpp/lpp_dma/lpp_dma_ip.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_ip.vhd @@ -151,7 +151,7 @@ BEGIN GENERIC MAP ( hindex => hindex, vendorid => VENDOR_LPP, - deviceid => 0, + deviceid => 11, version => 0, syncrst => 1, boundary => 1) -- FIX 11/01/2013 @@ -362,4 +362,4 @@ BEGIN DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; -END Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -0,0 +1,342 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_lfr IS + GENERIC ( + Mem_use : INTEGER := use_RAM; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq_ms : INTEGER := 0; + pirq_wfp : INTEGER := 1; + + hindex_wfp : INTEGER := 2; + hindex_ms : INTEGER := 3 + + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + -- + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + -- + ahbi_wfp : IN AHB_Mst_In_Type; + ahbo_wfp : OUT AHB_Mst_Out_Type; + -- + ahbi_ms : IN AHB_Mst_In_Type; + ahbo_ms : OUT AHB_Mst_Out_Type; + -- + coarse_time_0 : IN STD_LOGIC; + -- + data_shaping_BW : OUT STD_LOGIC + ); +END lpp_lfr; + +ARCHITECTURE beh OF lpp_lfr IS + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + -- + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; + -- + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f3_val : STD_LOGIC; + -- + SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + -- + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + -- SM + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- WFP + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- + SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0); + SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; + + SIGNAL val_f0_wfp : STD_LOGIC; + SIGNAL val_f1_wfp : STD_LOGIC; + SIGNAL val_f2_wfp : STD_LOGIC; + SIGNAL val_f3_wfp : STD_LOGIC; +BEGIN + + sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); + sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); + + all_channel: FOR i IN 7 DOWNTO 0 GENERATE + sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); + END GENERATE all_channel; + + ----------------------------------------------------------------------------- + lpp_lfr_filter_1 : lpp_lfr_filter + GENERIC MAP ( + Mem_use => Mem_use) + PORT MAP ( + sample => sample_s, + sample_val => sample_val, + clk => clk, + rstn => rstn, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + sample_f0_val => sample_f0_val, + sample_f1_val => sample_f1_val, + sample_f2_val => sample_f2_val, + sample_f3_val => sample_f3_val, + sample_f0_wdata => sample_f0_data, + sample_f1_wdata => sample_f1_data, + sample_f2_wdata => sample_f2_data, + sample_f3_wdata => sample_f3_data); + + ----------------------------------------------------------------------------- + lpp_top_apbreg_1 : lpp_lfr_apbreg + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + pindex => pindex, + paddr => paddr, + pmask => pmask, + pirq_ms => pirq_ms, + pirq_wfp => pirq_wfp) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + apbi => apbi, + apbo => apbo, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => data_shaping_BW, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + ----------------------------------------------------------------------------- + lpp_waveform_1: lpp_waveform + GENERIC MAP ( + hindex => hindex_wfp, + tech => inferred, + data_size => 160, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size) + PORT MAP ( + clk => clk, + rstn => rstn, + AHB_Master_In => ahbi_wfp, + AHB_Master_Out => ahbo_wfp, + coarse_time_0 => coarse_time_0, + + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3, + + data_f0_in => data_f0_wfp, + data_f1_in => data_f1_wfp, + data_f2_in => data_f2_wfp, + data_f3_in => data_f3_wfp, + data_f0_in_valid => sample_f0_val, + data_f1_in_valid => sample_f1_val, + data_f2_in_valid => sample_f2_val, + data_f3_in_valid => sample_f3_val); + + data_f0_wfp <= sample_f0_data & time_info; + data_f1_wfp <= sample_f1_data & time_info; + data_f2_wfp <= sample_f2_data & time_info; + data_f3_wfp <= sample_f3_data & time_info; + + ----------------------------------------------------------------------------- + sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & + NOT(sample_f0_val) & NOT(sample_f0_val) ; + sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & + NOT(sample_f1_val) & NOT(sample_f1_val) ; + sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & + NOT(sample_f3_val) & NOT(sample_f3_val) ; + + sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) + sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); + sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); + ----------------------------------------------------------------------------- + lpp_lfr_ms_1: lpp_lfr_ms + GENERIC MAP ( + hindex => hindex_ms) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => ahbi_ms, + AHB_Master_Out => ahbo_ms, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); + +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -0,0 +1,407 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_lfr_apbreg IS + GENERIC ( + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10; + + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq_ms : INTEGER := 0; + pirq_wfp : INTEGER := 1); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + --------------------------------------------------------------------------- + -- Spectral Matrix Reg + -- IN + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- OUT + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --------------------------------------------------------------------------- + --------------------------------------------------------------------------- + -- WaveForm picker Reg + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + -- OUT + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + --------------------------------------------------------------------------- + ); + +END lpp_lfr_apbreg; + +ARCHITECTURE beh OF lpp_lfr_apbreg IS + + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq_wfp), + 1 => apb_iobar(paddr, pmask)); + + TYPE lpp_SpectralMatrix_regs IS RECORD + config_active_interruption_onNewMatrix : STD_LOGIC; + config_active_interruption_onError : STD_LOGIC; + status_ready_matrix_f0_0 : STD_LOGIC; + status_ready_matrix_f0_1 : STD_LOGIC; + status_ready_matrix_f1 : STD_LOGIC; + status_ready_matrix_f2 : STD_LOGIC; + status_error_anticipating_empty_fifo : STD_LOGIC; + status_error_bad_component_error : STD_LOGIC; + addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + SIGNAL reg_sp : lpp_SpectralMatrix_regs; + + TYPE lpp_WaveformPicker_regs IS RECORD + status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : STD_LOGIC; + data_shaping_SP0 : STD_LOGIC; + data_shaping_SP1 : STD_LOGIC; + data_shaping_R0 : STD_LOGIC; + data_shaping_R1 : STD_LOGIC; + delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : STD_LOGIC; + enable_f1 : STD_LOGIC; + enable_f2 : STD_LOGIC; + enable_f3 : STD_LOGIC; + burst_f0 : STD_LOGIC; + burst_f1 : STD_LOGIC; + burst_f2 : STD_LOGIC; + addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + SIGNAL reg_wp : lpp_WaveformPicker_regs; + + SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; + status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; + status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; + status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; + status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; + status_error_bad_component_error <= reg_sp.status_error_bad_component_error; + + config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; + config_active_interruption_onError <= reg_sp.config_active_interruption_onError; + addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; + addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; + addr_matrix_f1 <= reg_sp.addr_matrix_f1; + addr_matrix_f2 <= reg_sp.addr_matrix_f2; + + + data_shaping_BW <= NOT reg_wp.data_shaping_BW; + data_shaping_SP0 <= reg_wp.data_shaping_SP0; + data_shaping_SP1 <= reg_wp.data_shaping_SP1; + data_shaping_R0 <= reg_wp.data_shaping_R0; + data_shaping_R1 <= reg_wp.data_shaping_R1; + + delta_snapshot <= reg_wp.delta_snapshot; + delta_f2_f1 <= reg_wp.delta_f2_f1; + delta_f2_f0 <= reg_wp.delta_f2_f0; + nb_burst_available <= reg_wp.nb_burst_available; + nb_snapshot_param <= reg_wp.nb_snapshot_param; + + enable_f0 <= reg_wp.enable_f0; + enable_f1 <= reg_wp.enable_f1; + enable_f2 <= reg_wp.enable_f2; + enable_f3 <= reg_wp.enable_f3; + + burst_f0 <= reg_wp.burst_f0; + burst_f1 <= reg_wp.burst_f1; + burst_f2 <= reg_wp.burst_f2; + + addr_data_f0 <= reg_wp.addr_data_f0; + addr_data_f1 <= reg_wp.addr_data_f1; + addr_data_f2 <= reg_wp.addr_data_f2; + addr_data_f3 <= reg_wp.addr_data_f3; + + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); + BEGIN -- PROCESS lpp_dma_top + IF HRESETn = '0' THEN -- asynchronous reset (active low) + reg_sp.config_active_interruption_onNewMatrix <= '0'; + reg_sp.config_active_interruption_onError <= '0'; + reg_sp.status_ready_matrix_f0_0 <= '0'; + reg_sp.status_ready_matrix_f0_1 <= '0'; + reg_sp.status_ready_matrix_f1 <= '0'; + reg_sp.status_ready_matrix_f2 <= '0'; + reg_sp.status_error_anticipating_empty_fifo <= '0'; + reg_sp.status_error_bad_component_error <= '0'; + reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); + reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f1 <= (OTHERS => '0'); + reg_sp.addr_matrix_f2 <= (OTHERS => '0'); + prdata <= (OTHERS => '0'); + + apbo.pirq <= (OTHERS => '0'); + + status_full_ack <= (OTHERS => '0'); + + reg_wp.data_shaping_BW <= '0'; + reg_wp.data_shaping_SP0 <= '0'; + reg_wp.data_shaping_SP1 <= '0'; + reg_wp.data_shaping_R0 <= '0'; + reg_wp.data_shaping_R1 <= '0'; + reg_wp.enable_f0 <= '0'; + reg_wp.enable_f1 <= '0'; + reg_wp.enable_f2 <= '0'; + reg_wp.enable_f3 <= '0'; + reg_wp.burst_f0 <= '0'; + reg_wp.burst_f1 <= '0'; + reg_wp.burst_f2 <= '0'; + reg_wp.addr_data_f0 <= (OTHERS => '0'); + reg_wp.addr_data_f1 <= (OTHERS => '0'); + reg_wp.addr_data_f2 <= (OTHERS => '0'); + reg_wp.addr_data_f3 <= (OTHERS => '0'); + reg_wp.status_full <= (OTHERS => '0'); + reg_wp.status_full_err <= (OTHERS => '0'); + reg_wp.status_new_err <= (OTHERS => '0'); + reg_wp.delta_snapshot <= (OTHERS => '0'); + reg_wp.delta_f2_f1 <= (OTHERS => '0'); + reg_wp.delta_f2_f0 <= (OTHERS => '0'); + reg_wp.nb_burst_available <= (OTHERS => '0'); + reg_wp.nb_snapshot_param <= (OTHERS => '0'); + + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + status_full_ack <= (OTHERS => '0'); + + reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; + reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; + reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; + reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; + + reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; + reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; + + reg_wp.status_full <= reg_wp.status_full OR status_full; + reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; + reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; + + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + prdata <= (OTHERS => '0'); + IF apbi.psel(pindex) = '1' THEN + -- APB DMA READ -- + CASE paddr(7 DOWNTO 2) IS + -- + WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; + prdata(1) <= reg_sp.config_active_interruption_onError; + WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; + prdata(1) <= reg_sp.status_ready_matrix_f0_1; + prdata(2) <= reg_sp.status_ready_matrix_f1; + prdata(3) <= reg_sp.status_ready_matrix_f2; + prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; + prdata(5) <= reg_sp.status_error_bad_component_error; + WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; + WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; + WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; + WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; + WHEN "000110" => prdata <= debug_reg; + -- + WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW; + prdata(1) <= reg_wp.data_shaping_SP0; + prdata(2) <= reg_wp.data_shaping_SP1; + prdata(3) <= reg_wp.data_shaping_R0; + prdata(4) <= reg_wp.data_shaping_R1; + WHEN "001001" => prdata(0) <= reg_wp.enable_f0; + prdata(1) <= reg_wp.enable_f1; + prdata(2) <= reg_wp.enable_f2; + prdata(3) <= reg_wp.enable_f3; + prdata(4) <= reg_wp.burst_f0; + prdata(5) <= reg_wp.burst_f1; + prdata(6) <= reg_wp.burst_f2; + WHEN "001010" => prdata <= reg_wp.addr_data_f0; + WHEN "001011" => prdata <= reg_wp.addr_data_f1; + WHEN "001100" => prdata <= reg_wp.addr_data_f2; + WHEN "001101" => prdata <= reg_wp.addr_data_f3; + WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full; + prdata(7 DOWNTO 4) <= reg_wp.status_full_err; + prdata(11 DOWNTO 8) <= reg_wp.status_new_err; + WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1; + WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0; + WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available; + WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; + -- + WHEN OTHERS => NULL; + END CASE; + IF (apbi.pwrite AND apbi.penable) = '1' THEN + -- APB DMA WRITE -- + CASE paddr(7 DOWNTO 2) IS + -- + WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); + reg_sp.config_active_interruption_onError <= apbi.pwdata(1); + WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); + reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); + reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); + reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); + reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); + reg_sp.status_error_bad_component_error <= apbi.pwdata(5); + WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; + WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; + WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; + WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; + -- + WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0); + reg_wp.data_shaping_SP0 <= apbi.pwdata(1); + reg_wp.data_shaping_SP1 <= apbi.pwdata(2); + reg_wp.data_shaping_R0 <= apbi.pwdata(3); + reg_wp.data_shaping_R1 <= apbi.pwdata(4); + WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0); + reg_wp.enable_f1 <= apbi.pwdata(1); + reg_wp.enable_f2 <= apbi.pwdata(2); + reg_wp.enable_f3 <= apbi.pwdata(3); + reg_wp.burst_f0 <= apbi.pwdata(4); + reg_wp.burst_f1 <= apbi.pwdata(5); + reg_wp.burst_f2 <= apbi.pwdata(6); + WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata; + WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata; + WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata; + WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata; + WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); + reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); + reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); + status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); + status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); + status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); + status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); + WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0); + WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0); + WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0); + WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0); + WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); + -- + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + + apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR + ready_matrix_f0_1 OR + ready_matrix_f1 OR + ready_matrix_f2) + ) + OR + (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR + error_bad_component_error) + ); + + apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR + status_full(1) OR status_full_err(1) OR status_new_err(1) OR + status_full(2) OR status_full_err(2) OR status_new_err(2) OR + status_full(3) OR status_full_err(3) OR status_new_err(3) + ); + + + END IF; + END PROCESS lpp_lfr_apbreg; + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.prdata <= prdata; + + +END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd @@ -0,0 +1,385 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_lfr_filter IS + GENERIC( + Mem_use : INTEGER := use_RAM + ); + PORT ( + sample : IN Samples(7 DOWNTO 0); + sample_val : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + -- + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + -- + sample_f0_val : OUT STD_LOGIC; + sample_f1_val : OUT STD_LOGIC; + sample_f2_val : OUT STD_LOGIC; + sample_f3_val : OUT STD_LOGIC; + -- + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0) + ); +END lpp_lfr_filter; + +ARCHITECTURE tb OF lpp_lfr_filter IS + + COMPONENT Downsampling + GENERIC ( + ChanelCount : INTEGER; + SampleSize : INTEGER; + DivideParam : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); + sample_out_val : OUT STD_LOGIC; + sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + CONSTANT ChanelCount : INTEGER := 8; + + ----------------------------------------------------------------------------- + SIGNAL sample_val_delay : STD_LOGIC; + ----------------------------------------------------------------------------- + CONSTANT Coef_SZ : INTEGER := 9; + CONSTANT CoefCntPerCel : INTEGER := 6; + CONSTANT CoefPerCel : INTEGER := 5; + CONSTANT Cels_count : INTEGER := 5; + + SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + -- + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_data_shaping_out_val : STD_LOGIC; + SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL sample_filter_v2_out_val_s : STD_LOGIC; + SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + ----------------------------------------------------------------------------- +-- SIGNAL sample_f0_val : STD_LOGIC; + SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- +-- SIGNAL sample_f1_val : STD_LOGIC; + SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- +-- SIGNAL sample_f2_val : STD_LOGIC; + SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + -- +-- SIGNAL sample_f3_val : STD_LOGIC; + SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + ----------------------------------------------------------------------------- + + SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + SIGNAL sample_f0_val_s : STD_LOGIC; + SIGNAL sample_f1_val_s : STD_LOGIC; +BEGIN + + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_val_delay <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_val_delay <= sample_val; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE + SampleLoop : FOR j IN 0 TO 15 GENERATE + sample_filter_in(i, j) <= sample(i)(j); + END GENERATE; + + sample_filter_in(i, 16) <= sample(i)(15); + sample_filter_in(i, 17) <= sample(i)(15); + END GENERATE; + + coefs_v2 <= CoefsInitValCst_v2; + + IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 + GENERIC MAP ( + tech => 0, + Mem_use => Mem_use, -- use_RAM + Sample_SZ => 18, + Coef_SZ => Coef_SZ, + Coef_Nb => 25, + Coef_sel_SZ => 5, + Cels_count => Cels_count, + ChanelsCount => ChanelCount) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => 7, + coefs => coefs_v2, + sample_in_val => sample_val_delay, + sample_in => sample_filter_in, + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); + + ----------------------------------------------------------------------------- + -- DATA_SHAPING + ----------------------------------------------------------------------------- + all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE + sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I); + sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I); + sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I); + END GENERATE all_data_shaping_in_loop; + + sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s; + sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_data_shaping_out_val <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out_val <= sample_filter_v2_out_val; + END IF; + END PROCESS; + + SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + sample_data_shaping_out(0, j) <= '0'; + sample_data_shaping_out(1, j) <= '0'; + sample_data_shaping_out(2, j) <= '0'; + sample_data_shaping_out(3, j) <= '0'; + sample_data_shaping_out(4, j) <= '0'; + sample_data_shaping_out(5, j) <= '0'; + sample_data_shaping_out(6, j) <= '0'; + sample_data_shaping_out(7, j) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j); + IF data_shaping_SP0 = '1' THEN + sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j); + ELSE + sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j); + END IF; + IF data_shaping_SP1 = '1' THEN + sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j); + ELSE + sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j); + END IF; + sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j); + sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j); + sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j); + sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j); + sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j); + END IF; + END PROCESS; + END GENERATE; + + sample_filter_v2_out_val_s <= sample_data_shaping_out_val; + ChanelLoopOut : FOR i IN 0 TO 7 GENERATE + SampleLoopOut : FOR j IN 0 TO 15 GENERATE + sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j); + END GENERATE; + END GENERATE; + ----------------------------------------------------------------------------- + -- F0 -- @24.576 kHz + ----------------------------------------------------------------------------- + Downsampling_f0 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_filter_v2_out_val_s, + sample_in => sample_filter_v2_out_s, + sample_out_val => sample_f0_val_s, + sample_out => sample_f0); + + sample_f0_val <= sample_f0_val_s; + + all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_wdata_s(I) <= sample_f0(0, I); -- V + sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1 + sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2 + sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1 + sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2 + sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0; + + --sample_f0_wen <= NOT(sample_f0_val) & + -- NOT(sample_f0_val) & + -- NOT(sample_f0_val) & + -- NOT(sample_f0_val) & + -- NOT(sample_f0_val) & + -- NOT(sample_f0_val); + + ----------------------------------------------------------------------------- + -- F1 -- @4096 Hz + ----------------------------------------------------------------------------- + Downsampling_f1 : Downsampling + GENERIC MAP ( + ChanelCount => 8, + SampleSize => 16, + DivideParam => 6) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val_s , + sample_in => sample_f0, + sample_out_val => sample_f1_val_s, + sample_out => sample_f1); + + sample_f1_val <= sample_f1_val_s; + + all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_wdata_s(I) <= sample_f1(0, I); -- V + sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1 + sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2 + sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1 + sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2 + sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1; + + --sample_f1_wen <= NOT(sample_f1_val) & + -- NOT(sample_f1_val) & + -- NOT(sample_f1_val) & + -- NOT(sample_f1_val) & + -- NOT(sample_f1_val) & + -- NOT(sample_f1_val); + + ----------------------------------------------------------------------------- + -- F2 -- @256 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f0_s(0, I) <= sample_f0(0, I); -- V + sample_f0_s(1, I) <= sample_f0(1, I); -- E1 + sample_f0_s(2, I) <= sample_f0(2, I); -- E2 + sample_f0_s(3, I) <= sample_f0(5, I); -- B1 + sample_f0_s(4, I) <= sample_f0(6, I); -- B2 + sample_f0_s(5, I) <= sample_f0(7, I); -- B3 + END GENERATE all_bit_sample_f0_s; + + Downsampling_f2 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 96) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f0_val_s , + sample_in => sample_f0_s, + sample_out_val => sample_f2_val, + sample_out => sample_f2); + + --sample_f2_wen <= NOT(sample_f2_val) & + -- NOT(sample_f2_val) & + -- NOT(sample_f2_val) & + -- NOT(sample_f2_val) & + -- NOT(sample_f2_val) & + -- NOT(sample_f2_val); + + all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f2_wdata_s(I) <= sample_f2(0, I); + sample_f2_wdata_s(16*1+I) <= sample_f2(1, I); + sample_f2_wdata_s(16*2+I) <= sample_f2(2, I); + sample_f2_wdata_s(16*3+I) <= sample_f2(3, I); + sample_f2_wdata_s(16*4+I) <= sample_f2(4, I); + sample_f2_wdata_s(16*5+I) <= sample_f2(5, I); + END GENERATE all_bit_sample_f2; + + ----------------------------------------------------------------------------- + -- F3 -- @16 Hz + ----------------------------------------------------------------------------- + all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE + sample_f1_s(0, I) <= sample_f1(0, I); -- V + sample_f1_s(1, I) <= sample_f1(1, I); -- E1 + sample_f1_s(2, I) <= sample_f1(2, I); -- E2 + sample_f1_s(3, I) <= sample_f1(5, I); -- B1 + sample_f1_s(4, I) <= sample_f1(6, I); -- B2 + sample_f1_s(5, I) <= sample_f1(7, I); -- B3 + END GENERATE all_bit_sample_f1_s; + + Downsampling_f3 : Downsampling + GENERIC MAP ( + ChanelCount => 6, + SampleSize => 16, + DivideParam => 256) + PORT MAP ( + clk => clk, + rstn => rstn, + sample_in_val => sample_f1_val_s , + sample_in => sample_f1_s, + sample_out_val => sample_f3_val, + sample_out => sample_f3); + + --sample_f3_wen <= (NOT sample_f3_val) & + -- (NOT sample_f3_val) & + -- (NOT sample_f3_val) & + -- (NOT sample_f3_val) & + -- (NOT sample_f3_val) & + -- (NOT sample_f3_val); + + all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE + sample_f3_wdata_s(I) <= sample_f3(0, I); + sample_f3_wdata_s(16*1+I) <= sample_f3(1, I); + sample_f3_wdata_s(16*2+I) <= sample_f3(2, I); + sample_f3_wdata_s(16*3+I) <= sample_f3(3, I); + sample_f3_wdata_s(16*4+I) <= sample_f3(4, I); + sample_f3_wdata_s(16*5+I) <= sample_f3(5, I); + END GENERATE all_bit_sample_f3; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + sample_f0_wdata <= sample_f0_wdata_s; + sample_f1_wdata <= sample_f1_wdata_s; + sample_f2_wdata <= sample_f2_wdata_s; + sample_f3_wdata <= sample_f3_wdata_s; + +END tb; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -0,0 +1,346 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_uart.ALL; +USE lpp.lpp_matrix.ALL; +USE lpp.lpp_delay.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.Filtercfg.ALL; +USE lpp.lpp_demux.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + + +ENTITY lpp_lfr_ms IS + GENERIC ( + hindex : INTEGER := 2 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- DATA INPUT + --------------------------------------------------------------------------- + -- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- DMA + --------------------------------------------------------------------------- + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- Reg out + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0_0 :IN STD_LOGIC; + status_ready_matrix_f0_1 :IN STD_LOGIC; + status_ready_matrix_f1 :IN STD_LOGIC; + status_ready_matrix_f2 :IN STD_LOGIC; + status_error_anticipating_empty_fifo :IN STD_LOGIC; + status_error_bad_component_error :IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms IS + ----------------------------------------------------------------------------- + SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FFT_Load : STD_LOGIC; + SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL SM_FlagError : STD_LOGIC; + SIGNAL SM_Pong : STD_LOGIC; + SIGNAL SM_Wen : STD_LOGIC; + SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL Head_Empty : STD_LOGIC; + SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL Head_Valid : STD_LOGIC; + SIGNAL Head_Val : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL DMA_Read : STD_LOGIC; + SIGNAL DMA_ack : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + Memf0: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => use_RAM, Data_sz => 16, + Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rst => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), + wdata => sample_f0_wdata, rdata => FifoF0_Data, + full => OPEN, empty => FifoF0_Empty); + + Memf1: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => use_RAM, Data_sz => 16, + Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rst => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), + wdata => sample_f1_wdata, rdata => FifoF1_Data, + full => OPEN, empty => FifoF1_Empty); + + + Memf2: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => use_RAM, Data_sz => 16, + Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rst => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), + wdata => sample_f3_wdata, rdata => FifoF3_Data, + full => OPEN, empty => FifoF3_Empty); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + DMUX0 : DEMUX + GENERIC MAP ( + Data_sz => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + Read => FFT_Read, + Load => FFT_Load, + EmptyF0 => FifoF0_Empty, + EmptyF1 => FifoF1_Empty, + EmptyF2 => FifoF3_Empty, + DataF0 => FifoF0_Data, + DataF1 => FifoF1_Data, + DataF2 => FifoF3_Data, + WorkFreq => DMUX_WorkFreq, + Read_DEMUX => DMUX_Read, + Empty => DMUX_Empty, + Data => DMUX_Data); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + FFT0: FFT + GENERIC MAP ( + Data_sz => 16, + NbData => 256) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Empty => DMUX_Empty, + FifoIN_Data => DMUX_Data, + FifoOUT_Full => FifoINT_Full, + Load => FFT_Load, + Read => FFT_Read, + Write => FFT_Write, + ReUse => FFT_ReUse, + Data => FFT_Data); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + MemInt : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '1') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => SM_ReUse, + wen => FFT_Write, + ren => SM_Read, + wdata => FFT_Data, + rdata => FifoINT_Data, + full => FifoINT_Full, + empty => OPEN); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + SM0 : MatriceSpectrale + GENERIC MAP ( + Input_SZ => 16, + Result_SZ => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Full => FifoINT_Full, + SetReUse => FFT_ReUse, + Valid => Head_Valid, + Data_IN => FifoINT_Data, + ACQ => DMA_ack, + SM_Write => SM_Wen, + FlagError => SM_FlagError, + Pong => SM_Pong, + Statu => SM_Param, + Write => SM_Write, + Read => SM_Read, + ReUse => SM_ReUse, + Data_OUT => SM_Data); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + MemOut : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + Data_sz => 32, + Addr_sz => 8, + FifoCnt => 2, + Enable_ReUse => '0') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + wen => SM_Write, + ren => Head_Read, + wdata => SM_Data, + rdata => FifoOUT_Data, + full => FifoOUT_Full, + empty => FifoOUT_Empty); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + Head0 : HeaderBuilder + GENERIC MAP ( + Data_sz => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, + pong => SM_Pong, + Statu => SM_Param, + Matrix_Type => DMUX_WorkFreq, + Matrix_Write => SM_Wen, + Valid => Head_Valid, + dataIN => FifoOUT_Data, + emptyIN => FifoOUT_Empty, + RenOUT => Head_Read, + dataOUT => Head_Data, + emptyOUT => Head_Empty, + RenIN => DMA_Read, + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack ); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + lpp_dma_ip_1: lpp_dma_ip + GENERIC MAP ( + tech => 0, + hindex => hindex) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + fifo_data => Head_Data, + fifo_empty => Head_Empty, + fifo_ren => DMA_Read, + + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); + ----------------------------------------------------------------------------- + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -0,0 +1,168 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_lfr_pkg IS + + COMPONENT lpp_lfr_ms + GENERIC ( + hindex : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : IN STD_LOGIC; + status_ready_matrix_f0_1 : IN STD_LOGIC; + status_ready_matrix_f1 : IN STD_LOGIC; + status_ready_matrix_f2 : IN STD_LOGIC; + status_error_anticipating_empty_fifo : IN STD_LOGIC; + status_error_bad_component_error : IN STD_LOGIC; + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr_filter + GENERIC ( + Mem_use : INTEGER); + PORT ( + sample : IN Samples(7 DOWNTO 0); + sample_val : IN STD_LOGIC; + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + data_shaping_SP0 : IN STD_LOGIC; + data_shaping_SP1 : IN STD_LOGIC; + data_shaping_R0 : IN STD_LOGIC; + data_shaping_R1 : IN STD_LOGIC; + sample_f0_val : OUT STD_LOGIC; + sample_f1_val : OUT STD_LOGIC; + sample_f2_val : OUT STD_LOGIC; + sample_f3_val : OUT STD_LOGIC; + sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_lfr + GENERIC ( + Mem_use : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + hindex_wfp : INTEGER; + hindex_ms : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ahbi_wfp : IN AHB_Mst_In_Type; + ahbo_wfp : OUT AHB_Mst_Out_Type; + ahbi_ms : IN AHB_Mst_In_Type; + ahbo_ms : OUT AHB_Mst_Out_Type; + coarse_time_0 : IN STD_LOGIC; + data_shaping_BW : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_lfr_apbreg + GENERIC ( + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + data_shaping_SP0 : OUT STD_LOGIC; + data_shaping_SP1 : OUT STD_LOGIC; + data_shaping_R0 : OUT STD_LOGIC; + data_shaping_R1 : OUT STD_LOGIC; + delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : OUT STD_LOGIC; + enable_f1 : OUT STD_LOGIC; + enable_f2 : OUT STD_LOGIC; + enable_f3 : OUT STD_LOGIC; + burst_f0 : OUT STD_LOGIC; + burst_f1 : OUT STD_LOGIC; + burst_f2 : OUT STD_LOGIC; + addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + +END lpp_lfr_pkg; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -27,7 +27,7 @@ ENTITY lpp_top_acq IS clk : IN STD_LOGIC; -- 25 MHz rstn : IN STD_LOGIC; -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); -- sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -1,8 +1,13 @@ lpp_top_lfr_pkg.vhd +lpp_lfr_pkg.vhd lpp_top_apbreg.vhd lpp_top_acq.vhd lpp_top_lfr_wf_picker.vhd lpp_top_lfr_wf_picker_ip.vhd lpp_top_lfr_wf_picker_ip_whitout_filter.vhd top_lfr_wf_picker.vhd +lpp_lfr_apbreg.vhd top_wf_picker.vhd +lpp_lfr_filter.vhd +lpp_lfr_ms.vhd +lpp_lfr.vhd