@@ -0,0 +1,95 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | ||||
|
23 | use IEEE.std_logic_1164.all; | |||
|
24 | use IEEE.numeric_std.all; | |||
|
25 | library lpp; | |||
|
26 | use lpp.lpp_fft.all; | |||
|
27 | use lpp.fft_components.all; | |||
|
28 | ||||
|
29 | -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau" | |||
|
30 | ||||
|
31 | entity FFT is | |||
|
32 | generic( | |||
|
33 | Data_sz : integer := 16; | |||
|
34 | NbData : integer := 256); | |||
|
35 | port( | |||
|
36 | clkm : in std_logic; | |||
|
37 | rstn : in std_logic; | |||
|
38 | FifoIN_Empty : in std_logic_vector(4 downto 0); | |||
|
39 | FifoIN_Data : in std_logic_vector(79 downto 0); | |||
|
40 | FifoOUT_Full : in std_logic_vector(4 downto 0); | |||
|
41 | Load : out std_logic; | |||
|
42 | Read : out std_logic_vector(4 downto 0); | |||
|
43 | Write : out std_logic_vector(4 downto 0); | |||
|
44 | ReUse : out std_logic_vector(4 downto 0); | |||
|
45 | Data : out std_logic_vector(79 downto 0) | |||
|
46 | ); | |||
|
47 | end entity; | |||
|
48 | ||||
|
49 | ||||
|
50 | architecture ar_FFT of FFT is | |||
|
51 | ||||
|
52 | signal Drive_Write : std_logic; | |||
|
53 | signal Drive_DataRE : std_logic_vector(15 downto 0); | |||
|
54 | signal Drive_DataIM : std_logic_vector(15 downto 0); | |||
|
55 | ||||
|
56 | signal Start : std_logic; | |||
|
57 | signal FFT_Load : std_logic; | |||
|
58 | signal FFT_Ready : std_logic; | |||
|
59 | signal FFT_Valid : std_logic; | |||
|
60 | signal FFT_DataRE : std_logic_vector(15 downto 0); | |||
|
61 | signal FFT_DataIM : std_logic_vector(15 downto 0); | |||
|
62 | ||||
|
63 | signal Link_Read : std_logic; | |||
|
64 | ||||
|
65 | begin | |||
|
66 | ||||
|
67 | Start <= '0'; | |||
|
68 | Load <= FFT_Load; | |||
|
69 | ||||
|
70 | DRIVE : Driver_FFT | |||
|
71 | generic map(Data_sz,NbData) | |||
|
72 | port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); | |||
|
73 | ||||
|
74 | FFT0 : CoreFFT | |||
|
75 | generic map( | |||
|
76 | LOGPTS => gLOGPTS, | |||
|
77 | LOGLOGPTS => gLOGLOGPTS, | |||
|
78 | WSIZE => gWSIZE, | |||
|
79 | TWIDTH => gTWIDTH, | |||
|
80 | DWIDTH => gDWIDTH, | |||
|
81 | TDWIDTH => gTDWIDTH, | |||
|
82 | RND_MODE => gRND_MODE, | |||
|
83 | SCALE_MODE => gSCALE_MODE, | |||
|
84 | PTS => gPTS, | |||
|
85 | HALFPTS => gHALFPTS, | |||
|
86 | inBuf_RWDLY => gInBuf_RWDLY) | |||
|
87 | port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready); | |||
|
88 | ||||
|
89 | ||||
|
90 | LINK : Linker_FFT | |||
|
91 | generic map(Data_sz,NbData) | |||
|
92 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); | |||
|
93 | ||||
|
94 | ||||
|
95 | end architecture; No newline at end of file |
@@ -0,0 +1,73 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.std_logic_1164.all; | |||
|
24 | use IEEE.numeric_std.all; | |||
|
25 | library lpp; | |||
|
26 | use work.FFT_config.all; | |||
|
27 | ||||
|
28 | --! Programme qui va permettre de gοΏ½nοΏ½rer des flags utilisοΏ½s au niveau du driver C | |||
|
29 | ||||
|
30 | entity Flag_Extremum is | |||
|
31 | port( | |||
|
32 | clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant | |||
|
33 | load : in std_logic; --! Signal en provenance de CoreFFT | |||
|
34 | y_rdy : in std_logic; --! Signal en provenance de CoreFFT | |||
|
35 | fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C) | |||
|
36 | ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C) | |||
|
37 | ); | |||
|
38 | end Flag_Extremum; | |||
|
39 | ||||
|
40 | --! @details Flags gοΏ½nοΏ½rοΏ½s a partir de signaux fourni par l'IP FFT d'actel | |||
|
41 | ||||
|
42 | architecture ar_Flag_Extremum of Flag_Extremum is | |||
|
43 | ||||
|
44 | begin | |||
|
45 | process (clk,raz) | |||
|
46 | begin | |||
|
47 | if(raz='0')then | |||
|
48 | fill <= '0'; | |||
|
49 | ready <= '0'; | |||
|
50 | ||||
|
51 | elsif(clk' event and clk='1')then | |||
|
52 | ||||
|
53 | if(load='1' and y_rdy='0')then | |||
|
54 | fill <= '1'; | |||
|
55 | ready <= '0'; | |||
|
56 | ||||
|
57 | elsif(y_rdy='1')then | |||
|
58 | fill <= '0'; | |||
|
59 | ready <= '1'; | |||
|
60 | ||||
|
61 | else | |||
|
62 | fill <= '0'; | |||
|
63 | ready <= '0'; | |||
|
64 | ||||
|
65 | end if; | |||
|
66 | end if; | |||
|
67 | end process; | |||
|
68 | ||||
|
69 | end ar_Flag_Extremum; | |||
|
70 | ||||
|
71 | ||||
|
72 | ||||
|
73 |
@@ -0,0 +1,216 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | use lpp.general_purpose.all; | |||
|
26 | ||||
|
27 | --! Driver de l'ALU | |||
|
28 | ||||
|
29 | entity ALU_Driver is | |||
|
30 | generic( | |||
|
31 | Input_SZ_1 : integer := 16; | |||
|
32 | Input_SZ_2 : integer := 16); | |||
|
33 | port( | |||
|
34 | clk : in std_logic; --! Horloge du composant | |||
|
35 | reset : in std_logic; --! Reset general du composant | |||
|
36 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! DonnοΏ½e d'entrοΏ½e | |||
|
37 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! DonnοΏ½e d'entrοΏ½e | |||
|
38 | Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½ | |||
|
39 | Received : in std_logic; --! Flag, RοΏ½sultat bien ressu | |||
|
40 | Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjuguοΏ½ | |||
|
41 | Valid : out std_logic; --! Flag, RοΏ½sultat disponible | |||
|
42 | Read : out std_logic; --! Flag, opοΏ½rande disponible | |||
|
43 | CTRL : out std_logic_vector(2 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e | |||
|
44 | COMP : out std_logic_vector(1 downto 0); --! (set) Permet de complοΏ½menter les opοΏ½randes | |||
|
45 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande | |||
|
46 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second OpοΏ½rande | |||
|
47 | ); | |||
|
48 | end ALU_Driver; | |||
|
49 | ||||
|
50 | --! @details Les opοΏ½randes sont issue des donnοΏ½es d'entrοΏ½es et associοΏ½ aux bonnes valeurs sur CTRL, les diffοΏ½rentes opοΏ½rations sont effectuοΏ½es | |||
|
51 | ||||
|
52 | architecture ar_ALU_Driver of ALU_Driver is | |||
|
53 | ||||
|
54 | signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0); | |||
|
55 | signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0); | |||
|
56 | signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0); | |||
|
57 | signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0); | |||
|
58 | ||||
|
59 | signal go_st : std_logic; | |||
|
60 | signal Take_reg : std_logic; | |||
|
61 | signal Received_reg : std_logic; | |||
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62 | ||||
|
63 | type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW); | |||
|
64 | signal ect : etat; | |||
|
65 | signal st : etat; | |||
|
66 | ||||
|
67 | begin | |||
|
68 | process(clk,reset) | |||
|
69 | begin | |||
|
70 | ||||
|
71 | if(reset='0')then | |||
|
72 | ect <= eX; | |||
|
73 | st <= e0; | |||
|
74 | go_st <= '0'; | |||
|
75 | CTRL <= ctrl_CLRMAC; | |||
|
76 | COMP <= "00"; -- pas de complement | |||
|
77 | Read <= '0'; | |||
|
78 | Valid <= '0'; | |||
|
79 | Take_reg <= '0'; | |||
|
80 | Received_reg <= '0'; | |||
|
81 | ||||
|
82 | elsif(clk'event and clk='1')then | |||
|
83 | Take_reg <= Take; | |||
|
84 | Received_reg <= Received; | |||
|
85 | ||||
|
86 | case ect is | |||
|
87 | when eX => | |||
|
88 | go_st <= '0'; | |||
|
89 | Read <= '1'; | |||
|
90 | CTRL <= ctrl_CLRMAC; | |||
|
91 | ect <= e0; | |||
|
92 | ||||
|
93 | when e0 => | |||
|
94 | OP1re <= IN1; | |||
|
95 | if(Conjugate='1')then -- | |||
|
96 | OP2re <= IN1; -- | |||
|
97 | else -- | |||
|
98 | OP2re <= IN2; -- modif 23/06/11 | |||
|
99 | end if; -- | |||
|
100 | if(Take_reg='0' and Take='1')then | |||
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101 | read <= '0'; | |||
|
102 | ect <= e1; | |||
|
103 | end if; | |||
|
104 | ||||
|
105 | when e1 => | |||
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106 | OP1 <= OP1re; | |||
|
107 | OP2 <= OP2re; | |||
|
108 | CTRL <= ctrl_MAC; | |||
|
109 | Read <= '1'; | |||
|
110 | ect <= eY; | |||
|
111 | ||||
|
112 | when eY => | |||
|
113 | OP1im <= IN1; | |||
|
114 | if(Conjugate='1')then -- | |||
|
115 | OP2im <= IN1; -- | |||
|
116 | else -- | |||
|
117 | OP2im <= IN2; -- modif 23/06/11 | |||
|
118 | end if; -- | |||
|
119 | CTRL <= ctrl_IDLE; | |||
|
120 | if(Take_reg='1' and Take='0')then | |||
|
121 | Read <= '0'; | |||
|
122 | ect <= e2; | |||
|
123 | end if; | |||
|
124 | ||||
|
125 | when e2 => | |||
|
126 | OP1 <= OP1im; | |||
|
127 | OP2 <= OP2im; | |||
|
128 | CTRL <= ctrl_MAC; | |||
|
129 | ect <= eZ; | |||
|
130 | ||||
|
131 | when eZ => | |||
|
132 | CTRL <= ctrl_IDLE; | |||
|
133 | go_st <= '1'; | |||
|
134 | if(Received_reg='0' and Received='1')then | |||
|
135 | if(Conjugate='1')then | |||
|
136 | ect <= eX; | |||
|
137 | else | |||
|
138 | ect <= e3; | |||
|
139 | end if; | |||
|
140 | end if; | |||
|
141 | ||||
|
142 | when e3 => | |||
|
143 | CTRL <= ctrl_CLRMAC; | |||
|
144 | go_st <= '0'; | |||
|
145 | ect <= e4; | |||
|
146 | ||||
|
147 | when e4 => | |||
|
148 | OP1 <= OP1im; | |||
|
149 | OP2 <= OP2re; | |||
|
150 | CTRL <= ctrl_MAC; | |||
|
151 | ect <= e5; | |||
|
152 | ||||
|
153 | when e5 => | |||
|
154 | OP1 <= OP1re; | |||
|
155 | OP2 <= OP2im; | |||
|
156 | COMP <= "10"; | |||
|
157 | ect <= eW; | |||
|
158 | ||||
|
159 | when eW => | |||
|
160 | CTRL <= ctrl_IDLE; | |||
|
161 | COMP <= "00"; | |||
|
162 | go_st <= '1'; | |||
|
163 | if(Received_reg='1' and Received='0')then | |||
|
164 | ect <= eX; | |||
|
165 | end if; | |||
|
166 | end case; | |||
|
167 | --------------------------------------------------------------------------------- | |||
|
168 | case st is | |||
|
169 | when e0 => | |||
|
170 | if(go_st='1')then | |||
|
171 | st <= e1; | |||
|
172 | end if; | |||
|
173 | ||||
|
174 | when e1 => | |||
|
175 | Valid <= '1'; | |||
|
176 | st <= e2; | |||
|
177 | ||||
|
178 | when e2 => | |||
|
179 | if(Received_reg='0' and Received='1')then | |||
|
180 | Valid <= '0'; | |||
|
181 | if(Conjugate='1')then | |||
|
182 | st <= eY; | |||
|
183 | else | |||
|
184 | st <= eX; | |||
|
185 | end if; | |||
|
186 | end if; | |||
|
187 | ||||
|
188 | when eX => | |||
|
189 | st <= e3; | |||
|
190 | ||||
|
191 | when e3 => | |||
|
192 | if(go_st='1')then | |||
|
193 | st <= e4; | |||
|
194 | end if; | |||
|
195 | ||||
|
196 | when e4 => | |||
|
197 | Valid <= '1'; | |||
|
198 | st <= e5; | |||
|
199 | ||||
|
200 | when e5 => | |||
|
201 | if(Received_reg='1' and Received='0')then | |||
|
202 | Valid <= '0'; | |||
|
203 | st <= eY; | |||
|
204 | end if; | |||
|
205 | ||||
|
206 | when eY => | |||
|
207 | st <= e0; | |||
|
208 | ||||
|
209 | when others => | |||
|
210 | null; | |||
|
211 | end case; | |||
|
212 | ||||
|
213 | end if; | |||
|
214 | end process; | |||
|
215 | ||||
|
216 | end ar_ALU_Driver; No newline at end of file |
@@ -0,0 +1,87 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.std_logic_1164.all; | |||
|
24 | use IEEE.numeric_std.all; | |||
|
25 | --library lpp; | |||
|
26 | --use lpp.lpp_matrix.all; | |||
|
27 | ||||
|
28 | entity MatriceSpectrale is | |||
|
29 | generic( | |||
|
30 | Input_SZ : integer := 16; | |||
|
31 | Result_SZ : integer := 32); | |||
|
32 | port( | |||
|
33 | clkm : in std_logic; | |||
|
34 | rstn : in std_logic; | |||
|
35 | ||||
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); | |||
|
37 | SetReUse : in std_logic_vector(4 downto 0); | |||
|
38 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |||
|
39 | Valid : in std_logic; | |||
|
40 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |||
|
41 | ACQ : in std_logic; | |||
|
42 | SM_Write : out std_logic; | |||
|
43 | FlagError : out std_logic; | |||
|
44 | Pong : out std_logic; | |||
|
45 | Statu : out std_logic_vector(3 downto 0); | |||
|
46 | Write : out std_logic_vector(1 downto 0); | |||
|
47 | Read : out std_logic_vector(4 downto 0); | |||
|
48 | ReUse : out std_logic_vector(4 downto 0); | |||
|
49 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |||
|
50 | ); | |||
|
51 | end entity; | |||
|
52 | ||||
|
53 | ||||
|
54 | architecture ar_MatriceSpectrale of MatriceSpectrale is | |||
|
55 | ||||
|
56 | signal Matrix_Write : std_logic; | |||
|
57 | signal Matrix_Read : std_logic_vector(1 downto 0); | |||
|
58 | signal Matrix_Result : std_logic_vector(31 downto 0); | |||
|
59 | ||||
|
60 | signal TopSM_Start : std_logic; | |||
|
61 | signal TopSM_Statu : std_logic_vector(3 downto 0); | |||
|
62 | signal TopSM_Data1 : std_logic_vector(15 downto 0); | |||
|
63 | signal TopSM_Data2 : std_logic_vector(15 downto 0); | |||
|
64 | ||||
|
65 | begin | |||
|
66 | ||||
|
67 | CTRL0 : entity work.ReUse_CTRLR | |||
|
68 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); | |||
|
69 | ||||
|
70 | ||||
|
71 | TopSM : entity work.TopSpecMatrix | |||
|
72 | generic map (Input_SZ) | |||
|
73 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); | |||
|
74 | ||||
|
75 | SM : entity work.SpectralMatrix | |||
|
76 | generic map (Input_SZ,Result_SZ) | |||
|
77 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |||
|
78 | ||||
|
79 | DISP : entity work.Dispatch | |||
|
80 | generic map(Result_SZ) | |||
|
81 | port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); | |||
|
82 | ||||
|
83 | Statu <= TopSM_Statu; | |||
|
84 | SM_Write <= Matrix_Write; | |||
|
85 | ||||
|
86 | end architecture; | |||
|
87 |
@@ -0,0 +1,84 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | use lpp.lpp_matrix.all; | |||
|
26 | ||||
|
27 | entity SpectralMatrix is | |||
|
28 | generic( | |||
|
29 | Input_SZ : integer := 16; | |||
|
30 | Result_SZ : integer := 32); | |||
|
31 | port( | |||
|
32 | clk : in std_logic; | |||
|
33 | reset : in std_logic; | |||
|
34 | Start : in std_logic; | |||
|
35 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
36 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |||
|
37 | Statu : in std_logic_vector(3 downto 0); | |||
|
38 | -- FullFIFO : in std_logic; | |||
|
39 | ReadFIFO : out std_logic_vector(1 downto 0); | |||
|
40 | WriteFIFO : out std_logic; | |||
|
41 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |||
|
42 | ); | |||
|
43 | end SpectralMatrix; | |||
|
44 | ||||
|
45 | ||||
|
46 | architecture ar_SpectralMatrix of SpectralMatrix is | |||
|
47 | ||||
|
48 | signal RaZ : std_logic; | |||
|
49 | signal Read_int : std_logic; | |||
|
50 | signal Take_int : std_logic; | |||
|
51 | signal Received_int : std_logic; | |||
|
52 | signal Valid_int : std_logic; | |||
|
53 | signal Conjugate_int : std_logic; | |||
|
54 | ||||
|
55 | signal Resultat : std_logic_vector(Result_SZ-1 downto 0); | |||
|
56 | ||||
|
57 | ||||
|
58 | begin | |||
|
59 | ||||
|
60 | RaZ <= reset and Start; | |||
|
61 | ||||
|
62 | IN1 : DriveInputs | |||
|
63 | port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO); | |||
|
64 | ||||
|
65 | ||||
|
66 | CALC0 : Matrix | |||
|
67 | generic map(Input_SZ) | |||
|
68 | port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat); | |||
|
69 | ||||
|
70 | ||||
|
71 | RES0 : GetResult | |||
|
72 | generic map(Result_SZ) | |||
|
73 | port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO | |||
|
74 | ||||
|
75 | ||||
|
76 | With Statu select | |||
|
77 | Conjugate_int <= '1' when "0001", | |||
|
78 | '1' when "0011", | |||
|
79 | '1' when "0110", | |||
|
80 | '1' when "1010", | |||
|
81 | '1' when "1111", | |||
|
82 | '0' when others; | |||
|
83 | ||||
|
84 | end ar_SpectralMatrix; No newline at end of file |
@@ -0,0 +1,264 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Alexis Jeandet | |||
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | -- APB_FIFO.vhd | |||
|
23 | library ieee; | |||
|
24 | use ieee.std_logic_1164.all; | |||
|
25 | use IEEE.numeric_std.all; | |||
|
26 | library techmap; | |||
|
27 | use techmap.gencomp.all; | |||
|
28 | library grlib; | |||
|
29 | use grlib.amba.all; | |||
|
30 | use grlib.stdlib.all; | |||
|
31 | use grlib.devices.all; | |||
|
32 | library lpp; | |||
|
33 | use lpp.lpp_amba.all; | |||
|
34 | use lpp.apb_devices_list.all; | |||
|
35 | use lpp.lpp_memory.all; | |||
|
36 | ||||
|
37 | ||||
|
38 | entity APB_FIFO is | |||
|
39 | generic ( | |||
|
40 | tech : integer := apa3; | |||
|
41 | pindex : integer := 0; | |||
|
42 | paddr : integer := 0; | |||
|
43 | pmask : integer := 16#fff#; | |||
|
44 | pirq : integer := 0; | |||
|
45 | abits : integer := 8; | |||
|
46 | FifoCnt : integer := 2; | |||
|
47 | Data_sz : integer := 16; | |||
|
48 | Addr_sz : integer := 9; | |||
|
49 | Enable_ReUse : std_logic := '0'; | |||
|
50 | Mem_use : integer := use_RAM; | |||
|
51 | R : integer := 1; | |||
|
52 | W : integer := 1 | |||
|
53 | ); | |||
|
54 | port ( | |||
|
55 | clk : in std_logic; --! Horloge du composant | |||
|
56 | rst : in std_logic; --! Reset general du composant | |||
|
57 | rclk : in std_logic; | |||
|
58 | wclk : in std_logic; | |||
|
59 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
60 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire | |||
|
61 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire | |||
|
62 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide | |||
|
63 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine | |||
|
64 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e | |||
|
65 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie | |||
|
66 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) | |||
|
67 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |||
|
68 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |||
|
69 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |||
|
70 | ); | |||
|
71 | end entity; | |||
|
72 | ||||
|
73 | architecture ar_APB_FIFO of APB_FIFO is | |||
|
74 | ||||
|
75 | constant REVISION : integer := 1; | |||
|
76 | ||||
|
77 | constant pconfig : apb_config_type := ( | |||
|
78 | 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0), | |||
|
79 | 1 => apb_iobar(paddr, pmask)); | |||
|
80 | ||||
|
81 | type FIFO_ctrlr_Reg is record | |||
|
82 | FIFO_Ctrl : std_logic_vector(31 downto 0); | |||
|
83 | FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0); | |||
|
84 | FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0); | |||
|
85 | end record; | |||
|
86 | ||||
|
87 | type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg; | |||
|
88 | type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0); | |||
|
89 | type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0); | |||
|
90 | ||||
|
91 | signal Rec : FIFO_ctrlr_Reg_Vec; | |||
|
92 | signal PRdata : std_logic_vector(31 downto 0); | |||
|
93 | signal FIFO_ID : std_logic_vector(31 downto 0); | |||
|
94 | signal autoloaded : std_logic_vector(FifoCnt-1 downto 0); | |||
|
95 | signal sFull : std_logic_vector(FifoCnt-1 downto 0); | |||
|
96 | signal sEmpty : std_logic_vector(FifoCnt-1 downto 0); | |||
|
97 | signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0); | |||
|
98 | signal sWen : std_logic_vector(FifoCnt-1 downto 0); | |||
|
99 | signal sRen : std_logic_vector(FifoCnt-1 downto 0); | |||
|
100 | signal sRclk : std_logic; | |||
|
101 | signal sWclk : std_logic; | |||
|
102 | signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0); | |||
|
103 | signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0); | |||
|
104 | signal sRDATA : fifodatabus; | |||
|
105 | signal sWDATA : fifodatabus; | |||
|
106 | signal sWADDR : fifoaddressbus; | |||
|
107 | signal sRADDR : fifoaddressbus; | |||
|
108 | signal sReUse : std_logic_vector(FifoCnt-1 downto 0); | |||
|
109 | signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); | |||
|
110 | ||||
|
111 | signal regDataValid : std_logic_vector(FifoCnt-1 downto 0); | |||
|
112 | signal regData : fifodatabus; | |||
|
113 | signal regREN : std_logic_vector(FifoCnt-1 downto 0); | |||
|
114 | ||||
|
115 | type state_t is (idle,Read); | |||
|
116 | signal fiforeadfsmst : state_t; | |||
|
117 | ||||
|
118 | begin | |||
|
119 | ||||
|
120 | FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4)); | |||
|
121 | FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8)); | |||
|
122 | FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8)); | |||
|
123 | ||||
|
124 | ||||
|
125 | Writeint : if W /= 0 generate | |||
|
126 | FIFO_ID(4) <= '1'; | |||
|
127 | sWen <= sWen_APB; | |||
|
128 | sReUse <= sReUse_APB; | |||
|
129 | sWclk <= clk; | |||
|
130 | Wrapb: for i in 0 to FifoCnt-1 generate | |||
|
131 | sWDATA(i) <= Rec(i).FIFO_Wdata; | |||
|
132 | end generate; | |||
|
133 | end generate; | |||
|
134 | ||||
|
135 | Writeext : if W = 0 generate | |||
|
136 | FIFO_ID(4) <= '0'; | |||
|
137 | sWen <= WEN; | |||
|
138 | sReUse <= ReUse; | |||
|
139 | sWclk <= Wclk; | |||
|
140 | Wrext: for i in 0 to FifoCnt-1 generate | |||
|
141 | sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i); | |||
|
142 | end generate; | |||
|
143 | end generate; | |||
|
144 | ||||
|
145 | Readint : if R /= 0 generate | |||
|
146 | FIFO_ID(5) <= '1'; | |||
|
147 | sRen <= sRen_APB; | |||
|
148 | srclk <= clk; | |||
|
149 | Rdapb: for i in 0 to FifoCnt-1 generate | |||
|
150 | Rec(i).FIFO_Rdata <= sRDATA(i); | |||
|
151 | end generate; | |||
|
152 | end generate; | |||
|
153 | ||||
|
154 | Readext : if R = 0 generate | |||
|
155 | FIFO_ID(5) <= '0'; | |||
|
156 | sRen <= REN; | |||
|
157 | srclk <= rclk; | |||
|
158 | Drext: for i in 0 to FifoCnt-1 generate | |||
|
159 | RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i); | |||
|
160 | end generate; | |||
|
161 | end generate; | |||
|
162 | ||||
|
163 | ctrlregs: for i in 0 to FifoCnt-1 generate | |||
|
164 | RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i); | |||
|
165 | WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i); | |||
|
166 | Rec(i).FIFO_Ctrl(16) <= sFull(i); | |||
|
167 | sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); | |||
|
168 | Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; | |||
|
169 | Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; | |||
|
170 | Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i); | |||
|
171 | Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); | |||
|
172 | end generate; | |||
|
173 | ||||
|
174 | Empty <= sEmpty; | |||
|
175 | Full <= sFull; | |||
|
176 | ||||
|
177 | fifos: for i in 0 to FifoCnt-1 generate | |||
|
178 | FIFO0 : lpp_fifo | |||
|
179 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |||
|
180 | port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); | |||
|
181 | end generate; | |||
|
182 | ||||
|
183 | process(rst,clk) | |||
|
184 | begin | |||
|
185 | if(rst='0')then | |||
|
186 | rstloop1: for i in 0 to FifoCnt-1 loop | |||
|
187 | Rec(i).FIFO_Wdata <= (others => '0'); | |||
|
188 | Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse | |||
|
189 | sWen_APB(i) <= '1'; | |||
|
190 | end loop; | |||
|
191 | elsif(clk'event and clk='1')then | |||
|
192 | ||||
|
193 | --APB Write OP | |||
|
194 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |||
|
195 | writelp: for i in 0 to FifoCnt-1 loop | |||
|
196 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then | |||
|
197 | Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1); | |||
|
198 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then | |||
|
199 | Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0); | |||
|
200 | sWen_APB(i) <= '0'; | |||
|
201 | end if; | |||
|
202 | end loop; | |||
|
203 | else | |||
|
204 | sWen_APB <= (others =>'1'); | |||
|
205 | end if; | |||
|
206 | ||||
|
207 | --APB Read OP | |||
|
208 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |||
|
209 | if(apbi.paddr(abits-1 downto 2)="000000") then | |||
|
210 | PRdata <= FIFO_ID; | |||
|
211 | else | |||
|
212 | readlp: for i in 0 to FifoCnt-1 loop | |||
|
213 | if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then | |||
|
214 | PRdata <= Rec(i).FIFO_Ctrl; | |||
|
215 | elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then | |||
|
216 | PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata; | |||
|
217 | end if; | |||
|
218 | end loop; | |||
|
219 | end if; | |||
|
220 | end if; | |||
|
221 | end if; | |||
|
222 | ||||
|
223 | apbo.pconfig <= pconfig; | |||
|
224 | ||||
|
225 | end process; | |||
|
226 | apbo.prdata <= PRdata when apbi.penable = '1'; | |||
|
227 | ||||
|
228 | process(rst,clk) | |||
|
229 | begin | |||
|
230 | if(rst='0')then | |||
|
231 | fiforeadfsmst <= idle; | |||
|
232 | rstloop: for i in 0 to FifoCnt-1 loop | |||
|
233 | sRen_APB(i) <= '1'; | |||
|
234 | autoloaded(i) <= '1'; | |||
|
235 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); | |||
|
236 | end loop; | |||
|
237 | elsif clk'event and clk = '1' then | |||
|
238 | sEmpty_d <= sEmpty; | |||
|
239 | case fiforeadfsmst is | |||
|
240 | when idle => | |||
|
241 | idlelp: for i in 0 to FifoCnt-1 loop | |||
|
242 | if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then | |||
|
243 | if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then | |||
|
244 | autoloaded(i) <= '0'; | |||
|
245 | else | |||
|
246 | autoloaded(i) <= '1'; | |||
|
247 | end if; | |||
|
248 | sRen_APB(i) <= '0'; | |||
|
249 | fiforeadfsmst <= read; | |||
|
250 | Rec(i).FIFO_Ctrl(0) <= sEmpty(i); | |||
|
251 | else | |||
|
252 | sRen_APB(i) <= '1'; | |||
|
253 | end if; | |||
|
254 | end loop; | |||
|
255 | when read => | |||
|
256 | sRen_APB <= (others => '1'); | |||
|
257 | fiforeadfsmst <= idle; | |||
|
258 | when others => | |||
|
259 | fiforeadfsmst <= idle; | |||
|
260 | end case; | |||
|
261 | end if; | |||
|
262 | end process; | |||
|
263 | ||||
|
264 | end ar_APB_FIFO; No newline at end of file |
@@ -0,0 +1,65 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.std_logic_1164.all; | |||
|
24 | use IEEE.numeric_std.all; | |||
|
25 | library lpp; | |||
|
26 | use lpp.lpp_memory.all; | |||
|
27 | library techmap; | |||
|
28 | use techmap.gencomp.all; | |||
|
29 | ||||
|
30 | entity lppFIFOxN is | |||
|
31 | generic( | |||
|
32 | tech : integer := 0; | |||
|
33 | Mem_use : integer := use_RAM; | |||
|
34 | Data_sz : integer range 1 to 32 := 8; | |||
|
35 | Addr_sz : integer range 1 to 32 := 8; | |||
|
36 | FifoCnt : integer := 1; | |||
|
37 | Enable_ReUse : std_logic := '0' | |||
|
38 | ); | |||
|
39 | port( | |||
|
40 | rst : in std_logic; | |||
|
41 | wclk : in std_logic; | |||
|
42 | rclk : in std_logic; | |||
|
43 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
44 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
45 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
46 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |||
|
47 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |||
|
48 | full : out std_logic_vector(FifoCnt-1 downto 0); | |||
|
49 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |||
|
50 | ); | |||
|
51 | end entity; | |||
|
52 | ||||
|
53 | ||||
|
54 | architecture ar_lppFIFOxN of lppFIFOxN is | |||
|
55 | ||||
|
56 | begin | |||
|
57 | ||||
|
58 | fifos: for i in 0 to FifoCnt-1 generate | |||
|
59 | FIFO0 : lpp_fifo | |||
|
60 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |||
|
61 | port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); | |||
|
62 | end generate; | |||
|
63 | ||||
|
64 | end architecture; | |||
|
65 |
@@ -0,0 +1,148 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | library ieee; | |||
|
23 | use ieee.std_logic_1164.all; | |||
|
24 | library grlib; | |||
|
25 | use grlib.amba.all; | |||
|
26 | use std.textio.all; | |||
|
27 | library lpp; | |||
|
28 | use lpp.lpp_amba.all; | |||
|
29 | library gaisler; | |||
|
30 | use gaisler.misc.all; | |||
|
31 | use gaisler.memctrl.all; | |||
|
32 | library techmap; | |||
|
33 | use techmap.gencomp.all; | |||
|
34 | ||||
|
35 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |||
|
36 | ||||
|
37 | package lpp_memory is | |||
|
38 | ||||
|
39 | component APB_FIFO is | |||
|
40 | generic ( | |||
|
41 | tech : integer := apa3; | |||
|
42 | pindex : integer := 0; | |||
|
43 | paddr : integer := 0; | |||
|
44 | pmask : integer := 16#fff#; | |||
|
45 | pirq : integer := 0; | |||
|
46 | abits : integer := 8; | |||
|
47 | FifoCnt : integer := 2; | |||
|
48 | Data_sz : integer := 16; | |||
|
49 | Addr_sz : integer := 9; | |||
|
50 | Enable_ReUse : std_logic := '0'; | |||
|
51 | Mem_use : integer := use_RAM; | |||
|
52 | R : integer := 1; | |||
|
53 | W : integer := 1 | |||
|
54 | ); | |||
|
55 | port ( | |||
|
56 | clk : in std_logic; --! Horloge du composant | |||
|
57 | rst : in std_logic; --! Reset general du composant | |||
|
58 | rclk : in std_logic; | |||
|
59 | wclk : in std_logic; | |||
|
60 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
61 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire | |||
|
62 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire | |||
|
63 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide | |||
|
64 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine | |||
|
65 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e | |||
|
66 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie | |||
|
67 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) | |||
|
68 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |||
|
69 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |||
|
70 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |||
|
71 | ); | |||
|
72 | end component; | |||
|
73 | ||||
|
74 | ||||
|
75 | component lpp_fifo is | |||
|
76 | generic( | |||
|
77 | tech : integer := 0; | |||
|
78 | Mem_use : integer := use_RAM; | |||
|
79 | Enable_ReUse : std_logic := '0'; | |||
|
80 | DataSz : integer range 1 to 32 := 8; | |||
|
81 | abits : integer range 2 to 12 := 8 | |||
|
82 | ); | |||
|
83 | port( | |||
|
84 | rstn : in std_logic; | |||
|
85 | ReUse : in std_logic; --27/01/12 | |||
|
86 | rclk : in std_logic; | |||
|
87 | ren : in std_logic; | |||
|
88 | rdata : out std_logic_vector(DataSz-1 downto 0); | |||
|
89 | empty : out std_logic; | |||
|
90 | raddr : out std_logic_vector(abits-1 downto 0); | |||
|
91 | wclk : in std_logic; | |||
|
92 | wen : in std_logic; | |||
|
93 | wdata : in std_logic_vector(DataSz-1 downto 0); | |||
|
94 | full : out std_logic; | |||
|
95 | waddr : out std_logic_vector(abits-1 downto 0) | |||
|
96 | ); | |||
|
97 | end component; | |||
|
98 | ||||
|
99 | ||||
|
100 | component lppFIFOxN is | |||
|
101 | generic( | |||
|
102 | tech : integer := 0; | |||
|
103 | Mem_use : integer := use_RAM; | |||
|
104 | Data_sz : integer range 1 to 32 := 8; | |||
|
105 | Addr_sz : integer range 1 to 32 := 8; | |||
|
106 | FifoCnt : integer := 1; | |||
|
107 | Enable_ReUse : std_logic := '0' | |||
|
108 | ); | |||
|
109 | port( | |||
|
110 | rst : in std_logic; | |||
|
111 | wclk : in std_logic; | |||
|
112 | rclk : in std_logic; | |||
|
113 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
114 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
115 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |||
|
116 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |||
|
117 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |||
|
118 | full : out std_logic_vector(FifoCnt-1 downto 0); | |||
|
119 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |||
|
120 | ); | |||
|
121 | end component; | |||
|
122 | ||||
|
123 | component ssram_plugin is | |||
|
124 | generic (tech : integer := 0); | |||
|
125 | port | |||
|
126 | ( | |||
|
127 | clk : in std_logic; | |||
|
128 | mem_ctrlr_o : in memory_out_type; | |||
|
129 | SSRAM_CLK : out std_logic; | |||
|
130 | nBWa : out std_logic; | |||
|
131 | nBWb : out std_logic; | |||
|
132 | nBWc : out std_logic; | |||
|
133 | nBWd : out std_logic; | |||
|
134 | nBWE : out std_logic; | |||
|
135 | nADSC : out std_logic; | |||
|
136 | nADSP : out std_logic; | |||
|
137 | nADV : out std_logic; | |||
|
138 | nGW : out std_logic; | |||
|
139 | nCE1 : out std_logic; | |||
|
140 | CE2 : out std_logic; | |||
|
141 | nCE3 : out std_logic; | |||
|
142 | nOE : out std_logic; | |||
|
143 | MODE : out std_logic; | |||
|
144 | ZZ : out std_logic | |||
|
145 | ); | |||
|
146 | end component; | |||
|
147 | ||||
|
148 | end; |
@@ -0,0 +1,304 | |||||
|
1 | LIBRARY ieee; | |||
|
2 | USE ieee.std_logic_1164.ALL; | |||
|
3 | LIBRARY lpp; | |||
|
4 | USE lpp.lpp_ad_conv.ALL; | |||
|
5 | USE lpp.iir_filter.ALL; | |||
|
6 | USE lpp.FILTERcfg.ALL; | |||
|
7 | USE lpp.lpp_memory.ALL; | |||
|
8 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
|
9 | LIBRARY techmap; | |||
|
10 | USE techmap.gencomp.ALL; | |||
|
11 | ||||
|
12 | ENTITY lpp_top_acq IS | |||
|
13 | GENERIC( | |||
|
14 | tech : INTEGER := 0, | |||
|
15 | Mem_use : integer := use_RAM | |||
|
16 | ); | |||
|
17 | PORT ( | |||
|
18 | -- ADS7886 | |||
|
19 | cnv_run : IN STD_LOGIC; | |||
|
20 | cnv : OUT STD_LOGIC; | |||
|
21 | sck : OUT STD_LOGIC; | |||
|
22 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
|
23 | -- | |||
|
24 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |||
|
25 | cnv_rstn : IN STD_LOGIC; | |||
|
26 | -- | |||
|
27 | clk : IN STD_LOGIC; -- 25 MHz | |||
|
28 | rstn : IN STD_LOGIC; | |||
|
29 | -- | |||
|
30 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
31 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
32 | -- | |||
|
33 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
34 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
35 | -- | |||
|
36 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
37 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
38 | -- | |||
|
39 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
40 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |||
|
41 | ); | |||
|
42 | END lpp_top_acq; | |||
|
43 | ||||
|
44 | ARCHITECTURE tb OF lpp_top_acq IS | |||
|
45 | ||||
|
46 | COMPONENT Downsampling | |||
|
47 | GENERIC ( | |||
|
48 | ChanelCount : INTEGER; | |||
|
49 | SampleSize : INTEGER; | |||
|
50 | DivideParam : INTEGER); | |||
|
51 | PORT ( | |||
|
52 | clk : IN STD_LOGIC; | |||
|
53 | rstn : IN STD_LOGIC; | |||
|
54 | sample_in_val : IN STD_LOGIC; | |||
|
55 | sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); | |||
|
56 | sample_out_val : OUT STD_LOGIC; | |||
|
57 | sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); | |||
|
58 | END COMPONENT; | |||
|
59 | ||||
|
60 | ----------------------------------------------------------------------------- | |||
|
61 | CONSTANT ChanelCount : INTEGER := 8; | |||
|
62 | CONSTANT ncycle_cnv_high : INTEGER := 79; | |||
|
63 | CONSTANT ncycle_cnv : INTEGER := 500; | |||
|
64 | ||||
|
65 | ----------------------------------------------------------------------------- | |||
|
66 | SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); | |||
|
67 | SIGNAL sample_val : STD_LOGIC; | |||
|
68 | SIGNAL sample_val_delay : STD_LOGIC; | |||
|
69 | ----------------------------------------------------------------------------- | |||
|
70 | CONSTANT Coef_SZ : INTEGER := 9; | |||
|
71 | CONSTANT CoefCntPerCel : INTEGER := 6; | |||
|
72 | CONSTANT CoefPerCel : INTEGER := 5; | |||
|
73 | CONSTANT Cels_count : INTEGER := 5; | |||
|
74 | ||||
|
75 | SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); | |||
|
76 | SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
77 | -- | |||
|
78 | SIGNAL sample_filter_v2_out_val : STD_LOGIC; | |||
|
79 | SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
80 | -- | |||
|
81 | SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; | |||
|
82 | SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
83 | ----------------------------------------------------------------------------- | |||
|
84 | SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
85 | SIGNAL sample_downsampling_out_val : STD_LOGIC; | |||
|
86 | SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
87 | -- | |||
|
88 | SIGNAL sample_f0_val : STD_LOGIC; | |||
|
89 | SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
90 | ----------------------------------------------------------------------------- | |||
|
91 | SIGNAL sample_f1_val : STD_LOGIC; | |||
|
92 | SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
93 | -- | |||
|
94 | SIGNAL sample_f2_val : STD_LOGIC; | |||
|
95 | SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
96 | -- | |||
|
97 | SIGNAL sample_f3_val : STD_LOGIC; | |||
|
98 | SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); | |||
|
99 | ||||
|
100 | BEGIN | |||
|
101 | ||||
|
102 | -- component instantiation | |||
|
103 | ----------------------------------------------------------------------------- | |||
|
104 | DIGITAL_acquisition : AD7688_drvr | |||
|
105 | GENERIC MAP ( | |||
|
106 | ChanelCount => ChanelCount, | |||
|
107 | ncycle_cnv_high => ncycle_cnv_high, | |||
|
108 | ncycle_cnv => ncycle_cnv) | |||
|
109 | PORT MAP ( | |||
|
110 | cnv_clk => cnv_clk, -- | |||
|
111 | cnv_rstn => cnv_rstn, -- | |||
|
112 | cnv_run => cnv_run, -- | |||
|
113 | cnv => cnv, -- | |||
|
114 | clk => clk, -- | |||
|
115 | rstn => rstn, -- | |||
|
116 | sck => sck, -- | |||
|
117 | sdo => sdo(ChanelCount-1 DOWNTO 0), -- | |||
|
118 | sample => sample, | |||
|
119 | sample_val => sample_val); | |||
|
120 | ||||
|
121 | ----------------------------------------------------------------------------- | |||
|
122 | ||||
|
123 | PROCESS (clk, rstn) | |||
|
124 | BEGIN -- PROCESS | |||
|
125 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
126 | sample_val_delay <= '0'; | |||
|
127 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
128 | sample_val_delay <= sample_val; | |||
|
129 | END IF; | |||
|
130 | END PROCESS; | |||
|
131 | ||||
|
132 | ----------------------------------------------------------------------------- | |||
|
133 | ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE | |||
|
134 | SampleLoop : FOR j IN 0 TO 15 GENERATE | |||
|
135 | sample_filter_in(i, j) <= sample(i)(j); | |||
|
136 | END GENERATE; | |||
|
137 | ||||
|
138 | sample_filter_in(i, 16) <= sample(i)(15); | |||
|
139 | sample_filter_in(i, 17) <= sample(i)(15); | |||
|
140 | END GENERATE; | |||
|
141 | ||||
|
142 | coefs_v2 <= CoefsInitValCst_v2; | |||
|
143 | ||||
|
144 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |||
|
145 | GENERIC MAP ( | |||
|
146 | tech => 0, | |||
|
147 | Mem_use => Mem_use, | |||
|
148 | Sample_SZ => 18, | |||
|
149 | Coef_SZ => Coef_SZ, | |||
|
150 | Coef_Nb => 25, -- TODO | |||
|
151 | Coef_sel_SZ => 5, -- TODO | |||
|
152 | Cels_count => Cels_count, | |||
|
153 | ChanelsCount => ChanelCount) | |||
|
154 | PORT MAP ( | |||
|
155 | rstn => rstn, | |||
|
156 | clk => clk, | |||
|
157 | virg_pos => 7, | |||
|
158 | coefs => coefs_v2, | |||
|
159 | sample_in_val => sample_val_delay, | |||
|
160 | sample_in => sample_filter_in, | |||
|
161 | sample_out_val => sample_filter_v2_out_val, | |||
|
162 | sample_out => sample_filter_v2_out); | |||
|
163 | ||||
|
164 | ----------------------------------------------------------------------------- | |||
|
165 | PROCESS (clk, rstn) | |||
|
166 | BEGIN -- PROCESS | |||
|
167 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
168 | sample_filter_v2_out_r_val <= '0'; | |||
|
169 | rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP | |||
|
170 | rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP | |||
|
171 | sample_filter_v2_out_r(I, J) <= '0'; | |||
|
172 | END LOOP rst_all_bits; | |||
|
173 | END LOOP rst_all_chanel; | |||
|
174 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
175 | sample_filter_v2_out_r_val <= sample_filter_v2_out_val; | |||
|
176 | IF sample_filter_v2_out_val = '1' THEN | |||
|
177 | sample_filter_v2_out_r <= sample_filter_v2_out; | |||
|
178 | END IF; | |||
|
179 | END IF; | |||
|
180 | END PROCESS; | |||
|
181 | ||||
|
182 | ----------------------------------------------------------------------------- | |||
|
183 | -- F0 -- @24.576 kHz | |||
|
184 | ----------------------------------------------------------------------------- | |||
|
185 | Downsampling_f0 : Downsampling | |||
|
186 | GENERIC MAP ( | |||
|
187 | ChanelCount => ChanelCount, | |||
|
188 | SampleSize => 18, | |||
|
189 | DivideParam => 4) | |||
|
190 | PORT MAP ( | |||
|
191 | clk => clk, | |||
|
192 | rstn => rstn, | |||
|
193 | sample_in_val => sample_filter_v2_out_val , | |||
|
194 | sample_in => sample_filter_v2_out, | |||
|
195 | sample_out_val => sample_f0_val, | |||
|
196 | sample_out => sample_f0); | |||
|
197 | ||||
|
198 | all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
199 | sample_f0_wdata(I) <= sample_f0(0, I); | |||
|
200 | sample_f0_wdata(16*1+I) <= sample_f0(1, I); | |||
|
201 | sample_f0_wdata(16*2+I) <= sample_f0(2, I); | |||
|
202 | sample_f0_wdata(16*3+I) <= sample_f0(6, I); | |||
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203 | sample_f0_wdata(16*4+I) <= sample_f0(7, I); | |||
|
204 | END GENERATE all_bit_sample_f0; | |||
|
205 | ||||
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206 | sample_f0_wen <= NOT(sample_f0_val) & | |||
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207 | NOT(sample_f0_val) & | |||
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208 | NOT(sample_f0_val) & | |||
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209 | NOT(sample_f0_val) & | |||
|
210 | NOT(sample_f0_val); | |||
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211 | ||||
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212 | ----------------------------------------------------------------------------- | |||
|
213 | -- F1 -- @4096 Hz | |||
|
214 | ----------------------------------------------------------------------------- | |||
|
215 | Downsampling_f1 : Downsampling | |||
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216 | GENERIC MAP ( | |||
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217 | ChanelCount => ChanelCount, | |||
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218 | SampleSize => 18, | |||
|
219 | DivideParam => 6) | |||
|
220 | PORT MAP ( | |||
|
221 | clk => clk, | |||
|
222 | rstn => rstn, | |||
|
223 | sample_in_val => sample_f0_val , | |||
|
224 | sample_in => sample_f0, | |||
|
225 | sample_out_val => sample_f1_val, | |||
|
226 | sample_out => sample_f1); | |||
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227 | ||||
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228 | sample_f1_wen <= NOT(sample_f1_val) & | |||
|
229 | NOT(sample_f1_val) & | |||
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230 | NOT(sample_f1_val) & | |||
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231 | NOT(sample_f1_val) & | |||
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232 | NOT(sample_f1_val); | |||
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233 | ||||
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234 | all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE | |||
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235 | sample_f1_wdata(I) <= sample_f1(0, I); | |||
|
236 | sample_f1_wdata(16*1+I) <= sample_f1(1, I); | |||
|
237 | sample_f1_wdata(16*2+I) <= sample_f1(2, I); | |||
|
238 | sample_f1_wdata(16*3+I) <= sample_f1(6, I); | |||
|
239 | sample_f1_wdata(16*4+I) <= sample_f1(7, I); | |||
|
240 | END GENERATE all_bit_sample_f1; | |||
|
241 | ||||
|
242 | ----------------------------------------------------------------------------- | |||
|
243 | -- F2 -- @16 Hz | |||
|
244 | ----------------------------------------------------------------------------- | |||
|
245 | Downsampling_f2 : Downsampling | |||
|
246 | GENERIC MAP ( | |||
|
247 | ChanelCount => ChanelCount, | |||
|
248 | SampleSize => 18, | |||
|
249 | DivideParam => 256) | |||
|
250 | PORT MAP ( | |||
|
251 | clk => clk, | |||
|
252 | rstn => rstn, | |||
|
253 | sample_in_val => sample_f1_val , | |||
|
254 | sample_in => sample_f1, | |||
|
255 | sample_out_val => sample_f2_val, | |||
|
256 | sample_out => sample_f2); | |||
|
257 | ||||
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258 | sample_f2_wen <= NOT(sample_f2_val) & | |||
|
259 | NOT(sample_f2_val) & | |||
|
260 | NOT(sample_f2_val) & | |||
|
261 | NOT(sample_f2_val) & | |||
|
262 | NOT(sample_f2_val); | |||
|
263 | ||||
|
264 | all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
265 | sample_f2_wdata(I) <= sample_f2(0, I); | |||
|
266 | sample_f2_wdata(16*1+I) <= sample_f2(1, I); | |||
|
267 | sample_f2_wdata(16*2+I) <= sample_f2(2, I); | |||
|
268 | sample_f2_wdata(16*3+I) <= sample_f2(6, I); | |||
|
269 | sample_f2_wdata(16*4+I) <= sample_f2(7, I); | |||
|
270 | END GENERATE all_bit_sample_f2; | |||
|
271 | ||||
|
272 | ----------------------------------------------------------------------------- | |||
|
273 | -- F3 -- @256 Hz | |||
|
274 | ----------------------------------------------------------------------------- | |||
|
275 | Downsampling_f3 : Downsampling | |||
|
276 | GENERIC MAP ( | |||
|
277 | ChanelCount => ChanelCount, | |||
|
278 | SampleSize => 18, | |||
|
279 | DivideParam => 96) | |||
|
280 | PORT MAP ( | |||
|
281 | clk => clk, | |||
|
282 | rstn => rstn, | |||
|
283 | sample_in_val => sample_f0_val , | |||
|
284 | sample_in => sample_f0, | |||
|
285 | sample_out_val => sample_f3_val, | |||
|
286 | sample_out => sample_f3); | |||
|
287 | ||||
|
288 | sample_f3_wen <= (NOT sample_f3_val) & | |||
|
289 | (NOT sample_f3_val) & | |||
|
290 | (NOT sample_f3_val) & | |||
|
291 | (NOT sample_f3_val) & | |||
|
292 | (NOT sample_f3_val); | |||
|
293 | ||||
|
294 | all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE | |||
|
295 | sample_f3_wdata(I) <= sample_f3(0, I); | |||
|
296 | sample_f3_wdata(16*1+I) <= sample_f3(1, I); | |||
|
297 | sample_f3_wdata(16*2+I) <= sample_f3(2, I); | |||
|
298 | sample_f3_wdata(16*3+I) <= sample_f3(6, I); | |||
|
299 | sample_f3_wdata(16*4+I) <= sample_f3(7, I); | |||
|
300 | END GENERATE all_bit_sample_f3; | |||
|
301 | ||||
|
302 | ||||
|
303 | ||||
|
304 | END tb; |
@@ -2,6 +2,7 LIBRARY ieee; | |||||
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | LIBRARY grlib; |
|
4 | LIBRARY grlib; | |
|
5 | USE grlib.amba.ALL; | |||
5 |
|
6 | |||
6 | LIBRARY lpp; |
|
7 | LIBRARY lpp; | |
7 | USE lpp.lpp_ad_conv.ALL; |
|
8 | USE lpp.lpp_ad_conv.ALL; | |
@@ -14,26 +15,35 USE techmap.gencomp.ALL; | |||||
14 | PACKAGE lpp_top_lfr_pkg IS |
|
15 | PACKAGE lpp_top_lfr_pkg IS | |
15 |
|
16 | |||
16 | COMPONENT lpp_top_acq |
|
17 | COMPONENT lpp_top_acq | |
17 |
|
|
18 | GENERIC( | |
18 | tech : integer); |
|
19 | tech : INTEGER := 0, | |
19 | PORT ( |
|
20 | Mem_use : integer := use_RAM | |
20 | cnv_run : IN STD_LOGIC; |
|
21 | ); | |
21 | cnv : OUT STD_LOGIC; |
|
22 | PORT ( | |
22 | sck : OUT STD_LOGIC; |
|
23 | -- ADS7886 | |
23 |
|
|
24 | cnv_run : IN STD_LOGIC; | |
24 |
|
|
25 | cnv : OUT STD_LOGIC; | |
25 |
|
|
26 | sck : OUT STD_LOGIC; | |
26 |
|
|
27 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
27 | rstn : IN STD_LOGIC; |
|
28 | -- | |
28 | sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
29 | cnv_clk : IN STD_LOGIC; -- 49 MHz | |
29 | sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
30 | cnv_rstn : IN STD_LOGIC; | |
30 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
31 | -- | |
31 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
32 | clk : IN STD_LOGIC; -- 25 MHz | |
32 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
33 | rstn : IN STD_LOGIC; | |
33 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | -- | |
34 |
|
|
35 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
35 |
|
|
36 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
36 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)); |
|
37 | -- | |
|
38 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
39 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
40 | -- | |||
|
41 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
42 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |||
|
43 | -- | |||
|
44 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
45 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) | |||
|
46 | ); | |||
37 | END COMPONENT; |
|
47 | END COMPONENT; | |
38 |
|
48 | |||
39 | COMPONENT lpp_top_apbreg |
|
49 | COMPONENT lpp_top_apbreg |
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