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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 #VHDLSIMFILES=testbench.vhd
17 #SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39
40 FILESKIP = i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48
49 ################## project specific targets ##########################
50
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
45 ENTITY leon3mp IS
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
54 );
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
60 errorn : OUT STD_ULOGIC;
61
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
91
92 -- ADC --------------------------------------------------------------------
93 bias_fail_sw : OUT STD_LOGIC;
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 ADC_smpclk : OUT STD_LOGIC;
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97
98 ---------------------------------------------------------------------------
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
100 );
101 END;
102
103 ARCHITECTURE Behavioral OF leon3mp IS
104
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 -- CFG_GRETH+CFG_AHB_JTAG;
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CFG_AHB_UART
109 +2;
110 -- 1 is for the SpaceWire module grspw, which is a master
111 -- 1 is for the LFR
112
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
114
115 --Clk & Rst g�n�
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL resetnl : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
129 SIGNAL cgi : clkgen_in_type;
130 SIGNAL cgo : clkgen_out_type;
131 --- AHB / APB
132 SIGNAL apbi : apb_slv_in_type;
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
134 SIGNAL ahbsi : ahb_slv_in_type;
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
136 SIGNAL ahbmi : ahb_mst_in_type;
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
138 --UART
139 SIGNAL ahbuarti : uart_in_type;
140 SIGNAL ahbuarto : uart_out_type;
141 SIGNAL apbuarti : uart_in_type;
142 SIGNAL apbuarto : uart_out_type;
143 --MEM CTRLR
144 SIGNAL memi : memory_in_type;
145 SIGNAL memo : memory_out_type;
146 SIGNAL wpo : wprot_out_type;
147 SIGNAL sdo : sdram_out_type;
148 SIGNAL ramcs : STD_ULOGIC;
149 --IRQ
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
152 --Timer
153 SIGNAL gpti : gptimer_in_type;
154 SIGNAL gpto : gptimer_out_type;
155 --GPIO
156 SIGNAL gpioi : gpio_in_type;
157 SIGNAL gpioo : gpio_out_type;
158 --DSU
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
161 SIGNAL dsui : dsu_in_type;
162 SIGNAL dsuo : dsu_out_type;
163
164 ---------------------------------------------------------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
166 ---------------------------------------------------------------------
167
168 ---------------------------------------------------------------------
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
171
172 -- time management signal
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
175
176 -- Spacewire signals
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
183 SIGNAL swni : grspw_in_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
187
188 -- AD Converter RHF1401
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
190 SIGNAL sample_val : STD_LOGIC;
191 -----------------------------------------------------------------------------
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
193
194 BEGIN
195
196
197 ----------------------------------------------------------------------
198 --- Reset and Clock generation -------------------------------------
199 ----------------------------------------------------------------------
200
201 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
202 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
203
204 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
205
206
207 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
208
209 clkgen0 : clkgen -- clock generator
210 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
211 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
212 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
213
214 PROCESS(lclk100MHz)
215 BEGIN
216 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
217 lclk50MHz <= NOT lclk50MHz;
218 END IF;
219 END PROCESS;
220
221 PROCESS(lclk50MHz)
222 BEGIN
223 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
224 lclk25MHz <= NOT lclk25MHz;
225 END IF;
226 END PROCESS;
227
228 lclk2x <= lclk50MHz;
229 spw_clk <= lclk50MHz;
230
231 ----------------------------------------------------------------------
232 --- LEON3 processor / DSU / IRQ ------------------------------------
233 ----------------------------------------------------------------------
234
235 l3 : IF CFG_LEON3 = 1 GENERATE
236 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
237 u0 : leon3s -- LEON3 processor
238 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
239 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
240 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
241 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
242 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
243 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
244 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
245 irqi(i), irqo(i), dbgi(i), dbgo(i));
246 END GENERATE;
247 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
248
249 dsugen : IF CFG_DSU = 1 GENERATE
250 dsu0 : dsu3 -- LEON3 Debug Support Unit
251 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
252 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
253 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
254 dsui.enable <= '1';
255 dsui.break <= '0';
256 led(2) <= dsuo.active;
257 END GENERATE;
258 END GENERATE;
259
260 nodsu : IF CFG_DSU = 0 GENERATE
261 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
262 END GENERATE;
263
264 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
265 irqctrl0 : irqmp -- interrupt controller
266 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
267 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
268 END GENERATE;
269 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
270 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
271 irqi(i).irl <= "0000";
272 END GENERATE;
273 apbo(2) <= apb_none;
274 END GENERATE;
275
276 ----------------------------------------------------------------------
277 --- Memory controllers ---------------------------------------------
278 ----------------------------------------------------------------------
279 memctrlr : mctrl GENERIC MAP (
280 hindex => 0,
281 pindex => 0,
282 paddr => 0,
283 srbanks => 1
284 )
285 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
286
287 memi.brdyn <= '1';
288 memi.bexcn <= '1';
289 memi.writen <= '1';
290 memi.wrn <= "1111";
291 memi.bwidth <= "10";
292
293 bdr : FOR i IN 0 TO 3 GENERATE
294 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
295 PORT MAP (
296 data(31-i*8 DOWNTO 24-i*8),
297 memo.data(31-i*8 DOWNTO 24-i*8),
298 memo.bdrive(i),
299 memi.data(31-i*8 DOWNTO 24-i*8));
300 END GENERATE;
301
302 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
303 PORT MAP (address, memo.address(21 DOWNTO 2));
304
305 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
306 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
307 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
308 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
309 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
310 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
311 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
312
313 ----------------------------------------------------------------------
314 --- AHB CONTROLLER -------------------------------------------------
315 ----------------------------------------------------------------------
316 ahb0 : ahbctrl -- AHB arbiter/multiplexer
317 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
318 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
319 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
320 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
321
322 ----------------------------------------------------------------------
323 --- AHB UART -------------------------------------------------------
324 ----------------------------------------------------------------------
325 dcomgen : IF CFG_AHB_UART = 1 GENERATE
326 dcom0 : ahbuart
327 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
328 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
329 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
330 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
331 led(0) <= NOT ahbuarti.rxd;
332 led(1) <= NOT ahbuarto.txd;
333 END GENERATE;
334 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
335
336 ----------------------------------------------------------------------
337 --- APB Bridge -----------------------------------------------------
338 ----------------------------------------------------------------------
339 apb0 : apbctrl -- AHB/APB bridge
340 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
341 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
342
343 ----------------------------------------------------------------------
344 --- GPT Timer ------------------------------------------------------
345 ----------------------------------------------------------------------
346 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
347 timer0 : gptimer -- timer unit
348 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
349 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
350 nbits => CFG_GPT_TW)
351 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
352 gpti.dhalt <= dsuo.tstop;
353 gpti.extclk <= '0';
354 END GENERATE;
355 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
356
357
358 ----------------------------------------------------------------------
359 --- APB UART -------------------------------------------------------
360 ----------------------------------------------------------------------
361 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
362 uart1 : apbuart -- UART 1
363 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
364 fifosize => CFG_UART1_FIFO)
365 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
366 apbuarti.rxd <= urxd1;
367 apbuarti.extclk <= '0';
368 utxd1 <= apbuarto.txd;
369 apbuarti.ctsn <= '0';
370 END GENERATE;
371 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
372
373 -------------------------------------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1: apb_lfr_time_management
377 GENERIC MAP (
378 pindex => 6,
379 paddr => 6,
380 pmask => 16#fff#,
381 pirq => 12)
382 PORT MAP (
383 clk25MHz => clkm,
384 clk49_152MHz => clk49_152MHz,
385 resetn => rstn,
386 grspw_tick => swno.tickout,
387 apbi => apbi,
388 apbo => apbo(6),
389 coarse_time => coarse_time,
390 fine_time => fine_time);
391
392 -----------------------------------------------------------------------
393 --- SpaceWire --------------------------------------------------------
394 -----------------------------------------------------------------------
395
396 spw_rxtxclk <= spw_clk;
397 spw_rxclkn <= NOT spw_rxtxclk;
398
399 -- PADS for SPW1
400 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw1_din, dtmp(0));
402 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw1_sin, stmp(0));
404 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw1_dout, swno.d(0));
406 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
407 PORT MAP (spw1_sout, swno.s(0));
408 -- PADS FOR SPW2
409 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
410 PORT MAP (spw2_din, dtmp(1));
411 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
412 PORT MAP (spw2_sin, stmp(1));
413 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
414 PORT MAP (spw2_dout, swno.d(1));
415 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
416 PORT MAP (spw2_sout, swno.s(1));
417
418 -- GRSPW PHY
419 --spw1_input: if CFG_SPW_GRSPW = 1 generate
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
422 GENERIC MAP(
423 tech => fabtech,
424 rxclkbuftype => 1,
425 scantest => 0)
426 PORT MAP(
427 rxrst => swno.rxrst,
428 di => dtmp(j),
429 si => stmp(j),
430 rxclko => spw_rxclk(j),
431 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
435
436 -- SPW core
437 sw0 : grspwm
438 GENERIC MAP(
439 tech => apa3e,
440 hindex => 1,
441 pindex => 5,
442 paddr => 5,
443 pirq => 11,
444 sysfreq => 25000, -- CPU_FREQ
445 rmap => 1,
446 rmapcrc => 1,
447 fifosize1 => 16,
448 fifosize2 => 16,
449 rxclkbuftype => 1,
450 rxunaligned => 0,
451 rmapbufs => 4,
452 ft => 0,
453 netlist => 0,
454 ports => 2,
455 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
456 memtech => apa3e,
457 destkey => 2,
458 spwcore => 1
459 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
460 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
461 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
462 )
463 PORT MAP(rstn, clkm, spw_rxclk(0),
464 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
465 ahbmi, ahbmo(1), apbi, apbo(5),
466 swni, swno);
467
468 swni.tickin <= '0';
469 swni.rmapen <= '1';
470 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
471 swni.tickinraw <= '0';
472 swni.timein <= (OTHERS => '0');
473 swni.dcrstval <= (OTHERS => '0');
474 swni.timerrstval <= (OTHERS => '0');
475
476 -------------------------------------------------------------------------------
477 -- LFR
478 -------------------------------------------------------------------------------
479 lpp_lfr_1 : lpp_lfr
480 GENERIC MAP (
481 Mem_use => use_RAM,
482 nb_data_by_buffer_size => 32,
483 nb_word_by_buffer_size => 30,
484 nb_snapshot_param_size => 32,
485 delta_vector_size => 32,
486 delta_vector_size_f0_2 => 7, -- log2(96)
487 pindex => 15,
488 paddr => 15,
489 pmask => 16#fff#,
490 pirq_ms => 6,
491 pirq_wfp => 14,
492 hindex => 2,
493 top_lfr_version => X"00000002")
494 PORT MAP (
495 clk => clkm,
496 rstn => rstn,
497 sample_B => sample(2 DOWNTO 0),
498 sample_E => sample(7 DOWNTO 3),
499 sample_val => sample_val,
500 apbi => apbi,
501 apbo => apbo(15),
502 ahbi => ahbmi,
503 ahbo => ahbmo(2),
504 coarse_time => coarse_time,
505 fine_time => fine_time,
506 data_shaping_BW => bias_fail_sw);
507
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
509 GENERIC MAP (
510 ChanelCount => 8,
511 ncycle_cnv_high => 79,
512 ncycle_cnv => 500)
513 PORT MAP (
514 cnv_clk => clk49_152MHz,
515 cnv_rstn => rstn,
516 cnv => ADC_smpclk,
517 clk => clkm,
518 rstn => rstn,
519 ADC_data => ADC_data,
520 ADC_nOE => ADC_OEB_bar_CH,
521 sample => sample,
522 sample_val => sample_val);
523
524 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
25
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29
30
31 ENTITY lpp_waveform_dma_genvalid IS
32 PORT (
33 HCLK : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
36
37 valid_in : IN STD_LOGIC;
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
39
40 ack_in : IN STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
43 error : OUT STD_LOGIC
44 );
45 END;
46
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
48 TYPE state_fsm IS (IDLE, VALID);
49 SIGNAL state : state_fsm;
50 BEGIN
51
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
53 BEGIN
54 IF HRESETn = '0' THEN
55 state <= IDLE;
56 valid_out <= '0';
57 error <= '0';
58 time_out <= (OTHERS => '0');
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
60 CASE state IS
61 WHEN IDLE =>
62
63 valid_out <= '0';
64 error <= '0';
65 IF run = '1' AND valid_in = '1' THEN
66 state <= VALID;
67 valid_out <= '1';
68 time_out <= time_in;
69 END IF;
70
71 WHEN VALID =>
72 IF run = '0' THEN
73 state <= IDLE;
74 valid_out <= '0';
75 error <= '0';
76 ELSE
77 IF valid_in = '1' THEN
78 IF ack_in = '1' THEN
79 state <= VALID;
80 valid_out <= '1';
81 time_out <= time_in;
82 ELSE
83 state <= IDLE;
84 error <= '1';
85 valid_out <= '0';
86 END IF;
87 ELSIF ack_in = '1' THEN
88 state <= IDLE;
89 valid_out <= '0';
90 END IF;
91 END IF;
92
93 WHEN OTHERS => NULL;
94 END CASE;
95 END IF;
96 END PROCESS FSM_SELECT_ADDRESS;
97
98 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
29
30 ENTITY lpp_waveform_fifo_arbiter_reg IS
31 GENERIC(
32 data_size : INTEGER;
33 data_nb : INTEGER
34 );
35 PORT(
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
40
41 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
42
43 enable : IN STD_LOGIC;
44 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
45
46 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
47 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
48 );
49 END ENTITY;
50
51
52 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
53
54 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
55 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
56
57 SIGNAL reg_sel : INTEGER;
58 SIGNAL reg_sel_s : INTEGER;
59
60 BEGIN
61
62 all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE
63 PROCESS (clk, rstn)
64 BEGIN -- PROCESS
65 IF rstn = '0' THEN -- asynchronous reset (active low)
66 reg(I) <= 0;
67 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
68 IF run = '0' THEN
69 reg(I) <= 0;
70 ELSE
71 IF sel(I) = '1' THEN
72 reg(I) <= reg_sel_s;
73 END IF;
74 END IF;
75 END IF;
76 END PROCESS;
77 END GENERATE all_reg;
78
79 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
80 reg(1) WHEN sel(1) = '1' ELSE
81 reg(2) WHEN sel(2) = '1' ELSE
82 reg(3);
83
84 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
85 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
86 0;
87
88 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size));
89 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size));
90
91 END ARCHITECTURE;
92
93
94
95
96
97
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102
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104
105
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_waveform_fifo_latencyCorrection IS
34 GENERIC(
35 tech : INTEGER := 0
36 );
37 PORT(
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
42
43 ---------------------------------------------------------------------------
44 empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b
45 empty : OUT STD_LOGIC;
46 data_ren : IN STD_LOGIC;
47 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 ---------------------------------------------------------------------------
49 empty_almost_fifo : IN STD_LOGIC;
50 empty_fifo : IN STD_LOGIC;
51 data_ren_fifo : OUT STD_LOGIC;
52 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 );
54 END ENTITY;
55
56
57 ARCHITECTURE ar_lpp_waveform_fifo_latencyCorrection OF lpp_waveform_fifo_latencyCorrection IS
58 SIGNAL data_ren_fifo_s : STD_LOGIC;
59 -- SIGNAL rdata_s : STD_LOGIC;
60
61 SIGNAL reg_full : STD_LOGIC;
62 SIGNAL empty_almost_reg : STD_LOGIC;
63 BEGIN
64
65 PROCESS (clk, rstn)
66 BEGIN -- PROCESS
67 IF rstn = '0' THEN -- asynchronous reset (active low)
68 empty_almost_reg <= '1';
69 empty <= '1';
70 data_ren_fifo_s <= '1';
71 rdata <= (OTHERS => '0');
72 reg_full <= '0';
73 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
74 IF run = '0' THEN
75 empty_almost_reg <= '1';
76 empty <= '1';
77 data_ren_fifo_s <= '1';
78 rdata <= (OTHERS => '0');
79 reg_full <= '0';
80 ELSE
81
82 IF data_ren_fifo_s = '0' THEN
83 reg_full <= '1';
84 ELSIF data_ren = '0' THEN
85 reg_full <= '0';
86 END IF;
87
88 IF data_ren_fifo_s = '0' THEN
89 rdata <= rdata_fifo;
90 END IF;
91
92 IF (reg_full = '0' OR data_ren = '0') AND empty_fifo = '0' THEN
93 data_ren_fifo_s <= '0';
94 ELSE
95 data_ren_fifo_s <= '1';
96 END IF;
97
98 IF empty_fifo = '1' AND ((reg_full = '0') OR ( data_ren = '0')) THEN
99 empty <= '1';
100 ELSE
101 empty <= '0';
102 END IF;
103
104 IF empty_almost_reg = '0' AND data_ren = '0' AND empty_almost_fifo = '1' THEN
105 empty_almost_reg <= '1';
106 ELSIF empty_almost_reg = '1' AND empty_almost_fifo = '0' THEN
107 empty_almost_reg <= '0';
108 END IF;
109
110 END IF;
111 END IF;
112 END PROCESS;
113
114 empty_almost <= empty_almost_reg;
115 data_ren_fifo <= data_ren_fifo_s;
116
117 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_waveform_fifo_withoutLatency IS
34 GENERIC(
35 tech : INTEGER := 0
36 );
37 PORT(
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
42
43 ---------------------------------------------------------------------------
44 empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b
45 empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
46 data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
47 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
50 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
51
52 ---------------------------------------------------------------------------
53 full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
54 full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
55 data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
56 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
57 );
58 END ENTITY;
59
60
61 ARCHITECTURE ar_lpp_waveform_fifo_withoutLatency OF lpp_waveform_fifo_withoutLatency IS
62 SIGNAL empty_almost_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
63 SIGNAL empty_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
64 SIGNAL data_ren_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
65 SIGNAL rdata_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
66
67 BEGIN
68
69
70
71
72 lpp_waveform_fifo_latencyCorrection_0: lpp_waveform_fifo_latencyCorrection
73 GENERIC MAP (
74 tech => tech)
75 PORT MAP (
76 clk => clk,
77 rstn => rstn,
78 run => run,
79
80 empty_almost => empty_almost(0),
81 empty => empty(0),
82 data_ren => data_ren(0),
83 rdata => rdata_0,
84
85 empty_almost_fifo => empty_almost_s(0),
86 empty_fifo => empty_s(0),
87 data_ren_fifo => data_ren_s(0),
88 rdata_fifo => rdata_s);
89
90 lpp_waveform_fifo_latencyCorrection_1: lpp_waveform_fifo_latencyCorrection
91 GENERIC MAP (
92 tech => tech)
93 PORT MAP (
94 clk => clk,
95 rstn => rstn,
96 run => run,
97
98 empty_almost => empty_almost(1),
99 empty => empty(1),
100 data_ren => data_ren(1),
101 rdata => rdata_1,
102
103 empty_almost_fifo => empty_almost_s(1),
104 empty_fifo => empty_s(1),
105 data_ren_fifo => data_ren_s(1),
106 rdata_fifo => rdata_s);
107
108 lpp_waveform_fifo_latencyCorrection_2: lpp_waveform_fifo_latencyCorrection
109 GENERIC MAP (
110 tech => tech)
111 PORT MAP (
112 clk => clk,
113 rstn => rstn,
114 run => run,
115
116 empty_almost => empty_almost(2),
117 empty => empty(2),
118 data_ren => data_ren(2),
119 rdata => rdata_2,
120
121 empty_almost_fifo => empty_almost_s(2),
122 empty_fifo => empty_s(2),
123 data_ren_fifo => data_ren_s(2),
124 rdata_fifo => rdata_s);
125
126 lpp_waveform_fifo_latencyCorrection_3: lpp_waveform_fifo_latencyCorrection
127 GENERIC MAP (
128 tech => tech)
129 PORT MAP (
130 clk => clk,
131 rstn => rstn,
132 run => run,
133
134 empty_almost => empty_almost(3),
135 empty => empty(3),
136 data_ren => data_ren(3),
137 rdata => rdata_3,
138
139 empty_almost_fifo => empty_almost_s(3),
140 empty_fifo => empty_s(3),
141 data_ren_fifo => data_ren_s(3),
142 rdata_fifo => rdata_s);
143
144 lpp_waveform_fifo_1: lpp_waveform_fifo
145 GENERIC MAP (
146 tech => tech)
147 PORT MAP (
148 clk => clk,
149 rstn => rstn,
150 run => run,
151
152 empty_almost => empty_almost_s,
153 empty => empty_s,
154 data_ren => data_ren_s,
155 rdata => rdata_s,
156
157 full_almost => full_almost,
158 full => full,
159 data_wen => data_wen,
160 wdata => wdata);
161
162 END ARCHITECTURE;
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1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:14:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY lpp;
24 24 USE lpp.lpp_lfr_time_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
28 28 nb_time_code_missing_limit : INTEGER := 60
29 29 );
30 30 PORT (
31 31 clk : IN STD_LOGIC;
32 32 rstn : IN STD_LOGIC;
33 33
34 34 new_timecode : IN STD_LOGIC; -- transition signal information
35 35 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 36 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 37
38 38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 39 fine_time_new : OUT STD_LOGIC;
40 40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 41 coarse_time_new : OUT STD_LOGIC
42 42 );
43 43 END lfr_time_management;
44 44
45 45 ARCHITECTURE Behavioral OF lfr_time_management IS
46 46
47 47 SIGNAL counter_clear : STD_LOGIC;
48 48 SIGNAL counter_full : STD_LOGIC;
49 49
50 50 SIGNAL nb_time_code_missing : INTEGER;
51 51 SIGNAL coarse_time_s : INTEGER;
52
53 SIGNAL new_coarsetime_s : STD_LOGIC;
52 54
53 55 BEGIN
54 56
55 57 lpp_counter_1 : lpp_counter
56 58 GENERIC MAP (
57 59 nb_wait_period => 750,
58 60 nb_bit_of_data => 16)
59 61 PORT MAP (
60 62 clk => clk,
61 63 rstn => rstn,
62 64 clear => counter_clear,
63 65 full => counter_full,
64 66 data => fine_time,
65 67 new_data => fine_time_new);
66 68
67 69 PROCESS (clk, rstn)
68 70 BEGIN -- PROCESS
69 71 IF rstn = '0' THEN -- asynchronous reset (active low)
70 72 nb_time_code_missing <= 0;
71 73 counter_clear <= '0';
72 74 coarse_time_s <= 0;
73 75 coarse_time_new <= '0';
74 76 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
77 IF new_coarsetime = '1' THEN
78 new_coarsetime_s <= '1';
79 ELSIF new_timecode = '1' THEN
80 new_coarsetime_s <= '0';
81 END IF;
82
75 83 IF new_timecode = '1' THEN
76 84 coarse_time_new <= '1';
77 IF new_coarsetime = '1' THEN
85 IF new_coarsetime_s = '1' THEN
78 86 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
79 87 ELSE
80 88 coarse_time_s <= coarse_time_s + 1;
81 89 END IF;
82 90 nb_time_code_missing <= 0;
83 91 counter_clear <= '1';
84 92 ELSE
85 93 coarse_time_new <= '0';
86 94 counter_clear <= '0';
87 95 IF counter_full = '1' THEN
88 96 coarse_time_new <= '1';
89 97 coarse_time_s <= coarse_time_s + 1;
90 98 IF nb_time_code_missing = nb_time_code_missing_limit THEN
91 99 nb_time_code_missing <= nb_time_code_missing_limit;
92 100 ELSE
93 101 nb_time_code_missing <= nb_time_code_missing + 1;
94 102 END IF;
95 103 END IF;
96 104 END IF;
97 105 END IF;
98 106 END PROCESS;
99 107
100 108 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
101 109 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
102 110
103 111 END Behavioral;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE std.textio.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 LIBRARY lpp;
35 35 USE lpp.lpp_amba.ALL;
36 36 USE lpp.apb_devices_list.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38
39 39 PACKAGE lpp_dma_pkg IS
40 40
41 41 COMPONENT lpp_dma
42 42 GENERIC (
43 43 tech : INTEGER;
44 44 hindex : INTEGER;
45 45 pindex : INTEGER;
46 46 paddr : INTEGER;
47 47 pmask : INTEGER;
48 48 pirq : INTEGER);
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 AHB_Master_In : IN AHB_Mst_In_Type;
55 55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 56 -- fifo interface
57 57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 fifo_empty : IN STD_LOGIC;
59 59 fifo_ren : OUT STD_LOGIC;
60 60 -- header
61 61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 header_val : IN STD_LOGIC;
63 63 header_ack : OUT STD_LOGIC);
64 64 END COMPONENT;
65 65
66 66 COMPONENT fifo_test_dma
67 67 GENERIC (
68 68 tech : INTEGER;
69 69 pindex : INTEGER;
70 70 paddr : INTEGER;
71 71 pmask : INTEGER);
72 72 PORT (
73 73 HCLK : IN STD_ULOGIC;
74 74 HRESETn : IN STD_ULOGIC;
75 75 apbi : IN apb_slv_in_type;
76 76 apbo : OUT apb_slv_out_type;
77 77 -- fifo interface
78 78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fifo_empty : OUT STD_LOGIC;
80 80 fifo_ren : IN STD_LOGIC;
81 81 -- header
82 82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 header_val : OUT STD_LOGIC;
84 84 header_ack : IN STD_LOGIC
85 85 );
86 86 END COMPONENT;
87 87
88 88 COMPONENT lpp_dma_apbreg
89 89 GENERIC (
90 90 pindex : INTEGER;
91 91 paddr : INTEGER;
92 92 pmask : INTEGER;
93 93 pirq : INTEGER);
94 94 PORT (
95 95 HCLK : IN STD_ULOGIC;
96 96 HRESETn : IN STD_ULOGIC;
97 97 apbi : IN apb_slv_in_type;
98 98 apbo : OUT apb_slv_out_type;
99 99 -- IN
100 100 ready_matrix_f0_0 : IN STD_LOGIC;
101 101 ready_matrix_f0_1 : IN STD_LOGIC;
102 102 ready_matrix_f1 : IN STD_LOGIC;
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107
108 108 -- OUT
109 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 114 status_error_bad_component_error : OUT STD_LOGIC;
115 115
116 116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 117 config_active_interruption_onError : OUT STD_LOGIC;
118 118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 122 );
123 123 END COMPONENT;
124 124
125 125 COMPONENT lpp_dma_send_1word
126 126 PORT (
127 127 HCLK : IN STD_ULOGIC;
128 128 HRESETn : IN STD_ULOGIC;
129 129 DMAIn : OUT DMA_In_Type;
130 130 DMAOut : IN DMA_OUt_Type;
131 131 send : IN STD_LOGIC;
132 132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 ren : OUT STD_LOGIC;
134 135 send_ok : OUT STD_LOGIC;
135 136 send_ko : OUT STD_LOGIC);
136 137 END COMPONENT;
137 138
138 139 COMPONENT lpp_dma_send_16word
139 140 PORT (
140 141 HCLK : IN STD_ULOGIC;
141 142 HRESETn : IN STD_ULOGIC;
142 143 DMAIn : OUT DMA_In_Type;
143 144 DMAOut : IN DMA_OUt_Type;
144 145 send : IN STD_LOGIC;
145 146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 148 ren : OUT STD_LOGIC;
148 149 send_ok : OUT STD_LOGIC;
149 150 send_ko : OUT STD_LOGIC);
150 151 END COMPONENT;
151 152
152 153 COMPONENT fifo_latency_correction
153 154 PORT (
154 155 HCLK : IN STD_ULOGIC;
155 156 HRESETn : IN STD_ULOGIC;
156 157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 158 fifo_empty : IN STD_LOGIC;
158 159 fifo_ren : OUT STD_LOGIC;
159 160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 161 dma_empty : OUT STD_LOGIC;
161 162 dma_ren : IN STD_LOGIC);
162 163 END COMPONENT;
163 164
164 165 COMPONENT lpp_dma_ip
165 166 GENERIC (
166 167 tech : INTEGER;
167 168 hindex : INTEGER);
168 169 PORT (
169 170 HCLK : IN STD_ULOGIC;
170 171 HRESETn : IN STD_ULOGIC;
171 172 AHB_Master_In : IN AHB_Mst_In_Type;
172 173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
173 174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
174 175 fifo_empty : IN STD_LOGIC;
175 176 fifo_ren : OUT STD_LOGIC;
176 177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 178 header_val : IN STD_LOGIC;
178 179 header_ack : OUT STD_LOGIC;
179 180 ready_matrix_f0_0 : OUT STD_LOGIC;
180 181 ready_matrix_f0_1 : OUT STD_LOGIC;
181 182 ready_matrix_f1 : OUT STD_LOGIC;
182 183 ready_matrix_f2 : OUT STD_LOGIC;
183 184 error_anticipating_empty_fifo : OUT STD_LOGIC;
184 185 error_bad_component_error : OUT STD_LOGIC;
185 186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 187 status_ready_matrix_f0_0 : IN STD_LOGIC;
187 188 status_ready_matrix_f0_1 : IN STD_LOGIC;
188 189 status_ready_matrix_f1 : IN STD_LOGIC;
189 190 status_ready_matrix_f2 : IN STD_LOGIC;
190 191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
191 192 status_error_bad_component_error : IN STD_LOGIC;
192 193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
193 194 config_active_interruption_onError : IN STD_LOGIC;
194 195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 199 END COMPONENT;
199 200
200 201 COMPONENT lpp_dma_singleOrBurst
201 202 GENERIC (
202 203 tech : INTEGER;
203 204 hindex : INTEGER);
204 205 PORT (
205 206 HCLK : IN STD_ULOGIC;
206 207 HRESETn : IN STD_ULOGIC;
207 208 run : IN STD_LOGIC;
208 209 AHB_Master_In : IN AHB_Mst_In_Type;
209 210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
210 211 send : IN STD_LOGIC;
211 212 valid_burst : IN STD_LOGIC;
212 213 done : OUT STD_LOGIC;
213 214 ren : OUT STD_LOGIC;
214 215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
216 217 END COMPONENT;
217 218
218 219 END;
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@@ -1,174 +1,176
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_dma_send_16word IS
40 40 PORT (
41 41 -- AMBA AHB system signals
42 42 HCLK : IN STD_ULOGIC;
43 43 HRESETn : IN STD_ULOGIC;
44 44
45 45 -- DMA
46 46 DMAIn : OUT DMA_In_Type;
47 47 DMAOut : IN DMA_OUt_Type;
48 48
49 49 --
50 50 send : IN STD_LOGIC;
51 51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 ren : OUT STD_LOGIC;
54 54 --
55 55 send_ok : OUT STD_LOGIC;
56 56 send_ko : OUT STD_LOGIC
57 57 );
58 58 END lpp_dma_send_16word;
59 59
60 60 ARCHITECTURE beh OF lpp_dma_send_16word IS
61 61
62 62 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
63 63 SIGNAL state : state_fsm_send_16word;
64 64
65 65 SIGNAL data_counter : INTEGER;
66 66 SIGNAL grant_counter : INTEGER;
67 67
68 68 BEGIN -- beh
69 69
70 70 DMAIn.Beat <= HINCR16;
71 71 DMAIn.Size <= HSIZE32;
72 72
73 73 PROCESS (HCLK, HRESETn)
74 74 BEGIN -- PROCESS
75 75 IF HRESETn = '0' THEN -- asynchronous reset (active low)
76 76 state <= IDLE;
77 77 send_ok <= '0';
78 78 send_ko <= '0';
79 79
80 80 DMAIn.Reset <= '1';
81 81 DMAIn.Address <= (OTHERS => '0');
82 82 DMAIn.Request <= '0';
83 83 DMAIn.Store <= '0';
84 84 DMAIn.Burst <= '1';
85 85 DMAIn.Lock <= '0';
86 86 data_counter <= 0;
87 87 grant_counter <= 0;
88 88 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
89 89
90 90 DMAIn.Reset <= '0';
91 91
92 92 CASE state IS
93 93 WHEN IDLE =>
94 94 DMAIn.Store <= '1';
95 95 DMAIn.Request <= '0';
96 96 send_ok <= '0';
97 97 send_ko <= '0';
98 98 DMAIn.Address <= address;
99 99 data_counter <= 0;
100 100 DMAIn.Lock <= '0'; -- FIX test
101 101 IF send = '1' THEN
102 102 state <= REQUEST_BUS;
103 103 DMAIn.Request <= '1';
104 104 DMAIn.Lock <= '1'; -- FIX test
105 105 DMAIn.Store <= '1';
106 106 END IF;
107 107 WHEN REQUEST_BUS =>
108 108 IF DMAOut.Grant = '1' THEN
109 109 data_counter <= 1;
110 110 grant_counter <= 1;
111 111 state <= SEND_DATA;
112 112 END IF;
113 113 WHEN SEND_DATA =>
114 114
115 115 IF DMAOut.Fault = '1' THEN
116 116 DMAIn.Reset <= '0';
117 117 DMAIn.Address <= (OTHERS => '0');
118 118 DMAIn.Request <= '0';
119 119 DMAIn.Store <= '0';
120 120 DMAIn.Burst <= '0';
121 121 state <= ERROR0;
122 122 ELSE
123 123
124 124 IF DMAOut.Grant = '1' THEN
125 125 IF grant_counter = 15 THEN
126 126 DMAIn.Reset <= '0';
127 127 DMAIn.Request <= '0';
128 128 DMAIn.Store <= '0';
129 129 DMAIn.Burst <= '0';
130 130 ELSE
131 131 grant_counter <= grant_counter+1;
132 132 END IF;
133 133 END IF;
134 134
135 135 IF DMAOut.OKAY = '1' THEN
136 136 IF data_counter = 15 THEN
137 137 DMAIn.Address <= (OTHERS => '0');
138 138 state <= WAIT_LAST_READY;
139 139 ELSE
140 140 data_counter <= data_counter + 1;
141 141 END IF;
142 142 END IF;
143 143 END IF;
144 144
145 145
146 146 WHEN WAIT_LAST_READY =>
147 147 IF DMAOut.Ready = '1' THEN
148 148 IF grant_counter = 15 THEN
149 149 state <= IDLE;
150 150 send_ok <= '1';
151 151 send_ko <= '0';
152 152 ELSE
153 153 state <= ERROR0;
154 154 END IF;
155 155 END IF;
156 156
157 157 WHEN ERROR0 =>
158 158 state <= ERROR1;
159 159 WHEN ERROR1 =>
160 160 send_ok <= '0';
161 161 send_ko <= '1';
162 162 state <= IDLE;
163 163 WHEN OTHERS => NULL;
164 164 END CASE;
165 165 END IF;
166 166 END PROCESS;
167 167
168 168 DMAIn.Data <= data;
169 169
170 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
171 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
170 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
171 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
172 -- '1';
173 ren <= '0' WHEN state = SEND_DATA ELSE
172 174 '1';
173
174 END beh; No newline at end of file
175
176 END beh;
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@@ -1,124 +1,127
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_dma_send_1word IS
40 40 PORT (
41 41 -- AMBA AHB system signals
42 42 HCLK : IN STD_ULOGIC;
43 43 HRESETn : IN STD_ULOGIC;
44 44
45 45 -- DMA
46 46 DMAIn : OUT DMA_In_Type;
47 47 DMAOut : IN DMA_OUt_Type;
48 48 --
49 49 send : IN STD_LOGIC;
50 50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51
52 51 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 ren : OUT STD_LOGIC;
53 53 --
54 54 send_ok : OUT STD_LOGIC;
55 55 send_ko : OUT STD_LOGIC
56 56 );
57 57 END lpp_dma_send_1word;
58 58
59 59 ARCHITECTURE beh OF lpp_dma_send_1word IS
60 60
61 61 TYPE state_fsm_send_1word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1);
62 62 SIGNAL state : state_fsm_send_1word;
63 63
64 64 BEGIN -- beh
65 65
66 66 DMAIn.Reset <= '0';
67 67 DMAIn.Address <= address;
68 68 DMAIn.Data <= data;
69 69 DMAIn.Beat <= (OTHERS => '0');
70 70 DMAIn.Size <= HSIZE32;
71 71 DMAIn.Burst <= '0';
72 72
73 73 PROCESS (HCLK, HRESETn)
74 74 BEGIN -- PROCESS
75 75 IF HRESETn = '0' THEN -- asynchronous reset (active low)
76 76 state <= IDLE;
77 77 DMAIn.Request <= '0';
78 78 DMAIn.Store <= '0';
79 79 send_ok <= '0';
80 80 send_ko <= '0';
81 81 DMAIn.Lock <= '0';
82 ren <= '1';
82 83 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
84 ren <= '1';
83 85 CASE state IS
84 86 WHEN IDLE =>
85 87 DMAIn.Store <= '1';
86 88 DMAIn.Request <= '0';
87 89 send_ok <= '0';
88 90 send_ko <= '0';
89 91 DMAIn.Lock <= '0';
90 92 IF send = '1' THEN
91 93 DMAIn.Request <= '1';
92 94 DMAIn.Lock <= '1';
93 95 state <= REQUEST_BUS;
94 96 END IF;
95 97 WHEN REQUEST_BUS =>
96 98 IF DMAOut.Grant = '1' THEN
97 99 DMAIn.Request <= '0';
98 100 DMAIn.Store <= '0';
99 101 state <= SEND_DATA;
102 ren <= '0';
100 103 END IF;
101 104 WHEN SEND_DATA =>
102 105 IF DMAOut.Fault = '1' THEN
103 106 DMAIn.Request <= '0';
104 107 DMAIn.Store <= '0';
105 108 state <= ERROR0;
106 109 ELSIF DMAOut.Ready = '1' THEN
107 110 DMAIn.Request <= '0';
108 111 DMAIn.Store <= '0';
109 send_ok <= '1';
110 send_ko <= '0';
111 state <= IDLE;
112 send_ok <= '1';
113 send_ko <= '0';
114 state <= IDLE;
112 115 END IF;
113 116 WHEN ERROR0 =>
114 117 state <= ERROR1;
115 118 WHEN ERROR1 =>
116 119 send_ok <= '0';
117 120 send_ko <= '1';
118 121 state <= IDLE;
119 122 WHEN OTHERS => NULL;
120 123 END CASE;
121 124 END IF;
122 125 END PROCESS;
123 126
124 127 END beh;
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@@ -1,164 +1,176
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35 LIBRARY lpp;
36 36 USE lpp.lpp_amba.ALL;
37 37 USE lpp.apb_devices_list.ALL;
38 38 USE lpp.lpp_memory.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_waveform_pkg.ALL;
41 41 LIBRARY techmap;
42 42 USE techmap.gencomp.ALL;
43 43
44 44
45 45 ENTITY lpp_dma_singleOrBurst IS
46 46 GENERIC (
47 47 tech : INTEGER := inferred;
48 48 hindex : INTEGER := 2
49 49 );
50 50 PORT (
51 51 -- AMBA AHB system signals
52 52 HCLK : IN STD_ULOGIC;
53 53 HRESETn : IN STD_ULOGIC;
54 54 --
55 55 run : IN STD_LOGIC;
56 56 -- AMBA AHB Master Interface
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59 --
60 60 send : IN STD_LOGIC;
61 61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 62 done : OUT STD_LOGIC;
63 63 ren : OUT STD_LOGIC;
64 64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
66 66 );
67 67 END;
68 68
69 69 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
70 70 -----------------------------------------------------------------------------
71 71 SIGNAL DMAIn : DMA_In_Type;
72 72 SIGNAL DMAOut : DMA_OUt_Type;
73 73 -----------------------------------------------------------------------------
74 74 -----------------------------------------------------------------------------
75 75 -- CONTROL
76 76 SIGNAL single_send : STD_LOGIC;
77 77 SIGNAL burst_send : STD_LOGIC;
78 78
79 79 -----------------------------------------------------------------------------
80 80 -- SEND SINGLE MODULE
81 81 SIGNAL single_dmai : DMA_In_Type;
82 82
83 83 SIGNAL single_send_ok : STD_LOGIC;
84 84 SIGNAL single_send_ko : STD_LOGIC;
85 SIGNAL single_ren : STD_LOGIC;
85 86 -----------------------------------------------------------------------------
86 87 -- SEND SINGLE MODULE
87 88 SIGNAL burst_dmai : DMA_In_Type;
88 89
89 90 SIGNAL burst_send_ok : STD_LOGIC;
90 91 SIGNAL burst_send_ko : STD_LOGIC;
91 92 SIGNAL burst_ren : STD_LOGIC;
92 93 -----------------------------------------------------------------------------
93 94 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 95 BEGIN
95 96
96 97 -----------------------------------------------------------------------------
97 98 -- DMA to AHB interface
98 99 DMA2AHB_1 : DMA2AHB
99 100 GENERIC MAP (
100 101 hindex => hindex,
101 102 vendorid => VENDOR_LPP,
102 103 deviceid => 10,
103 104 version => 0,
104 105 syncrst => 1,
105 106 boundary => 1) -- FIX 11/01/2013
106 107 PORT MAP (
107 108 HCLK => HCLK,
108 109 HRESETn => HRESETn,
109 110 DMAIn => DMAIn,
110 111 DMAOut => DMAOut,
111 112
112 113 AHBIn => AHB_Master_In,
113 114 AHBOut => AHB_Master_Out);
114 115 -----------------------------------------------------------------------------
115
116
117 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 -- LE PROBLEME EST LA !!!!!
120 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 -- C'est le signal valid_burst qui n'est pas assez long.
123 -----------------------------------------------------------------------------
116 124 single_send <= send WHEN valid_burst = '0' ELSE '0';
117 125 burst_send <= send WHEN valid_burst = '1' ELSE '0';
118 126 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
119 127
120 done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
121 burst_send_ok OR burst_send_ko;
128 -- TODO : verifier
129 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
130 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
131 -- burst_send_ok OR burst_send_ko;
122 132
123 ren <= burst_ren WHEN valid_burst = '1' ELSE
124 NOT single_send_ok;
133 --ren <= burst_ren WHEN valid_burst = '1' ELSE
134 -- NOT single_send_ok;
135 ren <= burst_ren AND single_ren;
125 136
126 137 -----------------------------------------------------------------------------
127 138 -- SEND 1 word by DMA
128 139 -----------------------------------------------------------------------------
129 140 lpp_dma_send_1word_1 : lpp_dma_send_1word
130 141 PORT MAP (
131 142 HCLK => HCLK,
132 143 HRESETn => HRESETn,
133 144 DMAIn => single_dmai,
134 145 DMAOut => DMAOut,
135 146
136 147 send => single_send,
137 148 address => address,
138 149 data => data,
150 ren => single_ren,
139 151
140 152 send_ok => single_send_ok, -- TODO
141 153 send_ko => single_send_ko -- TODO
142 154 );
143 155
144 156 -----------------------------------------------------------------------------
145 157 -- SEND 16 word by DMA (in burst mode)
146 158 -----------------------------------------------------------------------------
147 159 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
148 160
149 161 lpp_dma_send_16word_1 : lpp_dma_send_16word
150 162 PORT MAP (
151 163 HCLK => HCLK,
152 164 HRESETn => HRESETn,
153 165 DMAIn => burst_dmai,
154 166 DMAOut => DMAOut,
155 167
156 168 send => burst_send,
157 169 address => address,
158 170 data => data_2_halfword,
159 171 ren => burst_ren,
160 172
161 173 send_ok => burst_send_ok,
162 174 send_ko => burst_send_ko);
163 175
164 176 END Behavioral;
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@@ -1,548 +1,638
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 30 nb_snapshot_param_size : INTEGER := 11;
30 31 delta_vector_size : INTEGER := 20;
31 delta_vector_size_f0_2 : INTEGER := 3;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 33
33 34 pindex : INTEGER := 4;
34 35 paddr : INTEGER := 4;
35 36 pmask : INTEGER := 16#fff#;
36 37 pirq_ms : INTEGER := 0;
37 38 pirq_wfp : INTEGER := 1;
38 39
39 hindex : INTEGER := 2
40 hindex : INTEGER := 2;
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
40 43
41 44 );
42 45 PORT (
43 46 clk : IN STD_LOGIC;
44 47 rstn : IN STD_LOGIC;
45 48 -- SAMPLE
46 49 sample_B : IN Samples14v(2 DOWNTO 0);
47 50 sample_E : IN Samples14v(4 DOWNTO 0);
48 51 sample_val : IN STD_LOGIC;
49 52 -- APB
50 53 apbi : IN apb_slv_in_type;
51 54 apbo : OUT apb_slv_out_type;
52 55 -- AHB
53 56 ahbi : IN AHB_Mst_In_Type;
54 57 ahbo : OUT AHB_Mst_Out_Type;
55 58 -- TIME
56 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
57 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
58 61 --
59 62 data_shaping_BW : OUT STD_LOGIC
60 63 );
61 64 END lpp_lfr;
62 65
63 66 ARCHITECTURE beh OF lpp_lfr IS
64 67 SIGNAL sample : Samples14v(7 DOWNTO 0);
65 68 SIGNAL sample_s : Samples(7 DOWNTO 0);
66 69 --
67 70 SIGNAL data_shaping_SP0 : STD_LOGIC;
68 71 SIGNAL data_shaping_SP1 : STD_LOGIC;
69 72 SIGNAL data_shaping_R0 : STD_LOGIC;
70 73 SIGNAL data_shaping_R1 : STD_LOGIC;
71 74 --
72 75 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
73 76 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 77 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 78 --
76 79 SIGNAL sample_f0_val : STD_LOGIC;
77 80 SIGNAL sample_f1_val : STD_LOGIC;
78 81 SIGNAL sample_f2_val : STD_LOGIC;
79 82 SIGNAL sample_f3_val : STD_LOGIC;
80 83 --
81 84 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
82 85 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
83 86 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 87 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 88 --
86 89 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 90 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 91 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 92
90 93 -- SM
91 94 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
92 95 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
93 96 SIGNAL ready_matrix_f1 : STD_LOGIC;
94 97 SIGNAL ready_matrix_f2 : STD_LOGIC;
95 98 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
96 99 SIGNAL error_bad_component_error : STD_LOGIC;
97 100 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 101 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
99 102 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
100 103 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
101 104 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
102 105 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
103 106 SIGNAL status_error_bad_component_error : STD_LOGIC;
104 107 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
105 108 SIGNAL config_active_interruption_onError : STD_LOGIC;
106 109 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 110 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 111 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 112 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 113
111 114 -- WFP
112 115 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
113 116 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
114 117 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 118 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 119 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 120 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 121 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 122 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 123 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 124
122 125 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
126 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
123 127 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
124 128 SIGNAL enable_f0 : STD_LOGIC;
125 129 SIGNAL enable_f1 : STD_LOGIC;
126 130 SIGNAL enable_f2 : STD_LOGIC;
127 131 SIGNAL enable_f3 : STD_LOGIC;
128 132 SIGNAL burst_f0 : STD_LOGIC;
129 133 SIGNAL burst_f1 : STD_LOGIC;
130 134 SIGNAL burst_f2 : STD_LOGIC;
131 135 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 136 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 137 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 138 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 139
136 140 SIGNAL run : STD_LOGIC;
137 141 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
138 142
139 143 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 144 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 145 SIGNAL data_f0_data_out_valid : STD_LOGIC;
142 146 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
143 147 SIGNAL data_f0_data_out_ren : STD_LOGIC;
144 148 --f1
145 149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
148 152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
149 153 SIGNAL data_f1_data_out_ren : STD_LOGIC;
150 154 --f2
151 155 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 156 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 157 SIGNAL data_f2_data_out_valid : STD_LOGIC;
154 158 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
155 159 SIGNAL data_f2_data_out_ren : STD_LOGIC;
156 160 --f3
157 161 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 162 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 163 SIGNAL data_f3_data_out_valid : STD_LOGIC;
160 164 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
161 165 SIGNAL data_f3_data_out_ren : STD_LOGIC;
162 166
163 167 -----------------------------------------------------------------------------
164 168 --
165 169 -----------------------------------------------------------------------------
166 170 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 171 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
168 172 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
169 173 --f1
170 174 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 175 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
172 176 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
173 177 --f2
174 178 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 179 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
176 180 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
177 181 --f3
178 182 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 183 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
180 184 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
181 185
182 186 -----------------------------------------------------------------------------
183 187 -- DMA RR
184 188 -----------------------------------------------------------------------------
185 189 SIGNAL dma_sel_valid : STD_LOGIC;
186 190 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 191 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 192 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
189
193
194 -----------------------------------------------------------------------------
195 -- DMA_REG
196 -----------------------------------------------------------------------------
197 SIGNAL ongoing_reg : STD_LOGIC;
198 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 SIGNAL dma_send_reg : STD_LOGIC;
200 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
201 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
203
204
190 205 -----------------------------------------------------------------------------
191 206 -- DMA
192 207 -----------------------------------------------------------------------------
193 208 SIGNAL dma_send : STD_LOGIC;
194 209 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
195 210 SIGNAL dma_done : STD_LOGIC;
196 211 SIGNAL dma_ren : STD_LOGIC;
197 212 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 213 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 215
200 216 BEGIN
201 217
202 218 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
203 219 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
204 220
205 221 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
206 222 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
207 223 END GENERATE all_channel;
208 224
209 225 -----------------------------------------------------------------------------
210 226 lpp_lfr_filter_1 : lpp_lfr_filter
211 227 GENERIC MAP (
212 228 Mem_use => Mem_use)
213 229 PORT MAP (
214 230 sample => sample_s,
215 231 sample_val => sample_val,
216 232 clk => clk,
217 233 rstn => rstn,
218 234 data_shaping_SP0 => data_shaping_SP0,
219 235 data_shaping_SP1 => data_shaping_SP1,
220 236 data_shaping_R0 => data_shaping_R0,
221 237 data_shaping_R1 => data_shaping_R1,
222 238 sample_f0_val => sample_f0_val,
223 239 sample_f1_val => sample_f1_val,
224 240 sample_f2_val => sample_f2_val,
225 241 sample_f3_val => sample_f3_val,
226 242 sample_f0_wdata => sample_f0_data,
227 243 sample_f1_wdata => sample_f1_data,
228 244 sample_f2_wdata => sample_f2_data,
229 245 sample_f3_wdata => sample_f3_data);
230 246
231 247 -----------------------------------------------------------------------------
232 248 lpp_lfr_apbreg_1: lpp_lfr_apbreg
233 249 GENERIC MAP (
234 250 nb_data_by_buffer_size => nb_data_by_buffer_size,
251 nb_word_by_buffer_size => nb_word_by_buffer_size,
235 252 nb_snapshot_param_size => nb_snapshot_param_size,
236 253 delta_vector_size => delta_vector_size,
237 254 delta_vector_size_f0_2 => delta_vector_size_f0_2,
238 255 pindex => pindex,
239 256 paddr => paddr,
240 257 pmask => pmask,
241 258 pirq_ms => pirq_ms,
242 pirq_wfp => pirq_wfp)
259 pirq_wfp => pirq_wfp,
260 top_lfr_version => top_lfr_version)
243 261 PORT MAP (
244 262 HCLK => clk,
245 263 HRESETn => rstn,
246 264 apbi => apbi,
247 265 apbo => apbo,
248 266 ready_matrix_f0_0 => ready_matrix_f0_0,
249 267 ready_matrix_f0_1 => ready_matrix_f0_1,
250 268 ready_matrix_f1 => ready_matrix_f1,
251 269 ready_matrix_f2 => ready_matrix_f2,
252 270 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
253 271 error_bad_component_error => error_bad_component_error,
254 272 debug_reg => debug_reg,
255 273 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
256 274 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
257 275 status_ready_matrix_f1 => status_ready_matrix_f1,
258 276 status_ready_matrix_f2 => status_ready_matrix_f2,
259 277 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
260 278 status_error_bad_component_error => status_error_bad_component_error,
261 279 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
262 280 config_active_interruption_onError => config_active_interruption_onError,
263 281 addr_matrix_f0_0 => addr_matrix_f0_0,
264 282 addr_matrix_f0_1 => addr_matrix_f0_1,
265 283 addr_matrix_f1 => addr_matrix_f1,
266 284 addr_matrix_f2 => addr_matrix_f2,
267 285 status_full => status_full,
268 286 status_full_ack => status_full_ack,
269 287 status_full_err => status_full_err,
270 288 status_new_err => status_new_err,
271 289 data_shaping_BW => data_shaping_BW,
272 290 data_shaping_SP0 => data_shaping_SP0,
273 291 data_shaping_SP1 => data_shaping_SP1,
274 292 data_shaping_R0 => data_shaping_R0,
275 293 data_shaping_R1 => data_shaping_R1,
276 294 delta_snapshot => delta_snapshot,
277 295 delta_f0 => delta_f0,
278 296 delta_f0_2 => delta_f0_2,
279 297 delta_f1 => delta_f1,
280 298 delta_f2 => delta_f2,
281 299 nb_data_by_buffer => nb_data_by_buffer,
300 nb_word_by_buffer => nb_word_by_buffer,
282 301 nb_snapshot_param => nb_snapshot_param,
283 302 enable_f0 => enable_f0,
284 303 enable_f1 => enable_f1,
285 304 enable_f2 => enable_f2,
286 305 enable_f3 => enable_f3,
287 306 burst_f0 => burst_f0,
288 307 burst_f1 => burst_f1,
289 308 burst_f2 => burst_f2,
290 309 run => run,
291 310 addr_data_f0 => addr_data_f0,
292 311 addr_data_f1 => addr_data_f1,
293 312 addr_data_f2 => addr_data_f2,
294 313 addr_data_f3 => addr_data_f3,
295 314 start_date => start_date);
296 315
297 316 -----------------------------------------------------------------------------
298 317 lpp_waveform_1: lpp_waveform
299 318 GENERIC MAP (
300 319 tech => inferred,
301 320 data_size => 6*16,
302 nb_data_by_buffer_size => nb_data_by_buffer_size,
321 nb_data_by_buffer_size => nb_data_by_buffer_size,
322 nb_word_by_buffer_size => nb_word_by_buffer_size,
303 323 nb_snapshot_param_size => nb_snapshot_param_size,
304 324 delta_vector_size => delta_vector_size,
305 325 delta_vector_size_f0_2 => delta_vector_size_f0_2
306 326 )
307 327 PORT MAP (
308 328 clk => clk,
309 329 rstn => rstn,
310 330
311 331 reg_run => run,
312 332 reg_start_date => start_date,
313 333 reg_delta_snapshot => delta_snapshot,
314 334 reg_delta_f0 => delta_f0,
315 335 reg_delta_f0_2 => delta_f0_2,
316 336 reg_delta_f1 => delta_f1,
317 337 reg_delta_f2 => delta_f2,
318 338
319 339 enable_f0 => enable_f0,
320 340 enable_f1 => enable_f1,
321 341 enable_f2 => enable_f2,
322 342 enable_f3 => enable_f3,
323 343 burst_f0 => burst_f0,
324 344 burst_f1 => burst_f1,
325 345 burst_f2 => burst_f2,
326 346
327 347 nb_data_by_buffer => nb_data_by_buffer,
348 nb_word_by_buffer => nb_word_by_buffer,
328 349 nb_snapshot_param => nb_snapshot_param,
329 350 status_full => status_full,
330 351 status_full_ack => status_full_ack,
331 352 status_full_err => status_full_err,
332 353 status_new_err => status_new_err,
333 354
334 355 coarse_time => coarse_time,
335 356 fine_time => fine_time,
336 357
337 358 --f0
338 359 addr_data_f0 => addr_data_f0,
339 360 data_f0_in_valid => sample_f0_val,
340 361 data_f0_in => sample_f0_data,
341 362 --f1
342 363 addr_data_f1 => addr_data_f1,
343 364 data_f1_in_valid => sample_f1_val,
344 365 data_f1_in => sample_f1_data,
345 366 --f2
346 367 addr_data_f2 => addr_data_f2,
347 368 data_f2_in_valid => sample_f2_val,
348 369 data_f2_in => sample_f2_data,
349 370 --f3
350 371 addr_data_f3 => addr_data_f3,
351 372 data_f3_in_valid => sample_f3_val,
352 373 data_f3_in => sample_f3_data,
353 374 -- OUTPUT -- DMA interface
354 375 --f0
355 376 data_f0_addr_out => data_f0_addr_out_s,
356 377 data_f0_data_out => data_f0_data_out,
357 378 data_f0_data_out_valid => data_f0_data_out_valid_s,
358 379 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
359 380 data_f0_data_out_ren => data_f0_data_out_ren,
360 381 --f1
361 382 data_f1_addr_out => data_f1_addr_out_s,
362 383 data_f1_data_out => data_f1_data_out,
363 384 data_f1_data_out_valid => data_f1_data_out_valid_s,
364 385 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
365 386 data_f1_data_out_ren => data_f1_data_out_ren,
366 387 --f2
367 388 data_f2_addr_out => data_f2_addr_out_s,
368 389 data_f2_data_out => data_f2_data_out,
369 390 data_f2_data_out_valid => data_f2_data_out_valid_s,
370 391 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
371 392 data_f2_data_out_ren => data_f2_data_out_ren,
372 393 --f3
373 394 data_f3_addr_out => data_f3_addr_out_s,
374 395 data_f3_data_out => data_f3_data_out,
375 396 data_f3_data_out_valid => data_f3_data_out_valid_s,
376 397 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
377 398 data_f3_data_out_ren => data_f3_data_out_ren
378 399
379 400 );
380 401
381 402
382 403 -----------------------------------------------------------------------------
383 404 -- TEMP
384 405 -----------------------------------------------------------------------------
385 406
386 407 PROCESS (clk, rstn)
387 408 BEGIN -- PROCESS
388 409 IF rstn = '0' THEN -- asynchronous reset (active low)
389 data_f0_addr_out <= (OTHERS => '0');
390 410 data_f0_data_out_valid <= '0';
391 411 data_f0_data_out_valid_burst <= '0';
392 data_f1_addr_out <= (OTHERS => '0');
393 412 data_f1_data_out_valid <= '0';
394 413 data_f1_data_out_valid_burst <= '0';
395 data_f2_addr_out <= (OTHERS => '0');
396 414 data_f2_data_out_valid <= '0';
397 415 data_f2_data_out_valid_burst <= '0';
398 data_f3_addr_out <= (OTHERS => '0');
399 416 data_f3_data_out_valid <= '0';
400 417 data_f3_data_out_valid_burst <= '0';
401 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
402 data_f0_addr_out <= data_f0_addr_out_s;
418 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
403 419 data_f0_data_out_valid <= data_f0_data_out_valid_s;
404 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
405 data_f1_addr_out <= data_f1_addr_out_s;
420 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
406 421 data_f1_data_out_valid <= data_f1_data_out_valid_s;
407 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
408 data_f2_addr_out <= data_f2_addr_out_s;
422 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
409 423 data_f2_data_out_valid <= data_f2_data_out_valid_s;
410 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
411 data_f3_addr_out <= data_f3_addr_out_s;
424 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
412 425 data_f3_data_out_valid <= data_f3_data_out_valid_s;
413 426 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
414 427 END IF;
415 428 END PROCESS;
416
429
430 data_f0_addr_out <= data_f0_addr_out_s;
431 data_f1_addr_out <= data_f1_addr_out_s;
432 data_f2_addr_out <= data_f2_addr_out_s;
433 data_f3_addr_out <= data_f3_addr_out_s;
417 434
418 435 -----------------------------------------------------------------------------
419 436 -- RoundRobin Selection For DMA
420 437 -----------------------------------------------------------------------------
421 438
422 439 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
423 440 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
424 441 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
425 442 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
426 443
427 444 RR_Arbiter_4_1: RR_Arbiter_4
428 445 PORT MAP (
429 446 clk => clk,
430 447 rstn => rstn,
431 448 in_valid => dma_rr_valid,
432 449 out_grant => dma_rr_grant);
433
450
451
452 -----------------------------------------------------------------------------
453 -- in : dma_rr_grant
454 -- send
455 -- out : dma_sel
456 -- dma_valid_burst
457 -- dma_sel_valid
458 -----------------------------------------------------------------------------
434 459 PROCESS (clk, rstn)
435 460 BEGIN -- PROCESS
436 461 IF rstn = '0' THEN -- asynchronous reset (active low)
437 dma_sel <= (OTHERS => '0');
462 dma_sel <= (OTHERS => '0');
463 dma_send <= '0';
464 dma_valid_burst <= '0';
438 465 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
439 IF dma_sel = "0000" OR dma_send = '1' THEN
466 -- IF dma_sel = "0000" OR dma_send = '1' THEN
467 IF dma_sel = "0000" OR dma_done = '1' THEN
440 468 dma_sel <= dma_rr_grant;
469 IF dma_rr_grant(0) = '1' THEN
470 dma_send <= '1';
471 dma_valid_burst <= data_f0_data_out_valid_burst;
472 dma_sel_valid <= data_f0_data_out_valid;
473 ELSIF dma_rr_grant(1) = '1' THEN
474 dma_send <= '1';
475 dma_valid_burst <= data_f1_data_out_valid_burst;
476 dma_sel_valid <= data_f1_data_out_valid;
477 ELSIF dma_rr_grant(2) = '1' THEN
478 dma_send <= '1';
479 dma_valid_burst <= data_f2_data_out_valid_burst;
480 dma_sel_valid <= data_f2_data_out_valid;
481 ELSIF dma_rr_grant(3) = '1' THEN
482 dma_send <= '1';
483 dma_valid_burst <= data_f3_data_out_valid_burst;
484 dma_sel_valid <= data_f3_data_out_valid;
485 END IF;
441 486 ELSE
442 dma_sel <= dma_sel;
443 END IF;
487 dma_sel <= dma_sel;
488 dma_send <= '0';
489 END IF;
444 490 END IF;
445 491 END PROCESS;
446 492
447 493
448 494 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
449 495 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
450 496 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
451 497 data_f3_addr_out ;
452 498
453 499 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
454 500 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
455 501 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
456 502 data_f3_data_out ;
457
458 dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
459 data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
460 data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
461 data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
462 '0';
503
504 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
505 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
506 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
507 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
508 -- '0';
463 509
464 dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
465 data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
466 data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
467 data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
468 '0';
510 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
511 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
512 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
513 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
514 -- '0';
515
516 -- TODO
517 --dma_send <= dma_sel_valid OR dma_valid_burst;
469 518
470 dma_send <= dma_sel_valid OR dma_valid_burst;
471
519 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
520 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
521 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
522 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
523
472 524 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
473 525 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
474 526 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
475 527 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
528
529
530 --PROCESS (clk, rstn)
531 --BEGIN -- PROCESS
532 -- IF rstn = '0' THEN -- asynchronous reset (active low)
533 -- ongoing_reg <= '0';
534 -- dma_sel_reg <= (OTHERS => '0');
535 -- dma_send_reg <= '0';
536 -- dma_valid_burst_reg <= '0';
537 -- dma_address_reg <= (OTHERS => '0');
538 -- dma_data_reg <= (OTHERS => '0');
539 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
540 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
541 -- ongoing_reg <= '1';
542 -- dma_valid_burst_reg <= dma_valid_burst;
543 -- dma_sel_reg <= dma_sel;
544 -- ELSE
545 -- IF dma_done = '1' THEN
546 -- ongoing_reg <= '0';
547 -- END IF;
548 -- END IF;
549 -- dma_send_reg <= dma_send;
550 -- dma_address_reg <= dma_address;
551 -- dma_data_reg <= dma_data;
552 -- END IF;
553 --END PROCESS;
554
555 dma_data_2 <= dma_data;
556 --PROCESS (clk, rstn)
557 --BEGIN -- PROCESS
558 -- IF rstn = '0' THEN -- asynchronous reset (active low)
559 -- dma_data_2 <= (OTHERS => '0');
560 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
561 -- dma_data_2 <= dma_data;
562
563 -- END IF;
564 --END PROCESS;
565
476 566
477 567 -----------------------------------------------------------------------------
478 568 -- DMA
479 569 -----------------------------------------------------------------------------
480 570 lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst
481 571 GENERIC MAP (
482 572 tech => inferred,
483 573 hindex => hindex)
484 574 PORT MAP (
485 575 HCLK => clk,
486 576 HRESETn => rstn,
487 577 run => run,
488 578 AHB_Master_In => ahbi,
489 579 AHB_Master_Out => ahbo,
490 580
491 send => dma_send,
492 valid_burst => dma_valid_burst,
581 send => dma_send,--_reg,
582 valid_burst => dma_valid_burst,--_reg,
493 583 done => dma_done,
494 584 ren => dma_ren,
495 address => dma_address,
496 data => dma_data);
585 address => dma_address,--_reg,
586 data => dma_data_2);--_reg);
497 587
498 588 -----------------------------------------------------------------------------
499 589 -- Matrix Spectral - TODO
500 590 -----------------------------------------------------------------------------
501 591 -----------------------------------------------------------------------------
502 592 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
503 593 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
504 594 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
505 595 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
506 596 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
507 597 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
508 598
509 599 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
510 600 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
511 601 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
512 602 -------------------------------------------------------------------------------
513 603 --lpp_lfr_ms_1: lpp_lfr_ms
514 604 -- GENERIC MAP (
515 605 -- hindex => hindex_ms)
516 606 -- PORT MAP (
517 607 -- clk => clk,
518 608 -- rstn => rstn,
519 609 -- sample_f0_wen => sample_f0_wen,
520 610 -- sample_f0_wdata => sample_f0_wdata,
521 611 -- sample_f1_wen => sample_f1_wen,
522 612 -- sample_f1_wdata => sample_f1_wdata,
523 613 -- sample_f3_wen => sample_f3_wen,
524 614 -- sample_f3_wdata => sample_f3_wdata,
525 615 -- AHB_Master_In => ahbi_ms,
526 616 -- AHB_Master_Out => ahbo_ms,
527 617
528 618 -- ready_matrix_f0_0 => ready_matrix_f0_0,
529 619 -- ready_matrix_f0_1 => ready_matrix_f0_1,
530 620 -- ready_matrix_f1 => ready_matrix_f1,
531 621 -- ready_matrix_f2 => ready_matrix_f2,
532 622 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
533 623 -- error_bad_component_error => error_bad_component_error,
534 624 -- debug_reg => debug_reg,
535 625 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
536 626 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
537 627 -- status_ready_matrix_f1 => status_ready_matrix_f1,
538 628 -- status_ready_matrix_f2 => status_ready_matrix_f2,
539 629 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
540 630 -- status_error_bad_component_error => status_error_bad_component_error,
541 631 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
542 632 -- config_active_interruption_onError => config_active_interruption_onError,
543 633 -- addr_matrix_f0_0 => addr_matrix_f0_0,
544 634 -- addr_matrix_f0_1 => addr_matrix_f0_1,
545 635 -- addr_matrix_f1 => addr_matrix_f1,
546 636 -- addr_matrix_f2 => addr_matrix_f2);
547 637
548 638 END beh;
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@@ -1,433 +1,442
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_amba.ALL;
32 32 USE lpp.apb_devices_list.ALL;
33 33 USE lpp.lpp_memory.ALL;
34 34 LIBRARY techmap;
35 35 USE techmap.gencomp.ALL;
36 36
37 37 ENTITY lpp_lfr_apbreg IS
38 38 GENERIC (
39 39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 41 nb_snapshot_param_size : INTEGER := 11;
41 42 delta_vector_size : INTEGER := 20;
42 43 delta_vector_size_f0_2 : INTEGER := 3;
43 44
44 45 pindex : INTEGER := 4;
45 46 paddr : INTEGER := 4;
46 47 pmask : INTEGER := 16#fff#;
47 48 pirq_ms : INTEGER := 0;
48 pirq_wfp : INTEGER := 1);
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
49 51 PORT (
50 52 -- AMBA AHB system signals
51 53 HCLK : IN STD_ULOGIC;
52 54 HRESETn : IN STD_ULOGIC;
53 55
54 56 -- AMBA APB Slave Interface
55 57 apbi : IN apb_slv_in_type;
56 58 apbo : OUT apb_slv_out_type;
57 59
58 60 ---------------------------------------------------------------------------
59 61 -- Spectral Matrix Reg
60 62 -- IN
61 63 ready_matrix_f0_0 : IN STD_LOGIC;
62 64 ready_matrix_f0_1 : IN STD_LOGIC;
63 65 ready_matrix_f1 : IN STD_LOGIC;
64 66 ready_matrix_f2 : IN STD_LOGIC;
65 67 error_anticipating_empty_fifo : IN STD_LOGIC;
66 68 error_bad_component_error : IN STD_LOGIC;
67 69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 70
69 71 -- OUT
70 72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
71 73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
72 74 status_ready_matrix_f1 : OUT STD_LOGIC;
73 75 status_ready_matrix_f2 : OUT STD_LOGIC;
74 76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
75 77 status_error_bad_component_error : OUT STD_LOGIC;
76 78
77 79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
78 80 config_active_interruption_onError : OUT STD_LOGIC;
79 81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 85 ---------------------------------------------------------------------------
84 86 ---------------------------------------------------------------------------
85 87 -- WaveForm picker Reg
86 88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 92
91 93 -- OUT
92 94 data_shaping_BW : OUT STD_LOGIC;
93 95 data_shaping_SP0 : OUT STD_LOGIC;
94 96 data_shaping_SP1 : OUT STD_LOGIC;
95 97 data_shaping_R0 : OUT STD_LOGIC;
96 98 data_shaping_R1 : OUT STD_LOGIC;
97 99
98 100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
99 101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100 102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
101 103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
104 107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
105 108
106 109 enable_f0 : OUT STD_LOGIC;
107 110 enable_f1 : OUT STD_LOGIC;
108 111 enable_f2 : OUT STD_LOGIC;
109 112 enable_f3 : OUT STD_LOGIC;
110 113
111 114 burst_f0 : OUT STD_LOGIC;
112 115 burst_f1 : OUT STD_LOGIC;
113 116 burst_f2 : OUT STD_LOGIC;
114 117
115 118 run : OUT STD_LOGIC;
116 119
117 120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
122 125
123 126 ---------------------------------------------------------------------------
124 127 );
125 128
126 129 END lpp_lfr_apbreg;
127 130
128 131 ARCHITECTURE beh OF lpp_lfr_apbreg IS
129 132
130 133 CONSTANT REVISION : INTEGER := 1;
131 134
132 135 CONSTANT pconfig : apb_config_type := (
133 136 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
134 137 1 => apb_iobar(paddr, pmask));
135 138
136 139 TYPE lpp_SpectralMatrix_regs IS RECORD
137 140 config_active_interruption_onNewMatrix : STD_LOGIC;
138 141 config_active_interruption_onError : STD_LOGIC;
139 142 status_ready_matrix_f0_0 : STD_LOGIC;
140 143 status_ready_matrix_f0_1 : STD_LOGIC;
141 144 status_ready_matrix_f1 : STD_LOGIC;
142 145 status_ready_matrix_f2 : STD_LOGIC;
143 146 status_error_anticipating_empty_fifo : STD_LOGIC;
144 147 status_error_bad_component_error : STD_LOGIC;
145 148 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 149 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 150 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 151 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 152 END RECORD;
150 153 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
151 154
152 155 TYPE lpp_WaveformPicker_regs IS RECORD
153 156 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 157 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 158 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 159 data_shaping_BW : STD_LOGIC;
157 160 data_shaping_SP0 : STD_LOGIC;
158 161 data_shaping_SP1 : STD_LOGIC;
159 162 data_shaping_R0 : STD_LOGIC;
160 163 data_shaping_R1 : STD_LOGIC;
161 164 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 165 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 166 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 167 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 168 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 169 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
170 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
167 171 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
168 172 enable_f0 : STD_LOGIC;
169 173 enable_f1 : STD_LOGIC;
170 174 enable_f2 : STD_LOGIC;
171 175 enable_f3 : STD_LOGIC;
172 176 burst_f0 : STD_LOGIC;
173 177 burst_f1 : STD_LOGIC;
174 178 burst_f2 : STD_LOGIC;
175 179 run : STD_LOGIC;
176 180 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 181 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 182 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 183 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 184 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
181 185 END RECORD;
182 186 SIGNAL reg_wp : lpp_WaveformPicker_regs;
183 187
184 188 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 189
186 190 BEGIN -- beh
187 191
188 192 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
189 193 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
190 194 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
191 195 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
192 196 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
193 197 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
194 198
195 199 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
196 200 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
197 201 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
198 202 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
199 203 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
200 204 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
201 205
202 206
203 207 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
204 208 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
205 209 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
206 210 data_shaping_R0 <= reg_wp.data_shaping_R0;
207 211 data_shaping_R1 <= reg_wp.data_shaping_R1;
208 212
209 213 delta_snapshot <= reg_wp.delta_snapshot;
210 214 delta_f0 <= reg_wp.delta_f0;
211 215 delta_f0_2 <= reg_wp.delta_f0_2;
212 216 delta_f1 <= reg_wp.delta_f1;
213 217 delta_f2 <= reg_wp.delta_f2;
214 218 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
219 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
215 220 nb_snapshot_param <= reg_wp.nb_snapshot_param;
216 221
217 222 enable_f0 <= reg_wp.enable_f0;
218 223 enable_f1 <= reg_wp.enable_f1;
219 224 enable_f2 <= reg_wp.enable_f2;
220 225 enable_f3 <= reg_wp.enable_f3;
221 226
222 227 burst_f0 <= reg_wp.burst_f0;
223 228 burst_f1 <= reg_wp.burst_f1;
224 229 burst_f2 <= reg_wp.burst_f2;
225 230
226 231 run <= reg_wp.run;
227 232
228 233 addr_data_f0 <= reg_wp.addr_data_f0;
229 234 addr_data_f1 <= reg_wp.addr_data_f1;
230 235 addr_data_f2 <= reg_wp.addr_data_f2;
231 236 addr_data_f3 <= reg_wp.addr_data_f3;
232 237
233 238 start_date <= reg_wp.start_date;
234 239
235 240 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
236 241 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
237 242 BEGIN -- PROCESS lpp_dma_top
238 243 IF HRESETn = '0' THEN -- asynchronous reset (active low)
239 244 reg_sp.config_active_interruption_onNewMatrix <= '0';
240 245 reg_sp.config_active_interruption_onError <= '0';
241 246 reg_sp.status_ready_matrix_f0_0 <= '0';
242 247 reg_sp.status_ready_matrix_f0_1 <= '0';
243 248 reg_sp.status_ready_matrix_f1 <= '0';
244 249 reg_sp.status_ready_matrix_f2 <= '0';
245 250 reg_sp.status_error_anticipating_empty_fifo <= '0';
246 251 reg_sp.status_error_bad_component_error <= '0';
247 252 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
248 253 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
249 254 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
250 255 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
251 256 prdata <= (OTHERS => '0');
252 257
253 258 apbo.pirq <= (OTHERS => '0');
254 259
255 260 status_full_ack <= (OTHERS => '0');
256 261
257 262 reg_wp.data_shaping_BW <= '0';
258 263 reg_wp.data_shaping_SP0 <= '0';
259 264 reg_wp.data_shaping_SP1 <= '0';
260 265 reg_wp.data_shaping_R0 <= '0';
261 266 reg_wp.data_shaping_R1 <= '0';
262 267 reg_wp.enable_f0 <= '0';
263 268 reg_wp.enable_f1 <= '0';
264 269 reg_wp.enable_f2 <= '0';
265 270 reg_wp.enable_f3 <= '0';
266 271 reg_wp.burst_f0 <= '0';
267 272 reg_wp.burst_f1 <= '0';
268 273 reg_wp.burst_f2 <= '0';
269 274 reg_wp.run <= '0';
270 275 reg_wp.addr_data_f0 <= (OTHERS => '0');
271 276 reg_wp.addr_data_f1 <= (OTHERS => '0');
272 277 reg_wp.addr_data_f2 <= (OTHERS => '0');
273 278 reg_wp.addr_data_f3 <= (OTHERS => '0');
274 279 reg_wp.status_full <= (OTHERS => '0');
275 280 reg_wp.status_full_err <= (OTHERS => '0');
276 281 reg_wp.status_new_err <= (OTHERS => '0');
277 282 reg_wp.delta_snapshot <= (OTHERS => '0');
278 283 reg_wp.delta_f0 <= (OTHERS => '0');
279 284 reg_wp.delta_f0_2 <= (OTHERS => '0');
280 285 reg_wp.delta_f1 <= (OTHERS => '0');
281 286 reg_wp.delta_f2 <= (OTHERS => '0');
282 287 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
283 288 reg_wp.nb_snapshot_param <= (OTHERS => '0');
284 289 reg_wp.start_date <= (OTHERS => '0');
285 290
286 291 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
287 292 status_full_ack <= (OTHERS => '0');
288 293
289 294 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
290 295 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
291 296 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
292 297 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
293 298
294 299 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
295 300 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
296
297 reg_wp.status_full <= reg_wp.status_full OR status_full;
298 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
299 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
301 all_status: FOR I IN 3 DOWNTO 0 LOOP
302 reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
303 reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
304 reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
305 END LOOP all_status;
300 306
301 307 paddr := "000000";
302 308 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
303 309 prdata <= (OTHERS => '0');
304 310 IF apbi.psel(pindex) = '1' THEN
305 311 -- APB DMA READ --
306 312 CASE paddr(7 DOWNTO 2) IS
307 313 --
308 314 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
309 315 prdata(1) <= reg_sp.config_active_interruption_onError;
310 316 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
311 317 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
312 318 prdata(2) <= reg_sp.status_ready_matrix_f1;
313 319 prdata(3) <= reg_sp.status_ready_matrix_f2;
314 320 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
315 321 prdata(5) <= reg_sp.status_error_bad_component_error;
316 322 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
317 323 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
318 324 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
319 325 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
320 326 WHEN "000110" => prdata <= debug_reg;
321 327 --
322 328 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
323 329 prdata(1) <= reg_wp.data_shaping_SP0;
324 330 prdata(2) <= reg_wp.data_shaping_SP1;
325 331 prdata(3) <= reg_wp.data_shaping_R0;
326 332 prdata(4) <= reg_wp.data_shaping_R1;
327 333 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
328 334 prdata(1) <= reg_wp.enable_f1;
329 335 prdata(2) <= reg_wp.enable_f2;
330 336 prdata(3) <= reg_wp.enable_f3;
331 337 prdata(4) <= reg_wp.burst_f0;
332 338 prdata(5) <= reg_wp.burst_f1;
333 339 prdata(6) <= reg_wp.burst_f2;
334 340 prdata(7) <= reg_wp.run;
335 341 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
336 342 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
337 343 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
338 344 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
339 345 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
340 346 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
341 347 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
342 348 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
343 349 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
344 350 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
345 351 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
346 352 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
347 353 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
348 354 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
349 355 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
350 --
356 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
357 ----------------------------------------------------
358 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
351 359 WHEN OTHERS => NULL;
352 360 END CASE;
353 361 IF (apbi.pwrite AND apbi.penable) = '1' THEN
354 362 -- APB DMA WRITE --
355 363 CASE paddr(7 DOWNTO 2) IS
356 364 --
357 365 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
358 366 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
359 367 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
360 368 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
361 369 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
362 370 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
363 371 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
364 372 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
365 373 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
366 374 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
367 375 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
368 376 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
369 377 --
370 378 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
371 379 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
372 380 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
373 381 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
374 382 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
375 383 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
376 384 reg_wp.enable_f1 <= apbi.pwdata(1);
377 385 reg_wp.enable_f2 <= apbi.pwdata(2);
378 386 reg_wp.enable_f3 <= apbi.pwdata(3);
379 387 reg_wp.burst_f0 <= apbi.pwdata(4);
380 388 reg_wp.burst_f1 <= apbi.pwdata(5);
381 389 reg_wp.burst_f2 <= apbi.pwdata(6);
382 390 reg_wp.run <= apbi.pwdata(7);
383 391 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
384 392 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
385 393 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
386 394 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
387 395 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
388 396 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
389 397 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
390 398 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
391 399 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
392 400 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
393 401 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
394 402 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
395 403 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
396 404 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
397 405 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
398 406 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
399 407 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
400 408 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
401 409 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
410 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
402 411 --
403 412 WHEN OTHERS => NULL;
404 413 END CASE;
405 414 END IF;
406 415 END IF;
407 416
408 apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
409 ready_matrix_f0_1 OR
410 ready_matrix_f1 OR
411 ready_matrix_f2)
417 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
418 ready_matrix_f0_1 OR
419 ready_matrix_f1 OR
420 ready_matrix_f2)
412 421 )
413 422 OR
414 423 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
415 424 error_bad_component_error)
416 );
425 ));
417 426
418 427 apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
419 428 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
420 429 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
421 430 status_full(3) OR status_full_err(3) OR status_new_err(3)
422 431 );
423 432
424 433
425 434 END IF;
426 435 END PROCESS lpp_lfr_apbreg;
427 436
428 437 apbo.pindex <= pindex;
429 438 apbo.pconfig <= pconfig;
430 439 apbo.prdata <= prdata;
431 440
432 441
433 442 END beh;
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@@ -1,196 +1,202
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16
17 17 COMPONENT lpp_lfr_ms
18 18 GENERIC (
19 19 hindex : INTEGER);
20 20 PORT (
21 21 clk : IN STD_LOGIC;
22 22 rstn : IN STD_LOGIC;
23 23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 29 AHB_Master_In : IN AHB_Mst_In_Type;
30 30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 33 ready_matrix_f1 : OUT STD_LOGIC;
34 34 ready_matrix_f2 : OUT STD_LOGIC;
35 35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 36 error_bad_component_error : OUT STD_LOGIC;
37 37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 40 status_ready_matrix_f1 : IN STD_LOGIC;
41 41 status_ready_matrix_f2 : IN STD_LOGIC;
42 42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 43 status_error_bad_component_error : IN STD_LOGIC;
44 44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 45 config_active_interruption_onError : IN STD_LOGIC;
46 46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 50 END COMPONENT;
51 51
52 52 COMPONENT lpp_lfr_filter
53 53 GENERIC (
54 54 Mem_use : INTEGER);
55 55 PORT (
56 56 sample : IN Samples(7 DOWNTO 0);
57 57 sample_val : IN STD_LOGIC;
58 58 clk : IN STD_LOGIC;
59 59 rstn : IN STD_LOGIC;
60 60 data_shaping_SP0 : IN STD_LOGIC;
61 61 data_shaping_SP1 : IN STD_LOGIC;
62 62 data_shaping_R0 : IN STD_LOGIC;
63 63 data_shaping_R1 : IN STD_LOGIC;
64 64 sample_f0_val : OUT STD_LOGIC;
65 65 sample_f1_val : OUT STD_LOGIC;
66 66 sample_f2_val : OUT STD_LOGIC;
67 67 sample_f3_val : OUT STD_LOGIC;
68 68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 72 END COMPONENT;
73 73
74 74 COMPONENT lpp_lfr
75 75 GENERIC (
76 76 Mem_use : INTEGER;
77 77 nb_data_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
78 79 nb_snapshot_param_size : INTEGER;
79 80 delta_vector_size : INTEGER;
80 81 delta_vector_size_f0_2 : INTEGER;
81 82 pindex : INTEGER;
82 83 paddr : INTEGER;
83 84 pmask : INTEGER;
84 85 pirq_ms : INTEGER;
85 86 pirq_wfp : INTEGER;
86 hindex : INTEGER);
87 hindex : INTEGER;
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
89 );
87 90 PORT (
88 91 clk : IN STD_LOGIC;
89 92 rstn : IN STD_LOGIC;
90 93 sample_B : IN Samples14v(2 DOWNTO 0);
91 94 sample_E : IN Samples14v(4 DOWNTO 0);
92 95 sample_val : IN STD_LOGIC;
93 96 apbi : IN apb_slv_in_type;
94 97 apbo : OUT apb_slv_out_type;
95 98 ahbi : IN AHB_Mst_In_Type;
96 99 ahbo : OUT AHB_Mst_Out_Type;
97 100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
99 102 data_shaping_BW : OUT STD_LOGIC);
100 103 END COMPONENT;
101 104
102 105 COMPONENT lpp_lfr_apbreg
103 106 GENERIC (
104 107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
105 109 nb_snapshot_param_size : INTEGER;
106 110 delta_vector_size : INTEGER;
107 111 delta_vector_size_f0_2 : INTEGER;
108 112 pindex : INTEGER;
109 113 paddr : INTEGER;
110 114 pmask : INTEGER;
111 115 pirq_ms : INTEGER;
112 pirq_wfp : INTEGER);
116 pirq_wfp : INTEGER;
117 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
113 118 PORT (
114 119 HCLK : IN STD_ULOGIC;
115 120 HRESETn : IN STD_ULOGIC;
116 121 apbi : IN apb_slv_in_type;
117 122 apbo : OUT apb_slv_out_type;
118 123 ready_matrix_f0_0 : IN STD_LOGIC;
119 124 ready_matrix_f0_1 : IN STD_LOGIC;
120 125 ready_matrix_f1 : IN STD_LOGIC;
121 126 ready_matrix_f2 : IN STD_LOGIC;
122 127 error_anticipating_empty_fifo : IN STD_LOGIC;
123 128 error_bad_component_error : IN STD_LOGIC;
124 129 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
125 130 status_ready_matrix_f0_0 : OUT STD_LOGIC;
126 131 status_ready_matrix_f0_1 : OUT STD_LOGIC;
127 132 status_ready_matrix_f1 : OUT STD_LOGIC;
128 133 status_ready_matrix_f2 : OUT STD_LOGIC;
129 134 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
130 135 status_error_bad_component_error : OUT STD_LOGIC;
131 136 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
132 137 config_active_interruption_onError : OUT STD_LOGIC;
133 138 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
134 139 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 140 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 141 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
137 142 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 143 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
139 144 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
140 145 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 146 data_shaping_BW : OUT STD_LOGIC;
142 147 data_shaping_SP0 : OUT STD_LOGIC;
143 148 data_shaping_SP1 : OUT STD_LOGIC;
144 149 data_shaping_R0 : OUT STD_LOGIC;
145 150 data_shaping_R1 : OUT STD_LOGIC;
146 151 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
147 152 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
148 153 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
149 154 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
150 155 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
151 156 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
157 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
152 158 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
153 159 enable_f0 : OUT STD_LOGIC;
154 160 enable_f1 : OUT STD_LOGIC;
155 161 enable_f2 : OUT STD_LOGIC;
156 162 enable_f3 : OUT STD_LOGIC;
157 163 burst_f0 : OUT STD_LOGIC;
158 164 burst_f1 : OUT STD_LOGIC;
159 165 burst_f2 : OUT STD_LOGIC;
160 166 run : OUT STD_LOGIC;
161 167 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 168 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 169 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 170 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 171 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
166 172 END COMPONENT;
167 173
168 174 COMPONENT lpp_top_ms
169 175 GENERIC (
170 176 Mem_use : INTEGER;
171 177 nb_burst_available_size : INTEGER;
172 178 nb_snapshot_param_size : INTEGER;
173 179 delta_snapshot_size : INTEGER;
174 180 delta_f2_f0_size : INTEGER;
175 181 delta_f2_f1_size : INTEGER;
176 182 pindex : INTEGER;
177 183 paddr : INTEGER;
178 184 pmask : INTEGER;
179 185 pirq_ms : INTEGER;
180 186 pirq_wfp : INTEGER;
181 187 hindex_wfp : INTEGER;
182 188 hindex_ms : INTEGER);
183 189 PORT (
184 190 clk : IN STD_LOGIC;
185 191 rstn : IN STD_LOGIC;
186 192 sample_B : IN Samples14v(2 DOWNTO 0);
187 193 sample_E : IN Samples14v(4 DOWNTO 0);
188 194 sample_val : IN STD_LOGIC;
189 195 apbi : IN apb_slv_in_type;
190 196 apbo : OUT apb_slv_out_type;
191 197 ahbi_ms : IN AHB_Mst_In_Type;
192 198 ahbo_ms : OUT AHB_Mst_Out_Type;
193 199 data_shaping_BW : OUT STD_LOGIC);
194 200 END COMPONENT;
195 201
196 202 END lpp_lfr_pkg;
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@@ -1,426 +1,436
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 39 ENTITY lpp_waveform IS
40 40
41 41 GENERIC (
42 42 tech : INTEGER := inferred;
43 43 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
44 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
45 46 nb_snapshot_param_size : INTEGER := 11;
46 47 delta_vector_size : INTEGER := 20;
47 48 delta_vector_size_f0_2 : INTEGER := 3);
48 49
49 50 PORT (
50 51 clk : IN STD_LOGIC;
51 52 rstn : IN STD_LOGIC;
52 53
53 54 ---- AMBA AHB Master Interface
54 55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
55 56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
56 57
57 58 --config
58 59 reg_run : IN STD_LOGIC;
59 60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 66
66 67 enable_f0 : IN STD_LOGIC;
67 68 enable_f1 : IN STD_LOGIC;
68 69 enable_f2 : IN STD_LOGIC;
69 70 enable_f3 : IN STD_LOGIC;
70 71
71 72 burst_f0 : IN STD_LOGIC;
72 73 burst_f1 : IN STD_LOGIC;
73 74 burst_f2 : IN STD_LOGIC;
74 75
75 76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
76 78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
77 79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
81 83 ---------------------------------------------------------------------------
82 84 -- INPUT
83 85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
85 87
86 88 --f0
87 89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 90 data_f0_in_valid : IN STD_LOGIC;
89 91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
90 92 --f1
91 93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 94 data_f1_in_valid : IN STD_LOGIC;
93 95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
94 96 --f2
95 97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
96 98 data_f2_in_valid : IN STD_LOGIC;
97 99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
98 100 --f3
99 101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 102 data_f3_in_valid : IN STD_LOGIC;
101 103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 104
103 105 ---------------------------------------------------------------------------
104 106 -- OUTPUT
105 107 --f0
106 108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 110 data_f0_data_out_valid : OUT STD_LOGIC;
109 111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
110 112 data_f0_data_out_ren : IN STD_LOGIC;
111 113 --f1
112 114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 116 data_f1_data_out_valid : OUT STD_LOGIC;
115 117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
116 118 data_f1_data_out_ren : IN STD_LOGIC;
117 119 --f2
118 120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 122 data_f2_data_out_valid : OUT STD_LOGIC;
121 123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
122 124 data_f2_data_out_ren : IN STD_LOGIC;
123 125 --f3
124 126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 128 data_f3_data_out_valid : OUT STD_LOGIC;
127 129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
128 130 data_f3_data_out_ren : IN STD_LOGIC
129 131
130 132
131 133 );
132 134
133 135 END lpp_waveform;
134 136
135 137 ARCHITECTURE beh OF lpp_waveform IS
136 138 SIGNAL start_snapshot_f0 : STD_LOGIC;
137 139 SIGNAL start_snapshot_f1 : STD_LOGIC;
138 140 SIGNAL start_snapshot_f2 : STD_LOGIC;
139 141
140 142 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 143 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 144 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 145 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 146
145 147 SIGNAL data_f0_out_valid : STD_LOGIC;
146 148 SIGNAL data_f1_out_valid : STD_LOGIC;
147 149 SIGNAL data_f2_out_valid : STD_LOGIC;
148 150 SIGNAL data_f3_out_valid : STD_LOGIC;
149 151 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
150 152 --
151 153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 156 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 157 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 158 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 159 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 160 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 161 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 162 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 163 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 164 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 165 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 166 --
165 167 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 168 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 169 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 170 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 171 --
170 172 SIGNAL run : STD_LOGIC;
171 173 --
172 174 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
173 175 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
174 176 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
175 177 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
176 178 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 179 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 180
179 181 BEGIN -- beh
180 182
181 183 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
182 184 GENERIC MAP (
183 185 delta_vector_size => delta_vector_size,
184 186 delta_vector_size_f0_2 => delta_vector_size_f0_2
185 187 )
186 188 PORT MAP (
187 189 clk => clk,
188 190 rstn => rstn,
189 191 reg_run => reg_run,
190 192 reg_start_date => reg_start_date,
191 193 reg_delta_snapshot => reg_delta_snapshot,
192 194 reg_delta_f0 => reg_delta_f0,
193 195 reg_delta_f0_2 => reg_delta_f0_2,
194 196 reg_delta_f1 => reg_delta_f1,
195 197 reg_delta_f2 => reg_delta_f2,
196 198 coarse_time => coarse_time(30 DOWNTO 0),
197 199 data_f0_valid => data_f0_in_valid,
198 200 data_f2_valid => data_f2_in_valid,
199 201 start_snapshot_f0 => start_snapshot_f0,
200 202 start_snapshot_f1 => start_snapshot_f1,
201 203 start_snapshot_f2 => start_snapshot_f2,
202 204 wfp_on => run);
203 205
204 206 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
205 207 GENERIC MAP (
206 208 data_size => data_size,
207 209 nb_snapshot_param_size => nb_snapshot_param_size)
208 210 PORT MAP (
209 211 clk => clk,
210 212 rstn => rstn,
211 213 run => run,
212 214 enable => enable_f0,
213 215 burst_enable => burst_f0,
214 216 nb_snapshot_param => nb_snapshot_param,
215 217 start_snapshot => start_snapshot_f0,
216 218 data_in => data_f0_in,
217 219 data_in_valid => data_f0_in_valid,
218 220 data_out => data_f0_out,
219 221 data_out_valid => data_f0_out_valid);
220 222
221 223 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
222 224
223 225 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
224 226 GENERIC MAP (
225 227 data_size => data_size,
226 228 nb_snapshot_param_size => nb_snapshot_param_size+1)
227 229 PORT MAP (
228 230 clk => clk,
229 231 rstn => rstn,
230 232 run => run,
231 233 enable => enable_f1,
232 234 burst_enable => burst_f1,
233 235 nb_snapshot_param => nb_snapshot_param_more_one,
234 236 start_snapshot => start_snapshot_f1,
235 237 data_in => data_f1_in,
236 238 data_in_valid => data_f1_in_valid,
237 239 data_out => data_f1_out,
238 240 data_out_valid => data_f1_out_valid);
239 241
240 242 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
241 243 GENERIC MAP (
242 244 data_size => data_size,
243 245 nb_snapshot_param_size => nb_snapshot_param_size+1)
244 246 PORT MAP (
245 247 clk => clk,
246 248 rstn => rstn,
247 249 run => run,
248 250 enable => enable_f2,
249 251 burst_enable => burst_f2,
250 252 nb_snapshot_param => nb_snapshot_param_more_one,
251 253 start_snapshot => start_snapshot_f2,
252 254 data_in => data_f2_in,
253 255 data_in_valid => data_f2_in_valid,
254 256 data_out => data_f2_out,
255 257 data_out_valid => data_f2_out_valid);
256 258
257 259 lpp_waveform_burst_f3 : lpp_waveform_burst
258 260 GENERIC MAP (
259 261 data_size => data_size)
260 262 PORT MAP (
261 263 clk => clk,
262 264 rstn => rstn,
263 265 run => run,
264 266 enable => enable_f3,
265 267 data_in => data_f3_in,
266 268 data_in_valid => data_f3_in_valid,
267 269 data_out => data_f3_out,
268 270 data_out_valid => data_f3_out_valid);
269 271
270 272 PROCESS (clk, rstn)
271 273 BEGIN -- PROCESS
272 274 IF rstn = '0' THEN -- asynchronous reset (active low)
273 275 time_reg1 <= (OTHERS => '0');
274 276 time_reg2 <= (OTHERS => '0');
275 277 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
276 278 time_reg1 <= fine_time & coarse_time;
277 279 time_reg2 <= time_reg1;
278 280 END IF;
279 281 END PROCESS;
280 282
281 283 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
282 284 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
283 285 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
284 286 PORT MAP (
285 287 HCLK => clk,
286 288 HRESETn => rstn,
287 289 run => run,
288 290 valid_in => valid_in(I),
289 291 ack_in => valid_ack(I),
290 292 time_in => time_reg2, -- Todo
291 293 valid_out => valid_out(I),
292 294 time_out => time_out(I), -- Todo
293 295 error => status_new_err(I));
294 296 END GENERATE all_input_valid;
295 297
296 298 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
297 299 data_out(0,I) <= data_f0_out(I);
298 300 data_out(1,I) <= data_f1_out(I);
299 301 data_out(2,I) <= data_f2_out(I);
300 302 data_out(3,I) <= data_f3_out(I);
301 303 END GENERATE all_bit_of_data_out;
302 304
303 305 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
304 306 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
305 307 time_out_2(J,I) <= time_out(J)(I);
306 308 END GENERATE all_sample_of_time_out;
307 309 END GENERATE all_bit_of_time_out;
308 310
309 311 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
310 312 GENERIC MAP (tech => tech,
311 313 nb_data_by_buffer_size =>nb_data_by_buffer_size)
312 314 PORT MAP (
313 315 clk => clk,
314 316 rstn => rstn,
315 317 run => run,
316 318 nb_data_by_buffer => nb_data_by_buffer,
317 data_in_valid => valid_out,
318 data_in_ack => valid_ack,
319 data_in => data_out,
320 time_in => time_out_2,
319 data_in_valid => valid_out,
320 data_in_ack => valid_ack,
321 data_in => data_out,
322 time_in => time_out_2,
321 323
322 324 data_out => wdata,
323 325 data_out_wen => data_wen,
324 326 full => full);
325 327
326 328 lpp_waveform_fifo_1 : lpp_waveform_fifo
327 329 GENERIC MAP (tech => tech)
328 330 PORT MAP (
329 331 clk => clk,
330 332 rstn => rstn,
331 333 run => run,
332 334
333 335 empty => empty,
334 336 empty_almost => empty_almost,
335
337
336 338 data_ren => data_ren,
337 339 rdata => rdata,
338 340
339
341
340 342 full_almost => full_almost,
341 343 full => full,
342 344 data_wen => data_wen,
343 345 wdata => wdata);
344 346
345
347 data_f0_data_out <= rdata;
348 data_f1_data_out <= rdata;
349 data_f2_data_out <= rdata;
350 data_f3_data_out <= rdata;
351
352 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
353 -- GENERIC MAP (
354 -- tech => tech)
355 -- PORT MAP (
356 -- clk => clk,
357 -- rstn => rstn,
358 -- run => run,
359
360 -- empty_almost => empty_almost,
361 -- empty => empty,
362 -- data_ren => data_ren,
363
364 -- rdata_0 => data_f0_data_out,
365 -- rdata_1 => data_f1_data_out,
366 -- rdata_2 => data_f2_data_out,
367 -- rdata_3 => data_f3_data_out,
368
369 -- full_almost => full_almost,
370 -- full => full,
371 -- data_wen => data_wen,
372 -- wdata => wdata);
346 373
347 374
348 375
349 -----------------------------------------------------------------------------
350 -- TODO : set the alterance : time, data, data, .....
351 -----------------------------------------------------------------------------
352
353 376
354 -----------------------------------------------------------------------------
355 --
356 -----------------------------------------------------------------------------
357
358 377 data_ren <= data_f3_data_out_ren &
359 378 data_f2_data_out_ren &
360 379 data_f1_data_out_ren &
361 380 data_f0_data_out_ren;
362 381
363 data_f3_data_out <= rdata;
364 data_f2_data_out <= rdata;
365 data_f1_data_out <= rdata;
366 data_f0_data_out <= rdata;
367
368
369
370
371
372 382 -----------------------------------------------------------------------------
373 -- TODO
383 -- TODO : set the alterance : time, data, data, .....
374 384 -----------------------------------------------------------------------------
375 385 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
376 386 GENERIC MAP (
377 nb_data_by_buffer_size => nb_data_by_buffer_size)
387 nb_data_by_buffer_size => nb_word_by_buffer_size)
378 388 PORT MAP (
379 389 clk => clk,
380 390 rstn => rstn,
381 391 run => run,
382 392
383 393 -------------------------------------------------------------------------
384 394 -- CONFIG
385 395 -------------------------------------------------------------------------
386 nb_data_by_buffer => nb_data_by_buffer,
396 nb_data_by_buffer => nb_word_by_buffer,
387 397
388 398 addr_data_f0 => addr_data_f0,
389 399 addr_data_f1 => addr_data_f1,
390 400 addr_data_f2 => addr_data_f2,
391 401 addr_data_f3 => addr_data_f3,
392 402 -------------------------------------------------------------------------
393 403 -- CTRL
394 404 -------------------------------------------------------------------------
395 405 -- IN
396 406 empty => empty,
397 407 empty_almost => empty_almost,
398 408 data_ren => data_ren,
399 409
400 410 -------------------------------------------------------------------------
401 411 -- STATUS
402 412 -------------------------------------------------------------------------
403 413 status_full => status_full,
404 414 status_full_ack => status_full_ack,
405 415 status_full_err => status_full_err,
406 416
407 417 -------------------------------------------------------------------------
408 418 -- ADDR DATA OUT
409 419 -------------------------------------------------------------------------
410 420 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
411 421 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
412 422 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
413 423 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
414 424
415 425 data_f0_data_out_valid => data_f0_data_out_valid,
416 426 data_f1_data_out_valid => data_f1_data_out_valid,
417 427 data_f2_data_out_valid => data_f2_data_out_valid,
418 428 data_f3_data_out_valid => data_f3_data_out_valid,
419 429
420 430 data_f0_addr_out => data_f0_addr_out,
421 431 data_f1_addr_out => data_f1_addr_out,
422 432 data_f2_addr_out => data_f2_addr_out,
423 433 data_f3_addr_out => data_f3_addr_out
424 434 );
425 435
426 436 END beh;
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@@ -1,146 +1,146
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.lpp_memory.ALL;
27 27 USE lpp.iir_filter.ALL;
28 28 USE lpp.lpp_waveform_pkg.ALL;
29 29
30 30 LIBRARY techmap;
31 31 USE techmap.gencomp.ALL;
32 32
33 33 ENTITY lpp_waveform_fifo IS
34 34 GENERIC(
35 35 tech : INTEGER := 0
36 36 );
37 37 PORT(
38 38 clk : IN STD_LOGIC;
39 39 rstn : IN STD_LOGIC;
40 40 ---------------------------------------------------------------------------
41 41 run : IN STD_LOGIC;
42 42
43 43 ---------------------------------------------------------------------------
44 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
45 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b
45 empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
46 data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
47 47 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 48
49 49 ---------------------------------------------------------------------------
50 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
51 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
52 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
51 full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
52 data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
53 53 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
54 54 );
55 55 END ENTITY;
56 56
57 57
58 58 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
59 59
60 60 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
61 61 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
62 SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0);
64 64
65 65 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
66 66 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
67 SIGNAL ren : STD_LOGIC;
68 SIGNAL wen : STD_LOGIC;
67 SIGNAL re : STD_LOGIC;
68 SIGNAL we : STD_LOGIC;
69 69
70 70 BEGIN
71 71
72 72 SRAM : syncram_2p
73 73 GENERIC MAP(tech, 7, 32)
74 PORT MAP(clk, ren, data_addr_r, rdata,
75 clk, wen, data_addr_w, wdata);
74 PORT MAP(clk, re, data_addr_r, rdata,
75 clk, we, data_addr_w, wdata);
76 76
77 ren <= data_mem_ren(3) OR
78 data_mem_ren(2) OR
79 data_mem_ren(1) OR
80 data_mem_ren(0);
77 re <= data_mem_re(3) OR
78 data_mem_re(2) OR
79 data_mem_re(1) OR
80 data_mem_re(0);
81 81
82 wen <= data_mem_wen(3) OR
83 data_mem_wen(2) OR
84 data_mem_wen(1) OR
85 data_mem_wen(0);
82 we <= data_mem_we(3) OR
83 data_mem_we(2) OR
84 data_mem_we(1) OR
85 data_mem_we(0);
86 86
87 data_addr_r <= data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
88 data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
89 data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
87 data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE
88 data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE
89 data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE
90 90 data_mem_addr_r(3);
91 91
92 data_addr_w <= data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
93 data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
94 data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
92 data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE
93 data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE
94 data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE
95 95 data_mem_addr_w(3);
96 96
97 97 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
98 98 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
99 99 GENERIC MAP (
100 100 offset => 32*I,
101 101 length => 32)
102 102 PORT MAP (
103 103 clk => clk,
104 104 rstn => rstn,
105 105 run => run,
106 106 ren => data_ren(I),
107 107 wen => data_wen(I),
108 mem_re => data_mem_ren(I),
109 mem_we => data_mem_wen(I),
108 mem_re => data_mem_re(I),
109 mem_we => data_mem_we(I),
110 110 mem_addr_ren => data_mem_addr_r(I),
111 111 mem_addr_wen => data_mem_addr_w(I),
112 112 empty_almost => empty_almost(I),
113 113 empty => empty(I),
114 114 full_almost => full_almost(I),
115 115 full => full(I)
116 116 );
117 117 END GENERATE gen_fifo_ctrl_data;
118 118
119 119
120 120 END ARCHITECTURE;
121 121
122 122
123 123
124 124
125 125
126 126
127 127
128 128
129 129
130 130
131 131
132 132
133 133
134 134
135 135
136 136
137 137
138 138
139 139
140 140
141 141
142 142
143 143
144 144
145 145
146 146
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@@ -1,269 +1,297
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.lpp_waveform_pkg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_fifo_arbiter IS
31 31 GENERIC(
32 32 tech : INTEGER := 0;
33 33 nb_data_by_buffer_size : INTEGER
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
37 37 rstn : IN STD_LOGIC;
38 38 ---------------------------------------------------------------------------
39 39 run : IN STD_LOGIC;
40 40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 41 ---------------------------------------------------------------------------
42 42 -- SNAPSHOT INTERFACE (INPUT)
43 43 ---------------------------------------------------------------------------
44 44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48 48
49 49 ---------------------------------------------------------------------------
50 50 -- FIFO INTERFACE (OUTPUT)
51 51 ---------------------------------------------------------------------------
52 52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 54 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
55 55
56 56 );
57 57 END ENTITY;
58 58
59 59
60 60 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
61
61 -----------------------------------------------------------------------------
62 -- DATA MUX
62 63 -----------------------------------------------------------------------------
63 -- DATA FLOW
64 -----------------------------------------------------------------------------
64 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
65 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
66 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
67 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
65 68 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
66 SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0);
67 SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0);
68 SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0);
69 SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0);
70 SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0);
71 SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0);
72 SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0);
69 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
70 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
71 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
72 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
73 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
74
75 -----------------------------------------------------------------------------
76 -- RR and SELECTION
77 -----------------------------------------------------------------------------
78 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL no_sel : STD_LOGIC;
81
82 -----------------------------------------------------------------------------
83 -- REG
73 84 -----------------------------------------------------------------------------
74 -- CHANNEL SELECTION (RoundRobin)
85 SIGNAL count_enable : STD_LOGIC;
86 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
87 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
88
89 SIGNAL shift_data_enable : STD_LOGIC;
90 SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
92
93 SIGNAL shift_time_enable : STD_LOGIC;
94 SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
95 SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
96
97 BEGIN
98
75 99 -----------------------------------------------------------------------------
76 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
78 -----------------------------------------------------------------------------
79 -- FSM CONTROL
100 -- CONTROL
80 101 -----------------------------------------------------------------------------
81 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
82 SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0);
83 SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0);
84 SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0);
85 -- SHIFT_DATA ---------------------------------------------------------------
86 SIGNAL shift_data_pre : INTEGER;
87 SIGNAL shift_data : INTEGER;
88 SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0);
89 -- SHIFT_TIME ---------------------------------------------------------------
90 SIGNAL reg_shift_time_pre : INTEGER;
91 SIGNAL shift_time_pre : INTEGER;
92 SIGNAL shift_time : INTEGER;
93 SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0);
94 -- COUNT_DATA ---------------------------------------------------------------
95 SIGNAL count_data_pre : INTEGER;
96 SIGNAL count_data : INTEGER;
97 SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0);
98
99 BEGIN
102 PROCESS (clk, rstn)
103 BEGIN -- PROCESS
104 IF rstn = '0' THEN -- asynchronous reset (active low)
105 count_enable <= '0';
106 shift_time_enable <= '0';
107 shift_data_enable <= '0';
108 data_in_ack <= (OTHERS => '0');
109 data_out_wen <= (OTHERS => '1');
110 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
111 IF run = '0' OR no_sel = '1' THEN
112 count_enable <= '0';
113 shift_time_enable <= '0';
114 shift_data_enable <= '0';
115 data_in_ack <= (OTHERS => '0');
116 data_out_wen <= (OTHERS => '1');
117 ELSE
118 --COUNT
119 IF shift_data_s = "10" THEN
120 count_enable <= '1';
121 ELSE
122 count_enable <= '0';
123 END IF;
124 --DATA
125 IF shift_time_s = "10" THEN
126 shift_data_enable <= '1';
127 ELSE
128 shift_data_enable <= '0';
129 END IF;
100 130
101 -----------------------------------------------------------------------------
102 -- DATA FLOW
103 -----------------------------------------------------------------------------
131 --TIME
132 IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
133 shift_time_s = "00" OR
134 shift_time_s = "01"
135 THEN
136 shift_time_enable <= '1';
137 ELSE
138 shift_time_enable <= '0';
139 END IF;
140
141 --ACK
142 IF shift_data_s = "10" THEN
143 data_in_ack <= sel;
144 ELSE
145 data_in_ack <= (OTHERS => '0');
146 END IF;
147
148 --VALID OUT
149 all_wen: FOR I IN 3 DOWNTO 0 LOOP
150 IF sel(I) = '1' AND count_enable = '0' THEN
151 data_out_wen(I) <= '0';
152 ELSE
153 data_out_wen(I) <= '1';
154 END IF;
155 END LOOP all_wen;
104 156
157 END IF;
158 END IF;
159 END PROCESS;
105 160
106 all_input : FOR I IN 3 DOWNTO 0 GENERATE
107
108 all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE
109 time_temp_0(I)(J) <= time_in(I,J);
110 J_47DOWNTO32: IF J+32 < 48 GENERATE
111 time_temp_1(I)(J) <= time_in(I,32+J);
112 END GENERATE J_47DOWNTO32;
113 J_63DOWNTO48: IF J+32 > 47 GENERATE
114 time_temp_1(I)(J) <= '0';
115 END GENERATE J_63DOWNTO48;
116 data_temp_0(I)(J) <= data_in(I,J);
117 data_temp_1(I)(J) <= data_in(I,J+32);
118 data_temp_2(I)(J) <= data_in(I,J+32*2);
119 END GENERATE all_bit_of_time;
120
121 data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE
122 time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE
123 data_temp_0(I) WHEN shift_data = 0 ELSE
124 data_temp_1(I) WHEN shift_data = 1 ELSE
125 data_temp_2(I);
126 END GENERATE all_input;
161 -----------------------------------------------------------------------------
162 -- DATA MUX
163 -----------------------------------------------------------------------------
164 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
165 I_time_in: IF I < 48 GENERATE
166 data_0_v(I) <= time_in(0,I);
167 data_1_v(I) <= time_in(1,I);
168 data_2_v(I) <= time_in(2,I);
169 data_3_v(I) <= time_in(3,I);
170 END GENERATE I_time_in;
171 I_null: IF (I > 47) AND (I < 32*2) GENERATE
172 data_0_v(I) <= '0';
173 data_1_v(I) <= '0';
174 data_2_v(I) <= '0';
175 data_3_v(I) <= '0';
176 END GENERATE I_null;
177 I_data_in: IF I > 32*2-1 GENERATE
178 data_0_v(I) <= data_in(0,I-32*2);
179 data_1_v(I) <= data_in(1,I-32*2);
180 data_2_v(I) <= data_in(2,I-32*2);
181 data_3_v(I) <= data_in(3,I-32*2);
182 END GENERATE I_data_in;
183 END GENERATE all_bit_data_in;
127 184
128 data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE
129 data_temp_v(1) WHEN sel_input = "0010" ELSE
130 data_temp_v(2) WHEN sel_input = "0100" ELSE
131 data_temp_v(3);
185 all_word: FOR J IN 4 DOWNTO 0 GENERATE
186 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
187 data_0(J)(I) <= data_0_v(J*32+I);
188 data_1(J)(I) <= data_1_v(J*32+I);
189 data_2(J)(I) <= data_2_v(J*32+I);
190 data_3(J)(I) <= data_3_v(J*32+I);
191 END GENERATE all_data_bit;
192 END GENERATE all_word;
132 193
194 data_sel <= data_0 WHEN sel(0) = '1' ELSE
195 data_1 WHEN sel(1) = '1' ELSE
196 data_2 WHEN sel(2) = '1' ELSE
197 data_3;
198
199 data_out <= data_sel(0) WHEN shift_time = "00" ELSE
200 data_sel(1) WHEN shift_time = "01" ELSE
201 data_sel(2) WHEN shift_data = "00" ELSE
202 data_sel(3) WHEN shift_data = "01" ELSE
203 data_sel(4);
204
205
133 206 -----------------------------------------------------------------------------
134 -- CHANNEL SELECTION (RoundRobin)
207 -- RR and SELECTION
135 208 -----------------------------------------------------------------------------
136 209 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
137 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
138 210 valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
139 211 END GENERATE all_input_rr;
140 212
141 213 RR_Arbiter_4_1 : RR_Arbiter_4
142 214 PORT MAP (
143 215 clk => clk,
144 216 rstn => rstn,
145 217 in_valid => valid_in_rr,
146 out_grant => valid_out_rr);
147
148 -----------------------------------------------------------------------------
149 -- FSM CONTROL
150 -----------------------------------------------------------------------------
151
152 PROCESS (clk, rstn)
153 BEGIN -- PROCESS
154 IF rstn = '0' THEN -- asynchronous reset (active low)
155 reg_shift_data <= (0, 0, 0, 0);
156 reg_shift_time <= (0, 0, 0, 0);
157 reg_count_data <= (0, 0, 0, 0);
158 sel_input <= (OTHERS => '0');
159 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
160 IF run = '0' THEN
161 reg_shift_data <= (0, 0, 0, 0);
162 reg_shift_time <= (0, 0, 0, 0);
163 reg_count_data <= (0, 0, 0, 0);
164 sel_input <= (OTHERS => '0');
165 ELSE
166 sel_input <= valid_out_rr;
218 out_grant => sel);
167 219
168 IF count_data_pre = 0 THEN -- first buffer data
169 IF shift_time_pre < 2 THEN -- TIME not completly send
170 reg_shift_time <= reg_shift_time_s;
171 ELSE
172 reg_shift_data <= reg_shift_data_s;
173 IF shift_data_pre = 2 THEN
174 reg_count_data <= reg_count_data_s;
175 END IF;
176 END IF;
177 ELSE
178 reg_shift_data <= reg_shift_data_s;
179 IF shift_data_pre = 2 THEN
180 reg_count_data <= reg_count_data_s;
181 IF count_data = 0 THEN
182 reg_shift_time <= reg_shift_time_s;
183 END IF;
184 END IF;
185 END IF;
186 END IF;
187 END IF;
188 END PROCESS;
220 no_sel <= '1' WHEN sel = "0000" ELSE '0';
189 221
190 222 -----------------------------------------------------------------------------
191 data_out_wen <= NOT sel_input;
192 data_in_ack <= sel_input;
193
194 -- SHIFT_DATA ---------------------------------------------------------------
195 shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE
196 reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE
197 reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE
198 reg_shift_data(3);
199
200 shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0;
201
202 reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s
203 reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s
204 reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s
205 reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s
206
207 -- SHIFT_TIME ---------------------------------------------------------------
208 shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE
209 reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE
210 reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE
211 reg_shift_time(3);
212
213 shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0;
223 -- REG
224 -----------------------------------------------------------------------------
225 reg_count_i: lpp_waveform_fifo_arbiter_reg
226 GENERIC MAP (
227 data_size => nb_data_by_buffer_size,
228 data_nb => 4)
229 PORT MAP (
230 clk => clk,
231 rstn => rstn,
232 run => run,
233 max_count => nb_data_by_buffer,
234 enable => count_enable,
235 sel => sel,
236 data => count,
237 data_s => count_s);
214 238
215 reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s
216 reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s
217 reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s
218 reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s
239 reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
240 GENERIC MAP (
241 data_size => 2,
242 data_nb => 4)
243 PORT MAP (
244 clk => clk,
245 rstn => rstn,
246 run => run,
247 max_count => "10", -- 2
248 enable => shift_data_enable,
249 sel => sel,
250 data => shift_data,
251 data_s => shift_data_s);
219 252
220 -- COUNT_DATA ---------------------------------------------------------------
221 count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE
222 reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE
223 reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE
224 reg_count_data(3);
225
226 count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0;
227 253
228 reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s
229 reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s
230 reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s
231 reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s
232 -----------------------------------------------------------------------------
254 reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
255 GENERIC MAP (
256 data_size => 2,
257 data_nb => 4)
258 PORT MAP (
259 clk => clk,
260 rstn => rstn,
261 run => run,
262 max_count => "10", -- 2
263 enable => shift_time_enable,
264 sel => sel,
265 data => shift_time,
266 data_s => shift_time_s);
267
268
233 269
234 PROCESS (clk, rstn)
235 BEGIN -- PROCESS
236 IF rstn = '0' THEN -- asynchronous reset (active low)
237 reg_shift_time_pre <= 0;
238 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
239 reg_shift_time_pre <= shift_time_pre;
240 END IF;
241 END PROCESS ;
242
270
243 271 END ARCHITECTURE;
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@@ -1,237 +1,255
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress IS
40
41 GENERIC (
42 nb_data_by_buffer_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
52 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 -------------------------------------------------------------------------
57 -- CTRL
58 -------------------------------------------------------------------------
59 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
61 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
62
63 -------------------------------------------------------------------------
64 -- STATUS
65 -------------------------------------------------------------------------
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69
70 -------------------------------------------------------------------------
71 -- ADDR DATA OUT
72 -------------------------------------------------------------------------
73 data_f0_data_out_valid_burst : OUT STD_LOGIC;
74 data_f1_data_out_valid_burst : OUT STD_LOGIC;
75 data_f2_data_out_valid_burst : OUT STD_LOGIC;
76 data_f3_data_out_valid_burst : OUT STD_LOGIC;
77
78 data_f0_data_out_valid : OUT STD_LOGIC;
79 data_f1_data_out_valid : OUT STD_LOGIC;
80 data_f2_data_out_valid : OUT STD_LOGIC;
81 data_f3_data_out_valid : OUT STD_LOGIC;
82
83 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
87
88 );
89
90 END lpp_waveform_genaddress;
91
92 ARCHITECTURE beh OF lpp_waveform_genaddress IS
93 -----------------------------------------------------------------------------
94 -- Valid gen
95 -----------------------------------------------------------------------------
96 SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0);
99
100 -----------------------------------------------------------------------------
101 -- Register
102 -----------------------------------------------------------------------------
103 SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0);
104 SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0);
105 SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0);
106 SIGNAL data_addr_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
107 SIGNAL data_addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
108 SIGNAL data_addr_base : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
109
110 -----------------------------------------------------------------------------
111 --
112 -----------------------------------------------------------------------------
113 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
114
115 TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0);
117 SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0);
118
119 BEGIN -- beh
120
121 -----------------------------------------------------------------------------
122 -- valid gen
123 -----------------------------------------------------------------------------
124 data_f0_data_out_valid <= data_out_valid(0);
125 data_f1_data_out_valid <= data_out_valid(1);
126 data_f2_data_out_valid <= data_out_valid(2);
127 data_f3_data_out_valid <= data_out_valid(3);
128
129 data_f0_data_out_valid_burst <= data_out_valid_burst(0);
130 data_f1_data_out_valid_burst <= data_out_valid_burst(1);
131 data_f2_data_out_valid_burst <= data_out_valid_burst(2);
132 data_f3_data_out_valid_burst <= data_out_valid_burst(3);
133
134
135 all_bit_data_valid_out: FOR I IN 3 DOWNTO 0 GENERATE
136 addr_burst_avail(I) <= '1' WHEN data_addr_v_pre(I,2) = '0' AND
137 data_addr_v_pre(I,3) = '0' AND
138 data_addr_v_pre(I,4) = '0' AND
139 data_addr_v_pre(I,5) = '0' ELSE '0';
140
141 data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
142 '0' WHEN empty(I) = '1' ELSE
143 '0' WHEN addr_burst_avail(I) = '1' ELSE
144 '0' WHEN (run = '0') ELSE
145 '1';
146
147 data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
148 '0' WHEN empty(I) = '1' ELSE
149 '0' WHEN addr_burst_avail(I) = '0' ELSE
150 '0' WHEN empty_almost(I) = '1' ELSE
151 '0' WHEN (run = '0') ELSE
152 '1';
153 END GENERATE all_bit_data_valid_out;
154
155 -----------------------------------------------------------------------------
156 -- Register
157 -----------------------------------------------------------------------------
158 all_data_bit: FOR J IN 31 DOWNTO 0 GENERATE
159 all_data_addr: FOR I IN 3 DOWNTO 0 GENERATE
160 PROCESS (clk, rstn)
161 BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
163 data_addr_v_reg(I,J) <= '0';
164 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
165 IF run = '1' AND status_full_ack(I) = '0' THEN
166 data_addr_v_reg(I,J) <= data_addr_v_pre(I,J);
167 ELSE
168 data_addr_v_reg(I,J) <= data_addr_v_base(I,J);
169 END IF;
170 END IF;
171 END PROCESS;
172
173 data_addr_v_pre(I,J) <= data_addr_v_reg(I,J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J);
174
175 END GENERATE all_data_addr;
176
177 data_addr_reg(J) <= data_addr_v_reg(0,J) WHEN data_ren(0) = '1' ELSE
178 data_addr_v_reg(1,J) WHEN data_ren(1) = '1' ELSE
179 data_addr_v_reg(2,J) WHEN data_ren(2) = '1' ELSE
180 data_addr_v_reg(3,J);
181
182 data_addr_v_base(0,J) <= addr_data_f0(J);
183 data_addr_v_base(1,J) <= addr_data_f1(J);
184 data_addr_v_base(2,J) <= addr_data_f2(J);
185 data_addr_v_base(3,J) <= addr_data_f3(J);
186
187 data_f0_addr_out(J) <= data_addr_v_reg(0,J);
188 data_f1_addr_out(J) <= data_addr_v_reg(1,J);
189 data_f2_addr_out(J) <= data_addr_v_reg(2,J);
190 data_f3_addr_out(J) <= data_addr_v_reg(3,J);
191
192 END GENERATE all_data_bit;
193
194
195
196
197 -----------------------------------------------------------------------------
198 -- ADDER
199 -----------------------------------------------------------------------------
200
201 data_addr_pre <= data_addr_reg + 1;
202
203 -----------------------------------------------------------------------------
204 -- FULL STATUS
205 -----------------------------------------------------------------------------
206 all_status: FOR I IN 3 DOWNTO 0 GENERATE
207 all_bit_addr: FOR J IN 31 DOWNTO 0 GENERATE
208 addr_v_p(I)(J) <= data_addr_v_pre(I,J);
209 addr_v_b(I)(J) <= data_addr_v_base(I,J);
210 END GENERATE all_bit_addr;
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 status_full_s(I) <= '0';
216 status_full_err(I) <= '0';
217 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
218 IF run = '1' AND status_full_ack(I) = '0' THEN
219 IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN
220 status_full_s(I) <= '1';
221 IF status_full_s(I) = '1' AND data_ren(I)= '1' THEN
222 status_full_err(I) <= '1';
223 END IF;
224 END IF;
225 ELSE
226 status_full_s(I) <= '0';
227 status_full_err(I) <= '0';
228 END IF;
229 END IF;
230 END PROCESS;
231
232 END GENERATE all_status;
233
234 status_full <= status_full_s;
235
236
237 END beh;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress IS
40
41 GENERIC (
42 nb_data_by_buffer_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
52 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 -------------------------------------------------------------------------
57 -- CTRL
58 -------------------------------------------------------------------------
59 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
61 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
62
63 -------------------------------------------------------------------------
64 -- STATUS
65 -------------------------------------------------------------------------
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69
70 -------------------------------------------------------------------------
71 -- ADDR DATA OUT
72 -------------------------------------------------------------------------
73 data_f0_data_out_valid_burst : OUT STD_LOGIC;
74 data_f1_data_out_valid_burst : OUT STD_LOGIC;
75 data_f2_data_out_valid_burst : OUT STD_LOGIC;
76 data_f3_data_out_valid_burst : OUT STD_LOGIC;
77
78 data_f0_data_out_valid : OUT STD_LOGIC;
79 data_f1_data_out_valid : OUT STD_LOGIC;
80 data_f2_data_out_valid : OUT STD_LOGIC;
81 data_f3_data_out_valid : OUT STD_LOGIC;
82
83 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
87
88 );
89
90 END lpp_waveform_genaddress;
91
92 ARCHITECTURE beh OF lpp_waveform_genaddress IS
93 SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
94 SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
95 SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
96 SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
97 -----------------------------------------------------------------------------
98 -- Valid gen
99 -----------------------------------------------------------------------------
100 SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
102 SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0);
103
104 -----------------------------------------------------------------------------
105 -- Register
106 -----------------------------------------------------------------------------
107 SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
108 SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
109 SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
110 SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
111 SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
112 SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
113
114 -----------------------------------------------------------------------------
115 --
116 -----------------------------------------------------------------------------
117 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
118
119 TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0);
120 SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0);
121 SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0);
122
123 SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0);
124
125 BEGIN -- beh
126
127 -----------------------------------------------------------------------------
128 -- valid gen
129 -----------------------------------------------------------------------------
130 data_f0_data_out_valid <= data_out_valid(0);
131 data_f1_data_out_valid <= data_out_valid(1);
132 data_f2_data_out_valid <= data_out_valid(2);
133 data_f3_data_out_valid <= data_out_valid(3);
134
135 data_f0_data_out_valid_burst <= data_out_valid_burst(0);
136 data_f1_data_out_valid_burst <= data_out_valid_burst(1);
137 data_f2_data_out_valid_burst <= data_out_valid_burst(2);
138 data_f3_data_out_valid_burst <= data_out_valid_burst(3);
139
140
141
142 all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE
143 addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I));
144
145 addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000")
146 AND (UNSIGNED(addr_avail(I)) > 15)
147 ELSE '0';
148
149 data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
150 '0' WHEN empty(I) = '1' ELSE
151 '0' WHEN addr_burst_avail(I) = '1' ELSE
152 '0' WHEN (run = '0') ELSE
153 '1';
154
155 data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
156 '0' WHEN empty(I) = '1' ELSE
157 '0' WHEN addr_burst_avail(I) = '0' ELSE
158 '0' WHEN empty_almost(I) = '1' ELSE
159 '0' WHEN (run = '0') ELSE
160 '1';
161 END GENERATE all_bit_data_valid_out;
162
163 -----------------------------------------------------------------------------
164 -- Register
165 -----------------------------------------------------------------------------
166 all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE
167 all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE
168 PROCESS (clk, rstn)
169 BEGIN -- PROCESS
170 IF rstn = '0' THEN -- asynchronous reset (active low)
171 data_addr_v_reg(I, J) <= '0';
172 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
173 IF run = '1' AND status_full_ack(I) = '0' THEN
174 data_addr_v_reg(I, J) <= data_addr_v_pre(I, J);
175 ELSE
176 data_addr_v_reg(I, J) <= data_addr_v_base(I, J);
177 END IF;
178 END IF;
179 END PROCESS;
180
181 data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J);
182
183 END GENERATE all_data_addr;
184
185 data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE
186 data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE
187 data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE
188 data_addr_v_reg(3, J);
189
190 data_addr_v_base(0, J) <= addr_data_f0_s(J);
191 data_addr_v_base(1, J) <= addr_data_f1_s(J);
192 data_addr_v_base(2, J) <= addr_data_f2_s(J);
193 data_addr_v_base(3, J) <= addr_data_f3_s(J);
194
195 data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ;
196 data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ;
197 data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ;
198 data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ;
199
200 END GENERATE all_data_bit;
201
202 addr_data_f0_s <= addr_data_f0(31 DOWNTO 2);
203 addr_data_f1_s <= addr_data_f1(31 DOWNTO 2);
204 addr_data_f2_s <= addr_data_f2(31 DOWNTO 2);
205 addr_data_f3_s <= addr_data_f3(31 DOWNTO 2);
206
207 data_f0_addr_out(1 DOWNTO 0) <= "00";
208 data_f1_addr_out(1 DOWNTO 0) <= "00";
209 data_f2_addr_out(1 DOWNTO 0) <= "00";
210 data_f3_addr_out(1 DOWNTO 0) <= "00";
211
212
213
214
215 -----------------------------------------------------------------------------
216 -- ADDER
217 -----------------------------------------------------------------------------
218
219 data_addr_pre <= data_addr_reg + 1;
220
221 -----------------------------------------------------------------------------
222 -- FULL STATUS
223 -----------------------------------------------------------------------------
224 all_status : FOR I IN 3 DOWNTO 0 GENERATE
225 all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE
226 addr_v_p(I)(J) <= data_addr_v_pre(I, J);
227 addr_v_b(I)(J) <= data_addr_v_base(I, J);
228 END GENERATE all_bit_addr;
229
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 status_full_s(I) <= '0';
234 status_full_err(I) <= '0';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 IF run = '1' AND status_full_ack(I) = '0' THEN
237 IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN
238 status_full_s(I) <= '1';
239 IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN
240 status_full_err(I) <= '1';
241 END IF;
242 END IF;
243 ELSE
244 status_full_s(I) <= '0';
245 status_full_err(I) <= '0';
246 END IF;
247 END IF;
248 END PROCESS;
249
250 END GENERATE all_status;
251
252 status_full <= status_full_s;
253
254
255 END beh;
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@@ -1,277 +1,333
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 USE GRLIB.DMA2AHB_Package.ALL;
31 31
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34
35 35 PACKAGE lpp_waveform_pkg IS
36 36
37 37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38 38
39 39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>) OF STD_LOGIC;
40 40
41 41 -----------------------------------------------------------------------------
42 42 -- SNAPSHOT
43 43 -----------------------------------------------------------------------------
44 44
45 45 COMPONENT lpp_waveform_snapshot
46 46 GENERIC (
47 47 data_size : INTEGER;
48 48 nb_snapshot_param_size : INTEGER);
49 49 PORT (
50 50 clk : IN STD_LOGIC;
51 51 rstn : IN STD_LOGIC;
52 52 run : IN STD_LOGIC;
53 53 enable : IN STD_LOGIC;
54 54 burst_enable : IN STD_LOGIC;
55 55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 56 start_snapshot : IN STD_LOGIC;
57 57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 58 data_in_valid : IN STD_LOGIC;
59 59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 60 data_out_valid : OUT STD_LOGIC);
61 61 END COMPONENT;
62 62
63 63 COMPONENT lpp_waveform_burst
64 64 GENERIC (
65 65 data_size : INTEGER);
66 66 PORT (
67 67 clk : IN STD_LOGIC;
68 68 rstn : IN STD_LOGIC;
69 69 run : IN STD_LOGIC;
70 70 enable : IN STD_LOGIC;
71 71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 72 data_in_valid : IN STD_LOGIC;
73 73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 74 data_out_valid : OUT STD_LOGIC);
75 75 END COMPONENT;
76 76
77 77 COMPONENT lpp_waveform_snapshot_controler
78 78 GENERIC (
79 79 delta_vector_size : INTEGER;
80 80 delta_vector_size_f0_2 : INTEGER);
81 81 PORT (
82 82 clk : IN STD_LOGIC;
83 83 rstn : IN STD_LOGIC;
84 84 reg_run : IN STD_LOGIC;
85 85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 92 data_f0_valid : IN STD_LOGIC;
93 93 data_f2_valid : IN STD_LOGIC;
94 94 start_snapshot_f0 : OUT STD_LOGIC;
95 95 start_snapshot_f1 : OUT STD_LOGIC;
96 96 start_snapshot_f2 : OUT STD_LOGIC;
97 97 wfp_on : OUT STD_LOGIC);
98 98 END COMPONENT;
99 99
100 100 -----------------------------------------------------------------------------
101 101 --
102 102 -----------------------------------------------------------------------------
103 103 COMPONENT lpp_waveform
104 104 GENERIC (
105 105 tech : INTEGER;
106 106 data_size : INTEGER;
107 107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
108 109 nb_snapshot_param_size : INTEGER;
109 110 delta_vector_size : INTEGER;
110 111 delta_vector_size_f0_2 : INTEGER);
111 112 PORT (
112 113 clk : IN STD_LOGIC;
113 114 rstn : IN STD_LOGIC;
114 115 reg_run : IN STD_LOGIC;
115 116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
116 117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 122 enable_f0 : IN STD_LOGIC;
122 123 enable_f1 : IN STD_LOGIC;
123 124 enable_f2 : IN STD_LOGIC;
124 125 enable_f3 : IN STD_LOGIC;
125 126 burst_f0 : IN STD_LOGIC;
126 127 burst_f1 : IN STD_LOGIC;
127 128 burst_f2 : IN STD_LOGIC;
128 129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
130 132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
131 133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
132 134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
136 138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 139 data_f0_in_valid : IN STD_LOGIC;
138 140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 142 data_f1_in_valid : IN STD_LOGIC;
141 143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
143 145 data_f2_in_valid : IN STD_LOGIC;
144 146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 148 data_f3_in_valid : IN STD_LOGIC;
147 149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
148 150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 152 data_f0_data_out_valid : OUT STD_LOGIC;
151 153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
152 154 data_f0_data_out_ren : IN STD_LOGIC;
153 155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
154 156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 157 data_f1_data_out_valid : OUT STD_LOGIC;
156 158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
157 159 data_f1_data_out_ren : IN STD_LOGIC;
158 160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 162 data_f2_data_out_valid : OUT STD_LOGIC;
161 163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
162 164 data_f2_data_out_ren : IN STD_LOGIC;
163 165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 167 data_f3_data_out_valid : OUT STD_LOGIC;
166 168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
167 169 data_f3_data_out_ren : IN STD_LOGIC);
168 170 END COMPONENT;
169 171
170 172 COMPONENT lpp_waveform_dma_genvalid
171 173 PORT (
172 174 HCLK : IN STD_LOGIC;
173 175 HRESETn : IN STD_LOGIC;
174 176 run : IN STD_LOGIC;
175 177 valid_in : IN STD_LOGIC;
176 178 ack_in : IN STD_LOGIC;
177 179 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
178 180 valid_out : OUT STD_LOGIC;
179 181 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
180 182 error : OUT STD_LOGIC);
181 183 END COMPONENT;
182 184
183 185 -----------------------------------------------------------------------------
184 186 -- FIFO
185 187 -----------------------------------------------------------------------------
186 188 COMPONENT lpp_waveform_fifo_ctrl
187 189 GENERIC (
188 190 offset : INTEGER;
189 191 length : INTEGER);
190 192 PORT (
191 193 clk : IN STD_LOGIC;
192 194 rstn : IN STD_LOGIC;
193 195 run : IN STD_LOGIC;
194 196 ren : IN STD_LOGIC;
195 197 wen : IN STD_LOGIC;
196 198 mem_re : OUT STD_LOGIC;
197 199 mem_we : OUT STD_LOGIC;
198 200 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
199 201 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
200 202 empty_almost : OUT STD_LOGIC;
201 203 empty : OUT STD_LOGIC;
202 204 full_almost : OUT STD_LOGIC;
203 205 full : OUT STD_LOGIC);
204 206 END COMPONENT;
205 207
206 208 COMPONENT lpp_waveform_fifo_arbiter
207 209 GENERIC (
208 210 tech : INTEGER;
209 211 nb_data_by_buffer_size : INTEGER);
210 212 PORT (
211 213 clk : IN STD_LOGIC;
212 214 rstn : IN STD_LOGIC;
213 215 run : IN STD_LOGIC;
214 216 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
215 217 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
216 218 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
217 219 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
218 220 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
219 221 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
220 222 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
221 223 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
222 224 END COMPONENT;
223 225
224 226 COMPONENT lpp_waveform_fifo
225 227 GENERIC (
226 228 tech : INTEGER);
227 229 PORT (
228 230 clk : IN STD_LOGIC;
229 231 rstn : IN STD_LOGIC;
230 232 run : IN STD_LOGIC;
231 233 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
232 234 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 235 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 236 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
235 237 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
236 238 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
237 239 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
238 240 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
239 241 END COMPONENT;
240 242
243 COMPONENT lpp_waveform_fifo_latencyCorrection
244 GENERIC (
245 tech : INTEGER);
246 PORT (
247 clk : IN STD_LOGIC;
248 rstn : IN STD_LOGIC;
249 run : IN STD_LOGIC;
250 empty_almost : OUT STD_LOGIC;
251 empty : OUT STD_LOGIC;
252 data_ren : IN STD_LOGIC;
253 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
254 empty_almost_fifo : IN STD_LOGIC;
255 empty_fifo : IN STD_LOGIC;
256 data_ren_fifo : OUT STD_LOGIC;
257 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
258 END COMPONENT;
259
260 COMPONENT lpp_waveform_fifo_withoutLatency
261 GENERIC (
262 tech : INTEGER);
263 PORT (
264 clk : IN STD_LOGIC;
265 rstn : IN STD_LOGIC;
266 run : IN STD_LOGIC;
267 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
268 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
269 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
270 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
271 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
272 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
273 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
274 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
275 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
276 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
277 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
278 END COMPONENT;
279
241 280 -----------------------------------------------------------------------------
242 281 -- GEN ADDRESS
243 282 -----------------------------------------------------------------------------
244 283 COMPONENT lpp_waveform_genaddress
245 284 GENERIC (
246 285 nb_data_by_buffer_size : INTEGER);
247 286 PORT (
248 287 clk : IN STD_LOGIC;
249 288 rstn : IN STD_LOGIC;
250 289 run : IN STD_LOGIC;
251 290 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
252 291 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
253 292 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
254 293 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
255 294 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
256 295 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
257 296 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
258 297 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 298 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
260 299 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
261 300 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 301 data_f0_data_out_valid_burst : OUT STD_LOGIC;
263 302 data_f1_data_out_valid_burst : OUT STD_LOGIC;
264 303 data_f2_data_out_valid_burst : OUT STD_LOGIC;
265 304 data_f3_data_out_valid_burst : OUT STD_LOGIC;
266 305 data_f0_data_out_valid : OUT STD_LOGIC;
267 306 data_f1_data_out_valid : OUT STD_LOGIC;
268 307 data_f2_data_out_valid : OUT STD_LOGIC;
269 308 data_f3_data_out_valid : OUT STD_LOGIC;
270 309 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
271 310 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
272 311 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
273 312 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
274 313 END COMPONENT;
275 314
315 -----------------------------------------------------------------------------
316 -- lpp_waveform_fifo_arbiter_reg
317 -----------------------------------------------------------------------------
318 COMPONENT lpp_waveform_fifo_arbiter_reg
319 GENERIC (
320 data_size : INTEGER;
321 data_nb : INTEGER);
322 PORT (
323 clk : IN STD_LOGIC;
324 rstn : IN STD_LOGIC;
325 run : IN STD_LOGIC;
326 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
327 enable : IN STD_LOGIC;
328 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
329 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
330 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
331 END COMPONENT;
276 332
277 333 END lpp_waveform_pkg;
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@@ -1,226 +1,226
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.general_purpose.ALL;
29 29
30 30 ENTITY lpp_waveform_snapshot_controler IS
31 31
32 32 GENERIC (
33 33 delta_vector_size : INTEGER := 20;
34 34 delta_vector_size_f0_2 : INTEGER := 3
35 35 );
36 36
37 37 PORT (
38 38 clk : IN STD_LOGIC;
39 39 rstn : IN STD_LOGIC;
40 40 ---------------------------------------------------------------------------
41 41 --REGISTER CONTROL
42 42 reg_run : IN STD_LOGIC;
43 43 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
44 44 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
45 45 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
46 46 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
47 47 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
48 48 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
49 49 ---------------------------------------------------------------------------
50 50 -- INPUT
51 51 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
52 52 data_f0_valid : IN STD_LOGIC;
53 53 data_f2_valid : IN STD_LOGIC;
54 54 ---------------------------------------------------------------------------
55 55 -- OUTPUT
56 56 start_snapshot_f0 : OUT STD_LOGIC;
57 57 start_snapshot_f1 : OUT STD_LOGIC;
58 58 start_snapshot_f2 : OUT STD_LOGIC;
59 59 wfp_on : OUT STD_LOGIC
60 60 );
61 61
62 62 END lpp_waveform_snapshot_controler;
63 63
64 64 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
65 65 -----------------------------------------------------------------------------
66 66 -- WAVEFORM ON/OFF FSM
67 67 SIGNAL state_on : STD_LOGIC;
68 68 SIGNAL wfp_on_s : STD_LOGIC;
69 69 -----------------------------------------------------------------------------
70 70 -- StartSnapshot Generator for f2, f1 and f0_pre
71 71 SIGNAL start_snapshot_f0_pre : STD_LOGIC;
72 72 -- SIGNAL first_decount_s : STD_LOGIC;
73 73 SIGNAL first_decount : STD_LOGIC;
74 74 SIGNAL first_init : STD_LOGIC;
75 75 SIGNAL counter_delta_snapshot : INTEGER;
76 76 -----------------------------------------------------------------------------
77 77 -- StartSnapshot Generator for f0
78 78 SIGNAL counter_delta_f0 : INTEGER;
79 79 SIGNAL send_start_snapshot_f0 : STD_LOGIC;
80 80 BEGIN -- beh
81 81 wfp_on <= wfp_on_s;
82 82
83 83 -----------------------------------------------------------------------------
84 84 -- WAVEFORM ON/OFF FSM
85 85 -----------------------------------------------------------------------------
86 86 -- INPUT reg_run
87 87 -- coarse_time
88 88 -- reg_start_date
89 89 -- OUTPUT wfp_on_s
90 90 -----------------------------------------------------------------------------
91 91 waveform_on_off_fsm : PROCESS (clk, rstn)
92 92 BEGIN
93 93 IF rstn = '0' THEN
94 94 state_on <= '0';
95 95 ELSIF clk'EVENT AND clk = '1' THEN
96 96 IF state_on = '1' THEN -- Waveform Picker ON
97 97 state_on <= reg_run;
98 98 ELSE -- Waveform Picker OFF
99 99 IF coarse_time = reg_start_date THEN
100 100 state_on <= reg_run;
101 101 END IF;
102 102 END IF;
103 103 END IF;
104 104 END PROCESS waveform_on_off_fsm;
105 105 wfp_on_s <= state_on;
106 106 -----------------------------------------------------------------------------
107 107
108 108 -----------------------------------------------------------------------------
109 109 -- StartSnapshot Generator for f2, f1 and f0_pre
110 110 -----------------------------------------------------------------------------
111 111 -- INPUT wfp_on_s
112 112 -- reg_delta_snapshot
113 113 -- reg_delta_f0
114 114 -- reg_delta_f1
115 115 -- reg_delta_f2
116 116 -- data_f2_valid
117 117 -- OUTPUT start_snapshot_f0_pre
118 118 -- start_snapshot_f1
119 119 -- start_snapshot_f2
120 120 -----------------------------------------------------------------------------
121 121 --lpp_front_positive_detection_1 : lpp_front_positive_detection
122 122 -- PORT MAP (
123 123 -- clk => clk,
124 124 -- rstn => rstn,
125 125 -- sin => wfp_on_s,
126 126 -- sout => first_decount_s);
127 127
128 128 Decounter_Cyclic_DeltaSnapshot : PROCESS (clk, rstn)
129 129 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
130 130 IF rstn = '0' THEN -- asynchronous reset (active low)
131 131 counter_delta_snapshot <= 0;
132 first_decount <= '0';
133 first_init <= '0';
132 first_decount <= '1';
133 first_init <= '1';
134 134 start_snapshot_f0_pre <= '0';
135 135 start_snapshot_f1 <= '0';
136 136 start_snapshot_f2 <= '0';
137 137 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
138 138 IF wfp_on_s = '0' THEN
139 139 counter_delta_snapshot <= 0;
140 140 first_decount <= '1';
141 141 first_init <= '1';
142 142 start_snapshot_f0_pre <= '0';
143 143 start_snapshot_f1 <= '0';
144 144 start_snapshot_f2 <= '0';
145 145 ELSE
146 146 start_snapshot_f0_pre <= '0';
147 147 start_snapshot_f1 <= '0';
148 148 start_snapshot_f2 <= '0';
149 149
150 150 IF data_f2_valid = '1' THEN
151 151 IF first_init = '1' THEN
152 152 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_f2));
153 153 first_init <= '0';
154 154 ELSE
155 155 IF counter_delta_snapshot > 0 THEN
156 156 counter_delta_snapshot <= counter_delta_snapshot - 1;
157 157 ELSE
158 158 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_snapshot));
159 159 first_decount <= '0';
160 160 END IF;
161 161
162 162 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f0)) THEN
163 163 IF first_decount = '0' THEN
164 164 start_snapshot_f0_pre <= '1';
165 165 END IF;
166 166 END IF;
167 167
168 168 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f1)) THEN
169 169 IF first_decount = '0' THEN
170 170 start_snapshot_f1 <= '1';
171 171 END IF;
172 172 END IF;
173 173
174 174 IF counter_delta_snapshot = 0 THEN
175 175 start_snapshot_f2 <= '1';
176 176 END IF;
177 177 END IF;
178 178 END IF;
179 179 END IF;
180 180 END IF;
181 181 END PROCESS Decounter_Cyclic_DeltaSnapshot;
182 182 -----------------------------------------------------------------------------
183 183
184 184
185 185 -----------------------------------------------------------------------------
186 186 -- StartSnapshot Generator for f0
187 187 -----------------------------------------------------------------------------
188 188 -- INPUT wfp_on_s
189 189 -- start_snapshot_f0_pre
190 190 -- reg_delta_snapshot
191 191 -- reg_delta_f0_2
192 192 -- data_f0_valid
193 193 -- OUTPUT start_snapshot_f0
194 194 -----------------------------------------------------------------------------
195 195 Decounter_DeltaSnapshot_f0 : PROCESS (clk, rstn)
196 196 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
197 197 IF rstn = '0' THEN -- asynchronous reset (active low)
198 198 counter_delta_f0 <= 0;
199 199 start_snapshot_f0 <= '0';
200 200 send_start_snapshot_f0 <= '0';
201 201 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 202 start_snapshot_f0 <= '0';
203 203 IF wfp_on_s = '0' THEN
204 204 counter_delta_f0 <= 0;
205 205 send_start_snapshot_f0 <= '1';
206 206 ELSE
207 207 IF start_snapshot_f0_pre = '1' THEN
208 208 send_start_snapshot_f0 <= '0';
209 209 counter_delta_f0 <= to_integer(UNSIGNED(reg_delta_f0_2));
210 210 ELSIF data_f0_valid = '1' THEN
211 211 IF counter_delta_f0 > 0 THEN
212 212 send_start_snapshot_f0 <= '0';
213 213 counter_delta_f0 <= counter_delta_f0 - 1;
214 214 ELSE
215 215 IF send_start_snapshot_f0 = '0' THEN
216 216 send_start_snapshot_f0 <= '1';
217 217 start_snapshot_f0 <= '1';
218 218 END IF;
219 219 END IF;
220 220 END IF;
221 221 END IF;
222 222 END IF;
223 223 END PROCESS Decounter_DeltaSnapshot_f0;
224 224 -----------------------------------------------------------------------------
225 225
226 226 END beh;
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@@ -1,10 +1,13
1 1 lpp_waveform_pkg.vhd
2 2 lpp_waveform.vhd
3 3 lpp_waveform_burst.vhd
4 lpp_waveform_fifo_withoutLatency.vhd
5 lpp_waveform_fifo_latencyCorrection.vhd
4 6 lpp_waveform_fifo.vhd
5 7 lpp_waveform_fifo_arbiter.vhd
6 8 lpp_waveform_fifo_ctrl.vhd
7 9 lpp_waveform_snapshot.vhd
8 10 lpp_waveform_snapshot_controler.vhd
9 11 lpp_waveform_genaddress.vhd
10 12 lpp_waveform_dma_genvalid.vhd
13 lpp_waveform_fifo_arbiter_reg.vhd
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