diff --git a/designs/LFR-em-WaveFormPicker/.config b/designs/LFR-em-WaveFormPicker/.config new file mode 100644 --- /dev/null +++ b/designs/LFR-em-WaveFormPicker/.config @@ -0,0 +1,288 @@ +# +# Automatically generated make config: don't edit +# + +# +# Synthesis +# +# CONFIG_SYN_INFERRED is not set +# CONFIG_SYN_STRATIX is not set +# CONFIG_SYN_STRATIXII is not set +# CONFIG_SYN_STRATIXIII is not set +# CONFIG_SYN_CYCLONEIII is not set +# CONFIG_SYN_ALTERA is not set +# CONFIG_SYN_AXCEL is not set +# CONFIG_SYN_PROASIC is not set +# CONFIG_SYN_PROASICPLUS is not set +CONFIG_SYN_PROASIC3=y +# CONFIG_SYN_UT025CRH is not set +# CONFIG_SYN_ATC18 is not set +# CONFIG_SYN_ATC18RHA is not set +# CONFIG_SYN_CUSTOM1 is not set +# CONFIG_SYN_EASIC90 is not set +# CONFIG_SYN_IHP25 is not set +# CONFIG_SYN_IHP25RH is not set +# CONFIG_SYN_LATTICE is not set +# CONFIG_SYN_ECLIPSE is not set +# CONFIG_SYN_PEREGRINE is not set +# CONFIG_SYN_RH_LIB18T is not set +# CONFIG_SYN_RHUMC is not set +# CONFIG_SYN_SMIC13 is not set +# CONFIG_SYN_SPARTAN2 is not set +# CONFIG_SYN_SPARTAN3 is not set +# CONFIG_SYN_SPARTAN3E is not set +# CONFIG_SYN_VIRTEX is not set +# CONFIG_SYN_VIRTEXE is not set +# CONFIG_SYN_VIRTEX2 is not set +# CONFIG_SYN_VIRTEX4 is not set +# CONFIG_SYN_VIRTEX5 is not set +# CONFIG_SYN_UMC is not set +# CONFIG_SYN_TSMC90 is not set +# CONFIG_SYN_INFER_RAM is not set +# CONFIG_SYN_INFER_PADS is not set +# CONFIG_SYN_NO_ASYNC is not set +# CONFIG_SYN_SCAN is not set + +# +# Clock generation +# +# CONFIG_CLK_INFERRED is not set +# CONFIG_CLK_HCLKBUF is not set +# CONFIG_CLK_ALTDLL is not set +# CONFIG_CLK_LATDLL is not set +CONFIG_CLK_PRO3PLL=y +# CONFIG_CLK_LIB18T is not set +# CONFIG_CLK_RHUMC is not set +# CONFIG_CLK_CLKDLL is not set +# CONFIG_CLK_DCM is not set +CONFIG_CLK_MUL=2 +CONFIG_CLK_DIV=8 +CONFIG_OCLK_DIV=2 +# CONFIG_PCI_SYSCLK is not set +CONFIG_LEON3=y +CONFIG_PROC_NUM=1 + +# +# Processor +# + +# +# Integer unit +# +CONFIG_IU_NWINDOWS=8 +# CONFIG_IU_V8MULDIV is not set +# CONFIG_IU_SVT is not set +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=0 +# CONFIG_PWD is not set +CONFIG_IU_RSTADDR=00000 + +# +# Floating-point unit +# +# CONFIG_FPU_ENABLE is not set + +# +# Cache system +# +CONFIG_ICACHE_ENABLE=y +CONFIG_ICACHE_ASSO1=y +# CONFIG_ICACHE_ASSO2 is not set +# CONFIG_ICACHE_ASSO3 is not set +# CONFIG_ICACHE_ASSO4 is not set +# CONFIG_ICACHE_SZ1 is not set +# CONFIG_ICACHE_SZ2 is not set +CONFIG_ICACHE_SZ4=y +# CONFIG_ICACHE_SZ8 is not set +# CONFIG_ICACHE_SZ16 is not set +# CONFIG_ICACHE_SZ32 is not set +# CONFIG_ICACHE_SZ64 is not set +# CONFIG_ICACHE_SZ128 is not set +# CONFIG_ICACHE_SZ256 is not set +# CONFIG_ICACHE_LZ16 is not set +CONFIG_ICACHE_LZ32=y +CONFIG_DCACHE_ENABLE=y +CONFIG_DCACHE_ASSO1=y +# CONFIG_DCACHE_ASSO2 is not set +# CONFIG_DCACHE_ASSO3 is not set +# CONFIG_DCACHE_ASSO4 is not set +# CONFIG_DCACHE_SZ1 is not set +# CONFIG_DCACHE_SZ2 is not set +CONFIG_DCACHE_SZ4=y +# CONFIG_DCACHE_SZ8 is not set +# CONFIG_DCACHE_SZ16 is not set +# CONFIG_DCACHE_SZ32 is not set +# CONFIG_DCACHE_SZ64 is not set +# CONFIG_DCACHE_SZ128 is not set +# CONFIG_DCACHE_SZ256 is not set +# CONFIG_DCACHE_LZ16 is not set +CONFIG_DCACHE_LZ32=y +# CONFIG_DCACHE_SNOOP is not set +CONFIG_CACHE_FIXED=0 + +# +# MMU +# +CONFIG_MMU_ENABLE=y +# CONFIG_MMU_COMBINED is not set +CONFIG_MMU_SPLIT=y +# CONFIG_MMU_REPARRAY is not set +CONFIG_MMU_REPINCREMENT=y +# CONFIG_MMU_I2 is not set +# CONFIG_MMU_I4 is not set +CONFIG_MMU_I8=y +# CONFIG_MMU_I16 is not set +# CONFIG_MMU_I32 is not set +# CONFIG_MMU_D2 is not set +# CONFIG_MMU_D4 is not set +CONFIG_MMU_D8=y +# CONFIG_MMU_D16 is not set +# CONFIG_MMU_D32 is not set +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +# CONFIG_MMU_PAGE_8K is not set +# CONFIG_MMU_PAGE_16K is not set +# CONFIG_MMU_PAGE_32K is not set +# CONFIG_MMU_PAGE_PROG is not set + +# +# Debug Support Unit +# +# CONFIG_DSU_ENABLE is not set + +# +# Fault-tolerance +# + +# +# VHDL debug settings +# +# CONFIG_IU_DISAS is not set +# CONFIG_DEBUG_PC32 is not set + +# +# AMBA configuration +# +CONFIG_AHB_DEFMST=0 +CONFIG_AHB_RROBIN=y +# CONFIG_AHB_SPLIT is not set +CONFIG_AHB_IOADDR=FFF +CONFIG_APB_HADDR=800 +# CONFIG_AHB_MON is not set + +# +# Debug Link +# +CONFIG_DSU_UART=y +# CONFIG_DSU_JTAG is not set + +# +# Peripherals +# + +# +# Memory controllers +# + +# +# 8/32-bit PROM/SRAM controller +# +CONFIG_SRCTRL=y +# CONFIG_SRCTRL_8BIT is not set +CONFIG_SRCTRL_PROMWS=3 +CONFIG_SRCTRL_RAMWS=0 +CONFIG_SRCTRL_IOWS=0 +# CONFIG_SRCTRL_RMW is not set +CONFIG_SRCTRL_SRBANKS1=y +# CONFIG_SRCTRL_SRBANKS2 is not set +# CONFIG_SRCTRL_SRBANKS3 is not set +# CONFIG_SRCTRL_SRBANKS4 is not set +# CONFIG_SRCTRL_SRBANKS5 is not set +# CONFIG_SRCTRL_BANKSZ0 is not set +# CONFIG_SRCTRL_BANKSZ1 is not set +# CONFIG_SRCTRL_BANKSZ2 is not set +# CONFIG_SRCTRL_BANKSZ3 is not set +# CONFIG_SRCTRL_BANKSZ4 is not set +# CONFIG_SRCTRL_BANKSZ5 is not set +# CONFIG_SRCTRL_BANKSZ6 is not set +# CONFIG_SRCTRL_BANKSZ7 is not set +# CONFIG_SRCTRL_BANKSZ8 is not set +# CONFIG_SRCTRL_BANKSZ9 is not set +# CONFIG_SRCTRL_BANKSZ10 is not set +# CONFIG_SRCTRL_BANKSZ11 is not set +# CONFIG_SRCTRL_BANKSZ12 is not set +# CONFIG_SRCTRL_BANKSZ13 is not set +CONFIG_SRCTRL_ROMASEL=19 + +# +# Leon2 memory controller +# +CONFIG_MCTRL_LEON2=y +# CONFIG_MCTRL_8BIT is not set +# CONFIG_MCTRL_16BIT is not set +# CONFIG_MCTRL_5CS is not set +# CONFIG_MCTRL_SDRAM is not set + +# +# PC133 SDRAM controller +# +# CONFIG_SDCTRL is not set + +# +# On-chip RAM/ROM +# +# CONFIG_AHBROM_ENABLE is not set +# CONFIG_AHBRAM_ENABLE is not set + +# +# Ethernet +# +# CONFIG_GRETH_ENABLE is not set + +# +# CAN +# +# CONFIG_CAN_ENABLE is not set + +# +# PCI +# +# CONFIG_PCI_SIMPLE_TARGET is not set +# CONFIG_PCI_MASTER_TARGET is not set +# CONFIG_PCI_ARBITER is not set +# CONFIG_PCI_TRACE is not set + +# +# Spacewire +# +# CONFIG_SPW_ENABLE is not set + +# +# UARTs, timers and irq control +# +CONFIG_UART1_ENABLE=y +# CONFIG_UA1_FIFO1 is not set +# CONFIG_UA1_FIFO2 is not set +CONFIG_UA1_FIFO4=y +# CONFIG_UA1_FIFO8 is not set +# CONFIG_UA1_FIFO16 is not set +# CONFIG_UA1_FIFO32 is not set +# CONFIG_UART2_ENABLE is not set +CONFIG_IRQ3_ENABLE=y +# CONFIG_IRQ3_SEC is not set +CONFIG_GPT_ENABLE=y +CONFIG_GPT_NTIM=2 +CONFIG_GPT_SW=8 +CONFIG_GPT_TW=32 +CONFIG_GPT_IRQ=8 +CONFIG_GPT_SEPIRQ=y +CONFIG_GPT_WDOGEN=y +CONFIG_GPT_WDOG=FFFF +CONFIG_GRGPIO_ENABLE=y +CONFIG_GRGPIO_WIDTH=8 +CONFIG_GRGPIO_IMASK=0000 + +# +# VHDL Debugging +# +# CONFIG_DEBUG_UART is not set diff --git a/designs/LFR-em-WaveFormPicker/Makefile b/designs/LFR-em-WaveFormPicker/Makefile new file mode 100644 --- /dev/null +++ b/designs/LFR-em-WaveFormPicker/Makefile @@ -0,0 +1,50 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES=config.vhd leon3mp.vhd +#VHDLSIMFILES=testbench.vhd +#SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/LFR-em-WaveFormPicker/config.vhd b/designs/LFR-em-WaveFormPicker/config.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR-em-WaveFormPicker/config.vhd @@ -0,0 +1,182 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is + + +-- Technology and synthesis options + constant CFG_FABTECH : integer := apa3e; + constant CFG_MEMTECH : integer := apa3e; + constant CFG_PADTECH : integer := inferred; + constant CFG_NOASYNC : integer := 0; + constant CFG_SCAN : integer := 0; + +-- Clock generator + constant CFG_CLKTECH : integer := inferred; + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; + +-- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := (1); + --constant CFG_NWIN : integer := (7); -- PLE + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist + --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE + constant CFG_GRFPUSH : integer := 0; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DFIXED : integer := 16#00F3#; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + constant CFG_DSU : integer := 1; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + constant CFG_LEON3FT_EN : integer := 0; + constant CFG_IUFT_EN : integer := 0; + constant CFG_FPUFT_EN : integer := 0; + constant CFG_RF_ERRINJ : integer := 0; + constant CFG_CACHE_FT_EN : integer := 0; + constant CFG_CACHE_ERRINJ : integer := 0; + constant CFG_LEON3_NETLIST: integer := 0; + constant CFG_DISAS : integer := 0 + 0; + constant CFG_PCLOW : integer := 2; + +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + +-- DSU UART + constant CFG_AHB_UART : integer := 1; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 0; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := 0 + 0; + constant CFG_ETH_BUF : integer := 1; + constant CFG_ETH_IPM : integer := 16#C0A8#; + constant CFG_ETH_IPL : integer := 16#0033#; + constant CFG_ETH_ENM : integer := 16#00007A#; + constant CFG_ETH_ENL : integer := 16#CC0001#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM16BIT : integer := 0; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; + +-- SSRAM controller + constant CFG_SSCTRL : integer := 0; + constant CFG_SSCTRLP16 : integer := 0; + +-- AHB ROM + constant CFG_AHBROMEN : integer := 0; + constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBRODDR : integer := 16#000#; + constant CFG_ROMADDR : integer := 16#000#; + constant CFG_ROMMASK : integer := 16#E00# + 16#000#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := 0; + constant CFG_AHBRSZ : integer := 1; + constant CFG_AHBRADDR : integer := 16#A00#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + constant CFG_GRETH1G : integer := 0; + constant CFG_ETH_FIFO : integer := 8; + +-- CAN 2.0 interface + constant CFG_CAN : integer := 0; + constant CFG_CANIO : integer := 16#0#; + constant CFG_CANIRQ : integer := 0; + constant CFG_CANLOOP : integer := 0; + constant CFG_CAN_SYNCRST : integer := 0; + constant CFG_CANFT : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 1; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := 1; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := 1; + constant CFG_GPT_NTIM : integer := (3); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := 1; + constant CFG_GRGPIO_IMASK : integer := 16#0000#; + constant CFG_GRGPIO_WIDTH : integer := (7); + +-- GRLIB debugging + constant CFG_DUART : integer := 0; + + +end; diff --git a/designs/LFR-em-WaveFormPicker/leon3mp.vhd b/designs/LFR-em-WaveFormPicker/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/designs/LFR-em-WaveFormPicker/leon3mp.vhd @@ -0,0 +1,524 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; + +ENTITY leon3mp IS + GENERIC ( + fabtech : INTEGER := CFG_FABTECH; + memtech : INTEGER := CFG_MEMTECH; + padtech : INTEGER := CFG_PADTECH; + clktech : INTEGER := CFG_CLKTECH; + disas : INTEGER := CFG_DISAS; -- Enable disassembly to console + dbguart : INTEGER := CFG_DUART; -- Print UART on console + pclow : INTEGER := CFG_PCLOW + ); + PORT ( + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- SPW -------------------------------------------------------------------- + spw1_din : IN STD_LOGIC; -- PLE + spw1_sin : IN STD_LOGIC; -- PLE + spw1_dout : OUT STD_LOGIC; -- PLE + spw1_sout : OUT STD_LOGIC; -- PLE + + spw2_din : IN STD_LOGIC; -- JCPE --TODO + spw2_sin : IN STD_LOGIC; -- JCPE --TODO + spw2_dout : OUT STD_LOGIC; -- JCPE --TODO + spw2_sout : OUT STD_LOGIC; -- JCPE --TODO + + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + + --------------------------------------------------------------------------- + led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF leon3mp IS + +--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ +-- CFG_GRETH+CFG_AHB_JTAG; + CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ + CFG_AHB_UART + +2; + -- 1 is for the SpaceWire module grspw, which is a master + -- 1 is for the LFR + + CONSTANT maxahbm : INTEGER := maxahbmsp; + +--Clk & Rst géné + SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL resetnl : STD_ULOGIC; + SIGNAL clk2x : STD_ULOGIC; + SIGNAL lclk2x : STD_ULOGIC; + SIGNAL lclk25MHz : STD_ULOGIC; + SIGNAL lclk50MHz : STD_ULOGIC; + SIGNAL lclk100MHz : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; +--- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); +--UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; +--MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + SIGNAL ramcs : STD_ULOGIC; +--IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); +--Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; +--DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- + CONSTANT IOAEN : INTEGER := CFG_CAN; + CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz + +-- time management signal + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; -- PLE + SIGNAL swno : grspw_out_type; -- PLE + SIGNAL clkmn : STD_ULOGIC; -- PLE + SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 + +-- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + + PROCESS(lclk100MHz) + BEGIN + IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN + lclk50MHz <= NOT lclk50MHz; + END IF; + END PROCESS; + + PROCESS(lclk50MHz) + BEGIN + IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN + lclk25MHz <= NOT lclk25MHz; + END IF; + END PROCESS; + + lclk2x <= lclk50MHz; + spw_clk <= lclk50MHz; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + led(2) <= dsuo.active; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + led(0) <= NOT ahbuarti.rxd; + led(1) <= NOT ahbuarto.txd; + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1: apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + pirq => 12) + PORT MAP ( + clk25MHz => clkm, + clk49_152MHz => clk49_152MHz, + resetn => rstn, + grspw_tick => swno.tickout, + apbi => apbi, + apbo => apbo(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sin, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sin, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => fabtech, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm + GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn, clkm, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbmi, ahbmo(1), apbi, apbo(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR +------------------------------------------------------------------------------- + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_RAM, + nb_data_by_buffer_size => 32, + nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 7, -- log2(96) + pindex => 15, + paddr => 15, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 2, + top_lfr_version => X"00000002") + PORT MAP ( + clk => clkm, + rstn => rstn, + sample_B => sample(2 DOWNTO 0), + sample_E => sample(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi, + apbo => apbo(15), + ahbi => ahbmi, + ahbo => ahbmo(2), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_sw); + + top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk49_152MHz, + cnv_rstn => rstn, + cnv => ADC_smpclk, + clk => clkm, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + +END Behavioral; diff --git a/lib/lpp/lfr_time_management/lfr_time_management.vhd b/lib/lpp/lfr_time_management/lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lfr_time_management.vhd @@ -49,6 +49,8 @@ ARCHITECTURE Behavioral OF lfr_time_mana SIGNAL nb_time_code_missing : INTEGER; SIGNAL coarse_time_s : INTEGER; + + SIGNAL new_coarsetime_s : STD_LOGIC; BEGIN @@ -72,9 +74,15 @@ BEGIN coarse_time_s <= 0; coarse_time_new <= '0'; ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF new_coarsetime = '1' THEN + new_coarsetime_s <= '1'; + ELSIF new_timecode = '1' THEN + new_coarsetime_s <= '0'; + END IF; + IF new_timecode = '1' THEN coarse_time_new <= '1'; - IF new_coarsetime = '1' THEN + IF new_coarsetime_s = '1' THEN coarse_time_s <= to_integer(unsigned(coarsetime_reg)); ELSE coarse_time_s <= coarse_time_s + 1; diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -131,6 +131,7 @@ PACKAGE lpp_dma_pkg IS send : IN STD_LOGIC; address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; send_ok : OUT STD_LOGIC; send_ko : OUT STD_LOGIC); END COMPONENT; diff --git a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_16word.vhd @@ -167,8 +167,10 @@ BEGIN -- beh DMAIn.Data <= data; - ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE - '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE + --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE + -- '1'; + ren <= '0' WHEN state = SEND_DATA ELSE '1'; - -END beh; \ No newline at end of file + +END beh; diff --git a/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd b/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd --- a/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_send_1word.vhd @@ -48,8 +48,8 @@ ENTITY lpp_dma_send_1word IS -- send : IN STD_LOGIC; address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; -- send_ok : OUT STD_LOGIC; send_ko : OUT STD_LOGIC @@ -79,7 +79,9 @@ BEGIN -- beh send_ok <= '0'; send_ko <= '0'; DMAIn.Lock <= '0'; + ren <= '1'; ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + ren <= '1'; CASE state IS WHEN IDLE => DMAIn.Store <= '1'; @@ -97,6 +99,7 @@ BEGIN -- beh DMAIn.Request <= '0'; DMAIn.Store <= '0'; state <= SEND_DATA; + ren <= '0'; END IF; WHEN SEND_DATA => IF DMAOut.Fault = '1' THEN @@ -106,9 +109,9 @@ BEGIN -- beh ELSIF DMAOut.Ready = '1' THEN DMAIn.Request <= '0'; DMAIn.Store <= '0'; - send_ok <= '1'; - send_ko <= '0'; - state <= IDLE; + send_ok <= '1'; + send_ko <= '0'; + state <= IDLE; END IF; WHEN ERROR0 => state <= ERROR1; diff --git a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd --- a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd @@ -82,6 +82,7 @@ ARCHITECTURE Behavioral OF lpp_dma_singl SIGNAL single_send_ok : STD_LOGIC; SIGNAL single_send_ko : STD_LOGIC; + SIGNAL single_ren : STD_LOGIC; ----------------------------------------------------------------------------- -- SEND SINGLE MODULE SIGNAL burst_dmai : DMA_In_Type; @@ -112,16 +113,26 @@ BEGIN AHBIn => AHB_Master_In, AHBOut => AHB_Master_Out); ----------------------------------------------------------------------------- - + + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + -- LE PROBLEME EST LA !!!!! + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + -- C'est le signal valid_burst qui n'est pas assez long. + ----------------------------------------------------------------------------- single_send <= send WHEN valid_burst = '0' ELSE '0'; burst_send <= send WHEN valid_burst = '1' ELSE '0'; DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; - done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE - burst_send_ok OR burst_send_ko; + -- TODO : verifier + done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko; + --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE + -- burst_send_ok OR burst_send_ko; - ren <= burst_ren WHEN valid_burst = '1' ELSE - NOT single_send_ok; + --ren <= burst_ren WHEN valid_burst = '1' ELSE + -- NOT single_send_ok; + ren <= burst_ren AND single_ren; ----------------------------------------------------------------------------- -- SEND 1 word by DMA @@ -136,6 +147,7 @@ BEGIN send => single_send, address => address, data => data, + ren => single_ren, send_ok => single_send_ok, -- TODO send_ko => single_send_ko -- TODO diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -26,9 +26,10 @@ ENTITY lpp_lfr IS GENERIC ( Mem_use : INTEGER := use_RAM; nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; - delta_vector_size_f0_2 : INTEGER := 3; + delta_vector_size_f0_2 : INTEGER := 7; pindex : INTEGER := 4; paddr : INTEGER := 4; @@ -36,7 +37,9 @@ ENTITY lpp_lfr IS pirq_ms : INTEGER := 0; pirq_wfp : INTEGER := 1; - hindex : INTEGER := 2 + hindex : INTEGER := 2; + + top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( @@ -120,6 +123,7 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); SIGNAL enable_f0 : STD_LOGIC; SIGNAL enable_f1 : STD_LOGIC; @@ -186,7 +190,18 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); - + + ----------------------------------------------------------------------------- + -- DMA_REG + ----------------------------------------------------------------------------- + SIGNAL ongoing_reg : STD_LOGIC; + SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL dma_send_reg : STD_LOGIC; + SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + + ----------------------------------------------------------------------------- -- DMA ----------------------------------------------------------------------------- @@ -196,6 +211,7 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL dma_ren : STD_LOGIC; SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN @@ -232,6 +248,7 @@ BEGIN lpp_lfr_apbreg_1: lpp_lfr_apbreg GENERIC MAP ( nb_data_by_buffer_size => nb_data_by_buffer_size, + nb_word_by_buffer_size => nb_word_by_buffer_size, nb_snapshot_param_size => nb_snapshot_param_size, delta_vector_size => delta_vector_size, delta_vector_size_f0_2 => delta_vector_size_f0_2, @@ -239,7 +256,8 @@ BEGIN paddr => paddr, pmask => pmask, pirq_ms => pirq_ms, - pirq_wfp => pirq_wfp) + pirq_wfp => pirq_wfp, + top_lfr_version => top_lfr_version) PORT MAP ( HCLK => clk, HRESETn => rstn, @@ -279,6 +297,7 @@ BEGIN delta_f1 => delta_f1, delta_f2 => delta_f2, nb_data_by_buffer => nb_data_by_buffer, + nb_word_by_buffer => nb_word_by_buffer, nb_snapshot_param => nb_snapshot_param, enable_f0 => enable_f0, enable_f1 => enable_f1, @@ -299,7 +318,8 @@ BEGIN GENERIC MAP ( tech => inferred, data_size => 6*16, - nb_data_by_buffer_size => nb_data_by_buffer_size, + nb_data_by_buffer_size => nb_data_by_buffer_size, + nb_word_by_buffer_size => nb_word_by_buffer_size, nb_snapshot_param_size => nb_snapshot_param_size, delta_vector_size => delta_vector_size, delta_vector_size_f0_2 => delta_vector_size_f0_2 @@ -325,6 +345,7 @@ BEGIN burst_f2 => burst_f2, nb_data_by_buffer => nb_data_by_buffer, + nb_word_by_buffer => nb_word_by_buffer, nb_snapshot_param => nb_snapshot_param, status_full => status_full, status_full_ack => status_full_ack, @@ -386,34 +407,30 @@ BEGIN PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - data_f0_addr_out <= (OTHERS => '0'); data_f0_data_out_valid <= '0'; data_f0_data_out_valid_burst <= '0'; - data_f1_addr_out <= (OTHERS => '0'); data_f1_data_out_valid <= '0'; data_f1_data_out_valid_burst <= '0'; - data_f2_addr_out <= (OTHERS => '0'); data_f2_data_out_valid <= '0'; data_f2_data_out_valid_burst <= '0'; - data_f3_addr_out <= (OTHERS => '0'); data_f3_data_out_valid <= '0'; data_f3_data_out_valid_burst <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - data_f0_addr_out <= data_f0_addr_out_s; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge data_f0_data_out_valid <= data_f0_data_out_valid_s; - data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; - data_f1_addr_out <= data_f1_addr_out_s; + data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; data_f1_data_out_valid <= data_f1_data_out_valid_s; - data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; - data_f2_addr_out <= data_f2_addr_out_s; + data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; data_f2_data_out_valid <= data_f2_data_out_valid_s; - data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; - data_f3_addr_out <= data_f3_addr_out_s; + data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; data_f3_data_out_valid <= data_f3_data_out_valid_s; data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; END IF; END PROCESS; - + + data_f0_addr_out <= data_f0_addr_out_s; + data_f1_addr_out <= data_f1_addr_out_s; + data_f2_addr_out <= data_f2_addr_out_s; + data_f3_addr_out <= data_f3_addr_out_s; ----------------------------------------------------------------------------- -- RoundRobin Selection For DMA @@ -430,17 +447,46 @@ BEGIN rstn => rstn, in_valid => dma_rr_valid, out_grant => dma_rr_grant); - + + + ----------------------------------------------------------------------------- + -- in : dma_rr_grant + -- send + -- out : dma_sel + -- dma_valid_burst + -- dma_sel_valid + ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - dma_sel <= (OTHERS => '0'); + dma_sel <= (OTHERS => '0'); + dma_send <= '0'; + dma_valid_burst <= '0'; ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF dma_sel = "0000" OR dma_send = '1' THEN +-- IF dma_sel = "0000" OR dma_send = '1' THEN + IF dma_sel = "0000" OR dma_done = '1' THEN dma_sel <= dma_rr_grant; + IF dma_rr_grant(0) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f0_data_out_valid_burst; + dma_sel_valid <= data_f0_data_out_valid; + ELSIF dma_rr_grant(1) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f1_data_out_valid_burst; + dma_sel_valid <= data_f1_data_out_valid; + ELSIF dma_rr_grant(2) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f2_data_out_valid_burst; + dma_sel_valid <= data_f2_data_out_valid; + ELSIF dma_rr_grant(3) = '1' THEN + dma_send <= '1'; + dma_valid_burst <= data_f3_data_out_valid_burst; + dma_sel_valid <= data_f3_data_out_valid; + END IF; ELSE - dma_sel <= dma_sel; - END IF; + dma_sel <= dma_sel; + dma_send <= '0'; + END IF; END IF; END PROCESS; @@ -454,25 +500,69 @@ BEGIN data_f1_data_out WHEN dma_sel(1) = '1' ELSE data_f2_data_out WHEN dma_sel(2) = '1' ELSE data_f3_data_out ; - - dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE - data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE - data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE - data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE - '0'; + + --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE + -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE + -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE + -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE + -- '0'; - dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE - data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE - data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE - data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE - '0'; + --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE + -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE + -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE + -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE + -- '0'; + + -- TODO + --dma_send <= dma_sel_valid OR dma_valid_burst; - dma_send <= dma_sel_valid OR dma_valid_burst; - + --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1'; + --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1'; + --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1'; + --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1'; + data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; + + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- ongoing_reg <= '0'; + -- dma_sel_reg <= (OTHERS => '0'); + -- dma_send_reg <= '0'; + -- dma_valid_burst_reg <= '0'; + -- dma_address_reg <= (OTHERS => '0'); + -- dma_data_reg <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN + -- ongoing_reg <= '1'; + -- dma_valid_burst_reg <= dma_valid_burst; + -- dma_sel_reg <= dma_sel; + -- ELSE + -- IF dma_done = '1' THEN + -- ongoing_reg <= '0'; + -- END IF; + -- END IF; + -- dma_send_reg <= dma_send; + -- dma_address_reg <= dma_address; + -- dma_data_reg <= dma_data; + -- END IF; + --END PROCESS; + + dma_data_2 <= dma_data; + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- dma_data_2 <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- dma_data_2 <= dma_data; + + -- END IF; + --END PROCESS; + ----------------------------------------------------------------------------- -- DMA @@ -488,12 +578,12 @@ BEGIN AHB_Master_In => ahbi, AHB_Master_Out => ahbo, - send => dma_send, - valid_burst => dma_valid_burst, + send => dma_send,--_reg, + valid_burst => dma_valid_burst,--_reg, done => dma_done, ren => dma_ren, - address => dma_address, - data => dma_data); + address => dma_address,--_reg, + data => dma_data_2);--_reg); ----------------------------------------------------------------------------- -- Matrix Spectral - TODO diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -37,6 +37,7 @@ USE techmap.gencomp.ALL; ENTITY lpp_lfr_apbreg IS GENERIC ( nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; delta_vector_size_f0_2 : INTEGER := 3; @@ -45,7 +46,8 @@ ENTITY lpp_lfr_apbreg IS paddr : INTEGER := 4; pmask : INTEGER := 16#fff#; pirq_ms : INTEGER := 0; - pirq_wfp : INTEGER := 1); + pirq_wfp : INTEGER := 1; + top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)); PORT ( -- AMBA AHB system signals HCLK : IN STD_ULOGIC; @@ -101,6 +103,7 @@ ENTITY lpp_lfr_apbreg IS delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); enable_f0 : OUT STD_LOGIC; @@ -164,6 +167,7 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); enable_f0 : STD_LOGIC; enable_f1 : STD_LOGIC; @@ -212,6 +216,7 @@ BEGIN -- beh delta_f1 <= reg_wp.delta_f1; delta_f2 <= reg_wp.delta_f2; nb_data_by_buffer <= reg_wp.nb_data_by_buffer; + nb_word_by_buffer <= reg_wp.nb_word_by_buffer; nb_snapshot_param <= reg_wp.nb_snapshot_param; enable_f0 <= reg_wp.enable_f0; @@ -293,10 +298,11 @@ BEGIN -- beh reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; - - reg_wp.status_full <= reg_wp.status_full OR status_full; - reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err; - reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err; + all_status: FOR I IN 3 DOWNTO 0 LOOP + reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; + reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; + reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ; + END LOOP all_status; paddr := "000000"; paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); @@ -347,7 +353,9 @@ BEGIN -- beh WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date; - -- + WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; + ---------------------------------------------------- + WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0); WHEN OTHERS => NULL; END CASE; IF (apbi.pwrite AND apbi.penable) = '1' THEN @@ -399,21 +407,22 @@ BEGIN -- beh WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); + WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); -- WHEN OTHERS => NULL; END CASE; END IF; END IF; - apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR - ready_matrix_f0_1 OR - ready_matrix_f1 OR - ready_matrix_f2) + apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR + ready_matrix_f0_1 OR + ready_matrix_f1 OR + ready_matrix_f2) ) OR (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR error_bad_component_error) - ); + )); apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR status_full(1) OR status_full_err(1) OR status_new_err(1) OR diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -75,6 +75,7 @@ PACKAGE lpp_lfr_pkg IS GENERIC ( Mem_use : INTEGER; nb_data_by_buffer_size : INTEGER; + nb_word_by_buffer_size : INTEGER; nb_snapshot_param_size : INTEGER; delta_vector_size : INTEGER; delta_vector_size_f0_2 : INTEGER; @@ -83,7 +84,9 @@ PACKAGE lpp_lfr_pkg IS pmask : INTEGER; pirq_ms : INTEGER; pirq_wfp : INTEGER; - hindex : INTEGER); + hindex : INTEGER; + top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; @@ -102,6 +105,7 @@ PACKAGE lpp_lfr_pkg IS COMPONENT lpp_lfr_apbreg GENERIC ( nb_data_by_buffer_size : INTEGER; + nb_word_by_buffer_size : INTEGER; nb_snapshot_param_size : INTEGER; delta_vector_size : INTEGER; delta_vector_size_f0_2 : INTEGER; @@ -109,7 +113,8 @@ PACKAGE lpp_lfr_pkg IS paddr : INTEGER; pmask : INTEGER; pirq_ms : INTEGER; - pirq_wfp : INTEGER); + pirq_wfp : INTEGER; + top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)); PORT ( HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; @@ -149,6 +154,7 @@ PACKAGE lpp_lfr_pkg IS delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); enable_f0 : OUT STD_LOGIC; enable_f1 : OUT STD_LOGIC; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd.bak b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd.bak deleted file mode 100644 --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd.bak +++ /dev/null @@ -1,304 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_top_acq IS - GENERIC( - tech : INTEGER := 0, - Mem_use : integer := use_RAM - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; -- 49 MHz - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; -- 25 MHz - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) - ); -END lpp_top_acq; - -ARCHITECTURE tb OF lpp_top_acq IS - - COMPONENT Downsampling - GENERIC ( - ChanelCount : INTEGER; - SampleSize : INTEGER; - DivideParam : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sample_in_val : IN STD_LOGIC; - sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0); - sample_out_val : OUT STD_LOGIC; - sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0)); - END COMPONENT; - - ----------------------------------------------------------------------------- - CONSTANT ChanelCount : INTEGER := 8; - CONSTANT ncycle_cnv_high : INTEGER := 79; - CONSTANT ncycle_cnv : INTEGER := 500; - - ----------------------------------------------------------------------------- - SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0); - SIGNAL sample_val : STD_LOGIC; - SIGNAL sample_val_delay : STD_LOGIC; - ----------------------------------------------------------------------------- - CONSTANT Coef_SZ : INTEGER := 9; - CONSTANT CoefCntPerCel : INTEGER := 6; - CONSTANT CoefPerCel : INTEGER := 5; - CONSTANT Cels_count : INTEGER := 5; - - SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_val : STD_LOGIC; - SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; - SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sample_downsampling_out_val : STD_LOGIC; - SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f0_val : STD_LOGIC; - SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL sample_f1_val : STD_LOGIC; - SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f2_val : STD_LOGIC; - SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -- - SIGNAL sample_f3_val : STD_LOGIC; - SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - -BEGIN - - -- component instantiation - ----------------------------------------------------------------------------- - DIGITAL_acquisition : AD7688_drvr - GENERIC MAP ( - ChanelCount => ChanelCount, - ncycle_cnv_high => ncycle_cnv_high, - ncycle_cnv => ncycle_cnv) - PORT MAP ( - cnv_clk => cnv_clk, -- - cnv_rstn => cnv_rstn, -- - cnv_run => cnv_run, -- - cnv => cnv, -- - clk => clk, -- - rstn => rstn, -- - sck => sck, -- - sdo => sdo(ChanelCount-1 DOWNTO 0), -- - sample => sample, - sample_val => sample_val); - - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_val_delay <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_val_delay <= sample_val; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE - SampleLoop : FOR j IN 0 TO 15 GENERATE - sample_filter_in(i, j) <= sample(i)(j); - END GENERATE; - - sample_filter_in(i, 16) <= sample(i)(15); - sample_filter_in(i, 17) <= sample(i)(15); - END GENERATE; - - coefs_v2 <= CoefsInitValCst_v2; - - IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 - GENERIC MAP ( - tech => 0, - Mem_use => Mem_use, - Sample_SZ => 18, - Coef_SZ => Coef_SZ, - Coef_Nb => 25, -- TODO - Coef_sel_SZ => 5, -- TODO - Cels_count => Cels_count, - ChanelsCount => ChanelCount) - PORT MAP ( - rstn => rstn, - clk => clk, - virg_pos => 7, - coefs => coefs_v2, - sample_in_val => sample_val_delay, - sample_in => sample_filter_in, - sample_out_val => sample_filter_v2_out_val, - sample_out => sample_filter_v2_out); - - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - sample_filter_v2_out_r_val <= '0'; - rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP - rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP - sample_filter_v2_out_r(I, J) <= '0'; - END LOOP rst_all_bits; - END LOOP rst_all_chanel; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_filter_v2_out_r_val <= sample_filter_v2_out_val; - IF sample_filter_v2_out_val = '1' THEN - sample_filter_v2_out_r <= sample_filter_v2_out; - END IF; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - -- F0 -- @24.576 kHz - ----------------------------------------------------------------------------- - Downsampling_f0 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 4) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_filter_v2_out_val , - sample_in => sample_filter_v2_out, - sample_out_val => sample_f0_val, - sample_out => sample_f0); - - all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f0_wdata(I) <= sample_f0(0, I); - sample_f0_wdata(16*1+I) <= sample_f0(1, I); - sample_f0_wdata(16*2+I) <= sample_f0(2, I); - sample_f0_wdata(16*3+I) <= sample_f0(6, I); - sample_f0_wdata(16*4+I) <= sample_f0(7, I); - END GENERATE all_bit_sample_f0; - - sample_f0_wen <= NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val) & - NOT(sample_f0_val); - - ----------------------------------------------------------------------------- - -- F1 -- @4096 Hz - ----------------------------------------------------------------------------- - Downsampling_f1 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 6) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f1_val, - sample_out => sample_f1); - - sample_f1_wen <= NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val) & - NOT(sample_f1_val); - - all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f1_wdata(I) <= sample_f1(0, I); - sample_f1_wdata(16*1+I) <= sample_f1(1, I); - sample_f1_wdata(16*2+I) <= sample_f1(2, I); - sample_f1_wdata(16*3+I) <= sample_f1(6, I); - sample_f1_wdata(16*4+I) <= sample_f1(7, I); - END GENERATE all_bit_sample_f1; - - ----------------------------------------------------------------------------- - -- F2 -- @16 Hz - ----------------------------------------------------------------------------- - Downsampling_f2 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 256) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f1_val , - sample_in => sample_f1, - sample_out_val => sample_f2_val, - sample_out => sample_f2); - - sample_f2_wen <= NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val) & - NOT(sample_f2_val); - - all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f2_wdata(I) <= sample_f2(0, I); - sample_f2_wdata(16*1+I) <= sample_f2(1, I); - sample_f2_wdata(16*2+I) <= sample_f2(2, I); - sample_f2_wdata(16*3+I) <= sample_f2(6, I); - sample_f2_wdata(16*4+I) <= sample_f2(7, I); - END GENERATE all_bit_sample_f2; - - ----------------------------------------------------------------------------- - -- F3 -- @256 Hz - ----------------------------------------------------------------------------- - Downsampling_f3 : Downsampling - GENERIC MAP ( - ChanelCount => ChanelCount, - SampleSize => 18, - DivideParam => 96) - PORT MAP ( - clk => clk, - rstn => rstn, - sample_in_val => sample_f0_val , - sample_in => sample_f0, - sample_out_val => sample_f3_val, - sample_out => sample_f3); - - sample_f3_wen <= (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val) & - (NOT sample_f3_val); - - all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE - sample_f3_wdata(I) <= sample_f3(0, I); - sample_f3_wdata(16*1+I) <= sample_f3(1, I); - sample_f3_wdata(16*2+I) <= sample_f3(2, I); - sample_f3_wdata(16*3+I) <= sample_f3(6, I); - sample_f3_wdata(16*4+I) <= sample_f3(7, I); - END GENERATE all_bit_sample_f3; - - - -END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak deleted file mode 100644 --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak +++ /dev/null @@ -1,81 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -PACKAGE lpp_top_lfr_pkg IS - - COMPONENT lpp_top_acq - GENERIC( - tech : INTEGER := 0, - Mem_use : integer := use_RAM - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; -- 49 MHz - cnv_rstn : IN STD_LOGIC; - -- - clk : IN STD_LOGIC; -- 25 MHz - rstn : IN STD_LOGIC; - -- - sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpp_top_apbreg - GENERIC ( - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq : INTEGER); - PORT ( - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - ready_matrix_f0_0 : IN STD_LOGIC; - ready_matrix_f0_1 : IN STD_LOGIC; - ready_matrix_f1 : IN STD_LOGIC; - ready_matrix_f2 : IN STD_LOGIC; - error_anticipating_empty_fifo : IN STD_LOGIC; - error_bad_component_error : IN STD_LOGIC; - debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - status_ready_matrix_f0_0 : OUT STD_LOGIC; - status_ready_matrix_f0_1 : OUT STD_LOGIC; - status_ready_matrix_f1 : OUT STD_LOGIC; - status_ready_matrix_f2 : OUT STD_LOGIC; - status_error_anticipating_empty_fifo : OUT STD_LOGIC; - status_error_bad_component_error : OUT STD_LOGIC; - config_active_interruption_onNewMatrix : OUT STD_LOGIC; - config_active_interruption_onError : OUT STD_LOGIC; - addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); - END COMPONENT; - -END lpp_top_lfr_pkg; \ No newline at end of file diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -41,7 +41,8 @@ ENTITY lpp_waveform IS GENERIC ( tech : INTEGER := inferred; data_size : INTEGER := 96; --16*6 - nb_data_by_buffer_size : INTEGER := 11; + nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; delta_vector_size_f0_2 : INTEGER := 3); @@ -73,6 +74,7 @@ ENTITY lpp_waveform IS burst_f2 : IN STD_LOGIC; nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -314,10 +316,10 @@ BEGIN -- beh rstn => rstn, run => run, nb_data_by_buffer => nb_data_by_buffer, - data_in_valid => valid_out, - data_in_ack => valid_ack, - data_in => data_out, - time_in => time_out_2, + data_in_valid => valid_out, + data_in_ack => valid_ack, + data_in => data_out, + time_in => time_out_2, data_out => wdata, data_out_wen => data_wen, @@ -332,49 +334,57 @@ BEGIN -- beh empty => empty, empty_almost => empty_almost, - + data_ren => data_ren, rdata => rdata, - + full_almost => full_almost, full => full, data_wen => data_wen, wdata => wdata); - + data_f0_data_out <= rdata; + data_f1_data_out <= rdata; + data_f2_data_out <= rdata; + data_f3_data_out <= rdata; + + --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency + -- GENERIC MAP ( + -- tech => tech) + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- run => run, + + -- empty_almost => empty_almost, + -- empty => empty, + -- data_ren => data_ren, + + -- rdata_0 => data_f0_data_out, + -- rdata_1 => data_f1_data_out, + -- rdata_2 => data_f2_data_out, + -- rdata_3 => data_f3_data_out, + + -- full_almost => full_almost, + -- full => full, + -- data_wen => data_wen, + -- wdata => wdata); - ----------------------------------------------------------------------------- - -- TODO : set the alterance : time, data, data, ..... - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - data_ren <= data_f3_data_out_ren & data_f2_data_out_ren & data_f1_data_out_ren & data_f0_data_out_ren; - data_f3_data_out <= rdata; - data_f2_data_out <= rdata; - data_f1_data_out <= rdata; - data_f0_data_out <= rdata; - - - - - ----------------------------------------------------------------------------- - -- TODO + -- TODO : set the alterance : time, data, data, ..... ----------------------------------------------------------------------------- lpp_waveform_gen_address_1 : lpp_waveform_genaddress GENERIC MAP ( - nb_data_by_buffer_size => nb_data_by_buffer_size) + nb_data_by_buffer_size => nb_word_by_buffer_size) PORT MAP ( clk => clk, rstn => rstn, @@ -383,7 +393,7 @@ BEGIN -- beh ------------------------------------------------------------------------- -- CONFIG ------------------------------------------------------------------------- - nb_data_by_buffer => nb_data_by_buffer, + nb_data_by_buffer => nb_word_by_buffer, addr_data_f0 => addr_data_f0, addr_data_f1 => addr_data_f1, diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_gen_valid.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_gen_valid.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_gen_valid.vhd @@ -0,0 +1,98 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY lpp_waveform_dma_genvalid IS + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + run : IN STD_LOGIC; + + valid_in : IN STD_LOGIC; + time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + + ack_in : IN STD_LOGIC; + valid_out : OUT STD_LOGIC; + time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS + TYPE state_fsm IS (IDLE, VALID); + SIGNAL state : state_fsm; +BEGIN + + FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + state <= IDLE; + valid_out <= '0'; + error <= '0'; + time_out <= (OTHERS => '0'); + ELSIF HCLK'EVENT AND HCLK = '1' THEN + CASE state IS + WHEN IDLE => + + valid_out <= '0'; + error <= '0'; + IF run = '1' AND valid_in = '1' THEN + state <= VALID; + valid_out <= '1'; + time_out <= time_in; + END IF; + + WHEN VALID => + IF run = '0' THEN + state <= IDLE; + valid_out <= '0'; + error <= '0'; + ELSE + IF valid_in = '1' THEN + IF ack_in = '1' THEN + state <= VALID; + valid_out <= '1'; + time_out <= time_in; + ELSE + state <= IDLE; + error <= '1'; + valid_out <= '0'; + END IF; + ELSIF ack_in = '1' THEN + state <= IDLE; + valid_out <= '0'; + END IF; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS FSM_SELECT_ADDRESS; + +END Behavioral; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd @@ -41,15 +41,15 @@ ENTITY lpp_waveform_fifo IS run : IN STD_LOGIC; --------------------------------------------------------------------------- - empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b - empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b + empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --------------------------------------------------------------------------- - full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b - full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b + full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END ENTITY; @@ -59,39 +59,39 @@ ARCHITECTURE ar_lpp_waveform_fifo OF lpp SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); - SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); - SIGNAL ren : STD_LOGIC; - SIGNAL wen : STD_LOGIC; + SIGNAL re : STD_LOGIC; + SIGNAL we : STD_LOGIC; BEGIN SRAM : syncram_2p GENERIC MAP(tech, 7, 32) - PORT MAP(clk, ren, data_addr_r, rdata, - clk, wen, data_addr_w, wdata); + PORT MAP(clk, re, data_addr_r, rdata, + clk, we, data_addr_w, wdata); - ren <= data_mem_ren(3) OR - data_mem_ren(2) OR - data_mem_ren(1) OR - data_mem_ren(0); + re <= data_mem_re(3) OR + data_mem_re(2) OR + data_mem_re(1) OR + data_mem_re(0); - wen <= data_mem_wen(3) OR - data_mem_wen(2) OR - data_mem_wen(1) OR - data_mem_wen(0); + we <= data_mem_we(3) OR + data_mem_we(2) OR + data_mem_we(1) OR + data_mem_we(0); - data_addr_r <= data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE - data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE - data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE + data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE + data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE + data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE data_mem_addr_r(3); - data_addr_w <= data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE - data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE - data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE + data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE + data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE + data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE data_mem_addr_w(3); gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE @@ -105,8 +105,8 @@ BEGIN run => run, ren => data_ren(I), wen => data_wen(I), - mem_re => data_mem_ren(I), - mem_we => data_mem_wen(I), + mem_re => data_mem_re(I), + mem_we => data_mem_we(I), mem_addr_ren => data_mem_addr_r(I), mem_addr_wen => data_mem_addr_w(I), empty_almost => empty_almost(I), diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -58,83 +58,155 @@ END ENTITY; ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS - + ----------------------------------------------------------------------------- + -- DATA MUX ----------------------------------------------------------------------------- - -- DATA FLOW - ----------------------------------------------------------------------------- + SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL time_temp_0 : WORD_VECTOR(3 DOWNTO 0); - SIGNAL time_temp_1 : WORD_VECTOR(3 DOWNTO 0); - SIGNAL data_temp_0 : WORD_VECTOR(3 DOWNTO 0); - SIGNAL data_temp_1 : WORD_VECTOR(3 DOWNTO 0); - SIGNAL data_temp_2 : WORD_VECTOR(3 DOWNTO 0); - SIGNAL data_temp_v : WORD_VECTOR(3 DOWNTO 0); - SIGNAL sel_input : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- RR and SELECTION + ----------------------------------------------------------------------------- + SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL no_sel : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- REG ----------------------------------------------------------------------------- - -- CHANNEL SELECTION (RoundRobin) + SIGNAL count_enable : STD_LOGIC; + SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + + SIGNAL shift_data_enable : STD_LOGIC; + SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL shift_time_enable : STD_LOGIC; + SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + +BEGIN + ----------------------------------------------------------------------------- - SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL valid_out_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); - ----------------------------------------------------------------------------- - -- FSM CONTROL + -- CONTROL ----------------------------------------------------------------------------- - TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; - SIGNAL reg_shift_data : Counter_Vector(3 DOWNTO 0); - SIGNAL reg_shift_time : Counter_Vector(3 DOWNTO 0); - SIGNAL reg_count_data : Counter_Vector(3 DOWNTO 0); - -- SHIFT_DATA --------------------------------------------------------------- - SIGNAL shift_data_pre : INTEGER; - SIGNAL shift_data : INTEGER; - SIGNAL reg_shift_data_s : Counter_Vector(3 DOWNTO 0); - -- SHIFT_TIME --------------------------------------------------------------- - SIGNAL reg_shift_time_pre : INTEGER; - SIGNAL shift_time_pre : INTEGER; - SIGNAL shift_time : INTEGER; - SIGNAL reg_shift_time_s : Counter_Vector(3 DOWNTO 0); - -- COUNT_DATA --------------------------------------------------------------- - SIGNAL count_data_pre : INTEGER; - SIGNAL count_data : INTEGER; - SIGNAL reg_count_data_s : Counter_Vector(3 DOWNTO 0); - -BEGIN + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + count_enable <= '0'; + shift_time_enable <= '0'; + shift_data_enable <= '0'; + data_in_ack <= (OTHERS => '0'); + data_out_wen <= (OTHERS => '1'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '0' OR no_sel = '1' THEN + count_enable <= '0'; + shift_time_enable <= '0'; + shift_data_enable <= '0'; + data_in_ack <= (OTHERS => '0'); + data_out_wen <= (OTHERS => '1'); + ELSE + --COUNT + IF shift_data_s = "10" THEN + count_enable <= '1'; + ELSE + count_enable <= '0'; + END IF; + --DATA + IF shift_time_s = "10" THEN + shift_data_enable <= '1'; + ELSE + shift_data_enable <= '0'; + END IF; - ----------------------------------------------------------------------------- - -- DATA FLOW - ----------------------------------------------------------------------------- + --TIME + IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR + shift_time_s = "00" OR + shift_time_s = "01" + THEN + shift_time_enable <= '1'; + ELSE + shift_time_enable <= '0'; + END IF; + + --ACK + IF shift_data_s = "10" THEN + data_in_ack <= sel; + ELSE + data_in_ack <= (OTHERS => '0'); + END IF; + + --VALID OUT + all_wen: FOR I IN 3 DOWNTO 0 LOOP + IF sel(I) = '1' AND count_enable = '0' THEN + data_out_wen(I) <= '0'; + ELSE + data_out_wen(I) <= '1'; + END IF; + END LOOP all_wen; + END IF; + END IF; + END PROCESS; - all_input : FOR I IN 3 DOWNTO 0 GENERATE - - all_bit_of_time: FOR J IN 31 DOWNTO 0 GENERATE - time_temp_0(I)(J) <= time_in(I,J); - J_47DOWNTO32: IF J+32 < 48 GENERATE - time_temp_1(I)(J) <= time_in(I,32+J); - END GENERATE J_47DOWNTO32; - J_63DOWNTO48: IF J+32 > 47 GENERATE - time_temp_1(I)(J) <= '0'; - END GENERATE J_63DOWNTO48; - data_temp_0(I)(J) <= data_in(I,J); - data_temp_1(I)(J) <= data_in(I,J+32); - data_temp_2(I)(J) <= data_in(I,J+32*2); - END GENERATE all_bit_of_time; - - data_temp_v(I) <= time_temp_0(I) WHEN reg_shift_time_pre = 0 ELSE - time_temp_1(I) WHEN reg_shift_time_pre = 1 ELSE - data_temp_0(I) WHEN shift_data = 0 ELSE - data_temp_1(I) WHEN shift_data = 1 ELSE - data_temp_2(I); - END GENERATE all_input; + ----------------------------------------------------------------------------- + -- DATA MUX + ----------------------------------------------------------------------------- + all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE + I_time_in: IF I < 48 GENERATE + data_0_v(I) <= time_in(0,I); + data_1_v(I) <= time_in(1,I); + data_2_v(I) <= time_in(2,I); + data_3_v(I) <= time_in(3,I); + END GENERATE I_time_in; + I_null: IF (I > 47) AND (I < 32*2) GENERATE + data_0_v(I) <= '0'; + data_1_v(I) <= '0'; + data_2_v(I) <= '0'; + data_3_v(I) <= '0'; + END GENERATE I_null; + I_data_in: IF I > 32*2-1 GENERATE + data_0_v(I) <= data_in(0,I-32*2); + data_1_v(I) <= data_in(1,I-32*2); + data_2_v(I) <= data_in(2,I-32*2); + data_3_v(I) <= data_in(3,I-32*2); + END GENERATE I_data_in; + END GENERATE all_bit_data_in; - data_out <= data_temp_v(0) WHEN sel_input = "0001" ELSE - data_temp_v(1) WHEN sel_input = "0010" ELSE - data_temp_v(2) WHEN sel_input = "0100" ELSE - data_temp_v(3); + all_word: FOR J IN 4 DOWNTO 0 GENERATE + all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE + data_0(J)(I) <= data_0_v(J*32+I); + data_1(J)(I) <= data_1_v(J*32+I); + data_2(J)(I) <= data_2_v(J*32+I); + data_3(J)(I) <= data_3_v(J*32+I); + END GENERATE all_data_bit; + END GENERATE all_word; + data_sel <= data_0 WHEN sel(0) = '1' ELSE + data_1 WHEN sel(1) = '1' ELSE + data_2 WHEN sel(2) = '1' ELSE + data_3; + + data_out <= data_sel(0) WHEN shift_time = "00" ELSE + data_sel(1) WHEN shift_time = "01" ELSE + data_sel(2) WHEN shift_data = "00" ELSE + data_sel(3) WHEN shift_data = "01" ELSE + data_sel(4); + + ----------------------------------------------------------------------------- - -- CHANNEL SELECTION (RoundRobin) + -- RR and SELECTION ----------------------------------------------------------------------------- all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE --- valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); valid_in_rr(I) <= data_in_valid(I) AND NOT full(I); END GENERATE all_input_rr; @@ -143,103 +215,59 @@ BEGIN clk => clk, rstn => rstn, in_valid => valid_in_rr, - out_grant => valid_out_rr); - - ----------------------------------------------------------------------------- - -- FSM CONTROL - ----------------------------------------------------------------------------- - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - reg_shift_data <= (0, 0, 0, 0); - reg_shift_time <= (0, 0, 0, 0); - reg_count_data <= (0, 0, 0, 0); - sel_input <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF run = '0' THEN - reg_shift_data <= (0, 0, 0, 0); - reg_shift_time <= (0, 0, 0, 0); - reg_count_data <= (0, 0, 0, 0); - sel_input <= (OTHERS => '0'); - ELSE - sel_input <= valid_out_rr; + out_grant => sel); - IF count_data_pre = 0 THEN -- first buffer data - IF shift_time_pre < 2 THEN -- TIME not completly send - reg_shift_time <= reg_shift_time_s; - ELSE - reg_shift_data <= reg_shift_data_s; - IF shift_data_pre = 2 THEN - reg_count_data <= reg_count_data_s; - END IF; - END IF; - ELSE - reg_shift_data <= reg_shift_data_s; - IF shift_data_pre = 2 THEN - reg_count_data <= reg_count_data_s; - IF count_data = 0 THEN - reg_shift_time <= reg_shift_time_s; - END IF; - END IF; - END IF; - END IF; - END IF; - END PROCESS; + no_sel <= '1' WHEN sel = "0000" ELSE '0'; ----------------------------------------------------------------------------- - data_out_wen <= NOT sel_input; - data_in_ack <= sel_input; - - -- SHIFT_DATA --------------------------------------------------------------- - shift_data_pre <= reg_shift_data(0) WHEN valid_out_rr(0) = '1' ELSE - reg_shift_data(1) WHEN valid_out_rr(1) = '1' ELSE - reg_shift_data(2) WHEN valid_out_rr(2) = '1' ELSE - reg_shift_data(3); - - shift_data <= shift_data_pre + 1 WHEN shift_data_pre < 2 ELSE 0; - - reg_shift_data_s(0) <= shift_data WHEN valid_out_rr(0) = '1' ELSE reg_shift_data(0);--_s - reg_shift_data_s(1) <= shift_data WHEN valid_out_rr(1) = '1' ELSE reg_shift_data(1);--_s - reg_shift_data_s(2) <= shift_data WHEN valid_out_rr(2) = '1' ELSE reg_shift_data(2);--_s - reg_shift_data_s(3) <= shift_data WHEN valid_out_rr(3) = '1' ELSE reg_shift_data(3);--_s - - -- SHIFT_TIME --------------------------------------------------------------- - shift_time_pre <= reg_shift_time(0) WHEN valid_out_rr(0) = '1' ELSE - reg_shift_time(1) WHEN valid_out_rr(1) = '1' ELSE - reg_shift_time(2) WHEN valid_out_rr(2) = '1' ELSE - reg_shift_time(3); - - shift_time <= shift_time_pre + 1 WHEN shift_time_pre < 2 ELSE 0; + -- REG + ----------------------------------------------------------------------------- + reg_count_i: lpp_waveform_fifo_arbiter_reg + GENERIC MAP ( + data_size => nb_data_by_buffer_size, + data_nb => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + max_count => nb_data_by_buffer, + enable => count_enable, + sel => sel, + data => count, + data_s => count_s); - reg_shift_time_s(0) <= shift_time WHEN valid_out_rr(0) = '1' ELSE reg_shift_time(0);--_s - reg_shift_time_s(1) <= shift_time WHEN valid_out_rr(1) = '1' ELSE reg_shift_time(1);--_s - reg_shift_time_s(2) <= shift_time WHEN valid_out_rr(2) = '1' ELSE reg_shift_time(2);--_s - reg_shift_time_s(3) <= shift_time WHEN valid_out_rr(3) = '1' ELSE reg_shift_time(3);--_s + reg_shift_data_i: lpp_waveform_fifo_arbiter_reg + GENERIC MAP ( + data_size => 2, + data_nb => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + max_count => "10", -- 2 + enable => shift_data_enable, + sel => sel, + data => shift_data, + data_s => shift_data_s); - -- COUNT_DATA --------------------------------------------------------------- - count_data_pre <= reg_count_data(0) WHEN valid_out_rr(0) = '1' ELSE - reg_count_data(1) WHEN valid_out_rr(1) = '1' ELSE - reg_count_data(2) WHEN valid_out_rr(2) = '1' ELSE - reg_count_data(3); - - count_data <= count_data_pre + 1 WHEN count_data_pre < UNSIGNED(nb_data_by_buffer) ELSE 0; - reg_count_data_s(0) <= count_data WHEN valid_out_rr(0) = '1' ELSE reg_count_data(0);--_s - reg_count_data_s(1) <= count_data WHEN valid_out_rr(1) = '1' ELSE reg_count_data(1);--_s - reg_count_data_s(2) <= count_data WHEN valid_out_rr(2) = '1' ELSE reg_count_data(2);--_s - reg_count_data_s(3) <= count_data WHEN valid_out_rr(3) = '1' ELSE reg_count_data(3);--_s - ----------------------------------------------------------------------------- + reg_shift_time_i: lpp_waveform_fifo_arbiter_reg + GENERIC MAP ( + data_size => 2, + data_nb => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + max_count => "10", -- 2 + enable => shift_time_enable, + sel => sel, + data => shift_time, + data_s => shift_time_s); + + - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - reg_shift_time_pre <= 0; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - reg_shift_time_pre <= shift_time_pre; - END IF; - END PROCESS ; - + END ARCHITECTURE; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd @@ -0,0 +1,117 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.general_purpose.ALL; + +ENTITY lpp_waveform_fifo_arbiter_reg IS + GENERIC( + data_size : INTEGER; + data_nb : INTEGER + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + + max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); + + enable : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); + + data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS + + TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; + SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0); + + SIGNAL reg_sel : INTEGER; + SIGNAL reg_sel_s : INTEGER; + +BEGIN + + all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + reg(I) <= 0; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '0' THEN + reg(I) <= 0; + ELSE + IF sel(I) = '1' THEN + reg(I) <= reg_sel_s; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_reg; + + reg_sel <= reg(0) WHEN sel(0) = '1' ELSE + reg(1) WHEN sel(1) = '1' ELSE + reg(2) WHEN sel(2) = '1' ELSE + reg(3); + + reg_sel_s <= reg_sel WHEN enable = '0' ELSE + reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE + 0; + + data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size)); + data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size)); + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd @@ -0,0 +1,143 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo_latencyCorrection IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + + --------------------------------------------------------------------------- + empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b + empty : OUT STD_LOGIC; + data_ren : IN STD_LOGIC; + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + --------------------------------------------------------------------------- + empty_almost_fifo : IN STD_LOGIC; + empty_fifo : IN STD_LOGIC; + data_ren_fifo : OUT STD_LOGIC; + rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_latencyCorrection OF lpp_waveform_fifo_latencyCorrection IS + SIGNAL data_ren_fifo_s : STD_LOGIC; +-- SIGNAL rdata_s : STD_LOGIC; + + SIGNAL reg_full : STD_LOGIC; + SIGNAL empty_almost_reg : STD_LOGIC; +BEGIN + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + empty_almost_reg <= '1'; + empty <= '1'; + data_ren_fifo_s <= '1'; + rdata <= (OTHERS => '0'); + reg_full <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF run = '0' THEN + empty_almost_reg <= '1'; + empty <= '1'; + data_ren_fifo_s <= '1'; + rdata <= (OTHERS => '0'); + reg_full <= '0'; + ELSE + + IF data_ren_fifo_s = '0' THEN + reg_full <= '1'; + ELSIF data_ren = '0' THEN + reg_full <= '0'; + END IF; + + IF data_ren_fifo_s = '0' THEN + rdata <= rdata_fifo; + END IF; + + IF (reg_full = '0' OR data_ren = '0') AND empty_fifo = '0' THEN + data_ren_fifo_s <= '0'; + ELSE + data_ren_fifo_s <= '1'; + END IF; + + IF empty_fifo = '1' AND ((reg_full = '0') OR ( data_ren = '0')) THEN + empty <= '1'; + ELSE + empty <= '0'; + END IF; + + IF empty_almost_reg = '0' AND data_ren = '0' AND empty_almost_fifo = '1' THEN + empty_almost_reg <= '1'; + ELSIF empty_almost_reg = '1' AND empty_almost_fifo = '0' THEN + empty_almost_reg <= '0'; + END IF; + + END IF; + END IF; + END PROCESS; + + empty_almost <= empty_almost_reg; + data_ren_fifo <= data_ren_fifo_s; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd @@ -0,0 +1,188 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_fifo_withoutLatency IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + + --------------------------------------------------------------------------- + empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b + empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); + rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --------------------------------------------------------------------------- + full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b + full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_withoutLatency OF lpp_waveform_fifo_withoutLatency IS + SIGNAL empty_almost_s : STD_LOGIC_VECTOR( 3 DOWNTO 0); + SIGNAL empty_s : STD_LOGIC_VECTOR( 3 DOWNTO 0); + SIGNAL data_ren_s : STD_LOGIC_VECTOR( 3 DOWNTO 0); + SIGNAL rdata_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN + + + + + lpp_waveform_fifo_latencyCorrection_0: lpp_waveform_fifo_latencyCorrection + GENERIC MAP ( + tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty_almost => empty_almost(0), + empty => empty(0), + data_ren => data_ren(0), + rdata => rdata_0, + + empty_almost_fifo => empty_almost_s(0), + empty_fifo => empty_s(0), + data_ren_fifo => data_ren_s(0), + rdata_fifo => rdata_s); + + lpp_waveform_fifo_latencyCorrection_1: lpp_waveform_fifo_latencyCorrection + GENERIC MAP ( + tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty_almost => empty_almost(1), + empty => empty(1), + data_ren => data_ren(1), + rdata => rdata_1, + + empty_almost_fifo => empty_almost_s(1), + empty_fifo => empty_s(1), + data_ren_fifo => data_ren_s(1), + rdata_fifo => rdata_s); + + lpp_waveform_fifo_latencyCorrection_2: lpp_waveform_fifo_latencyCorrection + GENERIC MAP ( + tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty_almost => empty_almost(2), + empty => empty(2), + data_ren => data_ren(2), + rdata => rdata_2, + + empty_almost_fifo => empty_almost_s(2), + empty_fifo => empty_s(2), + data_ren_fifo => data_ren_s(2), + rdata_fifo => rdata_s); + + lpp_waveform_fifo_latencyCorrection_3: lpp_waveform_fifo_latencyCorrection + GENERIC MAP ( + tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty_almost => empty_almost(3), + empty => empty(3), + data_ren => data_ren(3), + rdata => rdata_3, + + empty_almost_fifo => empty_almost_s(3), + empty_fifo => empty_s(3), + data_ren_fifo => data_ren_s(3), + rdata_fifo => rdata_s); + + lpp_waveform_fifo_1: lpp_waveform_fifo + GENERIC MAP ( + tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty_almost => empty_almost_s, + empty => empty_s, + data_ren => data_ren_s, + rdata => rdata_s, + + full_almost => full_almost, + full => full, + data_wen => data_wen, + wdata => wdata); + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_waveform/lpp_waveform_genaddress.vhd b/lib/lpp/lpp_waveform/lpp_waveform_genaddress.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_genaddress.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_genaddress.vhd @@ -1,237 +1,255 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -LIBRARY lpp; -USE lpp.lpp_waveform_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY lpp_waveform_genaddress IS - - GENERIC ( - nb_data_by_buffer_size : INTEGER); - - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - run : IN STD_LOGIC; - ------------------------------------------------------------------------- - -- CONFIG - ------------------------------------------------------------------------- - nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - ------------------------------------------------------------------------- - -- CTRL - ------------------------------------------------------------------------- - empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - - ------------------------------------------------------------------------- - -- STATUS - ------------------------------------------------------------------------- - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - - ------------------------------------------------------------------------- - -- ADDR DATA OUT - ------------------------------------------------------------------------- - data_f0_data_out_valid_burst : OUT STD_LOGIC; - data_f1_data_out_valid_burst : OUT STD_LOGIC; - data_f2_data_out_valid_burst : OUT STD_LOGIC; - data_f3_data_out_valid_burst : OUT STD_LOGIC; - - data_f0_data_out_valid : OUT STD_LOGIC; - data_f1_data_out_valid : OUT STD_LOGIC; - data_f2_data_out_valid : OUT STD_LOGIC; - data_f3_data_out_valid : OUT STD_LOGIC; - - data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - - ); - -END lpp_waveform_genaddress; - -ARCHITECTURE beh OF lpp_waveform_genaddress IS - ----------------------------------------------------------------------------- - -- Valid gen - ----------------------------------------------------------------------------- - SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0); - - ----------------------------------------------------------------------------- - -- Register - ----------------------------------------------------------------------------- - SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0); - SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0); - SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 31 DOWNTO 0); - SIGNAL data_addr_pre : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO - SIGNAL data_addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO - SIGNAL data_addr_base : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO - - ----------------------------------------------------------------------------- - -- - ----------------------------------------------------------------------------- - SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); - - TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0); - SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0); - -BEGIN -- beh - - ----------------------------------------------------------------------------- - -- valid gen - ----------------------------------------------------------------------------- - data_f0_data_out_valid <= data_out_valid(0); - data_f1_data_out_valid <= data_out_valid(1); - data_f2_data_out_valid <= data_out_valid(2); - data_f3_data_out_valid <= data_out_valid(3); - - data_f0_data_out_valid_burst <= data_out_valid_burst(0); - data_f1_data_out_valid_burst <= data_out_valid_burst(1); - data_f2_data_out_valid_burst <= data_out_valid_burst(2); - data_f3_data_out_valid_burst <= data_out_valid_burst(3); - - - all_bit_data_valid_out: FOR I IN 3 DOWNTO 0 GENERATE - addr_burst_avail(I) <= '1' WHEN data_addr_v_pre(I,2) = '0' AND - data_addr_v_pre(I,3) = '0' AND - data_addr_v_pre(I,4) = '0' AND - data_addr_v_pre(I,5) = '0' ELSE '0'; - - data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE - '0' WHEN empty(I) = '1' ELSE - '0' WHEN addr_burst_avail(I) = '1' ELSE - '0' WHEN (run = '0') ELSE - '1'; - - data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE - '0' WHEN empty(I) = '1' ELSE - '0' WHEN addr_burst_avail(I) = '0' ELSE - '0' WHEN empty_almost(I) = '1' ELSE - '0' WHEN (run = '0') ELSE - '1'; - END GENERATE all_bit_data_valid_out; - - ----------------------------------------------------------------------------- - -- Register - ----------------------------------------------------------------------------- - all_data_bit: FOR J IN 31 DOWNTO 0 GENERATE - all_data_addr: FOR I IN 3 DOWNTO 0 GENERATE - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - data_addr_v_reg(I,J) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF run = '1' AND status_full_ack(I) = '0' THEN - data_addr_v_reg(I,J) <= data_addr_v_pre(I,J); - ELSE - data_addr_v_reg(I,J) <= data_addr_v_base(I,J); - END IF; - END IF; - END PROCESS; - - data_addr_v_pre(I,J) <= data_addr_v_reg(I,J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J); - - END GENERATE all_data_addr; - - data_addr_reg(J) <= data_addr_v_reg(0,J) WHEN data_ren(0) = '1' ELSE - data_addr_v_reg(1,J) WHEN data_ren(1) = '1' ELSE - data_addr_v_reg(2,J) WHEN data_ren(2) = '1' ELSE - data_addr_v_reg(3,J); - - data_addr_v_base(0,J) <= addr_data_f0(J); - data_addr_v_base(1,J) <= addr_data_f1(J); - data_addr_v_base(2,J) <= addr_data_f2(J); - data_addr_v_base(3,J) <= addr_data_f3(J); - - data_f0_addr_out(J) <= data_addr_v_reg(0,J); - data_f1_addr_out(J) <= data_addr_v_reg(1,J); - data_f2_addr_out(J) <= data_addr_v_reg(2,J); - data_f3_addr_out(J) <= data_addr_v_reg(3,J); - - END GENERATE all_data_bit; - - - - - ----------------------------------------------------------------------------- - -- ADDER - ----------------------------------------------------------------------------- - - data_addr_pre <= data_addr_reg + 1; - - ----------------------------------------------------------------------------- - -- FULL STATUS - ----------------------------------------------------------------------------- - all_status: FOR I IN 3 DOWNTO 0 GENERATE - all_bit_addr: FOR J IN 31 DOWNTO 0 GENERATE - addr_v_p(I)(J) <= data_addr_v_pre(I,J); - addr_v_b(I)(J) <= data_addr_v_base(I,J); - END GENERATE all_bit_addr; - - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - status_full_s(I) <= '0'; - status_full_err(I) <= '0'; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge - IF run = '1' AND status_full_ack(I) = '0' THEN - IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN - status_full_s(I) <= '1'; - IF status_full_s(I) = '1' AND data_ren(I)= '1' THEN - status_full_err(I) <= '1'; - END IF; - END IF; - ELSE - status_full_s(I) <= '0'; - status_full_err(I) <= '0'; - END IF; - END IF; - END PROCESS; - - END GENERATE all_status; - - status_full <= status_full_s; - - -END beh; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY lpp; +USE lpp.lpp_waveform_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_genaddress IS + + GENERIC ( + nb_data_by_buffer_size : INTEGER); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + ------------------------------------------------------------------------- + -- CONFIG + ------------------------------------------------------------------------- + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ------------------------------------------------------------------------- + -- CTRL + ------------------------------------------------------------------------- + empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + ------------------------------------------------------------------------- + -- STATUS + ------------------------------------------------------------------------- + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + ------------------------------------------------------------------------- + -- ADDR DATA OUT + ------------------------------------------------------------------------- + data_f0_data_out_valid_burst : OUT STD_LOGIC; + data_f1_data_out_valid_burst : OUT STD_LOGIC; + data_f2_data_out_valid_burst : OUT STD_LOGIC; + data_f3_data_out_valid_burst : OUT STD_LOGIC; + + data_f0_data_out_valid : OUT STD_LOGIC; + data_f1_data_out_valid : OUT STD_LOGIC; + data_f2_data_out_valid : OUT STD_LOGIC; + data_f3_data_out_valid : OUT STD_LOGIC; + + data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + ); + +END lpp_waveform_genaddress; + +ARCHITECTURE beh OF lpp_waveform_genaddress IS + SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + ----------------------------------------------------------------------------- + -- Valid gen + ----------------------------------------------------------------------------- + SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- Register + ----------------------------------------------------------------------------- + SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); + SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); + SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); + SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO + SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO + SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0); + SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0); + + SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- valid gen + ----------------------------------------------------------------------------- + data_f0_data_out_valid <= data_out_valid(0); + data_f1_data_out_valid <= data_out_valid(1); + data_f2_data_out_valid <= data_out_valid(2); + data_f3_data_out_valid <= data_out_valid(3); + + data_f0_data_out_valid_burst <= data_out_valid_burst(0); + data_f1_data_out_valid_burst <= data_out_valid_burst(1); + data_f2_data_out_valid_burst <= data_out_valid_burst(2); + data_f3_data_out_valid_burst <= data_out_valid_burst(3); + + + + all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE + addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I)); + + addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000") + AND (UNSIGNED(addr_avail(I)) > 15) + ELSE '0'; + + data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE + '0' WHEN empty(I) = '1' ELSE + '0' WHEN addr_burst_avail(I) = '1' ELSE + '0' WHEN (run = '0') ELSE + '1'; + + data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE + '0' WHEN empty(I) = '1' ELSE + '0' WHEN addr_burst_avail(I) = '0' ELSE + '0' WHEN empty_almost(I) = '1' ELSE + '0' WHEN (run = '0') ELSE + '1'; + END GENERATE all_bit_data_valid_out; + + ----------------------------------------------------------------------------- + -- Register + ----------------------------------------------------------------------------- + all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE + all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_addr_v_reg(I, J) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF run = '1' AND status_full_ack(I) = '0' THEN + data_addr_v_reg(I, J) <= data_addr_v_pre(I, J); + ELSE + data_addr_v_reg(I, J) <= data_addr_v_base(I, J); + END IF; + END IF; + END PROCESS; + + data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J); + + END GENERATE all_data_addr; + + data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE + data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE + data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE + data_addr_v_reg(3, J); + + data_addr_v_base(0, J) <= addr_data_f0_s(J); + data_addr_v_base(1, J) <= addr_data_f1_s(J); + data_addr_v_base(2, J) <= addr_data_f2_s(J); + data_addr_v_base(3, J) <= addr_data_f3_s(J); + + data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ; + data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ; + data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ; + data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ; + + END GENERATE all_data_bit; + + addr_data_f0_s <= addr_data_f0(31 DOWNTO 2); + addr_data_f1_s <= addr_data_f1(31 DOWNTO 2); + addr_data_f2_s <= addr_data_f2(31 DOWNTO 2); + addr_data_f3_s <= addr_data_f3(31 DOWNTO 2); + + data_f0_addr_out(1 DOWNTO 0) <= "00"; + data_f1_addr_out(1 DOWNTO 0) <= "00"; + data_f2_addr_out(1 DOWNTO 0) <= "00"; + data_f3_addr_out(1 DOWNTO 0) <= "00"; + + + + + ----------------------------------------------------------------------------- + -- ADDER + ----------------------------------------------------------------------------- + + data_addr_pre <= data_addr_reg + 1; + + ----------------------------------------------------------------------------- + -- FULL STATUS + ----------------------------------------------------------------------------- + all_status : FOR I IN 3 DOWNTO 0 GENERATE + all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE + addr_v_p(I)(J) <= data_addr_v_pre(I, J); + addr_v_b(I)(J) <= data_addr_v_base(I, J); + END GENERATE all_bit_addr; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + status_full_s(I) <= '0'; + status_full_err(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF run = '1' AND status_full_ack(I) = '0' THEN + IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN + status_full_s(I) <= '1'; + IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN + status_full_err(I) <= '1'; + END IF; + END IF; + ELSE + status_full_s(I) <= '0'; + status_full_err(I) <= '0'; + END IF; + END IF; + END PROCESS; + + END GENERATE all_status; + + status_full <= status_full_s; + + +END beh; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -105,6 +105,7 @@ PACKAGE lpp_waveform_pkg IS tech : INTEGER; data_size : INTEGER; nb_data_by_buffer_size : INTEGER; + nb_word_by_buffer_size : INTEGER; nb_snapshot_param_size : INTEGER; delta_vector_size : INTEGER; delta_vector_size_f0_2 : INTEGER); @@ -126,6 +127,7 @@ PACKAGE lpp_waveform_pkg IS burst_f1 : IN STD_LOGIC; burst_f2 : IN STD_LOGIC; nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -238,6 +240,43 @@ PACKAGE lpp_waveform_pkg IS wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; + COMPONENT lpp_waveform_fifo_latencyCorrection + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + empty_almost : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + data_ren : IN STD_LOGIC; + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + empty_almost_fifo : IN STD_LOGIC; + empty_fifo : IN STD_LOGIC; + data_ren_fifo : OUT STD_LOGIC; + rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_waveform_fifo_withoutLatency + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + ----------------------------------------------------------------------------- -- GEN ADDRESS ----------------------------------------------------------------------------- @@ -273,5 +312,22 @@ PACKAGE lpp_waveform_pkg IS data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; + ----------------------------------------------------------------------------- + -- lpp_waveform_fifo_arbiter_reg + ----------------------------------------------------------------------------- + COMPONENT lpp_waveform_fifo_arbiter_reg + GENERIC ( + data_size : INTEGER; + data_nb : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); + enable : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); + END COMPONENT; END lpp_waveform_pkg; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd @@ -129,8 +129,8 @@ BEGIN -- beh BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot IF rstn = '0' THEN -- asynchronous reset (active low) counter_delta_snapshot <= 0; - first_decount <= '0'; - first_init <= '0'; + first_decount <= '1'; + first_init <= '1'; start_snapshot_f0_pre <= '0'; start_snapshot_f1 <= '0'; start_snapshot_f2 <= '0'; diff --git a/lib/lpp/lpp_waveform/vhdlsyn.txt b/lib/lpp/lpp_waveform/vhdlsyn.txt --- a/lib/lpp/lpp_waveform/vhdlsyn.txt +++ b/lib/lpp/lpp_waveform/vhdlsyn.txt @@ -1,6 +1,8 @@ lpp_waveform_pkg.vhd lpp_waveform.vhd lpp_waveform_burst.vhd +lpp_waveform_fifo_withoutLatency.vhd +lpp_waveform_fifo_latencyCorrection.vhd lpp_waveform_fifo.vhd lpp_waveform_fifo_arbiter.vhd lpp_waveform_fifo_ctrl.vhd @@ -8,3 +10,4 @@ lpp_waveform_snapshot.vhd lpp_waveform_snapshot_controler.vhd lpp_waveform_genaddress.vhd lpp_waveform_dma_genvalid.vhd +lpp_waveform_fifo_arbiter_reg.vhd