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modif alexis - CNA
pellion -
r538:38ae5b4bc50b JC
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@@ -21,34 +21,34
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22
22
23
23
24 library IEEE;
24 LIBRARY IEEE;
25 use IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 use IEEE.NUMERIC_STD.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
27
28 entity SPI_DAC_DRIVER is
28 ENTITY SPI_DAC_DRIVER IS
29 Generic(
29 GENERIC(
30 datawidth : INTEGER := 16;
30 datawidth : INTEGER := 16;
31 MSBFIRST : INTEGER := 1
31 MSBFIRST : INTEGER := 1
32 );
32 );
33 Port (
33 PORT (
34 clk : in STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : in STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 DATA : in STD_LOGIC_VECTOR(datawidth-1 downto 0);
36 DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
37 SMP_CLK : in STD_LOGIC;
37 SMP_CLK : IN STD_LOGIC;
38 SYNC : out STD_LOGIC;
38 SYNC : OUT STD_LOGIC;
39 DOUT : out STD_LOGIC;
39 DOUT : OUT STD_LOGIC;
40 SCLK : out STD_LOGIC
40 SCLK : OUT STD_LOGIC
41 );
41 );
42 end entity SPI_DAC_DRIVER;
42 END ENTITY SPI_DAC_DRIVER;
43
43
44 architecture behav of SPI_DAC_DRIVER is
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
45 signal SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 downto 0):=(others=>'0');
45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 signal INPUTREG : STD_LOGIC_VECTOR(datawidth-1 downto 0):=(others=>'0');
46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
47 signal SMP_CLK_R : STD_LOGIC:='0';
47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
48 signal shiftcnt : INTEGER:=0;
48 SIGNAL shiftcnt : INTEGER := 0;
49 signal shifting : STD_LOGIC:='0';
49 SIGNAL shifting : STD_LOGIC := '0';
50 signal shifting_R : STD_LOGIC:='0';
50 SIGNAL shifting_R : STD_LOGIC := '0';
51 begin
51 BEGIN
52
52
53 DOUT <= SHIFTREG(datawidth-1);
53 DOUT <= SHIFTREG(datawidth-1);
54
54
@@ -57,49 +57,49 MSB:IF MSBFIRST=1 GENERATE
57 END GENERATE;
57 END GENERATE;
58
58
59 LSB:IF MSBFIRST=0 GENERATE
59 LSB : IF MSBFIRST = 0 GENERATE
60 INPUTREG(datawidth-1 downto 0) <= DATA(0 to datawidth-1);
60 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
61 END GENERATE;
61 END GENERATE;
62
62
63 SCLK <= clk;
63 SCLK <= clk;
64
64
65 process(clk,rstn)
65 PROCESS(clk, rstn)
66 begin
66 BEGIN
67 if rstn='0' then
67 IF rstn = '0' then
68 shifting_R <= '0';
68 shifting_R <= '0';
69 SMP_CLK_R <= '0';
69 SMP_CLK_R <= '0';
70 elsif clk'event and clk='1' then
70 ELSIF clk'EVENT AND clk = '1' then
71 SMP_CLK_R <= SMP_CLK;
71 SMP_CLK_R <= SMP_CLK;
72 shifting_R <= shifting;
72 shifting_R <= shifting;
73 end if;
73 END IF;
74 end process;
74 END PROCESS;
75
75
76 process(clk,rstn)
76 PROCESS(clk, rstn)
77 begin
77 BEGIN
78 if rstn='0' then
78 IF rstn = '0' then
79 shifting <= '0';
79 shifting <= '0';
80 SHIFTREG <= (others=>'0');
80 SHIFTREG <= (OTHERS => '0');
81 SYNC <= '0';
81 SYNC <= '0';
82 shiftcnt <= 0;
82 shiftcnt <= 0;
83 elsif clk'event and clk='1' then
83 ELSIF clk'EVENT AND clk = '1' then
84 if(SMP_CLK='1' and SMP_CLK_R='0') then
84 IF(SMP_CLK = '1' and SMP_CLK_R = '0') THEN
85 SYNC <= '1';
85 SYNC <= '1';
86 shifting <= '1';
86 shifting <= '1';
87 else
87 ELSE
88 SYNC <= '0';
88 SYNC <= '0';
89 if shiftcnt = datawidth-1 then
89 IF shiftcnt = datawidth-1 THEN
90 shifting <= '0';
90 shifting <= '0';
91 end if;
91 END IF;
92 end if;
92 END IF;
93 if shifting_R='1' then
93 IF shifting = '1' then
94 shiftcnt <= shiftcnt + 1;
94 shiftcnt <= shiftcnt + 1;
95 SHIFTREG <= SHIFTREG (datawidth-2 downto 0) & '0';
95 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
96 else
96 ELSE
97 SHIFTREG <= INPUTREG;
97 SHIFTREG <= INPUTREG;
98 shiftcnt <= 0;
98 shiftcnt <= 0;
99 end if;
99 END IF;
100 end if;
100 END IF;
101 end process;
101 END PROCESS;
102
102
103 end architecture behav;
103 END ARCHITECTURE behav;
104
104
105
105
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