@@ -1,114 +1,114 | |||
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1 | 1 | |
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2 | 2 | LIBRARY IEEE; |
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3 | 3 | USE IEEE.STD_LOGIC_1164.ALL; |
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4 | 4 | LIBRARY lpp; |
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5 | 5 | USE lpp.lpp_ad_conv.ALL; |
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6 | 6 | USE lpp.general_purpose.SYNC_FF; |
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7 | 7 | |
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8 | 8 | ENTITY top_ad_conv_RHF1401 IS |
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9 | 9 | GENERIC( |
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10 | 10 | ChanelCount : INTEGER := 8; |
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11 | 11 | ncycle_cnv_high : INTEGER := 79; |
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12 | 12 | ncycle_cnv : INTEGER := 500); |
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13 | 13 | PORT ( |
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14 | 14 | cnv_clk : IN STD_LOGIC; |
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15 | 15 | cnv_rstn : IN STD_LOGIC; |
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16 | 16 | |
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17 | 17 | cnv : OUT STD_LOGIC; |
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18 | 18 | |
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19 | 19 | clk : IN STD_LOGIC; |
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20 | 20 | rstn : IN STD_LOGIC; |
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21 | 21 | ADC_data : IN Samples14; |
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22 | 22 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
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23 | 23 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
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24 | 24 | sample_val : OUT STD_LOGIC |
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25 | 25 | ); |
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26 | 26 | END top_ad_conv_RHF1401; |
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27 | 27 | |
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28 | 28 | ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401 IS |
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29 | 29 | |
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30 | 30 | SIGNAL cnv_cycle_counter : INTEGER; |
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31 | 31 | SIGNAL cnv_s : STD_LOGIC; |
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32 | 32 | SIGNAL cnv_sync : STD_LOGIC; |
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33 | 33 | |
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34 | 34 | BEGIN |
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35 | 35 | |
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36 | 36 | |
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37 | 37 | ----------------------------------------------------------------------------- |
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38 | 38 | -- CONV |
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39 | 39 | ----------------------------------------------------------------------------- |
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40 | 40 | PROCESS (cnv_clk, cnv_rstn) |
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41 | 41 | BEGIN -- PROCESS |
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42 | 42 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
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43 | 43 | cnv_cycle_counter <= 0; |
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44 | 44 | cnv_s <= '0'; |
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45 | 45 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
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46 | 46 | -- IF cnv_run = '1' THEN |
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47 | IF cnv_cycle_counter < ncycle_cnv THEN | |
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47 | IF cnv_cycle_counter < ncycle_cnv-1 THEN | |
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48 | 48 | cnv_cycle_counter <= cnv_cycle_counter +1; |
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49 | 49 | IF cnv_cycle_counter < ncycle_cnv_high THEN |
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50 | 50 | cnv_s <= '1'; |
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51 | 51 | ELSE |
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52 | 52 | cnv_s <= '0'; |
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53 | 53 | END IF; |
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54 | 54 | ELSE |
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55 | 55 | cnv_s <= '1'; |
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56 | 56 | cnv_cycle_counter <= 0; |
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57 | 57 | END IF; |
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58 | 58 | --ELSE |
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59 | 59 | -- cnv_s <= '0'; |
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60 | 60 | -- cnv_cycle_counter <= 0; |
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61 | 61 | --END IF; |
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62 | 62 | END IF; |
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63 | 63 | END PROCESS; |
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64 | 64 | |
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65 | 65 | cnv <= cnv_s; |
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66 | 66 | |
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67 | 67 | |
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68 | 68 | ----------------------------------------------------------------------------- |
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69 | 69 | -- SYNC CNV |
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70 | 70 | ----------------------------------------------------------------------------- |
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71 | 71 | |
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72 | 72 | SYNC_FF_cnv : SYNC_FF |
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73 | 73 | GENERIC MAP ( |
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74 | 74 | NB_FF_OF_SYNC => 2) |
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75 | 75 | PORT MAP ( |
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76 | 76 | clk => clk, |
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77 | 77 | rstn => rstn, |
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78 | 78 | A => cnv_s, |
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79 | 79 | A_sync => cnv_sync); |
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80 | 80 | |
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81 | 81 | ----------------------------------------------------------------------------- |
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82 | 82 | RHF1401_drvr_1: RHF1401_drvr |
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83 | 83 | GENERIC MAP ( |
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84 | 84 | ChanelCount => ChanelCount) |
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85 | 85 | PORT MAP ( |
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86 | 86 | cnv_clk => cnv_sync, |
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87 | 87 | clk => clk, |
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88 | 88 | rstn => rstn, |
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89 | 89 | ADC_data => ADC_data, |
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90 | 90 | --ADC_smpclk => OPEN, |
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91 | 91 | ADC_nOE => ADC_nOE, |
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92 | 92 | sample => sample, |
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93 | 93 | sample_val => sample_val); |
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94 | 94 | |
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95 | 95 | |
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96 | 96 | |
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97 | 97 | |
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98 | 98 | END ar_top_ad_conv_RHF1401; |
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99 | 99 | |
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100 | 100 | |
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101 | 101 | |
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102 | 102 | |
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103 | 103 | |
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109 | 109 | |
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