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Change clk divider parameter of ad_conv_RHF401
pellion -
r349:36f3a1a19c4e JC
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@@ -1,114 +1,114
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 LIBRARY lpp;
5 5 USE lpp.lpp_ad_conv.ALL;
6 6 USE lpp.general_purpose.SYNC_FF;
7 7
8 8 ENTITY top_ad_conv_RHF1401 IS
9 9 GENERIC(
10 10 ChanelCount : INTEGER := 8;
11 11 ncycle_cnv_high : INTEGER := 79;
12 12 ncycle_cnv : INTEGER := 500);
13 13 PORT (
14 14 cnv_clk : IN STD_LOGIC;
15 15 cnv_rstn : IN STD_LOGIC;
16 16
17 17 cnv : OUT STD_LOGIC;
18 18
19 19 clk : IN STD_LOGIC;
20 20 rstn : IN STD_LOGIC;
21 21 ADC_data : IN Samples14;
22 22 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
23 23 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
24 24 sample_val : OUT STD_LOGIC
25 25 );
26 26 END top_ad_conv_RHF1401;
27 27
28 28 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401 IS
29 29
30 30 SIGNAL cnv_cycle_counter : INTEGER;
31 31 SIGNAL cnv_s : STD_LOGIC;
32 32 SIGNAL cnv_sync : STD_LOGIC;
33 33
34 34 BEGIN
35 35
36 36
37 37 -----------------------------------------------------------------------------
38 38 -- CONV
39 39 -----------------------------------------------------------------------------
40 40 PROCESS (cnv_clk, cnv_rstn)
41 41 BEGIN -- PROCESS
42 42 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
43 43 cnv_cycle_counter <= 0;
44 44 cnv_s <= '0';
45 45 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
46 46 -- IF cnv_run = '1' THEN
47 IF cnv_cycle_counter < ncycle_cnv THEN
47 IF cnv_cycle_counter < ncycle_cnv-1 THEN
48 48 cnv_cycle_counter <= cnv_cycle_counter +1;
49 49 IF cnv_cycle_counter < ncycle_cnv_high THEN
50 50 cnv_s <= '1';
51 51 ELSE
52 52 cnv_s <= '0';
53 53 END IF;
54 54 ELSE
55 55 cnv_s <= '1';
56 56 cnv_cycle_counter <= 0;
57 57 END IF;
58 58 --ELSE
59 59 -- cnv_s <= '0';
60 60 -- cnv_cycle_counter <= 0;
61 61 --END IF;
62 62 END IF;
63 63 END PROCESS;
64 64
65 65 cnv <= cnv_s;
66 66
67 67
68 68 -----------------------------------------------------------------------------
69 69 -- SYNC CNV
70 70 -----------------------------------------------------------------------------
71 71
72 72 SYNC_FF_cnv : SYNC_FF
73 73 GENERIC MAP (
74 74 NB_FF_OF_SYNC => 2)
75 75 PORT MAP (
76 76 clk => clk,
77 77 rstn => rstn,
78 78 A => cnv_s,
79 79 A_sync => cnv_sync);
80 80
81 81 -----------------------------------------------------------------------------
82 82 RHF1401_drvr_1: RHF1401_drvr
83 83 GENERIC MAP (
84 84 ChanelCount => ChanelCount)
85 85 PORT MAP (
86 86 cnv_clk => cnv_sync,
87 87 clk => clk,
88 88 rstn => rstn,
89 89 ADC_data => ADC_data,
90 90 --ADC_smpclk => OPEN,
91 91 ADC_nOE => ADC_nOE,
92 92 sample => sample,
93 93 sample_val => sample_val);
94 94
95 95
96 96
97 97
98 98 END ar_top_ad_conv_RHF1401;
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