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Update Sample transformation from ADC to IIR_FILTER
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 ---------------------------------------------------------------------------
86 86 TAG8 : OUT STD_LOGIC;
87 87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 88 );
89 89
90 90 END LFR_em;
91 91
92 92
93 93 ARCHITECTURE beh OF LFR_em IS
94 94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 95 SIGNAL clk_25 : STD_LOGIC := '0';
96 96 SIGNAL clk_24 : STD_LOGIC := '0';
97 97 -----------------------------------------------------------------------------
98 98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 100
101 101 -- CONSTANTS
102 102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106 106
107 107 SIGNAL apbi_ext : apb_slv_in_type;
108 108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113 113
114 114 -- Spacewire signals
115 115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 120 SIGNAL spw_clk : STD_LOGIC;
121 121 SIGNAL swni : grspw_in_type;
122 122 SIGNAL swno : grspw_out_type;
123 123
124 124 --GPIO
125 125 SIGNAL gpioi : gpio_in_type;
126 126 SIGNAL gpioo : gpio_out_type;
127 127
128 128 -- AD Converter ADS7886
129 129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
130 131 SIGNAL sample_val : STD_LOGIC;
131 132 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 133 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 135
135 136 -----------------------------------------------------------------------------
136 137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 138
138 139 -----------------------------------------------------------------------------
139 140 SIGNAL rstn : STD_LOGIC;
140 141 BEGIN -- beh
141 142
142 143 -----------------------------------------------------------------------------
143 144 -- CLK
144 145 -----------------------------------------------------------------------------
145 146 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146 147
147 148 PROCESS(clk100MHz)
148 149 BEGIN
149 150 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 151 clk_50_s <= NOT clk_50_s;
151 152 END IF;
152 153 END PROCESS;
153 154
154 155 PROCESS(clk_50_s)
155 156 BEGIN
156 157 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 158 clk_25 <= NOT clk_25;
158 159 END IF;
159 160 END PROCESS;
160 161
161 162 PROCESS(clk49_152MHz)
162 163 BEGIN
163 164 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 165 clk_24 <= NOT clk_24;
165 166 END IF;
166 167 END PROCESS;
167 168
168 169 -----------------------------------------------------------------------------
169 170
170 171 PROCESS (clk_25, rstn)
171 172 BEGIN -- PROCESS
172 173 IF rstn = '0' THEN -- asynchronous reset (active low)
173 174 led(0) <= '0';
174 175 led(1) <= '0';
175 176 led(2) <= '0';
176 177 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 178 led(0) <= '0';
178 179 led(1) <= '1';
179 180 led(2) <= '1';
180 181 END IF;
181 182 END PROCESS;
182 183
183 184 --
184 185 leon3_soc_1 : leon3_soc
185 186 GENERIC MAP (
186 187 fabtech => apa3e,
187 188 memtech => apa3e,
188 189 padtech => inferred,
189 190 clktech => inferred,
190 191 disas => 0,
191 192 dbguart => 0,
192 193 pclow => 2,
193 194 clk_freq => 25000,
194 195 NB_CPU => 1,
195 196 ENABLE_FPU => 1,
196 197 FPU_NETLIST => 0,
197 198 ENABLE_DSU => 1,
198 199 ENABLE_AHB_UART => 1,
199 200 ENABLE_APB_UART => 1,
200 201 ENABLE_IRQMP => 1,
201 202 ENABLE_GPT => 1,
202 203 NB_AHB_MASTER => NB_AHB_MASTER,
203 204 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 205 NB_APB_SLAVE => NB_APB_SLAVE)
205 206 PORT MAP (
206 207 clk => clk_25,
207 208 reset => rstn,
208 209 errorn => OPEN,
209 210
210 211 ahbrxd => TAG1,
211 212 ahbtxd => TAG3,
212 213 urxd1 => TAG2,
213 214 utxd1 => TAG4,
214 215
215 216 address => address,
216 217 data => data,
217 218 nSRAM_BE0 => nSRAM_BE0,
218 219 nSRAM_BE1 => nSRAM_BE1,
219 220 nSRAM_BE2 => nSRAM_BE2,
220 221 nSRAM_BE3 => nSRAM_BE3,
221 222 nSRAM_WE => nSRAM_WE,
222 223 nSRAM_CE => nSRAM_CE,
223 224 nSRAM_OE => nSRAM_OE,
224 225
225 226 apbi_ext => apbi_ext,
226 227 apbo_ext => apbo_ext,
227 228 ahbi_s_ext => ahbi_s_ext,
228 229 ahbo_s_ext => ahbo_s_ext,
229 230 ahbi_m_ext => ahbi_m_ext,
230 231 ahbo_m_ext => ahbo_m_ext);
231 232
232 233
233 234 -------------------------------------------------------------------------------
234 235 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 236 -------------------------------------------------------------------------------
236 237 apb_lfr_time_management_1 : apb_lfr_time_management
237 238 GENERIC MAP (
238 239 pindex => 6,
239 240 paddr => 6,
240 241 pmask => 16#fff#,
241 242 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 243 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 244 PORT MAP (
244 245 clk25MHz => clk_25,
245 246 clk24_576MHz => clk_24, -- 49.152MHz/2
246 247 resetn => rstn,
247 248 grspw_tick => swno.tickout,
248 249 apbi => apbi_ext,
249 250 apbo => apbo_ext(6),
250 251 coarse_time => coarse_time,
251 252 fine_time => fine_time);
252 253
253 254 -----------------------------------------------------------------------
254 255 --- SpaceWire --------------------------------------------------------
255 256 -----------------------------------------------------------------------
256 257
257 258 -- SPW_EN <= '1';
258 259
259 260 spw_clk <= clk_50_s;
260 261 spw_rxtxclk <= spw_clk;
261 262 spw_rxclkn <= NOT spw_rxtxclk;
262 263
263 264 -- PADS for SPW1
264 265 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 266 PORT MAP (spw1_din, dtmp(0));
266 267 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 268 PORT MAP (spw1_sin, stmp(0));
268 269 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 270 PORT MAP (spw1_dout, swno.d(0));
270 271 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 272 PORT MAP (spw1_sout, swno.s(0));
272 273 -- PADS FOR SPW2
273 274 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 275 PORT MAP (spw2_sin, dtmp(1));
275 276 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 277 PORT MAP (spw2_din, stmp(1));
277 278 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 279 PORT MAP (spw2_dout, swno.d(1));
279 280 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 281 PORT MAP (spw2_sout, swno.s(1));
281 282
282 283 -- GRSPW PHY
283 284 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 285 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 286 spw_phy0 : grspw_phy
286 287 GENERIC MAP(
287 288 tech => apa3e,
288 289 rxclkbuftype => 1,
289 290 scantest => 0)
290 291 PORT MAP(
291 292 rxrst => swno.rxrst,
292 293 di => dtmp(j),
293 294 si => stmp(j),
294 295 rxclko => spw_rxclk(j),
295 296 do => swni.d(j),
296 297 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 298 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 299 END GENERATE spw_inputloop;
299 300
300 301 -- SPW core
301 302 sw0 : grspwm GENERIC MAP(
302 303 tech => apa3e,
303 304 hindex => 1,
304 305 pindex => 5,
305 306 paddr => 5,
306 307 pirq => 11,
307 308 sysfreq => 25000, -- CPU_FREQ
308 309 rmap => 1,
309 310 rmapcrc => 1,
310 311 fifosize1 => 16,
311 312 fifosize2 => 16,
312 313 rxclkbuftype => 1,
313 314 rxunaligned => 0,
314 315 rmapbufs => 4,
315 316 ft => 0,
316 317 netlist => 0,
317 318 ports => 2,
318 319 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 320 memtech => apa3e,
320 321 destkey => 2,
321 322 spwcore => 1
322 323 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 324 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 325 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 326 )
326 327 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 328 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 329 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 330 swni, swno);
330 331
331 332 swni.tickin <= '0';
332 333 swni.rmapen <= '1';
333 334 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 335 swni.tickinraw <= '0';
335 336 swni.timein <= (OTHERS => '0');
336 337 swni.dcrstval <= (OTHERS => '0');
337 338 swni.timerrstval <= (OTHERS => '0');
338 339
339 340 -------------------------------------------------------------------------------
340 341 -- LFR ------------------------------------------------------------------------
341 342 -------------------------------------------------------------------------------
342 343 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 344 GENERIC MAP (
344 345 Mem_use => use_RAM,
345 346 nb_data_by_buffer_size => 32,
346 347 nb_word_by_buffer_size => 30,
347 348 nb_snapshot_param_size => 32,
348 349 delta_vector_size => 32,
349 350 delta_vector_size_f0_2 => 7, -- log2(96)
350 351 pindex => 15,
351 352 paddr => 15,
352 353 pmask => 16#fff#,
353 354 pirq_ms => 6,
354 355 pirq_wfp => 14,
355 356 hindex => 2,
356 top_lfr_version => X"00010A") -- aa.bb.cc version
357 top_lfr_version => X"00010B") -- aa.bb.cc version
357 358 -- AA : BOARD NUMBER
358 359 -- 0 => MINI_LFR
359 360 -- 1 => EM
360 361 PORT MAP (
361 362 clk => clk_25,
362 363 rstn => rstn,
363 sample_B => sample(2 DOWNTO 0),
364 sample_E => sample(7 DOWNTO 3),
364 sample_B => sample_s(2 DOWNTO 0),
365 sample_E => sample_s(7 DOWNTO 3),
365 366 sample_val => sample_val,
366 367 apbi => apbi_ext,
367 368 apbo => apbo_ext(15),
368 369 ahbi => ahbi_m_ext,
369 370 ahbo => ahbo_m_ext(2),
370 371 coarse_time => coarse_time,
371 372 fine_time => fine_time,
372 373 data_shaping_BW => bias_fail_sw,
373 374 observation_reg => observation_reg);
374 375
376
377 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
378 sample_s(I) <= sample(I) & '0' & '0';
379 END GENERATE all_sample;
380
375 381 -----------------------------------------------------------------------------
376 382 --
377 383 -----------------------------------------------------------------------------
378 384 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
379 385 GENERIC MAP (
380 386 ChanelCount => 8,
381 387 ncycle_cnv_high => 40, -- TODO : 79
382 388 ncycle_cnv => 250) -- TODO : 500
383 389 PORT MAP (
384 390 cnv_clk => clk_24, -- TODO : 49.152
385 391 cnv_rstn => rstn, -- ok
386 392 cnv => ADC_smpclk, -- ok
387 393 clk => clk_25, -- ok
388 394 rstn => rstn, -- ok
389 395 ADC_data => ADC_data, -- ok
390 396 ADC_nOE => ADC_OEB_bar_CH, -- ok
391 397 sample => sample, -- ok
392 398 sample_val => sample_val); -- ok
393 399
394 400 TAG8 <= ADC_smpclk;
395 401
396 402 END beh;
Show file before | Show file after | Hide comments
@@ -1,580 +1,587
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 167 SIGNAL sample_val : STD_LOGIC;
167 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 171
171 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 173
173 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 175 -----------------------------------------------------------------------------
175 176
176 177 BEGIN -- beh
177 178
178 179 -----------------------------------------------------------------------------
179 180 -- CLK
180 181 -----------------------------------------------------------------------------
181 182
182 183 PROCESS(clk_50)
183 184 BEGIN
184 185 IF clk_50'EVENT AND clk_50 = '1' THEN
185 186 clk_50_s <= NOT clk_50_s;
186 187 END IF;
187 188 END PROCESS;
188 189
189 190 PROCESS(clk_50_s)
190 191 BEGIN
191 192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 193 clk_25 <= NOT clk_25;
193 194 END IF;
194 195 END PROCESS;
195 196
196 197 PROCESS(clk_49)
197 198 BEGIN
198 199 IF clk_49'EVENT AND clk_49 = '1' THEN
199 200 clk_24 <= NOT clk_24;
200 201 END IF;
201 202 END PROCESS;
202 203
203 204 -----------------------------------------------------------------------------
204 205
205 206 PROCESS (clk_25, reset)
206 207 BEGIN -- PROCESS
207 208 IF reset = '0' THEN -- asynchronous reset (active low)
208 209 LED0 <= '0';
209 210 LED1 <= '0';
210 211 LED2 <= '0';
211 212 --IO1 <= '0';
212 213 --IO2 <= '1';
213 214 --IO3 <= '0';
214 215 --IO4 <= '0';
215 216 --IO5 <= '0';
216 217 --IO6 <= '0';
217 218 --IO7 <= '0';
218 219 --IO8 <= '0';
219 220 --IO9 <= '0';
220 221 --IO10 <= '0';
221 222 --IO11 <= '0';
222 223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 224 LED0 <= '0';
224 225 LED1 <= '1';
225 226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 227 --IO1 <= '1';
227 228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 229 --IO3 <= ADC_SDO(0);
229 230 --IO4 <= ADC_SDO(1);
230 231 --IO5 <= ADC_SDO(2);
231 232 --IO6 <= ADC_SDO(3);
232 233 --IO7 <= ADC_SDO(4);
233 234 --IO8 <= ADC_SDO(5);
234 235 --IO9 <= ADC_SDO(6);
235 236 --IO10 <= ADC_SDO(7);
236 237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 238 END IF;
238 239 END PROCESS;
239 240
240 241 PROCESS (clk_24, reset)
241 242 BEGIN -- PROCESS
242 243 IF reset = '0' THEN -- asynchronous reset (active low)
243 244 I00_s <= '0';
244 245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 246 I00_s <= NOT I00_s ;
246 247 END IF;
247 248 END PROCESS;
248 249 -- IO0 <= I00_s;
249 250
250 251 --UARTs
251 252 nCTS1 <= '1';
252 253 nCTS2 <= '1';
253 254 nDCD2 <= '1';
254 255
255 256 --EXT CONNECTOR
256 257
257 258 --SPACE WIRE
258 259
259 260 leon3_soc_1 : leon3_soc
260 261 GENERIC MAP (
261 262 fabtech => apa3e,
262 263 memtech => apa3e,
263 264 padtech => inferred,
264 265 clktech => inferred,
265 266 disas => 0,
266 267 dbguart => 0,
267 268 pclow => 2,
268 269 clk_freq => 25000,
269 270 NB_CPU => 1,
270 271 ENABLE_FPU => 1,
271 272 FPU_NETLIST => 0,
272 273 ENABLE_DSU => 1,
273 274 ENABLE_AHB_UART => 1,
274 275 ENABLE_APB_UART => 1,
275 276 ENABLE_IRQMP => 1,
276 277 ENABLE_GPT => 1,
277 278 NB_AHB_MASTER => NB_AHB_MASTER,
278 279 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 280 NB_APB_SLAVE => NB_APB_SLAVE)
280 281 PORT MAP (
281 282 clk => clk_25,
282 283 reset => reset,
283 284 errorn => errorn,
284 285 ahbrxd => TXD1,
285 286 ahbtxd => RXD1,
286 287 urxd1 => TXD2,
287 288 utxd1 => RXD2,
288 289 address => SRAM_A,
289 290 data => SRAM_DQ,
290 291 nSRAM_BE0 => SRAM_nBE(0),
291 292 nSRAM_BE1 => SRAM_nBE(1),
292 293 nSRAM_BE2 => SRAM_nBE(2),
293 294 nSRAM_BE3 => SRAM_nBE(3),
294 295 nSRAM_WE => SRAM_nWE,
295 296 nSRAM_CE => SRAM_CE,
296 297 nSRAM_OE => SRAM_nOE,
297 298
298 299 apbi_ext => apbi_ext,
299 300 apbo_ext => apbo_ext,
300 301 ahbi_s_ext => ahbi_s_ext,
301 302 ahbo_s_ext => ahbo_s_ext,
302 303 ahbi_m_ext => ahbi_m_ext,
303 304 ahbo_m_ext => ahbo_m_ext);
304 305
305 306 -------------------------------------------------------------------------------
306 307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 308 -------------------------------------------------------------------------------
308 309 apb_lfr_time_management_1 : apb_lfr_time_management
309 310 GENERIC MAP (
310 311 pindex => 6,
311 312 paddr => 6,
312 313 pmask => 16#fff#,
313 314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 316 PORT MAP (
316 317 clk25MHz => clk_25,
317 318 clk24_576MHz => clk_24, -- 49.152MHz/2
318 319 resetn => reset,
319 320 grspw_tick => swno.tickout,
320 321 apbi => apbi_ext,
321 322 apbo => apbo_ext(6),
322 323 coarse_time => coarse_time,
323 324 fine_time => fine_time);
324 325
325 326 -----------------------------------------------------------------------
326 327 --- SpaceWire --------------------------------------------------------
327 328 -----------------------------------------------------------------------
328 329
329 330 SPW_EN <= '1';
330 331
331 332 spw_clk <= clk_50_s;
332 333 spw_rxtxclk <= spw_clk;
333 334 spw_rxclkn <= NOT spw_rxtxclk;
334 335
335 336 -- PADS for SPW1
336 337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 338 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 340 PORT MAP (SPW_NOM_SIN, stmp(0));
340 341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 345 -- PADS FOR SPW2
345 346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 347 PORT MAP (SPW_RED_SIN, dtmp(1));
347 348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 349 PORT MAP (SPW_RED_DIN, stmp(1));
349 350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 351 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 353 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 354
354 355 -- GRSPW PHY
355 356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 358 spw_phy0 : grspw_phy
358 359 GENERIC MAP(
359 360 tech => apa3e,
360 361 rxclkbuftype => 1,
361 362 scantest => 0)
362 363 PORT MAP(
363 364 rxrst => swno.rxrst,
364 365 di => dtmp(j),
365 366 si => stmp(j),
366 367 rxclko => spw_rxclk(j),
367 368 do => swni.d(j),
368 369 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 371 END GENERATE spw_inputloop;
371 372
372 373 -- SPW core
373 374 sw0 : grspwm GENERIC MAP(
374 375 tech => apa3e,
375 376 hindex => 1,
376 377 pindex => 5,
377 378 paddr => 5,
378 379 pirq => 11,
379 380 sysfreq => 25000, -- CPU_FREQ
380 381 rmap => 1,
381 382 rmapcrc => 1,
382 383 fifosize1 => 16,
383 384 fifosize2 => 16,
384 385 rxclkbuftype => 1,
385 386 rxunaligned => 0,
386 387 rmapbufs => 4,
387 388 ft => 0,
388 389 netlist => 0,
389 390 ports => 2,
390 391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 392 memtech => apa3e,
392 393 destkey => 2,
393 394 spwcore => 1
394 395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 398 )
398 399 PORT MAP(reset, clk_25, spw_rxclk(0),
399 400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 402 swni, swno);
402 403
403 404 swni.tickin <= '0';
404 405 swni.rmapen <= '1';
405 406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 407 swni.tickinraw <= '0';
407 408 swni.timein <= (OTHERS => '0');
408 409 swni.dcrstval <= (OTHERS => '0');
409 410 swni.timerrstval <= (OTHERS => '0');
410 411
411 412 -------------------------------------------------------------------------------
412 413 -- LFR ------------------------------------------------------------------------
413 414 -------------------------------------------------------------------------------
414 415 lpp_lfr_1 : lpp_lfr
415 416 GENERIC MAP (
416 417 Mem_use => use_RAM,
417 418 nb_data_by_buffer_size => 32,
418 419 nb_word_by_buffer_size => 30,
419 420 nb_snapshot_param_size => 32,
420 421 delta_vector_size => 32,
421 422 delta_vector_size_f0_2 => 7, -- log2(96)
422 423 pindex => 15,
423 424 paddr => 15,
424 425 pmask => 16#fff#,
425 426 pirq_ms => 6,
426 427 pirq_wfp => 14,
427 428 hindex => 2,
428 429 top_lfr_version => X"00010A") -- aa.bb.cc version
429 430 PORT MAP (
430 431 clk => clk_25,
431 432 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_B => sample_s(2 DOWNTO 0),
434 sample_E => sample_s(7 DOWNTO 3),
434 435 sample_val => sample_val,
435 436 apbi => apbi_ext,
436 437 apbo => apbo_ext(15),
437 438 ahbi => ahbi_m_ext,
438 439 ahbo => ahbo_m_ext(2),
439 440 coarse_time => coarse_time,
440 441 fine_time => fine_time,
441 442 data_shaping_BW => bias_fail_sw_sig,
442 443 observation_reg => observation_reg);
443 444
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 sample_s(I) <= sample(I) & '0' & '0';
447 END GENERATE all_sample;
448
449
450
444 451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 452 GENERIC MAP(
446 453 ChannelCount => 8,
447 454 SampleNbBits => 14,
448 455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 457 PORT MAP (
451 458 -- CONV
452 459 cnv_clk => clk_24,
453 460 cnv_rstn => reset,
454 461 cnv => ADC_nCS_sig,
455 462 -- DATA
456 463 clk => clk_25,
457 464 rstn => reset,
458 465 sck => ADC_CLK_sig,
459 466 sdo => ADC_SDO_sig,
460 467 -- SAMPLE
461 468 sample => sample,
462 469 sample_val => sample_val);
463 470
464 471 --IO10 <= ADC_SDO_sig(5);
465 472 --IO9 <= ADC_SDO_sig(4);
466 473 --IO8 <= ADC_SDO_sig(3);
467 474
468 475 ADC_nCS <= ADC_nCS_sig;
469 476 ADC_CLK <= ADC_CLK_sig;
470 477 ADC_SDO_sig <= ADC_SDO;
471 478
472 479 ----------------------------------------------------------------------
473 480 --- GPIO -----------------------------------------------------------
474 481 ----------------------------------------------------------------------
475 482
476 483 grgpio0 : grgpio
477 484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479 486
480 487 --pio_pad_0 : iopad
481 488 -- GENERIC MAP (tech => CFG_PADTECH)
482 489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 490 --pio_pad_1 : iopad
484 491 -- GENERIC MAP (tech => CFG_PADTECH)
485 492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 493 --pio_pad_2 : iopad
487 494 -- GENERIC MAP (tech => CFG_PADTECH)
488 495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 496 --pio_pad_3 : iopad
490 497 -- GENERIC MAP (tech => CFG_PADTECH)
491 498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 499 --pio_pad_4 : iopad
493 500 -- GENERIC MAP (tech => CFG_PADTECH)
494 501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 502 --pio_pad_5 : iopad
496 503 -- GENERIC MAP (tech => CFG_PADTECH)
497 504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 505 --pio_pad_6 : iopad
499 506 -- GENERIC MAP (tech => CFG_PADTECH)
500 507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 508 --pio_pad_7 : iopad
502 509 -- GENERIC MAP (tech => CFG_PADTECH)
503 510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504 511
505 512 PROCESS (clk_25, reset)
506 513 BEGIN -- PROCESS
507 514 IF reset = '0' THEN -- asynchronous reset (active low)
508 515 IO0 <= '0';
509 516 IO1 <= '0';
510 517 IO2 <= '0';
511 518 IO3 <= '0';
512 519 IO4 <= '0';
513 520 IO5 <= '0';
514 521 IO6 <= '0';
515 522 IO7 <= '0';
516 523 IO8 <= '0';
517 524 IO9 <= '0';
518 525 IO10 <= '0';
519 526 IO11 <= '0';
520 527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 528 CASE gpioo.dout(1 DOWNTO 0) IS
522 529 WHEN "00" =>
523 530 IO0 <= observation_reg(0 );
524 531 IO1 <= observation_reg(1 );
525 532 IO2 <= observation_reg(2 );
526 533 IO3 <= observation_reg(3 );
527 534 IO4 <= observation_reg(4 );
528 535 IO5 <= observation_reg(5 );
529 536 IO6 <= observation_reg(6 );
530 537 IO7 <= observation_reg(7 );
531 538 IO8 <= observation_reg(8 );
532 539 IO9 <= observation_reg(9 );
533 540 IO10 <= observation_reg(10);
534 541 IO11 <= observation_reg(11);
535 542 WHEN "01" =>
536 543 IO0 <= observation_reg(0 + 12);
537 544 IO1 <= observation_reg(1 + 12);
538 545 IO2 <= observation_reg(2 + 12);
539 546 IO3 <= observation_reg(3 + 12);
540 547 IO4 <= observation_reg(4 + 12);
541 548 IO5 <= observation_reg(5 + 12);
542 549 IO6 <= observation_reg(6 + 12);
543 550 IO7 <= observation_reg(7 + 12);
544 551 IO8 <= observation_reg(8 + 12);
545 552 IO9 <= observation_reg(9 + 12);
546 553 IO10 <= observation_reg(10 + 12);
547 554 IO11 <= observation_reg(11 + 12);
548 555 WHEN "10" =>
549 556 IO0 <= observation_reg(0 + 12 + 12);
550 557 IO1 <= observation_reg(1 + 12 + 12);
551 558 IO2 <= observation_reg(2 + 12 + 12);
552 559 IO3 <= observation_reg(3 + 12 + 12);
553 560 IO4 <= observation_reg(4 + 12 + 12);
554 561 IO5 <= observation_reg(5 + 12 + 12);
555 562 IO6 <= observation_reg(6 + 12 + 12);
556 563 IO7 <= observation_reg(7 + 12 + 12);
557 564 IO8 <= '0';
558 565 IO9 <= '0';
559 566 IO10 <= '0';
560 567 IO11 <= '0';
561 568 WHEN "11" =>
562 569 IO0 <= '0';
563 570 IO1 <= '0';
564 571 IO2 <= '0';
565 572 IO3 <= '0';
566 573 IO4 <= '0';
567 574 IO5 <= '0';
568 575 IO6 <= '0';
569 576 IO7 <= '0';
570 577 IO8 <= '0';
571 578 IO9 <= '0';
572 579 IO10 <= '0';
573 580 IO11 <= '0';
574 581 WHEN OTHERS => NULL;
575 582 END CASE;
576 583
577 584 END IF;
578 585 END PROCESS;
579 586
580 587 END beh;
Show file before | Show file after | Hide comments
@@ -1,764 +1,764
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63 --
64 64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65 65
66 66 --debug
67 67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 68 --debug_f0_data_valid : OUT STD_LOGIC;
69 69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 --debug_f1_data_valid : OUT STD_LOGIC;
71 71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 --debug_f2_data_valid : OUT STD_LOGIC;
73 73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 74 --debug_f3_data_valid : OUT STD_LOGIC;
75 75
76 76 ---- debug FIFO_IN
77 77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85 85
86 86 ----debug FIFO OUT
87 87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95 95
96 96 ----debug DMA IN
97 97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 105 );
106 106 END lpp_lfr;
107 107
108 108 ARCHITECTURE beh OF lpp_lfr IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
110 110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 111 --
112 112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 116 --
117 117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 120 --
121 121 SIGNAL sample_f0_val : STD_LOGIC;
122 122 SIGNAL sample_f1_val : STD_LOGIC;
123 123 SIGNAL sample_f2_val : STD_LOGIC;
124 124 SIGNAL sample_f3_val : STD_LOGIC;
125 125 --
126 126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 130 --
131 131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134 134
135 135 -- SM
136 136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 141 SIGNAL error_bad_component_error : STD_LOGIC;
142 142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155
156 156 -- WFP
157 157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 166
167 167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 170 SIGNAL enable_f0 : STD_LOGIC;
171 171 SIGNAL enable_f1 : STD_LOGIC;
172 172 SIGNAL enable_f2 : STD_LOGIC;
173 173 SIGNAL enable_f3 : STD_LOGIC;
174 174 SIGNAL burst_f0 : STD_LOGIC;
175 175 SIGNAL burst_f1 : STD_LOGIC;
176 176 SIGNAL burst_f2 : STD_LOGIC;
177 177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 181
182 182 SIGNAL run : STD_LOGIC;
183 183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184 184
185 185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 190 --f1
191 191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 196 --f2
197 197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 202 --f3
203 203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208 208
209 209 -----------------------------------------------------------------------------
210 210 --
211 211 -----------------------------------------------------------------------------
212 212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 215 --f1
216 216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 219 --f2
220 220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 223 --f3
224 224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227 227
228 228 -----------------------------------------------------------------------------
229 229 -- DMA RR
230 230 -----------------------------------------------------------------------------
231 231 SIGNAL dma_sel_valid : STD_LOGIC;
232 232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236 236
237 237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239 239
240 240 -----------------------------------------------------------------------------
241 241 -- DMA_REG
242 242 -----------------------------------------------------------------------------
243 243 SIGNAL ongoing_reg : STD_LOGIC;
244 244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 245 SIGNAL dma_send_reg : STD_LOGIC;
246 246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249
250 250
251 251 -----------------------------------------------------------------------------
252 252 -- DMA
253 253 -----------------------------------------------------------------------------
254 254 SIGNAL dma_send : STD_LOGIC;
255 255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 256 SIGNAL dma_done : STD_LOGIC;
257 257 SIGNAL dma_ren : STD_LOGIC;
258 258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 261
262 262 -----------------------------------------------------------------------------
263 263 -- DEBUG
264 264 -----------------------------------------------------------------------------
265 265 --
266 266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270 270
271 271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279 279
280 280 -----------------------------------------------------------------------------
281 281 -- MS
282 282 -----------------------------------------------------------------------------
283 283
284 284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 286 SIGNAL data_ms_valid : STD_LOGIC;
287 287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 288 SIGNAL data_ms_ren : STD_LOGIC;
289 289 SIGNAL data_ms_done : STD_LOGIC;
290 290
291 291 SIGNAL run_ms : STD_LOGIC;
292 292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
293 293
294 294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298 298
299 299
300 300 BEGIN
301 301
302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
302 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
304 304
305 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 END GENERATE all_channel;
305 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 --END GENERATE all_channel;
308 308
309 309 -----------------------------------------------------------------------------
310 310 lpp_lfr_filter_1 : lpp_lfr_filter
311 311 GENERIC MAP (
312 312 Mem_use => Mem_use)
313 313 PORT MAP (
314 314 sample => sample_s,
315 315 sample_val => sample_val,
316 316 clk => clk,
317 317 rstn => rstn,
318 318 data_shaping_SP0 => data_shaping_SP0,
319 319 data_shaping_SP1 => data_shaping_SP1,
320 320 data_shaping_R0 => data_shaping_R0,
321 321 data_shaping_R1 => data_shaping_R1,
322 322 sample_f0_val => sample_f0_val,
323 323 sample_f1_val => sample_f1_val,
324 324 sample_f2_val => sample_f2_val,
325 325 sample_f3_val => sample_f3_val,
326 326 sample_f0_wdata => sample_f0_data,
327 327 sample_f1_wdata => sample_f1_data,
328 328 sample_f2_wdata => sample_f2_data,
329 329 sample_f3_wdata => sample_f3_data);
330 330
331 331 -----------------------------------------------------------------------------
332 332 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
333 333 GENERIC MAP (
334 334 nb_data_by_buffer_size => nb_data_by_buffer_size,
335 335 nb_word_by_buffer_size => nb_word_by_buffer_size,
336 336 nb_snapshot_param_size => nb_snapshot_param_size,
337 337 delta_vector_size => delta_vector_size,
338 338 delta_vector_size_f0_2 => delta_vector_size_f0_2,
339 339 pindex => pindex,
340 340 paddr => paddr,
341 341 pmask => pmask,
342 342 pirq_ms => pirq_ms,
343 343 pirq_wfp => pirq_wfp,
344 344 top_lfr_version => top_lfr_version)
345 345 PORT MAP (
346 346 HCLK => clk,
347 347 HRESETn => rstn,
348 348 apbi => apbi,
349 349 apbo => apbo,
350 350
351 351 run_ms => run_ms,
352 352
353 353 ready_matrix_f0_0 => ready_matrix_f0_0,
354 354 ready_matrix_f0_1 => ready_matrix_f0_1,
355 355 ready_matrix_f1 => ready_matrix_f1,
356 356 ready_matrix_f2 => ready_matrix_f2,
357 357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 358 error_bad_component_error => error_bad_component_error,
359 359 debug_reg => debug_reg,
360 360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 362 status_ready_matrix_f1 => status_ready_matrix_f1,
363 363 status_ready_matrix_f2 => status_ready_matrix_f2,
364 364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 365 status_error_bad_component_error => status_error_bad_component_error,
366 366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 367 config_active_interruption_onError => config_active_interruption_onError,
368 368
369 369 matrix_time_f0_0 => matrix_time_f0_0,
370 370 matrix_time_f0_1 => matrix_time_f0_1,
371 371 matrix_time_f1 => matrix_time_f1,
372 372 matrix_time_f2 => matrix_time_f2,
373 373
374 374 addr_matrix_f0_0 => addr_matrix_f0_0,
375 375 addr_matrix_f0_1 => addr_matrix_f0_1,
376 376 addr_matrix_f1 => addr_matrix_f1,
377 377 addr_matrix_f2 => addr_matrix_f2,
378 378 status_full => status_full,
379 379 status_full_ack => status_full_ack,
380 380 status_full_err => status_full_err,
381 381 status_new_err => status_new_err,
382 382 data_shaping_BW => data_shaping_BW,
383 383 data_shaping_SP0 => data_shaping_SP0,
384 384 data_shaping_SP1 => data_shaping_SP1,
385 385 data_shaping_R0 => data_shaping_R0,
386 386 data_shaping_R1 => data_shaping_R1,
387 387 delta_snapshot => delta_snapshot,
388 388 delta_f0 => delta_f0,
389 389 delta_f0_2 => delta_f0_2,
390 390 delta_f1 => delta_f1,
391 391 delta_f2 => delta_f2,
392 392 nb_data_by_buffer => nb_data_by_buffer,
393 393 nb_word_by_buffer => nb_word_by_buffer,
394 394 nb_snapshot_param => nb_snapshot_param,
395 395 enable_f0 => enable_f0,
396 396 enable_f1 => enable_f1,
397 397 enable_f2 => enable_f2,
398 398 enable_f3 => enable_f3,
399 399 burst_f0 => burst_f0,
400 400 burst_f1 => burst_f1,
401 401 burst_f2 => burst_f2,
402 402 run => run,
403 403 addr_data_f0 => addr_data_f0,
404 404 addr_data_f1 => addr_data_f1,
405 405 addr_data_f2 => addr_data_f2,
406 406 addr_data_f3 => addr_data_f3,
407 407 start_date => start_date,
408 408 ---------------------------------------------------------------------------
409 409 debug_reg0 => debug_reg0,
410 410 debug_reg1 => debug_reg1,
411 411 debug_reg2 => debug_reg2,
412 412 debug_reg3 => debug_reg3,
413 413 debug_reg4 => debug_reg4,
414 414 debug_reg5 => debug_reg5,
415 415 debug_reg6 => debug_reg6,
416 416 debug_reg7 => debug_reg7);
417 417
418 418 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
419 419 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
420 420 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
421 421 -----------------------------------------------------------------------------
422 422 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
423 423 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
424 424 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
425 425 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
426 426
427 427
428 428 -----------------------------------------------------------------------------
429 429 lpp_waveform_1 : lpp_waveform
430 430 GENERIC MAP (
431 431 tech => inferred,
432 432 data_size => 6*16,
433 433 nb_data_by_buffer_size => nb_data_by_buffer_size,
434 434 nb_word_by_buffer_size => nb_word_by_buffer_size,
435 435 nb_snapshot_param_size => nb_snapshot_param_size,
436 436 delta_vector_size => delta_vector_size,
437 437 delta_vector_size_f0_2 => delta_vector_size_f0_2
438 438 )
439 439 PORT MAP (
440 440 clk => clk,
441 441 rstn => rstn,
442 442
443 443 reg_run => run,
444 444 reg_start_date => start_date,
445 445 reg_delta_snapshot => delta_snapshot,
446 446 reg_delta_f0 => delta_f0,
447 447 reg_delta_f0_2 => delta_f0_2,
448 448 reg_delta_f1 => delta_f1,
449 449 reg_delta_f2 => delta_f2,
450 450
451 451 enable_f0 => enable_f0,
452 452 enable_f1 => enable_f1,
453 453 enable_f2 => enable_f2,
454 454 enable_f3 => enable_f3,
455 455 burst_f0 => burst_f0,
456 456 burst_f1 => burst_f1,
457 457 burst_f2 => burst_f2,
458 458
459 459 nb_data_by_buffer => nb_data_by_buffer,
460 460 nb_word_by_buffer => nb_word_by_buffer,
461 461 nb_snapshot_param => nb_snapshot_param,
462 462 status_full => status_full,
463 463 status_full_ack => status_full_ack,
464 464 status_full_err => status_full_err,
465 465 status_new_err => status_new_err,
466 466
467 467 coarse_time => coarse_time,
468 468 fine_time => fine_time,
469 469
470 470 --f0
471 471 addr_data_f0 => addr_data_f0,
472 472 data_f0_in_valid => sample_f0_val,
473 473 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
474 474 --f1
475 475 addr_data_f1 => addr_data_f1,
476 476 data_f1_in_valid => sample_f1_val,
477 477 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
478 478 --f2
479 479 addr_data_f2 => addr_data_f2,
480 480 data_f2_in_valid => sample_f2_val,
481 481 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
482 482 --f3
483 483 addr_data_f3 => addr_data_f3,
484 484 data_f3_in_valid => sample_f3_val,
485 485 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
486 486 -- OUTPUT -- DMA interface
487 487 --f0
488 488 data_f0_addr_out => data_f0_addr_out_s,
489 489 data_f0_data_out => data_f0_data_out,
490 490 data_f0_data_out_valid => data_f0_data_out_valid_s,
491 491 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
492 492 data_f0_data_out_ren => data_f0_data_out_ren,
493 493 --f1
494 494 data_f1_addr_out => data_f1_addr_out_s,
495 495 data_f1_data_out => data_f1_data_out,
496 496 data_f1_data_out_valid => data_f1_data_out_valid_s,
497 497 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
498 498 data_f1_data_out_ren => data_f1_data_out_ren,
499 499 --f2
500 500 data_f2_addr_out => data_f2_addr_out_s,
501 501 data_f2_data_out => data_f2_data_out,
502 502 data_f2_data_out_valid => data_f2_data_out_valid_s,
503 503 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
504 504 data_f2_data_out_ren => data_f2_data_out_ren,
505 505 --f3
506 506 data_f3_addr_out => data_f3_addr_out_s,
507 507 data_f3_data_out => data_f3_data_out,
508 508 data_f3_data_out_valid => data_f3_data_out_valid_s,
509 509 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
510 510 data_f3_data_out_ren => data_f3_data_out_ren ,
511 511
512 512 -------------------------------------------------------------------------
513 513 observation_reg => OPEN
514 514
515 515 );
516 516
517 517
518 518 -----------------------------------------------------------------------------
519 519 -- TEMP
520 520 -----------------------------------------------------------------------------
521 521
522 522 PROCESS (clk, rstn)
523 523 BEGIN -- PROCESS
524 524 IF rstn = '0' THEN -- asynchronous reset (active low)
525 525 data_f0_data_out_valid <= '0';
526 526 data_f0_data_out_valid_burst <= '0';
527 527 data_f1_data_out_valid <= '0';
528 528 data_f1_data_out_valid_burst <= '0';
529 529 data_f2_data_out_valid <= '0';
530 530 data_f2_data_out_valid_burst <= '0';
531 531 data_f3_data_out_valid <= '0';
532 532 data_f3_data_out_valid_burst <= '0';
533 533 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
534 534 data_f0_data_out_valid <= data_f0_data_out_valid_s;
535 535 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
536 536 data_f1_data_out_valid <= data_f1_data_out_valid_s;
537 537 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
538 538 data_f2_data_out_valid <= data_f2_data_out_valid_s;
539 539 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
540 540 data_f3_data_out_valid <= data_f3_data_out_valid_s;
541 541 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
542 542 END IF;
543 543 END PROCESS;
544 544
545 545 data_f0_addr_out <= data_f0_addr_out_s;
546 546 data_f1_addr_out <= data_f1_addr_out_s;
547 547 data_f2_addr_out <= data_f2_addr_out_s;
548 548 data_f3_addr_out <= data_f3_addr_out_s;
549 549
550 550 -----------------------------------------------------------------------------
551 551 -- RoundRobin Selection For DMA
552 552 -----------------------------------------------------------------------------
553 553
554 554 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
555 555 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
556 556 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
557 557 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
558 558
559 559 RR_Arbiter_4_1 : RR_Arbiter_4
560 560 PORT MAP (
561 561 clk => clk,
562 562 rstn => rstn,
563 563 in_valid => dma_rr_valid,
564 564 out_grant => dma_rr_grant_s);
565 565
566 566 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
567 567 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
568 568 dma_rr_valid_ms(2) <= '0';
569 569 dma_rr_valid_ms(3) <= '0';
570 570
571 571 RR_Arbiter_4_2 : RR_Arbiter_4
572 572 PORT MAP (
573 573 clk => clk,
574 574 rstn => rstn,
575 575 in_valid => dma_rr_valid_ms,
576 576 out_grant => dma_rr_grant_ms);
577 577
578 578 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
579 579
580 580
581 581 -----------------------------------------------------------------------------
582 582 -- in : dma_rr_grant
583 583 -- send
584 584 -- out : dma_sel
585 585 -- dma_valid_burst
586 586 -- dma_sel_valid
587 587 -----------------------------------------------------------------------------
588 588 PROCESS (clk, rstn)
589 589 BEGIN -- PROCESS
590 590 IF rstn = '0' THEN -- asynchronous reset (active low)
591 591 dma_sel <= (OTHERS => '0');
592 592 dma_send <= '0';
593 593 dma_valid_burst <= '0';
594 594 data_ms_done <= '0';
595 595 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
596 596 IF run = '1' THEN
597 597 data_ms_done <= '0';
598 598 IF dma_sel = "00000" OR dma_done = '1' THEN
599 599 dma_sel <= dma_rr_grant;
600 600 IF dma_rr_grant(0) = '1' THEN
601 601 dma_send <= '1';
602 602 dma_valid_burst <= data_f0_data_out_valid_burst;
603 603 dma_sel_valid <= data_f0_data_out_valid;
604 604 ELSIF dma_rr_grant(1) = '1' THEN
605 605 dma_send <= '1';
606 606 dma_valid_burst <= data_f1_data_out_valid_burst;
607 607 dma_sel_valid <= data_f1_data_out_valid;
608 608 ELSIF dma_rr_grant(2) = '1' THEN
609 609 dma_send <= '1';
610 610 dma_valid_burst <= data_f2_data_out_valid_burst;
611 611 dma_sel_valid <= data_f2_data_out_valid;
612 612 ELSIF dma_rr_grant(3) = '1' THEN
613 613 dma_send <= '1';
614 614 dma_valid_burst <= data_f3_data_out_valid_burst;
615 615 dma_sel_valid <= data_f3_data_out_valid;
616 616 ELSIF dma_rr_grant(4) = '1' THEN
617 617 dma_send <= '1';
618 618 dma_valid_burst <= data_ms_valid_burst;
619 619 dma_sel_valid <= data_ms_valid;
620 620 END IF;
621 621
622 622 IF dma_sel(4) = '1' THEN
623 623 data_ms_done <= '1';
624 624 END IF;
625 625 ELSE
626 626 dma_sel <= dma_sel;
627 627 dma_send <= '0';
628 628 END IF;
629 629 ELSE
630 630 data_ms_done <= '0';
631 631 dma_sel <= (OTHERS => '0');
632 632 dma_send <= '0';
633 633 dma_valid_burst <= '0';
634 634 END IF;
635 635 END IF;
636 636 END PROCESS;
637 637
638 638
639 639 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
640 640 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
641 641 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
642 642 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
643 643 data_ms_addr;
644 644
645 645 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
646 646 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
647 647 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
648 648 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
649 649 data_ms_data;
650 650
651 651 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
652 652 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
653 653 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
654 654 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
655 655 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
656 656
657 657 dma_data_2 <= dma_data;
658 658
659 659
660 660
661 661
662 662
663 663 -----------------------------------------------------------------------------
664 664 -- DEBUG -- DMA IN
665 665 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
666 666 --debug_f0_data_dma_in <= dma_data;
667 667 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
668 668 --debug_f1_data_dma_in <= dma_data;
669 669 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
670 670 --debug_f2_data_dma_in <= dma_data;
671 671 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
672 672 --debug_f3_data_dma_in <= dma_data;
673 673 -----------------------------------------------------------------------------
674 674
675 675 -----------------------------------------------------------------------------
676 676 -- DMA
677 677 -----------------------------------------------------------------------------
678 678 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
679 679 GENERIC MAP (
680 680 tech => inferred,
681 681 hindex => hindex)
682 682 PORT MAP (
683 683 HCLK => clk,
684 684 HRESETn => rstn,
685 685 run => run,
686 686 AHB_Master_In => ahbi,
687 687 AHB_Master_Out => ahbo,
688 688
689 689 send => dma_send,
690 690 valid_burst => dma_valid_burst,
691 691 done => dma_done,
692 692 ren => dma_ren,
693 693 address => dma_address,
694 694 data => dma_data_2);
695 695
696 696 -----------------------------------------------------------------------------
697 697 -- Matrix Spectral
698 698 -----------------------------------------------------------------------------
699 699 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
700 700 NOT(sample_f0_val) & NOT(sample_f0_val);
701 701 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
702 702 NOT(sample_f1_val) & NOT(sample_f1_val);
703 703 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
704 704 NOT(sample_f3_val) & NOT(sample_f3_val);
705 705
706 706 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
707 707 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
708 708 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
709 709
710 710 -------------------------------------------------------------------------------
711 711
712 712 ms_softandhard_rstn <= rstn AND run_ms AND run;
713 713
714 714 -----------------------------------------------------------------------------
715 715 lpp_lfr_ms_1 : lpp_lfr_ms
716 716 GENERIC MAP (
717 717 Mem_use => Mem_use)
718 718 PORT MAP (
719 719 clk => clk,
720 720 rstn => ms_softandhard_rstn, --rstn,
721 721
722 722 coarse_time => coarse_time,
723 723 fine_time => fine_time,
724 724
725 725 sample_f0_wen => sample_f0_wen,
726 726 sample_f0_wdata => sample_f0_wdata,
727 727 sample_f1_wen => sample_f1_wen,
728 728 sample_f1_wdata => sample_f1_wdata,
729 729 sample_f3_wen => sample_f3_wen,
730 730 sample_f3_wdata => sample_f3_wdata,
731 731
732 732 dma_addr => data_ms_addr, --
733 733 dma_data => data_ms_data, --
734 734 dma_valid => data_ms_valid, --
735 735 dma_valid_burst => data_ms_valid_burst, --
736 736 dma_ren => data_ms_ren, --
737 737 dma_done => data_ms_done, --
738 738
739 739 ready_matrix_f0_0 => ready_matrix_f0_0,
740 740 ready_matrix_f0_1 => ready_matrix_f0_1,
741 741 ready_matrix_f1 => ready_matrix_f1,
742 742 ready_matrix_f2 => ready_matrix_f2,
743 743 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
744 744 error_bad_component_error => error_bad_component_error,
745 745 debug_reg => observation_reg, --debug_reg,
746 746 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
747 747 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
748 748 status_ready_matrix_f1 => status_ready_matrix_f1,
749 749 status_ready_matrix_f2 => status_ready_matrix_f2,
750 750 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
751 751 status_error_bad_component_error => status_error_bad_component_error,
752 752 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
753 753 config_active_interruption_onError => config_active_interruption_onError,
754 754 addr_matrix_f0_0 => addr_matrix_f0_0,
755 755 addr_matrix_f0_1 => addr_matrix_f0_1,
756 756 addr_matrix_f1 => addr_matrix_f1,
757 757 addr_matrix_f2 => addr_matrix_f2,
758 758
759 759 matrix_time_f0_0 => matrix_time_f0_0,
760 760 matrix_time_f0_1 => matrix_time_f0_1,
761 761 matrix_time_f1 => matrix_time_f1,
762 762 matrix_time_f2 => matrix_time_f2);
763 763
764 764 END beh;
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@@ -1,701 +1,702
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr_WFP_nMS IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63 --
64 64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65 65
66 66 --debug
67 67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 68 --debug_f0_data_valid : OUT STD_LOGIC;
69 69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 --debug_f1_data_valid : OUT STD_LOGIC;
71 71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 --debug_f2_data_valid : OUT STD_LOGIC;
73 73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 74 --debug_f3_data_valid : OUT STD_LOGIC;
75 75
76 76 ---- debug FIFO_IN
77 77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85 85
86 86 ----debug FIFO OUT
87 87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95 95
96 96 ----debug DMA IN
97 97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 105 );
106 106 END lpp_lfr_WFP_nMS;
107 107
108 108 ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 -- SIGNAL sample : Samples14v(7 DOWNTO 0);
110 110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 111 --
112 112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 116 --
117 117 -- SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 118 -- SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 119 -- SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 120 --
121 121 SIGNAL sample_f0_val : STD_LOGIC;
122 122 SIGNAL sample_f1_val : STD_LOGIC;
123 123 SIGNAL sample_f2_val : STD_LOGIC;
124 124 SIGNAL sample_f3_val : STD_LOGIC;
125 125 --
126 126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 130 --
131 131 --SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 --SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 133 --SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134 134
135 135 -- SM
136 136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 141 SIGNAL error_bad_component_error : STD_LOGIC;
142 142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155
156 156 -- WFP
157 157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 166
167 167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 170 SIGNAL enable_f0 : STD_LOGIC;
171 171 SIGNAL enable_f1 : STD_LOGIC;
172 172 SIGNAL enable_f2 : STD_LOGIC;
173 173 SIGNAL enable_f3 : STD_LOGIC;
174 174 SIGNAL burst_f0 : STD_LOGIC;
175 175 SIGNAL burst_f1 : STD_LOGIC;
176 176 SIGNAL burst_f2 : STD_LOGIC;
177 177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 181
182 182 SIGNAL run : STD_LOGIC;
183 183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184 184
185 185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 190 --f1
191 191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 196 --f2
197 197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 202 --f3
203 203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208 208
209 209 -----------------------------------------------------------------------------
210 210 --
211 211 -----------------------------------------------------------------------------
212 212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 215 --f1
216 216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 219 --f2
220 220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 223 --f3
224 224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227 227
228 228 -----------------------------------------------------------------------------
229 229 -- DMA RR
230 230 -----------------------------------------------------------------------------
231 231 SIGNAL dma_sel_valid : STD_LOGIC;
232 232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236 236
237 237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239 239
240 240 -----------------------------------------------------------------------------
241 241 -- DMA_REG
242 242 -----------------------------------------------------------------------------
243 243 SIGNAL ongoing_reg : STD_LOGIC;
244 244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 245 SIGNAL dma_send_reg : STD_LOGIC;
246 246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249
250 250
251 251 -----------------------------------------------------------------------------
252 252 -- DMA
253 253 -----------------------------------------------------------------------------
254 254 SIGNAL dma_send : STD_LOGIC;
255 255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 256 SIGNAL dma_done : STD_LOGIC;
257 257 SIGNAL dma_ren : STD_LOGIC;
258 258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 261
262 262 -----------------------------------------------------------------------------
263 263 -- DEBUG
264 264 -----------------------------------------------------------------------------
265 265 --
266 266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270 270
271 271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279 279
280 280 -----------------------------------------------------------------------------
281 281 -- MS
282 282 -----------------------------------------------------------------------------
283 283
284 284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 286 SIGNAL data_ms_valid : STD_LOGIC;
287 287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 288 SIGNAL data_ms_ren : STD_LOGIC;
289 289 SIGNAL data_ms_done : STD_LOGIC;
290 290
291 291 SIGNAL run_ms : STD_LOGIC;
292 292 --SIGNAL ms_softandhard_rstn : STD_LOGIC;
293 293
294 294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298 298
299 299
300 300 BEGIN
301 301
302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
302 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
304 304
305 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 END GENERATE all_channel;
305 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 -- --sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 -- sample_s(i) <= sample(i) & '0' & '0';
308 --END GENERATE all_channel;
308 309
309 310 -----------------------------------------------------------------------------
310 311 lpp_lfr_filter_1 : lpp_lfr_filter
311 312 GENERIC MAP (
312 313 Mem_use => Mem_use)
313 314 PORT MAP (
314 315 sample => sample_s,
315 316 sample_val => sample_val,
316 317 clk => clk,
317 318 rstn => rstn,
318 319 data_shaping_SP0 => data_shaping_SP0,
319 320 data_shaping_SP1 => data_shaping_SP1,
320 321 data_shaping_R0 => data_shaping_R0,
321 322 data_shaping_R1 => data_shaping_R1,
322 323 sample_f0_val => sample_f0_val,
323 324 sample_f1_val => sample_f1_val,
324 325 sample_f2_val => sample_f2_val,
325 326 sample_f3_val => sample_f3_val,
326 327 sample_f0_wdata => sample_f0_data,
327 328 sample_f1_wdata => sample_f1_data,
328 329 sample_f2_wdata => sample_f2_data,
329 330 sample_f3_wdata => sample_f3_data);
330 331
331 332 -----------------------------------------------------------------------------
332 333 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
333 334 GENERIC MAP (
334 335 nb_data_by_buffer_size => nb_data_by_buffer_size,
335 336 nb_word_by_buffer_size => nb_word_by_buffer_size,
336 337 nb_snapshot_param_size => nb_snapshot_param_size,
337 338 delta_vector_size => delta_vector_size,
338 339 delta_vector_size_f0_2 => delta_vector_size_f0_2,
339 340 pindex => pindex,
340 341 paddr => paddr,
341 342 pmask => pmask,
342 343 pirq_ms => pirq_ms,
343 344 pirq_wfp => pirq_wfp,
344 345 top_lfr_version => top_lfr_version)
345 346 PORT MAP (
346 347 HCLK => clk,
347 348 HRESETn => rstn,
348 349 apbi => apbi,
349 350 apbo => apbo,
350 351
351 352 run_ms => run_ms,
352 353
353 354 ready_matrix_f0_0 => ready_matrix_f0_0,
354 355 ready_matrix_f0_1 => ready_matrix_f0_1,
355 356 ready_matrix_f1 => ready_matrix_f1,
356 357 ready_matrix_f2 => ready_matrix_f2,
357 358 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 359 error_bad_component_error => error_bad_component_error,
359 360 debug_reg => debug_reg,
360 361 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 362 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 363 status_ready_matrix_f1 => status_ready_matrix_f1,
363 364 status_ready_matrix_f2 => status_ready_matrix_f2,
364 365 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 366 status_error_bad_component_error => status_error_bad_component_error,
366 367 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 368 config_active_interruption_onError => config_active_interruption_onError,
368 369
369 370 matrix_time_f0_0 => matrix_time_f0_0,
370 371 matrix_time_f0_1 => matrix_time_f0_1,
371 372 matrix_time_f1 => matrix_time_f1,
372 373 matrix_time_f2 => matrix_time_f2,
373 374
374 375 addr_matrix_f0_0 => addr_matrix_f0_0,
375 376 addr_matrix_f0_1 => addr_matrix_f0_1,
376 377 addr_matrix_f1 => addr_matrix_f1,
377 378 addr_matrix_f2 => addr_matrix_f2,
378 379 status_full => status_full,
379 380 status_full_ack => status_full_ack,
380 381 status_full_err => status_full_err,
381 382 status_new_err => status_new_err,
382 383 data_shaping_BW => data_shaping_BW,
383 384 data_shaping_SP0 => data_shaping_SP0,
384 385 data_shaping_SP1 => data_shaping_SP1,
385 386 data_shaping_R0 => data_shaping_R0,
386 387 data_shaping_R1 => data_shaping_R1,
387 388 delta_snapshot => delta_snapshot,
388 389 delta_f0 => delta_f0,
389 390 delta_f0_2 => delta_f0_2,
390 391 delta_f1 => delta_f1,
391 392 delta_f2 => delta_f2,
392 393 nb_data_by_buffer => nb_data_by_buffer,
393 394 nb_word_by_buffer => nb_word_by_buffer,
394 395 nb_snapshot_param => nb_snapshot_param,
395 396 enable_f0 => enable_f0,
396 397 enable_f1 => enable_f1,
397 398 enable_f2 => enable_f2,
398 399 enable_f3 => enable_f3,
399 400 burst_f0 => burst_f0,
400 401 burst_f1 => burst_f1,
401 402 burst_f2 => burst_f2,
402 403 run => run,
403 404 addr_data_f0 => addr_data_f0,
404 405 addr_data_f1 => addr_data_f1,
405 406 addr_data_f2 => addr_data_f2,
406 407 addr_data_f3 => addr_data_f3,
407 408 start_date => start_date,
408 409 ---------------------------------------------------------------------------
409 410 debug_reg0 => debug_reg0,
410 411 debug_reg1 => debug_reg1,
411 412 debug_reg2 => debug_reg2,
412 413 debug_reg3 => debug_reg3,
413 414 debug_reg4 => debug_reg4,
414 415 debug_reg5 => debug_reg5,
415 416 debug_reg6 => debug_reg6,
416 417 debug_reg7 => debug_reg7);
417 418
418 419 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
419 420 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
420 421 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
421 422 -----------------------------------------------------------------------------
422 423 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
423 424 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
424 425 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
425 426 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
426 427
427 428
428 429 -----------------------------------------------------------------------------
429 430 lpp_waveform_1 : lpp_waveform
430 431 GENERIC MAP (
431 432 tech => inferred,
432 433 data_size => 6*16,
433 434 nb_data_by_buffer_size => nb_data_by_buffer_size,
434 435 nb_word_by_buffer_size => nb_word_by_buffer_size,
435 436 nb_snapshot_param_size => nb_snapshot_param_size,
436 437 delta_vector_size => delta_vector_size,
437 438 delta_vector_size_f0_2 => delta_vector_size_f0_2
438 439 )
439 440 PORT MAP (
440 441 clk => clk,
441 442 rstn => rstn,
442 443
443 444 reg_run => run,
444 445 reg_start_date => start_date,
445 446 reg_delta_snapshot => delta_snapshot,
446 447 reg_delta_f0 => delta_f0,
447 448 reg_delta_f0_2 => delta_f0_2,
448 449 reg_delta_f1 => delta_f1,
449 450 reg_delta_f2 => delta_f2,
450 451
451 452 enable_f0 => enable_f0,
452 453 enable_f1 => enable_f1,
453 454 enable_f2 => enable_f2,
454 455 enable_f3 => enable_f3,
455 456 burst_f0 => burst_f0,
456 457 burst_f1 => burst_f1,
457 458 burst_f2 => burst_f2,
458 459
459 460 nb_data_by_buffer => nb_data_by_buffer,
460 461 nb_word_by_buffer => nb_word_by_buffer,
461 462 nb_snapshot_param => nb_snapshot_param,
462 463 status_full => status_full,
463 464 status_full_ack => status_full_ack,
464 465 status_full_err => status_full_err,
465 466 status_new_err => status_new_err,
466 467
467 468 coarse_time => coarse_time,
468 469 fine_time => fine_time,
469 470
470 471 --f0
471 472 addr_data_f0 => addr_data_f0,
472 473 data_f0_in_valid => sample_f0_val,
473 474 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
474 475 --f1
475 476 addr_data_f1 => addr_data_f1,
476 477 data_f1_in_valid => sample_f1_val,
477 478 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
478 479 --f2
479 480 addr_data_f2 => addr_data_f2,
480 481 data_f2_in_valid => sample_f2_val,
481 482 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
482 483 --f3
483 484 addr_data_f3 => addr_data_f3,
484 485 data_f3_in_valid => sample_f3_val,
485 486 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
486 487 -- OUTPUT -- DMA interface
487 488 --f0
488 489 data_f0_addr_out => data_f0_addr_out_s,
489 490 data_f0_data_out => data_f0_data_out,
490 491 data_f0_data_out_valid => data_f0_data_out_valid_s,
491 492 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
492 493 data_f0_data_out_ren => data_f0_data_out_ren,
493 494 --f1
494 495 data_f1_addr_out => data_f1_addr_out_s,
495 496 data_f1_data_out => data_f1_data_out,
496 497 data_f1_data_out_valid => data_f1_data_out_valid_s,
497 498 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
498 499 data_f1_data_out_ren => data_f1_data_out_ren,
499 500 --f2
500 501 data_f2_addr_out => data_f2_addr_out_s,
501 502 data_f2_data_out => data_f2_data_out,
502 503 data_f2_data_out_valid => data_f2_data_out_valid_s,
503 504 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
504 505 data_f2_data_out_ren => data_f2_data_out_ren,
505 506 --f3
506 507 data_f3_addr_out => data_f3_addr_out_s,
507 508 data_f3_data_out => data_f3_data_out,
508 509 data_f3_data_out_valid => data_f3_data_out_valid_s,
509 510 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
510 511 data_f3_data_out_ren => data_f3_data_out_ren ,
511 512
512 513 -------------------------------------------------------------------------
513 514 observation_reg => OPEN
514 515
515 516 );
516 517
517 518
518 519 -----------------------------------------------------------------------------
519 520 -- TEMP
520 521 -----------------------------------------------------------------------------
521 522
522 523 PROCESS (clk, rstn)
523 524 BEGIN -- PROCESS
524 525 IF rstn = '0' THEN -- asynchronous reset (active low)
525 526 data_f0_data_out_valid <= '0';
526 527 data_f0_data_out_valid_burst <= '0';
527 528 data_f1_data_out_valid <= '0';
528 529 data_f1_data_out_valid_burst <= '0';
529 530 data_f2_data_out_valid <= '0';
530 531 data_f2_data_out_valid_burst <= '0';
531 532 data_f3_data_out_valid <= '0';
532 533 data_f3_data_out_valid_burst <= '0';
533 534 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
534 535 data_f0_data_out_valid <= data_f0_data_out_valid_s;
535 536 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
536 537 data_f1_data_out_valid <= data_f1_data_out_valid_s;
537 538 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
538 539 data_f2_data_out_valid <= data_f2_data_out_valid_s;
539 540 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
540 541 data_f3_data_out_valid <= data_f3_data_out_valid_s;
541 542 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
542 543 END IF;
543 544 END PROCESS;
544 545
545 546 data_f0_addr_out <= data_f0_addr_out_s;
546 547 data_f1_addr_out <= data_f1_addr_out_s;
547 548 data_f2_addr_out <= data_f2_addr_out_s;
548 549 data_f3_addr_out <= data_f3_addr_out_s;
549 550
550 551 -----------------------------------------------------------------------------
551 552 -- RoundRobin Selection For DMA
552 553 -----------------------------------------------------------------------------
553 554
554 555 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
555 556 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
556 557 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
557 558 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
558 559
559 560 RR_Arbiter_4_1 : RR_Arbiter_4
560 561 PORT MAP (
561 562 clk => clk,
562 563 rstn => rstn,
563 564 in_valid => dma_rr_valid,
564 565 out_grant => dma_rr_grant_s);
565 566
566 567 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
567 568 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
568 569 dma_rr_valid_ms(2) <= '0';
569 570 dma_rr_valid_ms(3) <= '0';
570 571
571 572 RR_Arbiter_4_2 : RR_Arbiter_4
572 573 PORT MAP (
573 574 clk => clk,
574 575 rstn => rstn,
575 576 in_valid => dma_rr_valid_ms,
576 577 out_grant => dma_rr_grant_ms);
577 578
578 579 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
579 580
580 581
581 582 -----------------------------------------------------------------------------
582 583 -- in : dma_rr_grant
583 584 -- send
584 585 -- out : dma_sel
585 586 -- dma_valid_burst
586 587 -- dma_sel_valid
587 588 -----------------------------------------------------------------------------
588 589 PROCESS (clk, rstn)
589 590 BEGIN -- PROCESS
590 591 IF rstn = '0' THEN -- asynchronous reset (active low)
591 592 dma_sel <= (OTHERS => '0');
592 593 dma_send <= '0';
593 594 dma_valid_burst <= '0';
594 595 data_ms_done <= '0';
595 596 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
596 597 IF run = '1' THEN
597 598 data_ms_done <= '0';
598 599 IF dma_sel = "00000" OR dma_done = '1' THEN
599 600 dma_sel <= dma_rr_grant;
600 601 IF dma_rr_grant(0) = '1' THEN
601 602 dma_send <= '1';
602 603 dma_valid_burst <= data_f0_data_out_valid_burst;
603 604 dma_sel_valid <= data_f0_data_out_valid;
604 605 ELSIF dma_rr_grant(1) = '1' THEN
605 606 dma_send <= '1';
606 607 dma_valid_burst <= data_f1_data_out_valid_burst;
607 608 dma_sel_valid <= data_f1_data_out_valid;
608 609 ELSIF dma_rr_grant(2) = '1' THEN
609 610 dma_send <= '1';
610 611 dma_valid_burst <= data_f2_data_out_valid_burst;
611 612 dma_sel_valid <= data_f2_data_out_valid;
612 613 ELSIF dma_rr_grant(3) = '1' THEN
613 614 dma_send <= '1';
614 615 dma_valid_burst <= data_f3_data_out_valid_burst;
615 616 dma_sel_valid <= data_f3_data_out_valid;
616 617 ELSIF dma_rr_grant(4) = '1' THEN
617 618 dma_send <= '1';
618 619 dma_valid_burst <= data_ms_valid_burst;
619 620 dma_sel_valid <= data_ms_valid;
620 621 END IF;
621 622
622 623 IF dma_sel(4) = '1' THEN
623 624 data_ms_done <= '1';
624 625 END IF;
625 626 ELSE
626 627 dma_sel <= dma_sel;
627 628 dma_send <= '0';
628 629 END IF;
629 630 ELSE
630 631 data_ms_done <= '0';
631 632 dma_sel <= (OTHERS => '0');
632 633 dma_send <= '0';
633 634 dma_valid_burst <= '0';
634 635 END IF;
635 636 END IF;
636 637 END PROCESS;
637 638
638 639
639 640 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
640 641 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
641 642 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
642 643 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
643 644 data_ms_addr;
644 645
645 646 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
646 647 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
647 648 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
648 649 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
649 650 data_ms_data;
650 651
651 652 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
652 653 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
653 654 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
654 655 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
655 656 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
656 657
657 658 dma_data_2 <= dma_data;
658 659
659 660 -----------------------------------------------------------------------------
660 661 -- DMA
661 662 -----------------------------------------------------------------------------
662 663 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
663 664 GENERIC MAP (
664 665 tech => inferred,
665 666 hindex => hindex)
666 667 PORT MAP (
667 668 HCLK => clk,
668 669 HRESETn => rstn,
669 670 run => run,
670 671 AHB_Master_In => ahbi,
671 672 AHB_Master_Out => ahbo,
672 673
673 674 send => dma_send,
674 675 valid_burst => dma_valid_burst,
675 676 done => dma_done,
676 677 ren => dma_ren,
677 678 address => dma_address,
678 679 data => dma_data_2);
679 680
680 681 -----------------------------------------------------------------------------
681 682 -- Matrix Spectral
682 683 -----------------------------------------------------------------------------
683 684 data_ms_addr <= (OTHERS => '0');
684 685 data_ms_data <= (OTHERS => '0');
685 686 data_ms_valid <= '0';
686 687 data_ms_valid_burst <= '0';
687 688
688 689 ready_matrix_f0_0 <= '0';
689 690 ready_matrix_f0_1 <= '0';
690 691 ready_matrix_f1 <= '0';
691 692 ready_matrix_f2 <= '0';
692 693 error_anticipating_empty_fifo <= '0';
693 694 error_bad_component_error <= '0';
694 695 observation_reg <= (OTHERS => '0');
695 696
696 697 matrix_time_f2 <= (OTHERS => '0');
697 698 matrix_time_f1 <= (OTHERS => '0');
698 699 matrix_time_f0_1 <= (OTHERS => '0');
699 700 matrix_time_f0_0 <= (OTHERS => '0');
700 701
701 702 END beh;
Show file before | Show file after | Hide comments
@@ -1,323 +1,323
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16
17 17 COMPONENT lpp_lfr_ms
18 18 GENERIC (
19 19 Mem_use : INTEGER
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 26 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27 27
28 28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 30 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34
35 35 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
36 36 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 37 dma_valid : OUT STD_LOGIC;
38 38 dma_valid_burst : OUT STD_LOGIC;
39 39 dma_ren : IN STD_LOGIC;
40 40 dma_done : IN STD_LOGIC;
41 41
42 42 ready_matrix_f0_0 : OUT STD_LOGIC;
43 43 ready_matrix_f0_1 : OUT STD_LOGIC;
44 44 ready_matrix_f1 : OUT STD_LOGIC;
45 45 ready_matrix_f2 : OUT STD_LOGIC;
46 46 error_anticipating_empty_fifo : OUT STD_LOGIC;
47 47 error_bad_component_error : OUT STD_LOGIC;
48 48 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 49 status_ready_matrix_f0_0 : IN STD_LOGIC;
50 50 status_ready_matrix_f0_1 : IN STD_LOGIC;
51 51 status_ready_matrix_f1 : IN STD_LOGIC;
52 52 status_ready_matrix_f2 : IN STD_LOGIC;
53 53 status_error_anticipating_empty_fifo : IN STD_LOGIC;
54 54 status_error_bad_component_error : IN STD_LOGIC;
55 55 config_active_interruption_onNewMatrix : IN STD_LOGIC;
56 56 config_active_interruption_onError : IN STD_LOGIC;
57 57 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 59 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61
62 62 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
63 63 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
64 64 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
65 65 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
66 66 END COMPONENT;
67 67
68 68 COMPONENT lpp_lfr_ms_fsmdma
69 69 PORT (
70 70 HCLK : IN STD_ULOGIC;
71 71 HRESETn : IN STD_ULOGIC;
72 72 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
73 73 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74 fifo_empty : IN STD_LOGIC;
75 75 fifo_ren : OUT STD_LOGIC;
76 76 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 77 header_val : IN STD_LOGIC;
78 78 header_ack : OUT STD_LOGIC;
79 79 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 81 dma_valid : OUT STD_LOGIC;
82 82 dma_valid_burst : OUT STD_LOGIC;
83 83 dma_ren : IN STD_LOGIC;
84 84 dma_done : IN STD_LOGIC;
85 85 ready_matrix_f0_0 : OUT STD_LOGIC;
86 86 ready_matrix_f0_1 : OUT STD_LOGIC;
87 87 ready_matrix_f1 : OUT STD_LOGIC;
88 88 ready_matrix_f2 : OUT STD_LOGIC;
89 89 error_anticipating_empty_fifo : OUT STD_LOGIC;
90 90 error_bad_component_error : OUT STD_LOGIC;
91 91 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 status_ready_matrix_f0_0 : IN STD_LOGIC;
93 93 status_ready_matrix_f0_1 : IN STD_LOGIC;
94 94 status_ready_matrix_f1 : IN STD_LOGIC;
95 95 status_ready_matrix_f2 : IN STD_LOGIC;
96 96 status_error_anticipating_empty_fifo : IN STD_LOGIC;
97 97 status_error_bad_component_error : IN STD_LOGIC;
98 98 config_active_interruption_onNewMatrix : IN STD_LOGIC;
99 99 config_active_interruption_onError : IN STD_LOGIC;
100 100 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 101 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104
105 105 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
106 106 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
107 107 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 108 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
109 109 );
110 110 END COMPONENT;
111 111
112 112
113 113 COMPONENT lpp_lfr_filter
114 114 GENERIC (
115 115 Mem_use : INTEGER);
116 116 PORT (
117 117 sample : IN Samples(7 DOWNTO 0);
118 118 sample_val : IN STD_LOGIC;
119 119 clk : IN STD_LOGIC;
120 120 rstn : IN STD_LOGIC;
121 121 data_shaping_SP0 : IN STD_LOGIC;
122 122 data_shaping_SP1 : IN STD_LOGIC;
123 123 data_shaping_R0 : IN STD_LOGIC;
124 124 data_shaping_R1 : IN STD_LOGIC;
125 125 sample_f0_val : OUT STD_LOGIC;
126 126 sample_f1_val : OUT STD_LOGIC;
127 127 sample_f2_val : OUT STD_LOGIC;
128 128 sample_f3_val : OUT STD_LOGIC;
129 129 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 130 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 131 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 132 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
133 133 END COMPONENT;
134 134
135 135 COMPONENT lpp_lfr
136 136 GENERIC (
137 137 Mem_use : INTEGER;
138 138 nb_data_by_buffer_size : INTEGER;
139 139 nb_word_by_buffer_size : INTEGER;
140 140 nb_snapshot_param_size : INTEGER;
141 141 delta_vector_size : INTEGER;
142 142 delta_vector_size_f0_2 : INTEGER;
143 143 pindex : INTEGER;
144 144 paddr : INTEGER;
145 145 pmask : INTEGER;
146 146 pirq_ms : INTEGER;
147 147 pirq_wfp : INTEGER;
148 148 hindex : INTEGER;
149 149 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
150 150 );
151 151 PORT (
152 152 clk : IN STD_LOGIC;
153 153 rstn : IN STD_LOGIC;
154 sample_B : IN Samples14v(2 DOWNTO 0);
155 sample_E : IN Samples14v(4 DOWNTO 0);
154 sample_B : IN Samples(2 DOWNTO 0);
155 sample_E : IN Samples(4 DOWNTO 0);
156 156 sample_val : IN STD_LOGIC;
157 157 apbi : IN apb_slv_in_type;
158 158 apbo : OUT apb_slv_out_type;
159 159 ahbi : IN AHB_Mst_In_Type;
160 160 ahbo : OUT AHB_Mst_Out_Type;
161 161 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
162 162 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
163 163 data_shaping_BW : OUT STD_LOGIC;
164 164 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
165 165 );
166 166 END COMPONENT;
167 167
168 168 -----------------------------------------------------------------------------
169 169 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
170 170 -----------------------------------------------------------------------------
171 171 COMPONENT lpp_lfr_WFP_nMS
172 172 GENERIC (
173 173 Mem_use : INTEGER;
174 174 nb_data_by_buffer_size : INTEGER;
175 175 nb_word_by_buffer_size : INTEGER;
176 176 nb_snapshot_param_size : INTEGER;
177 177 delta_vector_size : INTEGER;
178 178 delta_vector_size_f0_2 : INTEGER;
179 179 pindex : INTEGER;
180 180 paddr : INTEGER;
181 181 pmask : INTEGER;
182 182 pirq_ms : INTEGER;
183 183 pirq_wfp : INTEGER;
184 184 hindex : INTEGER;
185 185 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
186 186 PORT (
187 187 clk : IN STD_LOGIC;
188 188 rstn : IN STD_LOGIC;
189 sample_B : IN Samples14v(2 DOWNTO 0);
190 sample_E : IN Samples14v(4 DOWNTO 0);
189 sample_B : IN Samples(2 DOWNTO 0);
190 sample_E : IN Samples(4 DOWNTO 0);
191 191 sample_val : IN STD_LOGIC;
192 192 apbi : IN apb_slv_in_type;
193 193 apbo : OUT apb_slv_out_type;
194 194 ahbi : IN AHB_Mst_In_Type;
195 195 ahbo : OUT AHB_Mst_Out_Type;
196 196 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
198 198 data_shaping_BW : OUT STD_LOGIC;
199 199 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
200 200 END COMPONENT;
201 201 -----------------------------------------------------------------------------
202 202
203 203
204 204 COMPONENT lpp_lfr_apbreg
205 205 GENERIC (
206 206 nb_data_by_buffer_size : INTEGER;
207 207 nb_word_by_buffer_size : INTEGER;
208 208 nb_snapshot_param_size : INTEGER;
209 209 delta_vector_size : INTEGER;
210 210 delta_vector_size_f0_2 : INTEGER;
211 211 pindex : INTEGER;
212 212 paddr : INTEGER;
213 213 pmask : INTEGER;
214 214 pirq_ms : INTEGER;
215 215 pirq_wfp : INTEGER;
216 216 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
217 217 PORT (
218 218 HCLK : IN STD_ULOGIC;
219 219 HRESETn : IN STD_ULOGIC;
220 220 apbi : IN apb_slv_in_type;
221 221 apbo : OUT apb_slv_out_type;
222 222 run_ms : OUT STD_LOGIC;
223 223 ready_matrix_f0_0 : IN STD_LOGIC;
224 224 ready_matrix_f0_1 : IN STD_LOGIC;
225 225 ready_matrix_f1 : IN STD_LOGIC;
226 226 ready_matrix_f2 : IN STD_LOGIC;
227 227 error_anticipating_empty_fifo : IN STD_LOGIC;
228 228 error_bad_component_error : IN STD_LOGIC;
229 229 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
230 230 status_ready_matrix_f0_0 : OUT STD_LOGIC;
231 231 status_ready_matrix_f0_1 : OUT STD_LOGIC;
232 232 status_ready_matrix_f1 : OUT STD_LOGIC;
233 233 status_ready_matrix_f2 : OUT STD_LOGIC;
234 234 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
235 235 status_error_bad_component_error : OUT STD_LOGIC;
236 236 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
237 237 config_active_interruption_onError : OUT STD_LOGIC;
238 238 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 239 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
240 240 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
241 241 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
242 242
243 243 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
244 244 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
245 245 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
246 246 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
247 247
248 248 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
249 249 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 250 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 251 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
252 252 data_shaping_BW : OUT STD_LOGIC;
253 253 data_shaping_SP0 : OUT STD_LOGIC;
254 254 data_shaping_SP1 : OUT STD_LOGIC;
255 255 data_shaping_R0 : OUT STD_LOGIC;
256 256 data_shaping_R1 : OUT STD_LOGIC;
257 257 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
258 258 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
259 259 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
260 260 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
261 261 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
262 262 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
263 263 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
264 264 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
265 265 enable_f0 : OUT STD_LOGIC;
266 266 enable_f1 : OUT STD_LOGIC;
267 267 enable_f2 : OUT STD_LOGIC;
268 268 enable_f3 : OUT STD_LOGIC;
269 269 burst_f0 : OUT STD_LOGIC;
270 270 burst_f1 : OUT STD_LOGIC;
271 271 burst_f2 : OUT STD_LOGIC;
272 272 run : OUT STD_LOGIC;
273 273 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
274 274 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
275 275 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
276 276 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 277 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
278 278 ---------------------------------------------------------------------------
279 279 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
280 280 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
281 281 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 282 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
283 283 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
284 284 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 285 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
286 286 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
287 287 END COMPONENT;
288 288
289 289 COMPONENT lpp_top_ms
290 290 GENERIC (
291 291 Mem_use : INTEGER;
292 292 nb_burst_available_size : INTEGER;
293 293 nb_snapshot_param_size : INTEGER;
294 294 delta_snapshot_size : INTEGER;
295 295 delta_f2_f0_size : INTEGER;
296 296 delta_f2_f1_size : INTEGER;
297 297 pindex : INTEGER;
298 298 paddr : INTEGER;
299 299 pmask : INTEGER;
300 300 pirq_ms : INTEGER;
301 301 pirq_wfp : INTEGER;
302 302 hindex_wfp : INTEGER;
303 303 hindex_ms : INTEGER);
304 304 PORT (
305 305 clk : IN STD_LOGIC;
306 306 rstn : IN STD_LOGIC;
307 307 sample_B : IN Samples14v(2 DOWNTO 0);
308 308 sample_E : IN Samples14v(4 DOWNTO 0);
309 309 sample_val : IN STD_LOGIC;
310 310 apbi : IN apb_slv_in_type;
311 311 apbo : OUT apb_slv_out_type;
312 312 ahbi_ms : IN AHB_Mst_In_Type;
313 313 ahbo_ms : OUT AHB_Mst_Out_Type;
314 314 data_shaping_BW : OUT STD_LOGIC;
315 315 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
316 316 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
317 317 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
318 318 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
319 319
320 320 );
321 321 END COMPONENT;
322 322
323 323 END lpp_lfr_pkg;
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