@@ -58,6 +58,7 vcom_tb: | |||
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58 | 58 | $(CMD_VCOM) lpp lpp_FIFO.vhd |
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59 | 59 | $(CMD_VCOM) lpp spectral_matrix_package.vhd |
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60 | 60 | $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd |
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61 | $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd | |
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61 | 62 | $(CMD_VCOM) lpp lpp_lfr_ms.vhd |
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62 | 63 | $(CMD_VCOM) work TB.vhd |
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63 | 64 | @echo "vcom done" |
@@ -344,7 +345,52 vcom_lpp: | |||
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344 | 345 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
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345 | 346 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
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346 | 347 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
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348 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |
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349 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd | |
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350 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd | |
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351 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd | |
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352 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd | |
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353 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd | |
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354 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd | |
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355 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd | |
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356 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd | |
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357 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd | |
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358 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd | |
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359 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd | |
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360 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd | |
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361 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd | |
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362 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd | |
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363 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd | |
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364 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd | |
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365 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd | |
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366 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd | |
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367 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd | |
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368 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd | |
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369 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd | |
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370 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
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371 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
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372 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
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373 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
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374 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |
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375 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd | |
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376 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd | |
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377 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |
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378 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd | |
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379 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
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380 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd | |
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381 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd | |
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382 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd | |
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383 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd | |
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384 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd | |
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385 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd | |
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386 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd | |
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387 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd | |
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388 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd | |
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389 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd | |
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390 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd | |
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347 | 391 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd |
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392 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |
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393 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
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348 | 394 | @echo "vcom lpp done" |
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349 | 395 | |
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350 | 396 | # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd |
@@ -19,52 +19,64 | |||
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19 | 19 | -- Author : Martin Morlot |
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20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------ |
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22 | library IEEE; | |
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23 |
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24 |
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25 | library lpp; | |
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26 |
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27 |
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28 | library techmap; | |
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29 |
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22 | LIBRARY IEEE; | |
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23 | USE IEEE.std_logic_1164.ALL; | |
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24 | USE IEEE.numeric_std.ALL; | |
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25 | LIBRARY lpp; | |
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26 | USE lpp.lpp_memory.ALL; | |
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27 | USE lpp.iir_filter.ALL; | |
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28 | LIBRARY techmap; | |
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29 | USE techmap.gencomp.ALL; | |
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30 | 30 | |
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31 | entity lppFIFOxN is | |
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32 | generic( | |
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33 |
tech |
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34 |
Mem_use |
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35 |
Data_sz |
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36 |
Addr_sz |
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37 |
FifoCnt |
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38 | Enable_ReUse : std_logic := '0' | |
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31 | ENTITY lppFIFOxN IS | |
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32 | GENERIC( | |
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33 | tech : INTEGER := 0; | |
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34 | Mem_use : INTEGER := use_RAM; | |
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35 | Data_sz : INTEGER RANGE 1 TO 32 := 8; | |
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36 | Addr_sz : INTEGER RANGE 2 TO 12 := 8; | |
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37 | FifoCnt : INTEGER := 1 | |
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39 | 38 | ); |
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40 | port( | |
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41 | rstn : in std_logic; | |
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42 | wclk : in std_logic; | |
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43 | rclk : in std_logic; | |
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44 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
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45 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
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46 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
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47 |
wdata |
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48 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
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49 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
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50 | almost_full : out std_logic_vector(FifoCnt-1 downto 0); -- TODO | |
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51 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
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39 | PORT( | |
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40 | clk : IN STD_LOGIC; | |
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41 | rstn : IN STD_LOGIC; | |
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42 | ||
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43 | ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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44 | ||
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45 | wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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46 | wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); | |
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47 | ||
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48 | ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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49 | rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); | |
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50 | ||
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51 | empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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52 | full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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53 | almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0) | |
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52 | 54 | ); |
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53 | end entity; | |
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55 | END ENTITY; | |
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54 | 56 | |
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55 | 57 | |
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56 |
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58 | ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS | |
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57 | 59 | |
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58 | begin | |
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60 | BEGIN | |
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59 | 61 | |
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60 | fifos: for i in 0 to FifoCnt-1 generate | |
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61 |
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62 | generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) | |
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63 | port map(rstn,ReUse(i), | |
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64 | rclk, | |
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65 | ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open, | |
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66 | wclk, | |
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67 | wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),almost_full(i),open); | |
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68 | end generate; | |
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62 | fifos : FOR i IN 0 TO FifoCnt-1 GENERATE | |
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63 | lpp_fifo_1: lpp_fifo | |
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64 | GENERIC MAP ( | |
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65 | tech => tech, | |
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66 | Mem_use => Mem_use, | |
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67 | DataSz => Data_sz, | |
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68 | AddrSz => Addr_sz) | |
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69 | PORT MAP ( | |
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70 | clk => clk, | |
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71 | rstn => rstn, | |
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72 | reUse => reUse(I), | |
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73 | ren => ren(I), | |
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74 | rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ), | |
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75 | wen => wen(I), | |
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76 | wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)), | |
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77 | empty => empty(I), | |
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78 | full => full(I), | |
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79 | almost_full => almost_full(I)); | |
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80 | END GENERATE; | |
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69 | 81 | |
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70 | end architecture; | |
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82 | END ARCHITECTURE; |
@@ -32,24 +32,26 ENTITY lpp_fifo IS | |||
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32 | 32 | GENERIC( |
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33 | 33 | tech : INTEGER := 0; |
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34 | 34 | Mem_use : INTEGER := use_RAM; |
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35 | Enable_ReUse : STD_LOGIC := '0'; | |
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36 | 35 | DataSz : INTEGER RANGE 1 TO 32 := 8; |
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37 | 36 | AddrSz : INTEGER RANGE 2 TO 12 := 8 |
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38 | 37 | ); |
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39 | 38 | PORT( |
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39 | clk : IN STD_LOGIC; | |
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40 | 40 | rstn : IN STD_LOGIC; |
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41 | ReUse : IN STD_LOGIC; | |
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42 |
r |
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41 | -- | |
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42 | reUse : IN STD_LOGIC; | |
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43 | ||
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44 | --IN | |
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43 | 45 | ren : IN STD_LOGIC; |
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44 | 46 | rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); |
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45 | empty : OUT STD_LOGIC; | |
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46 | raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0); | |
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47 | wclk : IN STD_LOGIC; | |
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47 | ||
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48 | --OUT | |
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48 | 49 | wen : IN STD_LOGIC; |
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49 | 50 | wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); |
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51 | ||
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52 | empty : OUT STD_LOGIC; | |
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50 | 53 | full : OUT STD_LOGIC; |
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51 |
almost_full : OUT STD_LOGIC |
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52 | waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) | |
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54 | almost_full : OUT STD_LOGIC | |
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53 | 55 | ); |
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54 | 56 | END ENTITY; |
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55 | 57 | |
@@ -82,13 +84,13 BEGIN | |||
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82 | 84 | memRAM : IF Mem_use = use_RAM GENERATE |
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83 | 85 | SRAM : syncram_2p |
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84 | 86 | GENERIC MAP(tech, AddrSz, DataSz) |
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85 |
PORT MAP( |
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87 | PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata); | |
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86 | 88 | END GENERATE; |
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87 | 89 | --================================================================================== |
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88 | 90 | memCEL : IF Mem_use = use_CEL GENERATE |
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89 | 91 | CRAM : RAM_CEL |
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90 | 92 | GENERIC MAP(DataSz, AddrSz) |
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91 |
PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, |
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93 | PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn); | |
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92 | 94 | END GENERATE; |
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93 | 95 | --================================================================================== |
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94 | 96 | |
@@ -98,19 +100,19 BEGIN | |||
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98 | 100 | sREN <= REN OR sEmpty; |
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99 | 101 | sRE <= NOT sREN; |
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100 | 102 | |
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101 |
sEmpty_s <= '0' WHEN ReUse = '1' |
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103 | sEmpty_s <= '0' WHEN ReUse = '1' else | |
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102 | 104 | '1' WHEN sEmpty = '1' AND Wen = '1' ELSE |
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103 | 105 | '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE |
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104 | 106 | '0'; |
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105 | 107 | |
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106 | 108 | Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1); |
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107 | 109 | |
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108 |
PROCESS ( |
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110 | PROCESS (clk, rstn) | |
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109 | 111 | BEGIN |
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110 | 112 | IF(rstn = '0')then |
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111 | 113 | Raddr_vect <= (OTHERS => '0'); |
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112 | 114 | sempty <= '1'; |
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113 |
ELSIF( |
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115 | ELSIF(clk'EVENT AND clk = '1')then | |
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114 | 116 | sEmpty <= sempty_s; |
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115 | 117 | |
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116 | 118 | IF(sREN = '0' and sempty = '0')then |
@@ -126,7 +128,7 BEGIN | |||
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126 | 128 | sWEN <= WEN OR sFull; |
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127 | 129 | sWE <= NOT sWEN; |
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128 | 130 | |
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129 |
sFull_s <= '1' WHEN ReUse = '1' |
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131 | sFull_s <= '1' WHEN ReUse = '1' else | |
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130 | 132 | '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE |
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131 | 133 | '1' WHEN sFull = '1' AND REN = '1' ELSE |
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132 | 134 | '0'; |
@@ -137,13 +139,13 BEGIN | |||
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137 | 139 | |
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138 | 140 | Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1); |
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139 | 141 | |
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140 |
PROCESS ( |
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142 | PROCESS (clk, rstn) | |
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141 | 143 | BEGIN |
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142 | 144 | IF(rstn = '0')then |
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143 | 145 | Waddr_vect <= (OTHERS => '0'); |
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144 | 146 | sfull <= '0'; |
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145 | 147 | almost_full_r <= '0'; |
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146 |
ELSIF( |
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148 | ELSIF(clk'EVENT AND clk = '1')then | |
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147 | 149 | sfull <= sfull_s; |
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148 | 150 | almost_full_r <= almost_full_s; |
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149 | 151 | |
@@ -157,8 +159,6 BEGIN | |||
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157 | 159 | almost_full <= almost_full_s; |
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158 | 160 | full <= sFull_s; |
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159 | 161 | empty <= sEmpty_s; |
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160 | waddr <= Waddr_vect; | |
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161 | raddr <= Raddr_vect; | |
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162 | 162 | |
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163 | 163 | END ARCHITECTURE; |
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164 | 164 |
This diff has been collapsed as it changes many lines, (598 lines changed) Show them Hide them | |||
@@ -6,9 +6,13 LIBRARY lpp; | |||
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6 | 6 | USE lpp.lpp_memory.ALL; |
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7 | 7 | USE lpp.iir_filter.ALL; |
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8 | 8 | USE lpp.spectral_matrix_package.ALL; |
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9 | ||
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10 | use lpp.lpp_fft.all; | |
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11 | use lpp.fft_components.all; | |
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9 | USE lpp.lpp_dma_pkg.ALL; | |
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10 | USE lpp.lpp_Header.ALL; | |
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11 | USE lpp.lpp_matrix.ALL; | |
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12 | USE lpp.lpp_matrix.ALL; | |
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13 | USE lpp.lpp_lfr_pkg.ALL; | |
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14 | USE lpp.lpp_fft.ALL; | |
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15 | USE lpp.fft_components.ALL; | |
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12 | 16 | |
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13 | 17 | ENTITY lpp_lfr_ms IS |
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14 | 18 | GENERIC ( |
@@ -116,6 +120,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
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116 | 120 | ----------------------------------------------------------------------------- |
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117 | 121 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
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118 | 122 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
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123 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
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119 | 124 | |
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120 | 125 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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121 | 126 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
@@ -125,7 +130,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
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125 | 130 | ----------------------------------------------------------------------------- |
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126 | 131 | -- FSM LOAD FFT |
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127 | 132 | ----------------------------------------------------------------------------- |
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128 |
TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5 |
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133 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
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129 | 134 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
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130 | 135 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
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131 | 136 | |
@@ -145,6 +150,66 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
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145 | 150 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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146 | 151 | SIGNAL fft_data_valid : STD_LOGIC; |
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147 | 152 | SIGNAL fft_ready : STD_LOGIC; |
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153 | ----------------------------------------------------------------------------- | |
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154 | SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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155 | ----------------------------------------------------------------------------- | |
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156 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
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157 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
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158 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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159 | SIGNAL current_fifo_empty : STD_LOGIC; | |
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160 | SIGNAL current_fifo_locked : STD_LOGIC; | |
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161 | SIGNAL current_fifo_full : STD_LOGIC; | |
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162 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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163 | ||
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164 | ----------------------------------------------------------------------------- | |
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165 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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166 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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167 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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168 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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169 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
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170 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
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171 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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172 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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173 | ----------------------------------------------------------------------------- | |
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174 | SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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175 | SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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176 | SIGNAL HEAD_SM_Wen : STD_LOGIC; | |
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177 | SIGNAL HEAD_Valid : STD_LOGIC; | |
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178 | SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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179 | SIGNAL HEAD_Empty : STD_LOGIC; | |
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180 | SIGNAL HEAD_Read : STD_LOGIC; | |
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181 | ----------------------------------------------------------------------------- | |
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182 | SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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183 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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184 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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185 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
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186 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
|
187 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
188 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
189 | ----------------------------------------------------------------------------- | |
|
190 | SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
191 | SIGNAL DMA_Header_Val : STD_LOGIC; | |
|
192 | SIGNAL DMA_Header_Ack : STD_LOGIC; | |
|
193 | ||
|
194 | ----------------------------------------------------------------------------- | |
|
195 | -- TIME REG & INFOs | |
|
196 | ----------------------------------------------------------------------------- | |
|
197 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
198 | ||
|
199 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
200 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
201 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
202 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
203 | ||
|
204 | SIGNAL time_update_f0_A : STD_LOGIC; | |
|
205 | SIGNAL time_update_f0_B : STD_LOGIC; | |
|
206 | SIGNAL time_update_f1 : STD_LOGIC; | |
|
207 | SIGNAL time_update_f2 : STD_LOGIC; | |
|
208 | -- | |
|
209 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
|
210 | ||
|
211 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
212 | ----------------------------------------------------------------------------- | |
|
148 | 213 | |
|
149 | 214 | BEGIN |
|
150 | 215 | |
@@ -174,21 +239,22 BEGIN | |||
|
174 | 239 | Mem_use => Mem_use, |
|
175 | 240 | Data_sz => 16, |
|
176 | 241 | Addr_sz => 8, |
|
177 |
FifoCnt => 5 |
|
|
178 | Enable_ReUse => '0') | |
|
242 | FifoCnt => 5) | |
|
179 | 243 | PORT MAP ( |
|
244 | clk => clk, | |
|
180 | 245 | rstn => rstn, |
|
181 | wclk => clk, | |
|
182 | rclk => clk, | |
|
246 | ||
|
183 | 247 |
|
|
184 | 248 | |
|
185 |
wen => sample_f0_A_wen, |
|
|
186 | ren => sample_f0_A_ren, -- OUT in | |
|
187 | wdata => sample_f0_wdata, -- IN in | |
|
188 |
|
|
|
189 | full => sample_f0_A_full, -- IN out | |
|
190 | almost_full => OPEN, -- IN out | |
|
191 |
|
|
|
249 | wen => sample_f0_A_wen, | |
|
250 | wdata => sample_f0_wdata, | |
|
251 | ||
|
252 | ren => sample_f0_A_ren, | |
|
253 | rdata => sample_f0_A_rdata, | |
|
254 | ||
|
255 | empty => sample_f0_A_empty, | |
|
256 | full => sample_f0_A_full, | |
|
257 | almost_full => OPEN); | |
|
192 | 258 |
|
|
193 | 259 |
|
|
194 | 260 | GENERIC MAP ( |
@@ -196,21 +262,20 BEGIN | |||
|
196 | 262 | Mem_use => Mem_use, |
|
197 | 263 | Data_sz => 16, |
|
198 | 264 | Addr_sz => 8, |
|
199 |
FifoCnt => 5 |
|
|
200 | Enable_ReUse => '0') | |
|
265 | FifoCnt => 5) | |
|
201 | 266 | PORT MAP ( |
|
267 | clk => clk, | |
|
202 | 268 | rstn => rstn, |
|
203 | wclk => clk, | |
|
204 | rclk => clk, | |
|
269 | ||
|
205 | 270 |
|
|
206 | 271 | |
|
207 |
wen => sample_f0_B_wen, |
|
|
208 | ren => sample_f0_B_ren, -- OUT in | |
|
209 | wdata => sample_f0_wdata, -- IN in | |
|
210 |
|
|
|
211 | full => sample_f0_B_full, -- IN out | |
|
212 | almost_full => OPEN, -- IN out | |
|
213 | empty => sample_f0_B_empty); -- OUT OUT | |
|
272 | wen => sample_f0_B_wen, | |
|
273 | wdata => sample_f0_wdata, | |
|
274 | ren => sample_f0_B_ren, | |
|
275 | rdata => sample_f0_B_rdata, | |
|
276 | empty => sample_f0_B_empty, | |
|
277 | full => sample_f0_B_full, | |
|
278 | almost_full => OPEN); | |
|
214 | 279 |
|
|
215 | 280 |
|
|
216 | 281 | GENERIC MAP ( |
@@ -218,21 +283,20 BEGIN | |||
|
218 | 283 | Mem_use => Mem_use, |
|
219 | 284 | Data_sz => 16, |
|
220 | 285 | Addr_sz => 8, |
|
221 |
FifoCnt => 5 |
|
|
222 | Enable_ReUse => '0') | |
|
286 | FifoCnt => 5) | |
|
223 | 287 | PORT MAP ( |
|
288 | clk => clk, | |
|
224 | 289 | rstn => rstn, |
|
225 | wclk => clk, | |
|
226 | rclk => clk, | |
|
290 | ||
|
227 | 291 |
|
|
228 | 292 | |
|
229 |
wen => sample_f1_wen, |
|
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
|
233 |
|
|
|
234 |
|
|
|
235 | empty => sample_f1_empty); -- OUT OUT | |
|
293 | wen => sample_f1_wen, | |
|
294 | wdata => sample_f1_wdata, | |
|
295 | ren => sample_f1_ren, | |
|
296 | rdata => sample_f1_rdata, | |
|
297 | empty => sample_f1_empty, | |
|
298 | full => sample_f1_full, | |
|
299 | almost_full => sample_f1_almost_full); | |
|
236 | 300 |
|
|
237 | 301 |
|
|
238 | 302 |
|
@@ -242,7 +306,7 BEGIN | |||
|
242 | 306 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
243 | 307 |
|
|
244 | 308 |
|
|
245 |
ELSIF clk' |
|
|
309 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
246 | 310 | IF sample_f1_full = "00000" THEN |
|
247 | 311 | one_sample_f1_full <= '0'; |
|
248 | 312 | ELSE |
@@ -259,21 +323,20 BEGIN | |||
|
259 | 323 | Mem_use => Mem_use, |
|
260 | 324 | Data_sz => 16, |
|
261 | 325 | Addr_sz => 8, |
|
262 |
FifoCnt => 5 |
|
|
263 | Enable_ReUse => '0') | |
|
326 | FifoCnt => 5) | |
|
264 | 327 | PORT MAP ( |
|
328 | clk => clk, | |
|
265 | 329 | rstn => rstn, |
|
266 | wclk => clk, | |
|
267 | rclk => clk, | |
|
330 | ||
|
268 | 331 |
|
|
269 | 332 | |
|
270 |
wen => sample_f2_wen, |
|
|
271 | ren => sample_f2_ren, -- OUT in | |
|
272 | wdata => sample_f2_wdata, -- IN in | |
|
273 |
|
|
|
274 | full => sample_f2_full, -- IN out | |
|
275 | almost_full => OPEN, -- IN out | |
|
276 | empty => sample_f2_empty); -- OUT OUT | |
|
333 | wen => sample_f2_wen, | |
|
334 | wdata => sample_f2_wdata, | |
|
335 | ren => sample_f2_ren, | |
|
336 | rdata => sample_f2_rdata, | |
|
337 | empty => sample_f2_empty, | |
|
338 | full => sample_f2_full, | |
|
339 | almost_full => OPEN); | |
|
277 | 340 |
|
|
278 | 341 |
|
|
279 | 342 |
|
@@ -283,7 +346,7 BEGIN | |||
|
283 | 346 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
284 | 347 |
|
|
285 | 348 |
|
|
286 |
ELSIF clk' |
|
|
349 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
287 | 350 | IF sample_f2_full = "00000" THEN |
|
288 | 351 | one_sample_f2_full <= '0'; |
|
289 | 352 | ELSE |
@@ -337,6 +400,14 BEGIN | |||
|
337 | 400 | END IF; |
|
338 | 401 | END PROCESS; |
|
339 | 402 | |
|
403 | PROCESS (clk, rstn) | |
|
404 | BEGIN | |
|
405 | IF rstn = '0' THEN | |
|
406 | pre_state_fsm_select_channel <= IDLE; | |
|
407 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
408 | pre_state_fsm_select_channel <= state_fsm_select_channel; | |
|
409 | END IF; | |
|
410 | END PROCESS; | |
|
340 | 411 | |
|
341 | 412 | |
|
342 | 413 | ----------------------------------------------------------------------------- |
@@ -354,9 +425,9 BEGIN | |||
|
354 | 425 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
355 | 426 | (OTHERS => '0'); |
|
356 | 427 | |
|
357 | sample_rdata <= sample_f0_A_rdata WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
|
358 | sample_f0_B_rdata WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
|
359 | sample_f1_rdata WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
|
428 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
|
429 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
|
430 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
|
360 | 431 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
361 | 432 | |
|
362 | 433 | |
@@ -365,77 +436,67 BEGIN | |||
|
365 | 436 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
366 | 437 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
367 | 438 | |
|
439 | ||
|
440 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
|
441 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
|
442 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
|
443 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
|
444 | ||
|
368 | 445 | ----------------------------------------------------------------------------- |
|
369 | 446 | -- FSM LOAD FFT |
|
370 | 447 | ----------------------------------------------------------------------------- |
|
371 | 448 | |
|
372 |
sample_ren <= sample_ren_s; |
|
|
449 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); | |
|
373 | 450 | |
|
374 | 451 | PROCESS (clk, rstn) |
|
375 | 452 | BEGIN |
|
376 | 453 | IF rstn = '0' THEN |
|
377 | 454 |
sample_ren_s |
|
378 | 455 |
state_fsm_load_FFT |
|
379 |
next_state_fsm_load_FFT |
|
|
380 | sample_valid <= '0'; | |
|
381 |
ELSIF clk' |
|
|
456 | --next_state_fsm_load_FFT <= IDLE; | |
|
457 | --sample_valid <= '0'; | |
|
458 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
382 | 459 | CASE state_fsm_load_FFT IS |
|
383 | 460 |
WHEN IDLE |
|
384 | sample_valid <= '0'; | |
|
461 | --sample_valid <= '0'; | |
|
385 | 462 | sample_ren_s <= (OTHERS => '1'); |
|
386 | 463 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
387 | 464 | state_fsm_load_FFT <= FIFO_1; |
|
388 | 465 | END IF; |
|
466 | ||
|
389 | 467 |
|
|
390 | 468 | sample_ren_s <= "1111" & NOT(sample_load); |
|
391 | sample_valid <= '1'; | |
|
392 | 469 | IF sample_empty(0) = '1' THEN |
|
393 | sample_valid <= '0'; | |
|
394 | 470 |
sample_ren_s <= |
|
395 |
state_fsm_load_FFT |
|
|
396 | next_state_fsm_load_FFT <= FIFO_2; | |
|
471 | state_fsm_load_FFT <= FIFO_2; | |
|
397 | 472 | END IF; |
|
398 | 473 | |
|
399 | WHEN FIFO_transition => | |
|
400 | sample_valid <= '0'; | |
|
401 | sample_ren_s <= (OTHERS => '1'); | |
|
402 | state_fsm_load_FFT <= next_state_fsm_load_FFT; | |
|
403 | ||
|
404 | 474 |
WHEN FIFO_2 => |
|
405 | 475 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
406 | sample_valid <= sample_load; | |
|
407 | 476 | IF sample_empty(1) = '1' THEN |
|
408 | sample_valid <= '0'; | |
|
409 | 477 |
sample_ren_s <= |
|
410 |
state_fsm_load_FFT <= FIFO_ |
|
|
411 | next_state_fsm_load_FFT <= FIFO_3; | |
|
478 | state_fsm_load_FFT <= FIFO_3; | |
|
412 | 479 | END IF; |
|
480 | ||
|
413 | 481 |
|
|
414 | 482 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
415 | sample_valid <= sample_load;--'1'; | |
|
416 | 483 | IF sample_empty(2) = '1' THEN |
|
417 | sample_valid <= '0'; | |
|
418 | 484 |
sample_ren_s <= |
|
419 |
state_fsm_load_FFT <= FIFO_ |
|
|
420 | next_state_fsm_load_FFT <= FIFO_4; | |
|
485 | state_fsm_load_FFT <= FIFO_4; | |
|
421 | 486 | END IF; |
|
487 | ||
|
422 | 488 |
|
|
423 | 489 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
424 | sample_valid <= sample_load;--'1'; | |
|
425 | 490 | IF sample_empty(3) = '1' THEN |
|
426 | sample_valid <= '0'; | |
|
427 | 491 |
sample_ren_s <= |
|
428 |
state_fsm_load_FFT <= FIFO_ |
|
|
429 | next_state_fsm_load_FFT <= FIFO_5; | |
|
492 | state_fsm_load_FFT <= FIFO_5; | |
|
430 | 493 | END IF; |
|
494 | ||
|
431 | 495 |
|
|
432 | 496 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
433 | sample_valid <= sample_load;--'1'; | |
|
434 | 497 | IF sample_empty(4) = '1' THEN |
|
435 | sample_valid <= '0'; | |
|
436 | 498 |
sample_ren_s <= |
|
437 |
state_fsm_load_FFT <= |
|
|
438 | next_state_fsm_load_FFT <= IDLE; | |
|
499 | state_fsm_load_FFT <= IDLE; | |
|
439 | 500 | END IF; |
|
440 | 501 | WHEN OTHERS => NULL; |
|
441 | 502 | END CASE; |
@@ -446,16 +507,24 BEGIN | |||
|
446 | 507 | BEGIN |
|
447 | 508 | IF rstn = '0' THEN |
|
448 | 509 | sample_valid_r <= '0'; |
|
449 | ELSIF clk'event AND clk = '1' THEN | |
|
450 | sample_valid_r <= sample_valid AND sample_load; | |
|
510 | next_state_fsm_load_FFT <= IDLE; | |
|
511 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
512 | next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
|
513 | IF sample_ren_s = "11111" THEN | |
|
514 | sample_valid_r <= '0'; | |
|
515 | ELSE | |
|
516 | sample_valid_r <= '1'; | |
|
517 | END IF; | |
|
451 | 518 | END IF; |
|
452 | 519 | END PROCESS; |
|
453 | 520 | |
|
454 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN state_fsm_load_FFT = FIFO_1 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_2) ELSE | |
|
455 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN state_fsm_load_FFT = FIFO_2 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_3) ELSE | |
|
456 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN state_fsm_load_FFT = FIFO_3 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_4) ELSE | |
|
457 |
sample_rdata(16* |
|
|
458 |
sample_rdata(16* |
|
|
521 | sample_valid <= sample_valid_r AND sample_load; | |
|
522 | ||
|
523 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
|
524 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
|
525 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
|
526 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
|
527 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
|
459 | 528 | |
|
460 | 529 | ----------------------------------------------------------------------------- |
|
461 | 530 | -- FFT |
@@ -478,7 +547,7 BEGIN | |||
|
478 | 547 |
ifiStart |
|
479 | 548 |
ifiNreset |
|
480 | 549 | |
|
481 |
ifiD_valid => sample_valid |
|
|
550 | ifiD_valid => sample_valid, -- IN | |
|
482 | 551 | ifiRead_y => fft_read, |
|
483 | 552 | ifiD_im => (OTHERS => '0'), -- IN |
|
484 | 553 | ifiD_re => sample_data, -- IN |
@@ -491,37 +560,336 BEGIN | |||
|
491 | 560 | ifoY_rdy => fft_ready); |
|
492 | 561 | |
|
493 | 562 | ----------------------------------------------------------------------------- |
|
494 | -- | |
|
563 | -- in fft_data_im & fft_data_re | |
|
564 | -- in fft_data_valid | |
|
565 | -- in fft_ready | |
|
566 | -- out fft_read | |
|
567 | PROCESS (clk, rstn) | |
|
568 | BEGIN | |
|
569 | IF rstn = '0' THEN | |
|
570 | state_fsm_load_MS_memory <= IDLE; | |
|
571 | current_fifo_load <= "00001"; | |
|
572 | ELSIF clk'event AND clk = '1' THEN | |
|
573 | CASE state_fsm_load_MS_memory IS | |
|
574 | WHEN IDLE => | |
|
575 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
|
576 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
|
577 | END IF; | |
|
578 | WHEN LOAD_FIFO => | |
|
579 | IF current_fifo_full = '1' THEN | |
|
580 | state_fsm_load_MS_memory <= TRASH_FFT; | |
|
581 | END IF; | |
|
582 | WHEN TRASH_FFT => | |
|
583 | IF fft_ready = '0' THEN | |
|
584 | state_fsm_load_MS_memory <= IDLE; | |
|
585 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
|
586 | END IF; | |
|
587 | WHEN OTHERS => NULL; | |
|
588 | END CASE; | |
|
589 | ||
|
590 | END IF; | |
|
591 | END PROCESS; | |
|
592 | ||
|
593 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
|
594 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
|
595 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
|
596 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
|
597 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
|
598 | ||
|
599 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
|
600 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
|
601 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
|
602 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
|
603 | MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
|
604 | ||
|
605 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
|
606 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
|
607 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
|
608 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
|
609 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
|
610 | ||
|
611 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
|
612 | ||
|
613 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE | |
|
614 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
|
615 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
|
616 | AND current_fifo_load(I) = '1' | |
|
617 | ELSE '1'; | |
|
618 | END GENERATE all_fifo; | |
|
619 | ||
|
620 | PROCESS (clk, rstn) | |
|
621 | BEGIN | |
|
622 | IF rstn = '0' THEN | |
|
623 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
|
624 | ELSIF clk'event AND clk = '1' THEN | |
|
625 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
|
626 | END IF; | |
|
627 | END PROCESS; | |
|
628 | ||
|
629 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
|
630 | (fft_data_im & fft_data_re) & | |
|
631 | (fft_data_im & fft_data_re) & | |
|
632 | (fft_data_im & fft_data_re) & | |
|
633 | (fft_data_im & fft_data_re); | |
|
634 | ||
|
635 | ||
|
636 | -- out SM_MEM_IN_wData | |
|
637 | -- out SM_MEM_IN_wen | |
|
638 | -- out SM_MEM_IN_Full | |
|
639 | ||
|
640 | -- out SM_MEM_IN_locked | |
|
495 | 641 | ----------------------------------------------------------------------------- |
|
496 | fft_read <= '1'; | |
|
497 | -- fft_read OUT | |
|
498 | -- fft_pong IN | |
|
499 | -- fft_data_im IN | |
|
500 | -- fft_data_re IN | |
|
501 | -- fft_data_valid IN | |
|
502 | -- fft_ready IN | |
|
642 | ----------------------------------------------------------------------------- | |
|
643 | ----------------------------------------------------------------------------- | |
|
644 | ----------------------------------------------------------------------------- | |
|
645 | --Linker_FFT_1 : Linker_FFT | |
|
646 | -- GENERIC MAP ( | |
|
647 | -- Data_sz => 16, | |
|
648 | -- NbData => 256) | |
|
649 | -- PORT MAP ( | |
|
650 | -- clk => clk, | |
|
651 | -- rstn => rstn, | |
|
652 | ||
|
653 | -- Ready => fft_ready, | |
|
654 | -- Valid => fft_data_valid, | |
|
655 | ||
|
656 | -- Full => MEM_IN_SM_Full, | |
|
657 | ||
|
658 | -- Data_re => fft_data_re, | |
|
659 | -- Data_im => fft_data_im, | |
|
660 | -- Read => fft_read, | |
|
661 | ||
|
662 | -- Write => MEM_IN_SM_wen, | |
|
663 | -- ReUse => fft_linker_ReUse, | |
|
664 | -- DATA => MEM_IN_SM_wData); | |
|
503 | 665 | |
|
504 | 666 |
|
|
505 | -- | |
|
667 | Mem_In_SpectralMatrix : lppFIFOxN | |
|
668 | GENERIC MAP ( | |
|
669 | tech => 0, | |
|
670 | Mem_use => Mem_use, | |
|
671 | Data_sz => 32, --16, | |
|
672 | Addr_sz => 7, --8 | |
|
673 | FifoCnt => 5) | |
|
674 | PORT MAP ( | |
|
675 | clk => clk, | |
|
676 | rstn => rstn, | |
|
677 | ||
|
678 | ReUse => MEM_IN_SM_ReUse, | |
|
679 | ||
|
680 | wen => MEM_IN_SM_wen, | |
|
681 | wdata => MEM_IN_SM_wData, | |
|
682 | ||
|
683 | ren => MEM_IN_SM_ren, | |
|
684 | rdata => MEM_IN_SM_rData, | |
|
685 | full => MEM_IN_SM_Full, | |
|
686 | empty => MEM_IN_SM_Empty); | |
|
687 | ||
|
688 | ||
|
689 | all_lock: FOR I IN 4 DOWNTO 0 GENERATE | |
|
690 | PROCESS (clk, rstn) | |
|
691 | BEGIN | |
|
692 | IF rstn = '0' THEN | |
|
693 | MEM_IN_SM_locked(I) <= '0'; | |
|
694 | ELSIF clk'event AND clk = '1' THEN | |
|
695 | MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO | |
|
696 | END IF; | |
|
697 | END PROCESS; | |
|
698 | END GENERATE all_lock; | |
|
699 | ||
|
700 | ||
|
701 | ||
|
702 | ----------------------------------------------------------------------------- | |
|
703 | SM0 : MatriceSpectrale | |
|
704 | GENERIC MAP ( | |
|
705 | Input_SZ => 16, | |
|
706 | Result_SZ => 32) | |
|
707 | PORT MAP ( | |
|
708 | clkm => clk, | |
|
709 | rstn => rstn, | |
|
710 | ||
|
711 | FifoIN_Full => MEM_IN_SM_Full, | |
|
712 | Data_IN => MEM_IN_SM_rData(79 DOWNTO 0), | |
|
713 | Read => MEM_IN_SM_ren, | |
|
714 | ReUse => MEM_IN_SM_ReUse, | |
|
715 | ||
|
716 | SetReUse => fft_linker_ReUse, | |
|
717 | ||
|
718 | Valid => HEAD_Valid, | |
|
719 | ACK => DMA_Header_Ack, | |
|
720 | SM_Write => HEAD_SM_Wen, | |
|
721 | FlagError => OPEN, | |
|
722 | Statu => HEAD_SM_Param, | |
|
723 | Write => MEM_OUT_SM_Write, | |
|
724 | Data_OUT => MEM_OUT_SM_Data_in); | |
|
725 | ----------------------------------------------------------------------------- | |
|
726 | Mem_Out_SpectralMatrix : lppFIFOxN | |
|
727 | GENERIC MAP ( | |
|
728 | tech => 0, | |
|
729 | Mem_use => Mem_use, | |
|
730 | Data_sz => 32, | |
|
731 | Addr_sz => 8, | |
|
732 | FifoCnt => 2) | |
|
733 | PORT MAP ( | |
|
734 | clk => clk, | |
|
735 | rstn => rstn, | |
|
736 | ||
|
737 | ReUse => (OTHERS => '0'), | |
|
738 | ||
|
739 | wen => MEM_OUT_SM_Write, | |
|
740 | wdata => MEM_OUT_SM_Data_in, | |
|
741 | ren => MEM_OUT_SM_Read, | |
|
742 | rdata => MEM_OUT_SM_Data_out, | |
|
743 | ||
|
744 | full => MEM_OUT_SM_Full, | |
|
745 | empty => MEM_OUT_SM_Empty); | |
|
746 | ----------------------------------------------------------------------------- | |
|
747 | Head0 : HeaderBuilder | |
|
748 | GENERIC MAP ( | |
|
749 | Data_sz => 32) | |
|
750 | PORT MAP ( | |
|
751 | clkm => clk, | |
|
752 | rstn => rstn, | |
|
753 | ||
|
754 | Statu => HEAD_SM_Param, | |
|
755 | Matrix_Type => HEAD_WorkFreq, -- TODO IN | |
|
756 | Matrix_Write => HEAD_SM_Wen, | |
|
757 | Valid => HEAD_Valid, | |
|
758 | ||
|
759 | dataIN => MEM_OUT_SM_Data_out, | |
|
760 | emptyIN => MEM_OUT_SM_Empty, | |
|
761 | RenOUT => MEM_OUT_SM_Read, | |
|
762 | ||
|
763 | dataOUT => HEAD_Data, | |
|
764 | emptyOUT => HEAD_Empty, | |
|
765 | RenIN => HEAD_Read, | |
|
766 | ||
|
767 | header => DMA_Header, | |
|
768 | header_val => DMA_Header_Val, | |
|
769 | header_ack => DMA_Header_Ack); | |
|
770 | ----------------------------------------------------------------------------- | |
|
771 | ----------------------------------------------------------------------------- | |
|
772 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
|
773 | PORT MAP ( | |
|
774 | HCLK => clk, | |
|
775 | HRESETn => rstn, | |
|
776 | ||
|
777 | data_time => dma_time, | |
|
778 | ||
|
779 | fifo_data => HEAD_Data, | |
|
780 | fifo_empty => HEAD_Empty, | |
|
781 | fifo_ren => HEAD_Read, | |
|
782 | ||
|
783 | header => DMA_Header, | |
|
784 | header_val => DMA_Header_Val, | |
|
785 | header_ack => DMA_Header_Ack, | |
|
786 | ||
|
787 | dma_addr => dma_addr, | |
|
788 | dma_data => dma_data, | |
|
789 | dma_valid => dma_valid, | |
|
790 | dma_valid_burst => dma_valid_burst, | |
|
791 | dma_ren => dma_ren, | |
|
792 | dma_done => dma_done, | |
|
793 | ||
|
794 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
795 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
796 | ready_matrix_f1 => ready_matrix_f1, | |
|
797 | ready_matrix_f2 => ready_matrix_f2, | |
|
798 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
799 | error_bad_component_error => error_bad_component_error, | |
|
800 | debug_reg => debug_reg, | |
|
801 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
802 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
803 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
804 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
805 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
806 | status_error_bad_component_error => status_error_bad_component_error, | |
|
807 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
808 | config_active_interruption_onError => config_active_interruption_onError, | |
|
809 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
810 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
811 | addr_matrix_f1 => addr_matrix_f1, | |
|
812 | addr_matrix_f2 => addr_matrix_f2, | |
|
813 | ||
|
814 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
815 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
816 | matrix_time_f1 => matrix_time_f1, | |
|
817 | matrix_time_f2 => matrix_time_f2 | |
|
818 | ); | |
|
506 | 819 | ----------------------------------------------------------------------------- |
|
507 | 820 | |
|
508 | dma_addr <= (OTHERS => '0'); | |
|
509 | dma_data <= (OTHERS => '0'); | |
|
510 | dma_valid <= '0'; | |
|
511 | dma_valid_burst <= '0'; | |
|
821 | ----------------------------------------------------------------------------- | |
|
822 | ----------------------------------------------------------------------------- | |
|
823 | ----------------------------------------------------------------------------- | |
|
824 | ----------------------------------------------------------------------------- | |
|
825 | ----------------------------------------------------------------------------- | |
|
826 | ----------------------------------------------------------------------------- | |
|
827 | ||
|
828 | ||
|
829 | ||
|
830 | ||
|
831 | ||
|
832 | ||
|
833 | ----------------------------------------------------------------------------- | |
|
834 | -- TIME MANAGMENT | |
|
835 | ----------------------------------------------------------------------------- | |
|
836 | all_time <= coarse_time & fine_time; | |
|
837 | -- | |
|
838 | time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE | |
|
839 | '1' WHEN sample_f0_A_empty = "11111" ELSE | |
|
840 | '0'; | |
|
841 | ||
|
842 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
|
843 | PORT MAP ( | |
|
844 | clk => clk, | |
|
845 | rstn => rstn, | |
|
846 | time_in => all_time, | |
|
847 | update_1 => time_update_f0_A, | |
|
848 | time_out => time_reg_f0_A); | |
|
849 | ||
|
850 | -- | |
|
851 | time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE | |
|
852 | '1' WHEN sample_f0_B_empty = "11111" ELSE | |
|
853 | '0'; | |
|
512 | 854 | |
|
513 | ready_matrix_f0_0 <= '0'; | |
|
514 | ready_matrix_f0_1 <= '0'; | |
|
515 | ready_matrix_f1 <= '0'; | |
|
516 | ready_matrix_f2 <= '0'; | |
|
517 | error_anticipating_empty_fifo <= '0'; | |
|
518 | error_bad_component_error <= '0'; | |
|
519 | debug_reg <= (OTHERS => '0'); | |
|
855 | s_m_t_m_f0_B : spectral_matrix_time_managment | |
|
856 | PORT MAP ( | |
|
857 | clk => clk, | |
|
858 | rstn => rstn, | |
|
859 | time_in => all_time, | |
|
860 | update_1 => time_update_f0_B, | |
|
861 | time_out => time_reg_f0_B); | |
|
862 | ||
|
863 | -- | |
|
864 | time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE | |
|
865 | '1' WHEN sample_f1_empty = "11111" ELSE | |
|
866 | '0'; | |
|
520 | 867 | |
|
521 | matrix_time_f0_0 <= (OTHERS => '0'); | |
|
522 | matrix_time_f0_1 <= (OTHERS => '0'); | |
|
523 | matrix_time_f1 <= (OTHERS => '0'); | |
|
524 | matrix_time_f2 <= (OTHERS => '0'); | |
|
868 | s_m_t_m_f1 : spectral_matrix_time_managment | |
|
869 | PORT MAP ( | |
|
870 | clk => clk, | |
|
871 | rstn => rstn, | |
|
872 | time_in => all_time, | |
|
873 | update_1 => time_update_f1, | |
|
874 | time_out => time_reg_f1); | |
|
875 | ||
|
876 | -- | |
|
877 | time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE | |
|
878 | '1' WHEN sample_f2_empty = "11111" ELSE | |
|
879 | '0'; | |
|
880 | ||
|
881 | s_m_t_m_f2 : spectral_matrix_time_managment | |
|
882 | PORT MAP ( | |
|
883 | clk => clk, | |
|
884 | rstn => rstn, | |
|
885 | time_in => all_time, | |
|
886 | update_1 => time_update_f2, | |
|
887 | time_out => time_reg_f2); | |
|
888 | ||
|
889 | ----------------------------------------------------------------------------- | |
|
890 | dma_time <= (OTHERS => '0'); -- TODO | |
|
891 | ----------------------------------------------------------------------------- | |
|
892 | ||
|
525 | 893 | |
|
526 | 894 | |
|
527 | 895 | END Behavioral; |
@@ -19,181 +19,223 | |||
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | library ieee; | |
|
23 |
|
|
|
24 | library grlib; | |
|
25 |
|
|
|
26 |
|
|
|
27 | library lpp; | |
|
28 |
|
|
|
29 |
|
|
|
30 | library gaisler; | |
|
31 |
|
|
|
32 |
|
|
|
33 | library techmap; | |
|
34 |
|
|
|
22 | LIBRARY ieee; | |
|
23 | USE ieee.std_logic_1164.ALL; | |
|
24 | LIBRARY grlib; | |
|
25 | USE grlib.amba.ALL; | |
|
26 | USE std.textio.ALL; | |
|
27 | LIBRARY lpp; | |
|
28 | USE lpp.lpp_amba.ALL; | |
|
29 | USE lpp.iir_filter.ALL; | |
|
30 | LIBRARY gaisler; | |
|
31 | USE gaisler.misc.ALL; | |
|
32 | USE gaisler.memctrl.ALL; | |
|
33 | LIBRARY techmap; | |
|
34 | USE techmap.gencomp.ALL; | |
|
35 | 35 | |
|
36 | 36 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
37 | 37 | |
|
38 | package lpp_memory is | |
|
38 | PACKAGE lpp_memory IS | |
|
39 | 39 | |
|
40 | component APB_FIFO is | |
|
41 | generic ( | |
|
42 | tech : integer := apa3; | |
|
43 | pindex : integer := 0; | |
|
44 | paddr : integer := 0; | |
|
45 | pmask : integer := 16#fff#; | |
|
46 | pirq : integer := 0; | |
|
47 | abits : integer := 8; | |
|
48 | FifoCnt : integer := 2; | |
|
49 | Data_sz : integer := 16; | |
|
50 | Addr_sz : integer := 9; | |
|
51 | Enable_ReUse : std_logic := '0'; | |
|
52 | Mem_use : integer := use_RAM; | |
|
53 | R : integer := 1; | |
|
54 | W : integer := 1 | |
|
55 | ); | |
|
56 | port ( | |
|
57 | clk : in std_logic; --! Horloge du composant | |
|
58 | rst : in std_logic; --! Reset general du composant | |
|
59 | rclk : in std_logic; | |
|
60 | wclk : in std_logic; | |
|
61 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
|
62 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire | |
|
63 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire | |
|
64 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide | |
|
65 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine | |
|
66 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e | |
|
67 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie | |
|
68 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture) | |
|
69 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) | |
|
70 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
|
71 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
|
72 | ); | |
|
73 | end component; | |
|
40 | COMPONENT lpp_fifo | |
|
41 | GENERIC ( | |
|
42 | tech : INTEGER; | |
|
43 | Mem_use : INTEGER; | |
|
44 | DataSz : INTEGER RANGE 1 TO 32; | |
|
45 | AddrSz : INTEGER RANGE 2 TO 12); | |
|
46 | PORT ( | |
|
47 | clk : IN STD_LOGIC; | |
|
48 | rstn : IN STD_LOGIC; | |
|
49 | reUse : IN STD_LOGIC; | |
|
50 | ren : IN STD_LOGIC; | |
|
51 | rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
|
52 | wen : IN STD_LOGIC; | |
|
53 | wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
|
54 | empty : OUT STD_LOGIC; | |
|
55 | full : OUT STD_LOGIC; | |
|
56 | almost_full : OUT STD_LOGIC); | |
|
57 | END COMPONENT; | |
|
74 | 58 | |
|
75 | component FIFO_pipeline is | |
|
76 | generic( | |
|
77 | tech : integer := 0; | |
|
78 | Mem_use : integer := use_RAM; | |
|
79 | fifoCount : integer range 2 to 32 := 8; | |
|
80 | DataSz : integer range 1 to 32 := 8; | |
|
81 | abits : integer range 2 to 12 := 8 | |
|
82 | ); | |
|
83 | port( | |
|
84 | rstn : in std_logic; | |
|
85 | ReUse : in std_logic; | |
|
86 | rclk : in std_logic; | |
|
87 | ren : in std_logic; | |
|
88 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
|
89 | empty : out std_logic; | |
|
90 | raddr : out std_logic_vector(abits-1 downto 0); | |
|
91 | wclk : in std_logic; | |
|
92 | wen : in std_logic; | |
|
93 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
|
94 | full : out std_logic; | |
|
95 | waddr : out std_logic_vector(abits-1 downto 0) | |
|
96 | ); | |
|
97 | end component; | |
|
59 | COMPONENT lppFIFOxN | |
|
60 | GENERIC ( | |
|
61 | tech : INTEGER; | |
|
62 | Mem_use : INTEGER; | |
|
63 | Data_sz : INTEGER RANGE 1 TO 32; | |
|
64 | Addr_sz : INTEGER RANGE 2 TO 12; | |
|
65 | FifoCnt : INTEGER); | |
|
66 | PORT ( | |
|
67 | clk : IN STD_LOGIC; | |
|
68 | rstn : IN STD_LOGIC; | |
|
69 | ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
70 | wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
71 | wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); | |
|
72 | ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
73 | rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); | |
|
74 | empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
75 | full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
|
76 | almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)); | |
|
77 | END COMPONENT; | |
|
98 | 78 | |
|
99 | component lpp_fifo is | |
|
100 | generic( | |
|
101 | tech : integer := 0; | |
|
102 | Mem_use : integer := use_RAM; | |
|
103 | Enable_ReUse : std_logic := '0'; | |
|
104 | DataSz : integer range 1 to 32 := 8; | |
|
105 | AddrSz : integer range 2 to 12 := 8 | |
|
106 | ); | |
|
107 | port( | |
|
108 | rstn : in std_logic; | |
|
109 | ReUse : in std_logic; --27/01/12 | |
|
110 | rclk : in std_logic; | |
|
111 | ren : in std_logic; | |
|
112 | rdata : out std_logic_vector(DataSz-1 downto 0); | |
|
113 | empty : out std_logic; | |
|
114 | raddr : out std_logic_vector(AddrSz-1 downto 0); | |
|
115 | wclk : in std_logic; | |
|
116 | wen : in std_logic; | |
|
117 | wdata : in std_logic_vector(DataSz-1 downto 0); | |
|
118 | full : out std_logic; | |
|
119 | almost_full : out std_logic; | |
|
120 | waddr : out std_logic_vector(AddrSz-1 downto 0) | |
|
121 | ); | |
|
122 | end component; | |
|
79 | ||
|
123 | 80 | |
|
124 | 81 |
|
|
125 | component lppFIFOxN is | |
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126 | generic( | |
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127 |
tech |
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128 | Mem_use : integer := use_RAM; | |
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129 | Data_sz : integer range 1 to 32 := 8; | |
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130 | Addr_sz : integer range 1 to 32 := 8; | |
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131 | FifoCnt : integer := 1; | |
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132 | Enable_ReUse : std_logic := '0' | |
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82 | COMPONENT APB_FIFO IS | |
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83 | GENERIC ( | |
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84 | tech : INTEGER := apa3; | |
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85 | pindex : INTEGER := 0; | |
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86 | paddr : INTEGER := 0; | |
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87 | pmask : INTEGER := 16#fff#; | |
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88 | pirq : INTEGER := 0; | |
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89 | abits : INTEGER := 8; | |
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90 | FifoCnt : INTEGER := 2; | |
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91 | Data_sz : INTEGER := 16; | |
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92 | Addr_sz : INTEGER := 9; | |
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93 | Enable_ReUse : STD_LOGIC := '0'; | |
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94 | Mem_use : INTEGER := use_RAM; | |
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95 | R : INTEGER := 1; | |
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96 | W : INTEGER := 1 | |
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133 | 97 | ); |
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134 | port( | |
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135 | rstn : in std_logic; | |
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136 | wclk : in std_logic; | |
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137 | rclk : in std_logic; | |
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138 | ReUse : in std_logic_vector(FifoCnt-1 downto 0); | |
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139 | wen : in std_logic_vector(FifoCnt-1 downto 0); | |
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140 | ren : in std_logic_vector(FifoCnt-1 downto 0); | |
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141 | wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
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142 | rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); | |
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143 | full : out std_logic_vector(FifoCnt-1 downto 0); | |
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144 | almost_full : out std_logic_vector(FifoCnt-1 downto 0); | |
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145 | empty : out std_logic_vector(FifoCnt-1 downto 0) | |
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98 | PORT ( | |
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99 | clk : IN STD_LOGIC; --! Horloge du composant | |
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100 | rst : IN STD_LOGIC; --! Reset general du composant | |
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101 | rclk : IN STD_LOGIC; | |
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102 | wclk : IN STD_LOGIC; | |
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103 | ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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104 | REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire | |
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105 | WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire | |
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106 | Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide | |
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107 | Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine | |
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108 | RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e | |
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109 | WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie | |
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110 | WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture) | |
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111 | RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture) | |
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112 | apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
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113 | apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus | |
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146 | 114 | ); |
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147 | end component; | |
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115 | END COMPONENT; | |
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148 | 116 | |
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149 | component FillFifo is | |
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150 | generic( | |
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151 | Data_sz : integer range 1 to 32 := 16; | |
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152 | Fifo_cnt : integer range 1 to 8 := 5 | |
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117 | COMPONENT FIFO_pipeline IS | |
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118 | GENERIC( | |
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119 | tech : INTEGER := 0; | |
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120 | Mem_use : INTEGER := use_RAM; | |
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121 | fifoCount : INTEGER RANGE 2 TO 32 := 8; | |
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122 | DataSz : INTEGER RANGE 1 TO 32 := 8; | |
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123 | abits : INTEGER RANGE 2 TO 12 := 8 | |
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153 | 124 | ); |
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154 | port( | |
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155 | clk : in std_logic; | |
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156 | raz : in std_logic; | |
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157 | write : out std_logic_vector(Fifo_cnt-1 downto 0); | |
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158 | reuse : out std_logic_vector(Fifo_cnt-1 downto 0); | |
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159 | data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) | |
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125 | PORT( | |
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126 | rstn : IN STD_LOGIC; | |
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127 | ReUse : IN STD_LOGIC; | |
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128 | rclk : IN STD_LOGIC; | |
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129 | ren : IN STD_LOGIC; | |
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130 | rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
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131 | empty : OUT STD_LOGIC; | |
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132 | raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0); | |
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133 | wclk : IN STD_LOGIC; | |
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134 | wen : IN STD_LOGIC; | |
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135 | wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
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136 | full : OUT STD_LOGIC; | |
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137 | waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0) | |
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160 | 138 | ); |
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161 | end component; | |
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139 | END COMPONENT; | |
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162 | 140 | |
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163 | component Bridge is | |
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164 | port( | |
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165 | clk : in std_logic; | |
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166 | raz : in std_logic; | |
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167 | EmptyUp : in std_logic; | |
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168 | FullDwn : in std_logic; | |
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169 | WriteDwn : out std_logic; | |
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170 | ReadUp : out std_logic | |
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141 | --COMPONENT lpp_fifo IS | |
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142 | -- GENERIC( | |
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143 | -- tech : INTEGER := 0; | |
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144 | -- Mem_use : INTEGER := use_RAM; | |
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145 | -- Enable_ReUse : STD_LOGIC := '0'; | |
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146 | -- DataSz : INTEGER RANGE 1 TO 32 := 8; | |
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147 | -- AddrSz : INTEGER RANGE 2 TO 12 := 8 | |
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148 | -- ); | |
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149 | -- PORT( | |
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150 | -- rstn : IN STD_LOGIC; | |
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151 | -- ReUse : IN STD_LOGIC; --27/01/12 | |
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152 | -- rclk : IN STD_LOGIC; | |
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153 | -- ren : IN STD_LOGIC; | |
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154 | -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
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155 | -- empty : OUT STD_LOGIC; | |
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156 | -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0); | |
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157 | -- wclk : IN STD_LOGIC; | |
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158 | -- wen : IN STD_LOGIC; | |
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159 | -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0); | |
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160 | -- full : OUT STD_LOGIC; | |
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161 | -- almost_full : OUT STD_LOGIC; | |
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162 | -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) | |
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163 | -- ); | |
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164 | --END COMPONENT; | |
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165 | ||
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166 | ||
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167 | --COMPONENT lppFIFOxN IS | |
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168 | -- GENERIC( | |
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169 | -- tech : INTEGER := 0; | |
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170 | -- Mem_use : INTEGER := use_RAM; | |
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171 | -- Data_sz : INTEGER RANGE 1 TO 32 := 8; | |
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172 | -- Addr_sz : INTEGER RANGE 1 TO 32 := 8; | |
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173 | -- FifoCnt : INTEGER := 1; | |
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174 | -- Enable_ReUse : STD_LOGIC := '0' | |
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175 | -- ); | |
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176 | -- PORT( | |
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177 | -- rstn : IN STD_LOGIC; | |
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178 | -- wclk : IN STD_LOGIC; | |
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179 | -- rclk : IN STD_LOGIC; | |
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180 | -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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181 | -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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182 | -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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183 | -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); | |
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184 | -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); | |
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185 | -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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186 | -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); | |
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187 | -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0) | |
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188 | -- ); | |
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189 | --END COMPONENT; | |
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190 | ||
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191 | COMPONENT FillFifo IS | |
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192 | GENERIC( | |
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193 | Data_sz : INTEGER RANGE 1 TO 32 := 16; | |
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194 | Fifo_cnt : INTEGER RANGE 1 TO 8 := 5 | |
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171 | 195 |
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172 | end component; | |
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196 | PORT( | |
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197 | clk : IN STD_LOGIC; | |
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198 | raz : IN STD_LOGIC; | |
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199 | write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0); | |
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200 | reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0); | |
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201 | data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0) | |
|
202 | ); | |
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203 | END COMPONENT; | |
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173 | 204 | |
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174 | component ssram_plugin is | |
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175 | generic (tech : integer := 0); | |
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176 | port | |
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205 | COMPONENT Bridge IS | |
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206 | PORT( | |
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207 | clk : IN STD_LOGIC; | |
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208 | raz : IN STD_LOGIC; | |
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209 | EmptyUp : IN STD_LOGIC; | |
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210 | FullDwn : IN STD_LOGIC; | |
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211 | WriteDwn : OUT STD_LOGIC; | |
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212 | ReadUp : OUT STD_LOGIC | |
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213 | ); | |
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214 | END COMPONENT; | |
|
215 | ||
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216 | COMPONENT ssram_plugin IS | |
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217 | GENERIC (tech : INTEGER := 0); | |
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218 | PORT | |
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177 | 219 | ( |
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178 | clk : in std_logic; | |
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179 |
mem_ctrlr_o |
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180 | SSRAM_CLK : out std_logic; | |
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181 | nBWa : out std_logic; | |
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182 | nBWb : out std_logic; | |
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183 | nBWc : out std_logic; | |
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184 | nBWd : out std_logic; | |
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185 | nBWE : out std_logic; | |
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186 | nADSC : out std_logic; | |
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187 | nADSP : out std_logic; | |
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188 | nADV : out std_logic; | |
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189 | nGW : out std_logic; | |
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190 | nCE1 : out std_logic; | |
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191 | CE2 : out std_logic; | |
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192 | nCE3 : out std_logic; | |
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193 | nOE : out std_logic; | |
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194 | MODE : out std_logic; | |
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195 | ZZ : out std_logic | |
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220 | clk : IN STD_LOGIC; | |
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221 | mem_ctrlr_o : IN memory_out_type; | |
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222 | SSRAM_CLK : OUT STD_LOGIC; | |
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223 | nBWa : OUT STD_LOGIC; | |
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224 | nBWb : OUT STD_LOGIC; | |
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225 | nBWc : OUT STD_LOGIC; | |
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226 | nBWd : OUT STD_LOGIC; | |
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227 | nBWE : OUT STD_LOGIC; | |
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228 | nADSC : OUT STD_LOGIC; | |
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229 | nADSP : OUT STD_LOGIC; | |
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230 | nADV : OUT STD_LOGIC; | |
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231 | nGW : OUT STD_LOGIC; | |
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232 | nCE1 : OUT STD_LOGIC; | |
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233 | CE2 : OUT STD_LOGIC; | |
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234 | nCE3 : OUT STD_LOGIC; | |
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235 | nOE : OUT STD_LOGIC; | |
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236 | MODE : OUT STD_LOGIC; | |
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237 | ZZ : OUT STD_LOGIC | |
|
196 | 238 | ); |
|
197 | end component; | |
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239 | END COMPONENT; | |
|
198 | 240 | |
|
199 | end; | |
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241 | END; |
@@ -17,4 +17,13 PACKAGE spectral_matrix_package IS | |||
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17 | 17 | error_wen : OUT STD_LOGIC); |
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18 | 18 | END COMPONENT; |
|
19 | 19 | |
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20 | COMPONENT spectral_matrix_time_managment | |
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21 | PORT ( | |
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22 | clk : IN STD_LOGIC; | |
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23 | rstn : IN STD_LOGIC; | |
|
24 | time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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25 | update_1 : IN STD_LOGIC; | |
|
26 | time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); | |
|
27 | END COMPONENT; | |
|
28 | ||
|
20 | 29 | END spectral_matrix_package; |
@@ -41,12 +41,29 add wave -noupdate -expand -group FFT_RE | |||
|
41 | 41 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong |
|
42 | 42 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy |
|
43 | 43 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid |
|
44 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_im | |
|
45 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_re | |
|
44 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im | |
|
45 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re | |
|
46 | add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray | |
|
47 | add wave -noupdate /tb/lpp_lfr_ms_1/status_channel | |
|
48 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray | |
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49 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray | |
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50 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray | |
|
51 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray | |
|
52 | add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray | |
|
53 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load | |
|
54 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory | |
|
55 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full | |
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56 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty | |
|
57 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full | |
|
58 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata | |
|
59 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen | |
|
60 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked | |
|
61 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata | |
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62 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren | |
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46 | 63 | TreeUpdate [SetDefaultTree] |
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47 |
WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} { |
|
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48 |
configure wave -namecolwidth 4 |
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|
49 |
configure wave -valuecolwidth 1 |
|
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64 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {33725957281 ps} 0} {{Cursor 3} {10434056078 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {82561584962 ps} 0} | |
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65 | configure wave -namecolwidth 469 | |
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66 | configure wave -valuecolwidth 112 | |
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50 | 67 | configure wave -justifyvalue left |
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51 | 68 | configure wave -signalnamewidth 0 |
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52 | 69 | configure wave -snapdistance 10 |
@@ -59,6 +76,6 configure wave -griddelta 40 | |||
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59 | 76 | configure wave -timeline 0 |
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60 | 77 | configure wave -timelineunits ps |
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61 | 78 | update |
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62 |
WaveRestoreZoom {10 |
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79 | WaveRestoreZoom {10429891270 ps} {10442522246 ps} | |
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63 | 80 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
|
64 | 81 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
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