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1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=TB
6 6
7 7 CMD_VLIB=vlib
8 8 CMD_VMAP=vmap
9 9 CMD_VCOM=@vcom -quiet -93 -work
10 10
11 11 ################## project specific targets ##########################
12 12
13 13 all:
14 14 @echo "make vsim"
15 15 @echo "make libs"
16 16 @echo "make clean"
17 17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18 18
19 19 run:
20 20 @vsim work.TB -do run.do
21 21 # @vsim work.TB
22 22 # @vsim lpp.lpp_lfr_ms
23 23
24 24 vsim: libs vcom run
25 25
26 26 libs:
27 27 @$(CMD_VLIB) modelsim
28 28 @$(CMD_VMAP) modelsim modelsim
29 29 @$(CMD_VLIB) modelsim/techmap
30 30 @$(CMD_VMAP) techmap modelsim/techmap
31 31 @$(CMD_VLIB) modelsim/grlib
32 32 @$(CMD_VMAP) grlib modelsim/grlib
33 33 @$(CMD_VLIB) modelsim/gaisler
34 34 @$(CMD_VMAP) gaisler modelsim/gaisler
35 35 @$(CMD_VLIB) modelsim/work
36 36 @$(CMD_VMAP) work modelsim/work
37 37 @$(CMD_VLIB) modelsim/lpp
38 38 @$(CMD_VMAP) lpp modelsim/lpp
39 39 @echo "libs done"
40 40
41 41
42 42 clean:
43 43 @rm -Rf modelsim
44 44 @rm -Rf modelsim.ini
45 45 @rm -Rf *~
46 46 @rm -Rf transcript
47 47 @rm -Rf wlft*
48 48 @rm -Rf *.wlf
49 49 @rm -Rf vish_stacktrace.vstf
50 50 @rm -Rf libs.do
51 51
52 52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
53 53
54 54
55 55 vcom_tb:
56 56 $(CMD_VCOM) lpp lpp_memory.vhd
57 57 $(CMD_VCOM) lpp lppFIFOxN.vhd
58 58 $(CMD_VCOM) lpp lpp_FIFO.vhd
59 59 $(CMD_VCOM) lpp spectral_matrix_package.vhd
60 60 $(CMD_VCOM) lpp spectral_matrix_switch_f0.vhd
61 $(CMD_VCOM) lpp spectral_matrix_time_managment.vhd
61 62 $(CMD_VCOM) lpp lpp_lfr_ms.vhd
62 63 $(CMD_VCOM) work TB.vhd
63 64 @echo "vcom done"
64 65
65 66 vcom_grlib:
66 67 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
67 68 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
68 69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
69 70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
70 71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
71 72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
72 73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
73 74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
74 75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
75 76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
76 77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
77 78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
78 79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
79 80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
80 81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
81 82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
82 83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
83 84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
84 85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
85 86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
86 87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
87 88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
88 89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
89 90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
90 91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
91 92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
92 93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
93 94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
94 95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
95 96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
96 97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
97 98 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
98 99 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
99 100 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
100 101 @echo "vcom grlib done"
101 102
102 103 vcom_gaisler:
103 104 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
104 105 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
105 106 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
106 107 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
107 108 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
108 109 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
109 110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
110 111 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
111 112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
112 113 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
113 114 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
114 115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
115 116 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
116 117 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
117 118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
118 119 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
119 120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
120 121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
121 122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
122 123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
123 124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
124 125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
125 126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
126 127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
127 128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
128 129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
129 130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
130 131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
131 132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
132 133 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
133 134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
134 135 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
135 136 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
136 137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
137 138 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
138 139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
139 140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
140 141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
141 142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
142 143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
143 144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
144 145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
145 146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
146 147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
147 148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
148 149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
149 150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
150 151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
151 152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
152 153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
153 154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
154 155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
155 156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
156 157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
157 158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
158 159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
159 160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
160 161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
161 162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
162 163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
163 164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
164 165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
165 166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
166 167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
167 168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
168 169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
169 170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
170 171 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
171 172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
172 173 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
173 174 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
174 175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
175 176 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
176 177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
177 178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
178 179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
179 180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
180 181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
181 182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
182 183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
183 184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
184 185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
185 186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
186 187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
187 188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
188 189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
189 190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
190 191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
191 192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
192 193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
193 194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
194 195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
195 196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
196 197 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
197 198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
198 199 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
199 200 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
200 201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
201 202 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
202 203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
203 204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
204 205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
205 206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
206 207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
207 208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
208 209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
209 210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
210 211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
211 212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
212 213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
213 214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
214 215 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
215 216 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
216 217 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
217 218 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
218 219 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
219 220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
220 221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
221 222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
222 223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
223 224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
224 225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
225 226 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
226 227 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
227 228 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
228 229 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
229 230 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
230 231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
231 232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
232 233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
233 234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
234 235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
235 236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
236 237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
237 238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
238 239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
239 240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
240 241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
241 242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
242 243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
243 244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
244 245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
245 246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
246 247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
247 248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
248 249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
249 250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
250 251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
251 252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
252 253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
253 254 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
254 255 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
255 256 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
256 257 @echo "vcom gaisler done"
257 258
258 259 vcom_techmap:
259 260 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
260 261 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
261 262 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
262 263 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
263 264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
264 265 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
265 266 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
266 267 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
267 268 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
268 269 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
269 270 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
270 271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
271 272 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
272 273 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
273 274 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
274 275 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
275 276 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
276 277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
277 278 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
278 279 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
279 280 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
280 281 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
281 282 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
282 283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
283 284 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
284 285 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
285 286 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
286 287 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
287 288 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
288 289 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
289 290 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
290 291 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
291 292 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
292 293 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
293 294 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
294 295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
295 296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
296 297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
297 298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
298 299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
299 300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
300 301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
301 302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
302 303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
303 304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
304 305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
305 306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
306 307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
307 308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
308 309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
309 310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
310 311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
311 312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
312 313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
313 314 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
314 315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
315 316 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
316 317 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
317 318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
318 319 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
319 320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
320 321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
321 322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
322 323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
323 324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
324 325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
325 326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
326 327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
327 328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
328 329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
329 330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
330 331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
331 332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
332 333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
333 334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
334 335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
335 336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
336 337 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
337 338 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
338 339 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
339 340 @echo "vcom techmap done"
340 341
341 342 vcom_lpp:
342 343 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
343 344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
344 345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
345 346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
346 347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
347 391 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
348 394 @echo "vcom lpp done"
349 395
350 396 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
351 397 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
352 398 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
353 399 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
354 400 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
355 401 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
356 402 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
357 403 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
358 404 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
359 405 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
360 406 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
361 407 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
362 408 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
363 409 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
364 410 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
365 411 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
366 412 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
367 413 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
368 414 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
369 415 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
370 416 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
371 417 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
372 418 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
373 419 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
374 420 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
375 421 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
376 422 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
377 423 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
378 424 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
379 425 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
380 426 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
381 427 # @echo "vcom lpp done"
382 428
383 429 #include Makefile_vcom_lpp
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@@ -1,70 +1,82
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
28 library techmap;
29 use techmap.gencomp.all;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 30
31 entity lppFIFOxN is
32 generic(
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 2 to 12 := 8;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
31 ENTITY lppFIFOxN IS
32 GENERIC(
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
35 Data_sz : INTEGER RANGE 1 TO 32 := 8;
36 Addr_sz : INTEGER RANGE 2 TO 12 := 8;
37 FifoCnt : INTEGER := 1
39 38 );
40 port(
41 rstn : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 almost_full : out std_logic_vector(FifoCnt-1 downto 0); -- TODO
51 empty : out std_logic_vector(FifoCnt-1 downto 0)
52 );
53 end entity;
39 PORT(
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
44
45 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
46 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
47
48 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
50
51 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
52 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
53 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
54 );
55 END ENTITY;
54 56
55 57
56 architecture ar_lppFIFOxN of lppFIFOxN is
58 ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
57 59
58 begin
60 BEGIN
59 61
60 fifos: for i in 0 to FifoCnt-1 generate
61 FIFO0 : lpp_fifo
62 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
63 port map(rstn,ReUse(i),
64 rclk,
65 ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,
66 wclk,
67 wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),almost_full(i),open);
68 end generate;
62 fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
63 lpp_fifo_1: lpp_fifo
64 GENERIC MAP (
65 tech => tech,
66 Mem_use => Mem_use,
67 DataSz => Data_sz,
68 AddrSz => Addr_sz)
69 PORT MAP (
70 clk => clk,
71 rstn => rstn,
72 reUse => reUse(I),
73 ren => ren(I),
74 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
75 wen => wen(I),
76 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
77 empty => empty(I),
78 full => full(I),
79 almost_full => almost_full(I));
80 END GENERATE;
69 81
70 end architecture;
82 END ARCHITECTURE;
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@@ -1,188 +1,188
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.lpp_memory.ALL;
27 27 USE lpp.iir_filter.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30
31 31 ENTITY lpp_fifo IS
32 32 GENERIC(
33 33 tech : INTEGER := 0;
34 34 Mem_use : INTEGER := use_RAM;
35 Enable_ReUse : STD_LOGIC := '0';
36 35 DataSz : INTEGER RANGE 1 TO 32 := 8;
37 36 AddrSz : INTEGER RANGE 2 TO 12 := 8
38 37 );
39 38 PORT(
39 clk : IN STD_LOGIC;
40 40 rstn : IN STD_LOGIC;
41 ReUse : IN STD_LOGIC;
42 rclk : IN STD_LOGIC;
41 --
42 reUse : IN STD_LOGIC;
43
44 --IN
43 45 ren : IN STD_LOGIC;
44 46 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
45 empty : OUT STD_LOGIC;
46 raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
47 wclk : IN STD_LOGIC;
47
48 --OUT
48 49 wen : IN STD_LOGIC;
49 50 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51
52 empty : OUT STD_LOGIC;
50 53 full : OUT STD_LOGIC;
51 almost_full : OUT STD_LOGIC; -- TODO
52 waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
54 almost_full : OUT STD_LOGIC
53 55 );
54 56 END ENTITY;
55 57
56 58
57 59 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
58 60
59 61 SIGNAL sFull : STD_LOGIC;
60 62 SIGNAL sFull_s : STD_LOGIC;
61 63 SIGNAL sEmpty_s : STD_LOGIC;
62 64
63 65 SIGNAL sEmpty : STD_LOGIC;
64 66 SIGNAL sREN : STD_LOGIC;
65 67 SIGNAL sWEN : STD_LOGIC;
66 68 SIGNAL sRE : STD_LOGIC;
67 69 SIGNAL sWE : STD_LOGIC;
68 70
69 71 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
70 72 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
71 73 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72 74 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
73 75
74 76 SIGNAL almost_full_s : STD_LOGIC;
75 77 SIGNAL almost_full_r : STD_LOGIC;
76 78 BEGIN
77 79
78 80 --==================================================================================
79 81 -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\
80 82 -- A l'inverse de RAM_CEL !!!
81 83 --==================================================================================
82 84 memRAM : IF Mem_use = use_RAM GENERATE
83 85 SRAM : syncram_2p
84 86 GENERIC MAP(tech, AddrSz, DataSz)
85 PORT MAP(RCLK, sRE, Raddr_vect, rdata, WCLK, sWE, Waddr_vect, wdata);
87 PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
86 88 END GENERATE;
87 89 --==================================================================================
88 90 memCEL : IF Mem_use = use_CEL GENERATE
89 91 CRAM : RAM_CEL
90 92 GENERIC MAP(DataSz, AddrSz)
91 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
93 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
92 94 END GENERATE;
93 95 --==================================================================================
94 96
95 97 --=============================
96 98 -- Read section
97 99 --=============================
98 100 sREN <= REN OR sEmpty;
99 101 sRE <= NOT sREN;
100 102
101 sEmpty_s <= '0' WHEN ReUse = '1' AND Enable_ReUse = '1' else
103 sEmpty_s <= '0' WHEN ReUse = '1' else
102 104 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
103 105 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
104 106 '0';
105 107
106 108 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
107 109
108 PROCESS (rclk, rstn)
110 PROCESS (clk, rstn)
109 111 BEGIN
110 112 IF(rstn = '0')then
111 113 Raddr_vect <= (OTHERS => '0');
112 114 sempty <= '1';
113 ELSIF(rclk'EVENT AND rclk = '1')then
115 ELSIF(clk'EVENT AND clk = '1')then
114 116 sEmpty <= sempty_s;
115 117
116 118 IF(sREN = '0' and sempty = '0')then
117 119 Raddr_vect <= Raddr_vect_s;
118 120 END IF;
119 121
120 122 END IF;
121 123 END PROCESS;
122 124
123 125 --=============================
124 126 -- Write section
125 127 --=============================
126 128 sWEN <= WEN OR sFull;
127 129 sWE <= NOT sWEN;
128 130
129 sFull_s <= '1' WHEN ReUse = '1' AND Enable_ReUse = '1' else
131 sFull_s <= '1' WHEN ReUse = '1' else
130 132 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
131 133 '1' WHEN sFull = '1' AND REN = '1' ELSE
132 134 '0';
133 135
134 136 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
135 137 '1' WHEN almost_full_r = '1' AND WEN = REN ELSE
136 138 '0';
137 139
138 140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
139 141
140 PROCESS (wclk, rstn)
142 PROCESS (clk, rstn)
141 143 BEGIN
142 144 IF(rstn = '0')then
143 145 Waddr_vect <= (OTHERS => '0');
144 146 sfull <= '0';
145 147 almost_full_r <= '0';
146 ELSIF(wclk'EVENT AND wclk = '1')then
148 ELSIF(clk'EVENT AND clk = '1')then
147 149 sfull <= sfull_s;
148 150 almost_full_r <= almost_full_s;
149 151
150 152 IF(sWEN = '0' and sfull = '0')THEN
151 153 Waddr_vect <= Waddr_vect_s;
152 154 END IF;
153 155
154 156 END IF;
155 157 END PROCESS;
156 158
157 159 almost_full <= almost_full_s;
158 160 full <= sFull_s;
159 161 empty <= sEmpty_s;
160 waddr <= Waddr_vect;
161 raddr <= Raddr_vect;
162 162
163 163 END ARCHITECTURE;
164 164
165 165
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1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9
10 use lpp.lpp_fft.all;
11 use lpp.fft_components.all;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
12 16
13 17 ENTITY lpp_lfr_ms IS
14 18 GENERIC (
15 19 Mem_use : INTEGER := use_RAM
16 20 );
17 21 PORT (
18 22 clk : IN STD_LOGIC;
19 23 rstn : IN STD_LOGIC;
20 24
21 25 ---------------------------------------------------------------------------
22 26 -- DATA INPUT
23 27 ---------------------------------------------------------------------------
24 28 -- TIME
25 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
26 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
27 31 --
28 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 34 --
31 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 37 --
34 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 40
37 41 ---------------------------------------------------------------------------
38 42 -- DMA
39 43 ---------------------------------------------------------------------------
40 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 46 dma_valid : OUT STD_LOGIC;
43 47 dma_valid_burst : OUT STD_LOGIC;
44 48 dma_ren : IN STD_LOGIC;
45 49 dma_done : IN STD_LOGIC;
46 50
47 51 -- Reg out
48 52 ready_matrix_f0_0 : OUT STD_LOGIC;
49 53 ready_matrix_f0_1 : OUT STD_LOGIC;
50 54 ready_matrix_f1 : OUT STD_LOGIC;
51 55 ready_matrix_f2 : OUT STD_LOGIC;
52 56 error_anticipating_empty_fifo : OUT STD_LOGIC;
53 57 error_bad_component_error : OUT STD_LOGIC;
54 58 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 59
56 60 -- Reg In
57 61 status_ready_matrix_f0_0 : IN STD_LOGIC;
58 62 status_ready_matrix_f0_1 : IN STD_LOGIC;
59 63 status_ready_matrix_f1 : IN STD_LOGIC;
60 64 status_ready_matrix_f2 : IN STD_LOGIC;
61 65 status_error_anticipating_empty_fifo : IN STD_LOGIC;
62 66 status_error_bad_component_error : IN STD_LOGIC;
63 67
64 68 config_active_interruption_onNewMatrix : IN STD_LOGIC;
65 69 config_active_interruption_onError : IN STD_LOGIC;
66 70 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 71 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 74
71 75 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
72 76 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
73 77 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
74 78 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
75 79
76 80 );
77 81 END;
78 82
79 83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
80 84
81 85 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 86 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 87 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 88 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 89 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 90
87 91 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 92 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 93 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 94 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 95 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 96
93 97 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94 98 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 99 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 100 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97
101
98 102 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 103
100 104 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 105 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 106 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 107 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 108
105 109 SIGNAL error_wen_f0 : STD_LOGIC;
106 110 SIGNAL error_wen_f1 : STD_LOGIC;
107 111 SIGNAL error_wen_f2 : STD_LOGIC;
108
112
109 113 SIGNAL one_sample_f1_full : STD_LOGIC;
110 114 SIGNAL one_sample_f1_wen : STD_LOGIC;
111 115 SIGNAL one_sample_f2_full : STD_LOGIC;
112 116 SIGNAL one_sample_f2_wen : STD_LOGIC;
113
117
114 118 -----------------------------------------------------------------------------
115 119 -- FSM / SWITCH SELECT CHANNEL
116 120 -----------------------------------------------------------------------------
117 121 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
118 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL state_fsm_select_channel : fsm_select_channel;
123 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
119 124
120 125 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
121 126 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 127 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 128 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 129
125 130 -----------------------------------------------------------------------------
126 131 -- FSM LOAD FFT
127 132 -----------------------------------------------------------------------------
128 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, FIFO_transition);
129 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
134 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
130 135 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
131 136
132 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 SIGNAL sample_load : STD_LOGIC;
134 SIGNAL sample_valid : STD_LOGIC;
137 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
138 SIGNAL sample_load : STD_LOGIC;
139 SIGNAL sample_valid : STD_LOGIC;
135 140 SIGNAL sample_valid_r : STD_LOGIC;
136 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
137
141 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
142
138 143
139 144 -----------------------------------------------------------------------------
140 145 -- FFT
141 146 -----------------------------------------------------------------------------
142 SIGNAL fft_read : STD_LOGIC;
143 SIGNAL fft_pong : STD_LOGIC;
144 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
145 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
146 SIGNAL fft_data_valid : STD_LOGIC;
147 SIGNAL fft_ready : STD_LOGIC;
147 SIGNAL fft_read : STD_LOGIC;
148 SIGNAL fft_pong : STD_LOGIC;
149 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 SIGNAL fft_data_valid : STD_LOGIC;
152 SIGNAL fft_ready : STD_LOGIC;
153 -----------------------------------------------------------------------------
154 SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 -----------------------------------------------------------------------------
156 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
157 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
158 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 SIGNAL current_fifo_empty : STD_LOGIC;
160 SIGNAL current_fifo_locked : STD_LOGIC;
161 SIGNAL current_fifo_full : STD_LOGIC;
162 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
148 163
164 -----------------------------------------------------------------------------
165 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 -----------------------------------------------------------------------------
174 SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 SIGNAL HEAD_SM_Wen : STD_LOGIC;
177 SIGNAL HEAD_Valid : STD_LOGIC;
178 SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL HEAD_Empty : STD_LOGIC;
180 SIGNAL HEAD_Read : STD_LOGIC;
181 -----------------------------------------------------------------------------
182 SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
183 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
185 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
188 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
189 -----------------------------------------------------------------------------
190 SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL DMA_Header_Val : STD_LOGIC;
192 SIGNAL DMA_Header_Ack : STD_LOGIC;
193
194 -----------------------------------------------------------------------------
195 -- TIME REG & INFOs
196 -----------------------------------------------------------------------------
197 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
198
199 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
200 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
201 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
202 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
203
204 SIGNAL time_update_f0_A : STD_LOGIC;
205 SIGNAL time_update_f0_B : STD_LOGIC;
206 SIGNAL time_update_f1 : STD_LOGIC;
207 SIGNAL time_update_f2 : STD_LOGIC;
208 --
209 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
210
211 SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 -----------------------------------------------------------------------------
213
149 214 BEGIN
150 215
151 216 switch_f0_inst : spectral_matrix_switch_f0
152 217 PORT MAP (
153 218 clk => clk,
154 219 rstn => rstn,
155 220
156 221 sample_wen => sample_f0_wen,
157 222
158 223 fifo_A_empty => sample_f0_A_empty,
159 224 fifo_A_full => sample_f0_A_full,
160 225 fifo_A_wen => sample_f0_A_wen,
161 226
162 227 fifo_B_empty => sample_f0_B_empty,
163 228 fifo_B_full => sample_f0_B_full,
164 229 fifo_B_wen => sample_f0_B_wen,
165 230
166 error_wen => error_wen_f0); -- TODO
231 error_wen => error_wen_f0); -- TODO
167 232
168 233 -----------------------------------------------------------------------------
169 234 -- FIFO IN
170 235 -----------------------------------------------------------------------------
171 236 lppFIFOxN_f0_a : lppFIFOxN
172 237 GENERIC MAP (
173 238 tech => 0,
174 239 Mem_use => Mem_use,
175 240 Data_sz => 16,
176 241 Addr_sz => 8,
177 FifoCnt => 5,
178 Enable_ReUse => '0')
242 FifoCnt => 5)
179 243 PORT MAP (
244 clk => clk,
180 245 rstn => rstn,
181 wclk => clk,
182 rclk => clk,
246
183 247 ReUse => (OTHERS => '0'),
184 248
185 wen => sample_f0_A_wen, -- IN in
186 ren => sample_f0_A_ren, -- OUT in
187 wdata => sample_f0_wdata, -- IN in
188 rdata => sample_f0_A_rdata, -- OUT in
189 full => sample_f0_A_full, -- IN out
190 almost_full => OPEN, -- IN out
191 empty => sample_f0_A_empty); -- OUT OUT
249 wen => sample_f0_A_wen,
250 wdata => sample_f0_wdata,
251
252 ren => sample_f0_A_ren,
253 rdata => sample_f0_A_rdata,
254
255 empty => sample_f0_A_empty,
256 full => sample_f0_A_full,
257 almost_full => OPEN);
192 258
193 259 lppFIFOxN_f0_b : lppFIFOxN
194 260 GENERIC MAP (
195 261 tech => 0,
196 262 Mem_use => Mem_use,
197 263 Data_sz => 16,
198 264 Addr_sz => 8,
199 FifoCnt => 5,
200 Enable_ReUse => '0')
265 FifoCnt => 5)
201 266 PORT MAP (
267 clk => clk,
202 268 rstn => rstn,
203 wclk => clk,
204 rclk => clk,
269
205 270 ReUse => (OTHERS => '0'),
206 271
207 wen => sample_f0_B_wen, -- IN in
208 ren => sample_f0_B_ren, -- OUT in
209 wdata => sample_f0_wdata, -- IN in
210 rdata => sample_f0_B_rdata, -- OUT in
211 full => sample_f0_B_full, -- IN out
212 almost_full => OPEN, -- IN out
213 empty => sample_f0_B_empty); -- OUT OUT
272 wen => sample_f0_B_wen,
273 wdata => sample_f0_wdata,
274 ren => sample_f0_B_ren,
275 rdata => sample_f0_B_rdata,
276 empty => sample_f0_B_empty,
277 full => sample_f0_B_full,
278 almost_full => OPEN);
214 279
215 280 lppFIFOxN_f1 : lppFIFOxN
216 281 GENERIC MAP (
217 282 tech => 0,
218 283 Mem_use => Mem_use,
219 284 Data_sz => 16,
220 285 Addr_sz => 8,
221 FifoCnt => 5,
222 Enable_ReUse => '0')
286 FifoCnt => 5)
223 287 PORT MAP (
288 clk => clk,
224 289 rstn => rstn,
225 wclk => clk,
226 rclk => clk,
290
227 291 ReUse => (OTHERS => '0'),
228 292
229 wen => sample_f1_wen, -- IN in
230 ren => sample_f1_ren, -- OUT in
231 wdata => sample_f1_wdata, -- IN in
232 rdata => sample_f1_rdata, -- OUT in
233 full => sample_f1_full, -- IN out
234 almost_full => sample_f1_almost_full, -- IN out
235 empty => sample_f1_empty); -- OUT OUT
293 wen => sample_f1_wen,
294 wdata => sample_f1_wdata,
295 ren => sample_f1_ren,
296 rdata => sample_f1_rdata,
297 empty => sample_f1_empty,
298 full => sample_f1_full,
299 almost_full => sample_f1_almost_full);
236 300
237 301
238 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
302 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
239 303
240 304 PROCESS (clk, rstn)
241 305 BEGIN -- PROCESS
242 306 IF rstn = '0' THEN -- asynchronous reset (active low)
243 one_sample_f1_full <= '0';
244 error_wen_f1 <= '0';
245 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
307 one_sample_f1_full <= '0';
308 error_wen_f1 <= '0';
309 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
246 310 IF sample_f1_full = "00000" THEN
247 311 one_sample_f1_full <= '0';
248 312 ELSE
249 313 one_sample_f1_full <= '1';
250 314 END IF;
251 315 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
252 316 END IF;
253 317 END PROCESS;
254
318
255 319
256 320 lppFIFOxN_f2 : lppFIFOxN
257 321 GENERIC MAP (
258 322 tech => 0,
259 323 Mem_use => Mem_use,
260 324 Data_sz => 16,
261 325 Addr_sz => 8,
262 FifoCnt => 5,
263 Enable_ReUse => '0')
326 FifoCnt => 5)
264 327 PORT MAP (
328 clk => clk,
265 329 rstn => rstn,
266 wclk => clk,
267 rclk => clk,
330
268 331 ReUse => (OTHERS => '0'),
269 332
270 wen => sample_f2_wen, -- IN in
271 ren => sample_f2_ren, -- OUT in
272 wdata => sample_f2_wdata, -- IN in
273 rdata => sample_f2_rdata, -- OUT in
274 full => sample_f2_full, -- IN out
275 almost_full => OPEN, -- IN out
276 empty => sample_f2_empty); -- OUT OUT
333 wen => sample_f2_wen,
334 wdata => sample_f2_wdata,
335 ren => sample_f2_ren,
336 rdata => sample_f2_rdata,
337 empty => sample_f2_empty,
338 full => sample_f2_full,
339 almost_full => OPEN);
277 340
278 341
279 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
280
342 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
343
281 344 PROCESS (clk, rstn)
282 345 BEGIN -- PROCESS
283 346 IF rstn = '0' THEN -- asynchronous reset (active low)
284 one_sample_f2_full <= '0';
285 error_wen_f2 <= '0';
286 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
347 one_sample_f2_full <= '0';
348 error_wen_f2 <= '0';
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
287 350 IF sample_f2_full = "00000" THEN
288 351 one_sample_f2_full <= '0';
289 352 ELSE
290 353 one_sample_f2_full <= '1';
291 354 END IF;
292 355 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
293 356 END IF;
294 357 END PROCESS;
295 358
296 359 -----------------------------------------------------------------------------
297 360 -- FSM SELECT CHANNEL
298 361 -----------------------------------------------------------------------------
299 362 PROCESS (clk, rstn)
300 363 BEGIN
301 364 IF rstn = '0' THEN
302 365 state_fsm_select_channel <= IDLE;
303 366 ELSIF clk'EVENT AND clk = '1' THEN
304 367 CASE state_fsm_select_channel IS
305 368 WHEN IDLE =>
306 369 IF sample_f1_full = "11111" THEN
307 370 state_fsm_select_channel <= SWITCH_F1;
308 371 ELSIF sample_f1_almost_full = "00000" THEN
309 372 IF sample_f0_A_full = "11111" THEN
310 373 state_fsm_select_channel <= SWITCH_F0_A;
311 374 ELSIF sample_f0_B_full = "11111" THEN
312 375 state_fsm_select_channel <= SWITCH_F0_B;
313 376 ELSIF sample_f2_full = "11111" THEN
314 377 state_fsm_select_channel <= SWITCH_F2;
315 378 END IF;
316 379 END IF;
317 380
318 381 WHEN SWITCH_F0_A =>
319 382 IF sample_f0_A_empty = "11111" THEN
320 383 state_fsm_select_channel <= IDLE;
321 384 END IF;
322 385 WHEN SWITCH_F0_B =>
323 386 IF sample_f0_B_empty = "11111" THEN
324 387 state_fsm_select_channel <= IDLE;
325 388 END IF;
326 389 WHEN SWITCH_F1 =>
327 390 IF sample_f1_empty = "11111" THEN
328 391 state_fsm_select_channel <= IDLE;
329 392 END IF;
330 393 WHEN SWITCH_F2 =>
331 394 IF sample_f2_empty = "11111" THEN
332 395 state_fsm_select_channel <= IDLE;
333 396 END IF;
334 397 WHEN OTHERS => NULL;
335 398 END CASE;
336 399
337 400 END IF;
338 401 END PROCESS;
339 402
403 PROCESS (clk, rstn)
404 BEGIN
405 IF rstn = '0' THEN
406 pre_state_fsm_select_channel <= IDLE;
407 ELSIF clk'EVENT AND clk = '1' THEN
408 pre_state_fsm_select_channel <= state_fsm_select_channel;
409 END IF;
410 END PROCESS;
340 411
341 412
342 413 -----------------------------------------------------------------------------
343 414 -- SWITCH SELECT CHANNEL
344 415 -----------------------------------------------------------------------------
345 416 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
346 417 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
347 418 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
348 419 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
349 420 (OTHERS => '1');
350 421
351 422 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
352 423 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
353 424 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
354 425 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
355 426 (OTHERS => '0');
356 427
357 sample_rdata <= sample_f0_A_rdata WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
358 sample_f0_B_rdata WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
359 sample_f1_rdata WHEN state_fsm_select_channel = SWITCH_F1 ELSE
428 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
429 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
430 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
360 431 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
361 432
362 433
363 434 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
364 435 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
365 436 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
366 437 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
367 438
439
440 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
441 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
442 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
443 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
444
368 445 -----------------------------------------------------------------------------
369 446 -- FSM LOAD FFT
370 447 -----------------------------------------------------------------------------
371 448
372 sample_ren <= sample_ren_s;-- OR sample_empty;
373
449 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
450
374 451 PROCESS (clk, rstn)
375 452 BEGIN
376 453 IF rstn = '0' THEN
377 sample_ren_s <= (OTHERS => '1');
378 state_fsm_load_FFT <= IDLE;
379 next_state_fsm_load_FFT <= IDLE;
380 sample_valid <= '0';
381 ELSIF clk'event AND clk = '1' THEN
454 sample_ren_s <= (OTHERS => '1');
455 state_fsm_load_FFT <= IDLE;
456 --next_state_fsm_load_FFT <= IDLE;
457 --sample_valid <= '0';
458 ELSIF clk'EVENT AND clk = '1' THEN
382 459 CASE state_fsm_load_FFT IS
383 WHEN IDLE =>
384 sample_valid <= '0';
460 WHEN IDLE =>
461 --sample_valid <= '0';
385 462 sample_ren_s <= (OTHERS => '1');
386 463 IF sample_full = "11111" AND sample_load = '1' THEN
387 464 state_fsm_load_FFT <= FIFO_1;
388 465 END IF;
389 WHEN FIFO_1 =>
466
467 WHEN FIFO_1 =>
390 468 sample_ren_s <= "1111" & NOT(sample_load);
391 sample_valid <= '1';
392 469 IF sample_empty(0) = '1' THEN
393 sample_valid <= '0';
394 sample_ren_s <= (OTHERS => '1');
395 state_fsm_load_FFT <= FIFO_transition;
396 next_state_fsm_load_FFT <= FIFO_2;
470 sample_ren_s <= (OTHERS => '1');
471 state_fsm_load_FFT <= FIFO_2;
472 END IF;
473
474 WHEN FIFO_2 =>
475 sample_ren_s <= "111" & NOT(sample_load) & '1';
476 IF sample_empty(1) = '1' THEN
477 sample_ren_s <= (OTHERS => '1');
478 state_fsm_load_FFT <= FIFO_3;
397 479 END IF;
398 480
399 WHEN FIFO_transition =>
400 sample_valid <= '0';
401 sample_ren_s <= (OTHERS => '1');
402 state_fsm_load_FFT <= next_state_fsm_load_FFT;
403
404 WHEN FIFO_2 =>
405 sample_ren_s <= "111" & NOT(sample_load) & '1';
406 sample_valid <= sample_load;
407 IF sample_empty(1) = '1' THEN
408 sample_valid <= '0';
409 sample_ren_s <= (OTHERS => '1');
410 state_fsm_load_FFT <= FIFO_transition;
411 next_state_fsm_load_FFT <= FIFO_3;
412 END IF;
413 WHEN FIFO_3 =>
481 WHEN FIFO_3 =>
414 482 sample_ren_s <= "11" & NOT(sample_load) & "11";
415 sample_valid <= sample_load;--'1';
416 483 IF sample_empty(2) = '1' THEN
417 sample_valid <= '0';
418 sample_ren_s <= (OTHERS => '1');
419 state_fsm_load_FFT <= FIFO_transition;
420 next_state_fsm_load_FFT <= FIFO_4;
484 sample_ren_s <= (OTHERS => '1');
485 state_fsm_load_FFT <= FIFO_4;
421 486 END IF;
422 WHEN FIFO_4 =>
487
488 WHEN FIFO_4 =>
423 489 sample_ren_s <= '1' & NOT(sample_load) & "111";
424 sample_valid <= sample_load;--'1';
425 490 IF sample_empty(3) = '1' THEN
426 sample_valid <= '0';
427 sample_ren_s <= (OTHERS => '1');
428 state_fsm_load_FFT <= FIFO_transition;
429 next_state_fsm_load_FFT <= FIFO_5;
491 sample_ren_s <= (OTHERS => '1');
492 state_fsm_load_FFT <= FIFO_5;
430 493 END IF;
431 WHEN FIFO_5 =>
494
495 WHEN FIFO_5 =>
432 496 sample_ren_s <= NOT(sample_load) & "1111";
433 sample_valid <= sample_load;--'1';
434 497 IF sample_empty(4) = '1' THEN
435 sample_valid <= '0';
436 sample_ren_s <= (OTHERS => '1');
437 state_fsm_load_FFT <= FIFO_transition;
438 next_state_fsm_load_FFT <= IDLE;
498 sample_ren_s <= (OTHERS => '1');
499 state_fsm_load_FFT <= IDLE;
439 500 END IF;
440 501 WHEN OTHERS => NULL;
441 502 END CASE;
442 503 END IF;
443 504 END PROCESS;
444 505
445 506 PROCESS (clk, rstn)
446 507 BEGIN
447 508 IF rstn = '0' THEN
448 sample_valid_r <= '0';
449 ELSIF clk'event AND clk = '1' THEN
450 sample_valid_r <= sample_valid AND sample_load;
509 sample_valid_r <= '0';
510 next_state_fsm_load_FFT <= IDLE;
511 ELSIF clk'EVENT AND clk = '1' THEN
512 next_state_fsm_load_FFT <= state_fsm_load_FFT;
513 IF sample_ren_s = "11111" THEN
514 sample_valid_r <= '0';
515 ELSE
516 sample_valid_r <= '1';
517 END IF;
451 518 END IF;
452 519 END PROCESS;
453 520
454 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN state_fsm_load_FFT = FIFO_1 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_2) ELSE
455 sample_rdata(16*2-1 DOWNTO 16*1) WHEN state_fsm_load_FFT = FIFO_2 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_3) ELSE
456 sample_rdata(16*3-1 DOWNTO 16*2) WHEN state_fsm_load_FFT = FIFO_3 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_4) ELSE
457 sample_rdata(16*4-1 DOWNTO 16*3) WHEN state_fsm_load_FFT = FIFO_4 OR (state_fsm_load_FFT = FIFO_transition AND next_state_fsm_load_FFT = FIFO_5) ELSE
458 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN state_fsm_load_FFT = FIFO_5 ELSE
521 sample_valid <= sample_valid_r AND sample_load;
522
523 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
524 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
525 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
526 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
527 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
459 528
460 529 -----------------------------------------------------------------------------
461 530 -- FFT
462 531 -----------------------------------------------------------------------------
463 CoreFFT_1: CoreFFT
532 CoreFFT_1 : CoreFFT
464 533 GENERIC MAP (
465 534 LOGPTS => gLOGPTS,
466 535 LOGLOGPTS => gLOGLOGPTS,
467 536 WSIZE => gWSIZE,
468 537 TWIDTH => gTWIDTH,
469 538 DWIDTH => gDWIDTH,
470 539 TDWIDTH => gTDWIDTH,
471 540 RND_MODE => gRND_MODE,
472 541 SCALE_MODE => gSCALE_MODE,
473 542 PTS => gPTS,
474 543 HALFPTS => gHALFPTS,
475 544 inBuf_RWDLY => gInBuf_RWDLY)
476 545 PORT MAP (
477 clk => clk,
478 ifiStart => '1',
479 ifiNreset => rstn,
480
481 ifiD_valid => sample_valid_r, -- IN
546 clk => clk,
547 ifiStart => '1',
548 ifiNreset => rstn,
549
550 ifiD_valid => sample_valid, -- IN
482 551 ifiRead_y => fft_read,
483 552 ifiD_im => (OTHERS => '0'), -- IN
484 553 ifiD_re => sample_data, -- IN
485 554 ifoLoad => sample_load, -- IN
486 555
487 556 ifoPong => fft_pong,
488 557 ifoY_im => fft_data_im,
489 558 ifoY_re => fft_data_re,
490 559 ifoY_valid => fft_data_valid,
491 560 ifoY_rdy => fft_ready);
492 561
493 562 -----------------------------------------------------------------------------
494 --
563 -- in fft_data_im & fft_data_re
564 -- in fft_data_valid
565 -- in fft_ready
566 -- out fft_read
567 PROCESS (clk, rstn)
568 BEGIN
569 IF rstn = '0' THEN
570 state_fsm_load_MS_memory <= IDLE;
571 current_fifo_load <= "00001";
572 ELSIF clk'event AND clk = '1' THEN
573 CASE state_fsm_load_MS_memory IS
574 WHEN IDLE =>
575 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
576 state_fsm_load_MS_memory <= LOAD_FIFO;
577 END IF;
578 WHEN LOAD_FIFO =>
579 IF current_fifo_full = '1' THEN
580 state_fsm_load_MS_memory <= TRASH_FFT;
581 END IF;
582 WHEN TRASH_FFT =>
583 IF fft_ready = '0' THEN
584 state_fsm_load_MS_memory <= IDLE;
585 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
586 END IF;
587 WHEN OTHERS => NULL;
588 END CASE;
589
590 END IF;
591 END PROCESS;
592
593 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
594 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
595 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
596 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
597 MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
598
599 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
600 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
601 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
602 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
603 MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
604
605 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
606 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
607 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
608 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
609 MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
610
611 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
612
613 all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
614 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
615 AND state_fsm_load_MS_memory = LOAD_FIFO
616 AND current_fifo_load(I) = '1'
617 ELSE '1';
618 END GENERATE all_fifo;
619
620 PROCESS (clk, rstn)
621 BEGIN
622 IF rstn = '0' THEN
623 MEM_IN_SM_wen <= (OTHERS => '1');
624 ELSIF clk'event AND clk = '1' THEN
625 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
626 END IF;
627 END PROCESS;
628
629 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
630 (fft_data_im & fft_data_re) &
631 (fft_data_im & fft_data_re) &
632 (fft_data_im & fft_data_re) &
633 (fft_data_im & fft_data_re);
634
635
636 -- out SM_MEM_IN_wData
637 -- out SM_MEM_IN_wen
638 -- out SM_MEM_IN_Full
639
640 -- out SM_MEM_IN_locked
641 -----------------------------------------------------------------------------
642 -----------------------------------------------------------------------------
643 -----------------------------------------------------------------------------
644 -----------------------------------------------------------------------------
645 --Linker_FFT_1 : Linker_FFT
646 -- GENERIC MAP (
647 -- Data_sz => 16,
648 -- NbData => 256)
649 -- PORT MAP (
650 -- clk => clk,
651 -- rstn => rstn,
652
653 -- Ready => fft_ready,
654 -- Valid => fft_data_valid,
655
656 -- Full => MEM_IN_SM_Full,
657
658 -- Data_re => fft_data_re,
659 -- Data_im => fft_data_im,
660 -- Read => fft_read,
661
662 -- Write => MEM_IN_SM_wen,
663 -- ReUse => fft_linker_ReUse,
664 -- DATA => MEM_IN_SM_wData);
665
495 666 -----------------------------------------------------------------------------
496 fft_read <= '1';
497 -- fft_read OUT
498 -- fft_pong IN
499 -- fft_data_im IN
500 -- fft_data_re IN
501 -- fft_data_valid IN
502 -- fft_ready IN
667 Mem_In_SpectralMatrix : lppFIFOxN
668 GENERIC MAP (
669 tech => 0,
670 Mem_use => Mem_use,
671 Data_sz => 32, --16,
672 Addr_sz => 7, --8
673 FifoCnt => 5)
674 PORT MAP (
675 clk => clk,
676 rstn => rstn,
677
678 ReUse => MEM_IN_SM_ReUse,
679
680 wen => MEM_IN_SM_wen,
681 wdata => MEM_IN_SM_wData,
682
683 ren => MEM_IN_SM_ren,
684 rdata => MEM_IN_SM_rData,
685 full => MEM_IN_SM_Full,
686 empty => MEM_IN_SM_Empty);
687
688
689 all_lock: FOR I IN 4 DOWNTO 0 GENERATE
690 PROCESS (clk, rstn)
691 BEGIN
692 IF rstn = '0' THEN
693 MEM_IN_SM_locked(I) <= '0';
694 ELSIF clk'event AND clk = '1' THEN
695 MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
696 END IF;
697 END PROCESS;
698 END GENERATE all_lock;
699
700
701
702 -----------------------------------------------------------------------------
703 SM0 : MatriceSpectrale
704 GENERIC MAP (
705 Input_SZ => 16,
706 Result_SZ => 32)
707 PORT MAP (
708 clkm => clk,
709 rstn => rstn,
710
711 FifoIN_Full => MEM_IN_SM_Full,
712 Data_IN => MEM_IN_SM_rData(79 DOWNTO 0),
713 Read => MEM_IN_SM_ren,
714 ReUse => MEM_IN_SM_ReUse,
715
716 SetReUse => fft_linker_ReUse,
717
718 Valid => HEAD_Valid,
719 ACK => DMA_Header_Ack,
720 SM_Write => HEAD_SM_Wen,
721 FlagError => OPEN,
722 Statu => HEAD_SM_Param,
723 Write => MEM_OUT_SM_Write,
724 Data_OUT => MEM_OUT_SM_Data_in);
725 -----------------------------------------------------------------------------
726 Mem_Out_SpectralMatrix : lppFIFOxN
727 GENERIC MAP (
728 tech => 0,
729 Mem_use => Mem_use,
730 Data_sz => 32,
731 Addr_sz => 8,
732 FifoCnt => 2)
733 PORT MAP (
734 clk => clk,
735 rstn => rstn,
736
737 ReUse => (OTHERS => '0'),
738
739 wen => MEM_OUT_SM_Write,
740 wdata => MEM_OUT_SM_Data_in,
741 ren => MEM_OUT_SM_Read,
742 rdata => MEM_OUT_SM_Data_out,
743
744 full => MEM_OUT_SM_Full,
745 empty => MEM_OUT_SM_Empty);
746 -----------------------------------------------------------------------------
747 Head0 : HeaderBuilder
748 GENERIC MAP (
749 Data_sz => 32)
750 PORT MAP (
751 clkm => clk,
752 rstn => rstn,
753
754 Statu => HEAD_SM_Param,
755 Matrix_Type => HEAD_WorkFreq, -- TODO IN
756 Matrix_Write => HEAD_SM_Wen,
757 Valid => HEAD_Valid,
758
759 dataIN => MEM_OUT_SM_Data_out,
760 emptyIN => MEM_OUT_SM_Empty,
761 RenOUT => MEM_OUT_SM_Read,
762
763 dataOUT => HEAD_Data,
764 emptyOUT => HEAD_Empty,
765 RenIN => HEAD_Read,
766
767 header => DMA_Header,
768 header_val => DMA_Header_Val,
769 header_ack => DMA_Header_Ack);
770 -----------------------------------------------------------------------------
771 -----------------------------------------------------------------------------
772 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
773 PORT MAP (
774 HCLK => clk,
775 HRESETn => rstn,
776
777 data_time => dma_time,
778
779 fifo_data => HEAD_Data,
780 fifo_empty => HEAD_Empty,
781 fifo_ren => HEAD_Read,
782
783 header => DMA_Header,
784 header_val => DMA_Header_Val,
785 header_ack => DMA_Header_Ack,
786
787 dma_addr => dma_addr,
788 dma_data => dma_data,
789 dma_valid => dma_valid,
790 dma_valid_burst => dma_valid_burst,
791 dma_ren => dma_ren,
792 dma_done => dma_done,
793
794 ready_matrix_f0_0 => ready_matrix_f0_0,
795 ready_matrix_f0_1 => ready_matrix_f0_1,
796 ready_matrix_f1 => ready_matrix_f1,
797 ready_matrix_f2 => ready_matrix_f2,
798 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
799 error_bad_component_error => error_bad_component_error,
800 debug_reg => debug_reg,
801 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
802 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
803 status_ready_matrix_f1 => status_ready_matrix_f1,
804 status_ready_matrix_f2 => status_ready_matrix_f2,
805 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
806 status_error_bad_component_error => status_error_bad_component_error,
807 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
808 config_active_interruption_onError => config_active_interruption_onError,
809 addr_matrix_f0_0 => addr_matrix_f0_0,
810 addr_matrix_f0_1 => addr_matrix_f0_1,
811 addr_matrix_f1 => addr_matrix_f1,
812 addr_matrix_f2 => addr_matrix_f2,
813
814 matrix_time_f0_0 => matrix_time_f0_0,
815 matrix_time_f0_1 => matrix_time_f0_1,
816 matrix_time_f1 => matrix_time_f1,
817 matrix_time_f2 => matrix_time_f2
818 );
819 -----------------------------------------------------------------------------
503 820
504 821 -----------------------------------------------------------------------------
505 --
822 -----------------------------------------------------------------------------
823 -----------------------------------------------------------------------------
824 -----------------------------------------------------------------------------
825 -----------------------------------------------------------------------------
506 826 -----------------------------------------------------------------------------
827
828
829
830
831
832
833 -----------------------------------------------------------------------------
834 -- TIME MANAGMENT
835 -----------------------------------------------------------------------------
836 all_time <= coarse_time & fine_time;
837 --
838 time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
839 '1' WHEN sample_f0_A_empty = "11111" ELSE
840 '0';
507 841
508 dma_addr <= (OTHERS => '0');
509 dma_data <= (OTHERS => '0');
510 dma_valid <= '0';
511 dma_valid_burst <= '0';
842 s_m_t_m_f0_A : spectral_matrix_time_managment
843 PORT MAP (
844 clk => clk,
845 rstn => rstn,
846 time_in => all_time,
847 update_1 => time_update_f0_A,
848 time_out => time_reg_f0_A);
849
850 --
851 time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
852 '1' WHEN sample_f0_B_empty = "11111" ELSE
853 '0';
512 854
513 ready_matrix_f0_0 <= '0';
514 ready_matrix_f0_1 <= '0';
515 ready_matrix_f1 <= '0';
516 ready_matrix_f2 <= '0';
517 error_anticipating_empty_fifo <= '0';
518 error_bad_component_error <= '0';
519 debug_reg <= (OTHERS => '0');
855 s_m_t_m_f0_B : spectral_matrix_time_managment
856 PORT MAP (
857 clk => clk,
858 rstn => rstn,
859 time_in => all_time,
860 update_1 => time_update_f0_B,
861 time_out => time_reg_f0_B);
862
863 --
864 time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
865 '1' WHEN sample_f1_empty = "11111" ELSE
866 '0';
867
868 s_m_t_m_f1 : spectral_matrix_time_managment
869 PORT MAP (
870 clk => clk,
871 rstn => rstn,
872 time_in => all_time,
873 update_1 => time_update_f1,
874 time_out => time_reg_f1);
520 875
521 matrix_time_f0_0 <= (OTHERS => '0');
522 matrix_time_f0_1 <= (OTHERS => '0');
523 matrix_time_f1 <= (OTHERS => '0');
524 matrix_time_f2 <= (OTHERS => '0');
876 --
877 time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
878 '1' WHEN sample_f2_empty = "11111" ELSE
879 '0';
880
881 s_m_t_m_f2 : spectral_matrix_time_managment
882 PORT MAP (
883 clk => clk,
884 rstn => rstn,
885 time_in => all_time,
886 update_1 => time_update_f2,
887 time_out => time_reg_f2);
525 888
526
889 -----------------------------------------------------------------------------
890 dma_time <= (OTHERS => '0'); -- TODO
891 -----------------------------------------------------------------------------
892
893
894
527 895 END Behavioral;
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@@ -1,199 +1,241
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
30 library gaisler;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
33 library techmap;
34 use techmap.gencomp.all;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
24 LIBRARY grlib;
25 USE grlib.amba.ALL;
26 USE std.textio.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_amba.ALL;
29 USE lpp.iir_filter.ALL;
30 LIBRARY gaisler;
31 USE gaisler.misc.ALL;
32 USE gaisler.memctrl.ALL;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
35 35
36 36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
37 37
38 package lpp_memory is
39
40 component APB_FIFO is
41 generic (
42 tech : integer := apa3;
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
54 W : integer := 1
55 );
56 port (
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
73 end component;
38 PACKAGE lpp_memory IS
74 39
75 component FIFO_pipeline is
76 generic(
77 tech : integer := 0;
78 Mem_use : integer := use_RAM;
79 fifoCount : integer range 2 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
81 abits : integer range 2 to 12 := 8
82 );
83 port(
84 rstn : in std_logic;
85 ReUse : in std_logic;
86 rclk : in std_logic;
87 ren : in std_logic;
88 rdata : out std_logic_vector(DataSz-1 downto 0);
89 empty : out std_logic;
90 raddr : out std_logic_vector(abits-1 downto 0);
91 wclk : in std_logic;
92 wen : in std_logic;
93 wdata : in std_logic_vector(DataSz-1 downto 0);
94 full : out std_logic;
95 waddr : out std_logic_vector(abits-1 downto 0)
96 );
97 end component;
40 COMPONENT lpp_fifo
41 GENERIC (
42 tech : INTEGER;
43 Mem_use : INTEGER;
44 DataSz : INTEGER RANGE 1 TO 32;
45 AddrSz : INTEGER RANGE 2 TO 12);
46 PORT (
47 clk : IN STD_LOGIC;
48 rstn : IN STD_LOGIC;
49 reUse : IN STD_LOGIC;
50 ren : IN STD_LOGIC;
51 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
52 wen : IN STD_LOGIC;
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
54 empty : OUT STD_LOGIC;
55 full : OUT STD_LOGIC;
56 almost_full : OUT STD_LOGIC);
57 END COMPONENT;
98 58
99 component lpp_fifo is
100 generic(
101 tech : integer := 0;
102 Mem_use : integer := use_RAM;
103 Enable_ReUse : std_logic := '0';
104 DataSz : integer range 1 to 32 := 8;
105 AddrSz : integer range 2 to 12 := 8
106 );
107 port(
108 rstn : in std_logic;
109 ReUse : in std_logic; --27/01/12
110 rclk : in std_logic;
111 ren : in std_logic;
112 rdata : out std_logic_vector(DataSz-1 downto 0);
113 empty : out std_logic;
114 raddr : out std_logic_vector(AddrSz-1 downto 0);
115 wclk : in std_logic;
116 wen : in std_logic;
117 wdata : in std_logic_vector(DataSz-1 downto 0);
118 full : out std_logic;
119 almost_full : out std_logic;
120 waddr : out std_logic_vector(AddrSz-1 downto 0)
121 );
122 end component;
59 COMPONENT lppFIFOxN
60 GENERIC (
61 tech : INTEGER;
62 Mem_use : INTEGER;
63 Data_sz : INTEGER RANGE 1 TO 32;
64 Addr_sz : INTEGER RANGE 2 TO 12;
65 FifoCnt : INTEGER);
66 PORT (
67 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
70 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
71 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
72 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
73 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
74 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
75 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
76 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
77 END COMPONENT;
123 78
124 79
125 component lppFIFOxN is
126 generic(
127 tech : integer := 0;
128 Mem_use : integer := use_RAM;
129 Data_sz : integer range 1 to 32 := 8;
130 Addr_sz : integer range 1 to 32 := 8;
131 FifoCnt : integer := 1;
132 Enable_ReUse : std_logic := '0'
133 );
134 port(
135 rstn : in std_logic;
136 wclk : in std_logic;
137 rclk : in std_logic;
138 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
139 wen : in std_logic_vector(FifoCnt-1 downto 0);
140 ren : in std_logic_vector(FifoCnt-1 downto 0);
141 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
142 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
143 full : out std_logic_vector(FifoCnt-1 downto 0);
144 almost_full : out std_logic_vector(FifoCnt-1 downto 0);
145 empty : out std_logic_vector(FifoCnt-1 downto 0)
146 );
147 end component;
80
148 81
149 component FillFifo is
150 generic(
151 Data_sz : integer range 1 to 32 := 16;
152 Fifo_cnt : integer range 1 to 8 := 5
153 );
154 port(
155 clk : in std_logic;
156 raz : in std_logic;
157 write : out std_logic_vector(Fifo_cnt-1 downto 0);
158 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
159 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
160 );
161 end component;
82 COMPONENT APB_FIFO IS
83 GENERIC (
84 tech : INTEGER := apa3;
85 pindex : INTEGER := 0;
86 paddr : INTEGER := 0;
87 pmask : INTEGER := 16#fff#;
88 pirq : INTEGER := 0;
89 abits : INTEGER := 8;
90 FifoCnt : INTEGER := 2;
91 Data_sz : INTEGER := 16;
92 Addr_sz : INTEGER := 9;
93 Enable_ReUse : STD_LOGIC := '0';
94 Mem_use : INTEGER := use_RAM;
95 R : INTEGER := 1;
96 W : INTEGER := 1
97 );
98 PORT (
99 clk : IN STD_LOGIC; --! Horloge du composant
100 rst : IN STD_LOGIC; --! Reset general du composant
101 rclk : IN STD_LOGIC;
102 wclk : IN STD_LOGIC;
103 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
104 REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire
105 WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire
106 Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide
107 Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine
108 RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e
109 WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie
110 WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture)
111 RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
112 apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
113 apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
114 );
115 END COMPONENT;
116
117 COMPONENT FIFO_pipeline IS
118 GENERIC(
119 tech : INTEGER := 0;
120 Mem_use : INTEGER := use_RAM;
121 fifoCount : INTEGER RANGE 2 TO 32 := 8;
122 DataSz : INTEGER RANGE 1 TO 32 := 8;
123 abits : INTEGER RANGE 2 TO 12 := 8
124 );
125 PORT(
126 rstn : IN STD_LOGIC;
127 ReUse : IN STD_LOGIC;
128 rclk : IN STD_LOGIC;
129 ren : IN STD_LOGIC;
130 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
131 empty : OUT STD_LOGIC;
132 raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
133 wclk : IN STD_LOGIC;
134 wen : IN STD_LOGIC;
135 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
136 full : OUT STD_LOGIC;
137 waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
138 );
139 END COMPONENT;
162 140
163 component Bridge is
164 port(
165 clk : in std_logic;
166 raz : in std_logic;
167 EmptyUp : in std_logic;
168 FullDwn : in std_logic;
169 WriteDwn : out std_logic;
170 ReadUp : out std_logic
171 );
172 end component;
141 --COMPONENT lpp_fifo IS
142 -- GENERIC(
143 -- tech : INTEGER := 0;
144 -- Mem_use : INTEGER := use_RAM;
145 -- Enable_ReUse : STD_LOGIC := '0';
146 -- DataSz : INTEGER RANGE 1 TO 32 := 8;
147 -- AddrSz : INTEGER RANGE 2 TO 12 := 8
148 -- );
149 -- PORT(
150 -- rstn : IN STD_LOGIC;
151 -- ReUse : IN STD_LOGIC; --27/01/12
152 -- rclk : IN STD_LOGIC;
153 -- ren : IN STD_LOGIC;
154 -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
155 -- empty : OUT STD_LOGIC;
156 -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
157 -- wclk : IN STD_LOGIC;
158 -- wen : IN STD_LOGIC;
159 -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
160 -- full : OUT STD_LOGIC;
161 -- almost_full : OUT STD_LOGIC;
162 -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
163 -- );
164 --END COMPONENT;
165
166
167 --COMPONENT lppFIFOxN IS
168 -- GENERIC(
169 -- tech : INTEGER := 0;
170 -- Mem_use : INTEGER := use_RAM;
171 -- Data_sz : INTEGER RANGE 1 TO 32 := 8;
172 -- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
173 -- FifoCnt : INTEGER := 1;
174 -- Enable_ReUse : STD_LOGIC := '0'
175 -- );
176 -- PORT(
177 -- rstn : IN STD_LOGIC;
178 -- wclk : IN STD_LOGIC;
179 -- rclk : IN STD_LOGIC;
180 -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
181 -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
182 -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
183 -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
184 -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
185 -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
186 -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
187 -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
188 -- );
189 --END COMPONENT;
173 190
174 component ssram_plugin is
175 generic (tech : integer := 0);
176 port
177 (
178 clk : in std_logic;
179 mem_ctrlr_o : in memory_out_type;
180 SSRAM_CLK : out std_logic;
181 nBWa : out std_logic;
182 nBWb : out std_logic;
183 nBWc : out std_logic;
184 nBWd : out std_logic;
185 nBWE : out std_logic;
186 nADSC : out std_logic;
187 nADSP : out std_logic;
188 nADV : out std_logic;
189 nGW : out std_logic;
190 nCE1 : out std_logic;
191 CE2 : out std_logic;
192 nCE3 : out std_logic;
193 nOE : out std_logic;
194 MODE : out std_logic;
195 ZZ : out std_logic
196 );
197 end component;
191 COMPONENT FillFifo IS
192 GENERIC(
193 Data_sz : INTEGER RANGE 1 TO 32 := 16;
194 Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
195 );
196 PORT(
197 clk : IN STD_LOGIC;
198 raz : IN STD_LOGIC;
199 write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
200 reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
201 data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
202 );
203 END COMPONENT;
204
205 COMPONENT Bridge IS
206 PORT(
207 clk : IN STD_LOGIC;
208 raz : IN STD_LOGIC;
209 EmptyUp : IN STD_LOGIC;
210 FullDwn : IN STD_LOGIC;
211 WriteDwn : OUT STD_LOGIC;
212 ReadUp : OUT STD_LOGIC
213 );
214 END COMPONENT;
198 215
199 end;
216 COMPONENT ssram_plugin IS
217 GENERIC (tech : INTEGER := 0);
218 PORT
219 (
220 clk : IN STD_LOGIC;
221 mem_ctrlr_o : IN memory_out_type;
222 SSRAM_CLK : OUT STD_LOGIC;
223 nBWa : OUT STD_LOGIC;
224 nBWb : OUT STD_LOGIC;
225 nBWc : OUT STD_LOGIC;
226 nBWd : OUT STD_LOGIC;
227 nBWE : OUT STD_LOGIC;
228 nADSC : OUT STD_LOGIC;
229 nADSP : OUT STD_LOGIC;
230 nADV : OUT STD_LOGIC;
231 nGW : OUT STD_LOGIC;
232 nCE1 : OUT STD_LOGIC;
233 CE2 : OUT STD_LOGIC;
234 nCE3 : OUT STD_LOGIC;
235 nOE : OUT STD_LOGIC;
236 MODE : OUT STD_LOGIC;
237 ZZ : OUT STD_LOGIC
238 );
239 END COMPONENT;
240
241 END;
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@@ -1,20 +1,29
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 PACKAGE spectral_matrix_package IS
5 5
6 6 COMPONENT spectral_matrix_switch_f0
7 7 PORT (
8 8 clk : IN STD_LOGIC;
9 9 rstn : IN STD_LOGIC;
10 10 sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
11 11 fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
12 12 fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
13 13 fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
14 14 fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 15 fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
16 16 fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 17 error_wen : OUT STD_LOGIC);
18 18 END COMPONENT;
19 19
20 COMPONENT spectral_matrix_time_managment
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
25 update_1 : IN STD_LOGIC;
26 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
27 END COMPONENT;
28
20 29 END spectral_matrix_package;
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@@ -1,64 +1,81
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
6 6 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
7 7 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
8 8 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
9 9 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
10 10 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
11 11 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
12 12 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
13 13 add wave -noupdate -expand -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
14 14 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
15 15 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
16 16 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
17 17 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
18 18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
19 19 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
20 20 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
21 21 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
22 22 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
23 23 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
24 24 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
25 25 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
26 26 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
27 27 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
28 28 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
29 29 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
30 30 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
31 31 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload
32 32 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im
33 33 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re
34 34 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid
35 35 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset
36 36 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart
37 37 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
38 38 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
39 39 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
40 40 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y
41 41 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
42 42 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
43 43 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
44 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
45 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
44 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
45 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
46 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray
47 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
48 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
49 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(56) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(57) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(58) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(59) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(60) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(61) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(62) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(63) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(64) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(65) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(66) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(67) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(68) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(69) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(70) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(71) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(72) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(73) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(74) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(75) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(76) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(77) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(78) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(79) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(80) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(81) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(82) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(83) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(84) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(85) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(86) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(87) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(88) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(89) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(90) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(91) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(92) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(93) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(94) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(95) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(96) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(97) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(98) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(99) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(100) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(101) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(102) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(103) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(104) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(105) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(106) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(107) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(108) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(109) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(110) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(111) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(112) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(113) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(114) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(115) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(116) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(117) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(118) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(119) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(120) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(121) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(122) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(123) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(124) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(125) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(126) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray(127) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
50 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
51 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
52 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
53 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
54 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
55 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
56 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
57 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
58 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
59 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
60 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
61 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
62 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
46 63 TreeUpdate [SetDefaultTree]
47 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {27617887437 ps} 0} {{Cursor 3} {10382020000 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {95613018769 ps} 0}
48 configure wave -namecolwidth 402
49 configure wave -valuecolwidth 199
64 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {33725957281 ps} 0} {{Cursor 3} {10434056078 ps} 0} {{Cursor 4} {47317662811 ps} 0} {{Cursor 5} {82561584962 ps} 0}
65 configure wave -namecolwidth 469
66 configure wave -valuecolwidth 112
50 67 configure wave -justifyvalue left
51 68 configure wave -signalnamewidth 0
52 69 configure wave -snapdistance 10
53 70 configure wave -datasetprefix 0
54 71 configure wave -rowmargin 4
55 72 configure wave -childrowmargin 2
56 73 configure wave -gridoffset 0
57 74 configure wave -gridperiod 1
58 75 configure wave -griddelta 40
59 76 configure wave -timeline 0
60 77 configure wave -timelineunits ps
61 78 update
62 WaveRestoreZoom {10380205948 ps} {10383691010 ps}
79 WaveRestoreZoom {10429891270 ps} {10442522246 ps}
63 80 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
64 81 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
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