HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r497:2e89e897ccde

ajout de downsampler 6 apres le cic_lfr

pellion -

r497:2e89e897ccde (MINI-LFR) WFP_MS-0-1-42 JC

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r497:2e89e897ccde

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000129")  -- aa.bb.cc version
+                  top_lfr_version        => X"00012A")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,

lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +62 -19

@@ -126,8 +126,15 ARCHITECTURE tb OF lpp_lfr_filter IS
126	SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);	126	SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
127	--	127	--
128	-- SIGNAL sample_f2_val : STD_LOGIC;	128	-- SIGNAL sample_f2_val : STD_LOGIC;
129	SIGNAL sample_f2 : sampl~~e_vector~~(5 DOWNTO 0, 15 DOWNTO 0);	129	SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
130	SIGNAL sample_f3 : sampl~~e_vector~~(5 DOWNTO 0, 15 DOWNTO 0);	130	SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
		131	SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
		132	SIGNAL sample_f2_cic_val : STD_LOGIC;
		133
		134	SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
		135	SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
		136	SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
		137	SIGNAL sample_f3_cic_val : STD_LOGIC;
131		138
132	-----------------------------------------------------------------------------	139	-----------------------------------------------------------------------------
133	--SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');	140	--SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
@@ -341,29 +348,65 BEGIN
341	data_in => sample_f0_s,	348	data_in => sample_f0_s,
342	data_in_valid => sample_f0_val_s,	349	data_in_valid => sample_f0_val_s,
343		350
344	data_out_16 => sample_f2,	351	data_out_16 => sample_f2_cic,
345	data_out_16_valid => sample_f2_val,	352	data_out_16_valid => sample_f2_cic_val,
346		353
347	data_out_256 => sample_f3,	354	data_out_256 => sample_f3_cic,
348	data_out_256_valid => sample_f3_val);	355	data_out_256_valid => sample_f3_cic_val);
		356
		357	-----------------------------------------------------------------------------
		358
		359	all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE
		360	all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE
		361	sample_f2_cic_s(J,I) <= sample_f2_cic(J,I);
		362	END GENERATE all_channel_sample_f2_cic;
		363	END GENERATE all_bit_sample_f2_cic;
		364
		365	Downsampling_f2 : Downsampling
		366	GENERIC MAP (
		367	ChanelCount => 6,
		368	SampleSize => 16,
		369	DivideParam => 6)
		370	PORT MAP (
		371	clk => clk,
		372	rstn => rstn,
		373	sample_in_val => sample_f2_cic_val ,
		374	sample_in => sample_f2_cic_s,
		375	sample_out_val => sample_f2_val,
		376	sample_out => sample_f2);
349		377
350	all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE	378	all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
351	sample_f2_wdata_s(I) <= sample_f2(0, I);	379	all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
352	sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);	380	sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
353	sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);	381	END GENERATE all_channel_sample_f2;
354	sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
355	sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
356	sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
357	END GENERATE all_bit_sample_f2;	382	END GENERATE all_bit_sample_f2;
358		383
		384	-----------------------------------------------------------------------------
		385
359	all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE	386	all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
360	sample_f3_wdata_s(I) <= sample_f3(0, I);	387	all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
361	sample_f3_~~wdata~~_s(16*1+I) <= sample_f3(1, I);	388	sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
362	sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);	389	END GENERATE all_channel_sample_f3;
363	sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
364	sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
365	sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
366	END GENERATE all_bit_sample_f3;	390	END GENERATE all_bit_sample_f3;
		391
		392	Downsampling_f3 : Downsampling
		393	GENERIC MAP (
		394	ChanelCount => 6,
		395	SampleSize => 16,
		396	DivideParam => 6)
		397	PORT MAP (
		398	clk => clk,
		399	rstn => rstn,
		400	sample_in_val => sample_f3_cic_val ,
		401	sample_in => sample_f3_cic_s,
		402	sample_out_val => sample_f3_val,
		403	sample_out => sample_f3);
		404
		405	all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
		406	all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
		407	sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
		408	END GENERATE all_channel_sample_f3;
		409	END GENERATE all_bit_sample_f3;
367		410
368	-----------------------------------------------------------------------------	411	-----------------------------------------------------------------------------
369	--	412	--

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