##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Dirty sync.
Jeandet Alexis -
r278:2db6d24e2968 alexis
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,274
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 library esa;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
23
24 Library UNISIM;
25 use UNISIM.vcomponents.all;
26
27
28 use work.config.all;
29 --==================================================================
30 --
31 --
32 -- FPGA FREQ = 100MHz
33 --
34 --
35 --==================================================================
36
37 entity BeagleSynth_MCTRL is
38 generic (
39 fabtech : integer := CFG_FABTECH;
40 memtech : integer := CFG_MEMTECH;
41 padtech : integer := CFG_PADTECH;
42 clktech : integer := CFG_CLKTECH
43 );
44 port (
45 reset : in std_ulogic;
46 clk : in std_ulogic;
47 DAC_nCLR : out std_ulogic;
48 DAC_nCS : out std_ulogic;
49 CAL_IN_SCK : out std_ulogic;
50 DAC_SDI : out std_ulogic_vector(7 downto 0);
51 TXD : out std_ulogic;
52 RXD : in std_ulogic;
53 urxd1 : in std_ulogic;
54 utxd1 : out std_ulogic;
55 LED : out std_ulogic_vector(2 downto 0);
56 --------------------------------------------------------
57 ---- SDRAM
58 ---- For SDRAM config have a look on leon3-altera-ep1c20
59 ---- design from GRLIB, the IS42S32400E is similar to
60 ---- MT48LC4M32B2.
61 --------------------------------------------------------
62 sdcke : out std_logic; -- clk en
63 sdcsn : out std_logic; -- chip sel
64 sdwen : out std_logic; -- write en
65 sdrasn : out std_logic; -- row addr stb
66 sdcasn : out std_logic; -- col addr stb
67 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
68 sdclk : out std_logic; -- sdram clk output
69 sdba : out std_logic_vector (1 downto 0); -- bank select address
70 Address : out std_logic_vector(11 downto 0); -- sdram address
71 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
72 );
73 end;
74
75 architecture rtl of BeagleSynth_MCTRL is
76 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
77 CFG_GRETH+CFG_AHB_JTAG;
78 constant maxahbm : integer := maxahbmsp;
79 constant IOAEN : integer := CFG_CAN;
80 constant boardfreq : integer := 100000;
81
82 signal clk2x : std_ulogic;
83 signal lclk : std_ulogic;
84 signal clkm : std_ulogic;
85 signal rstn : std_ulogic;
86 signal rst : std_ulogic;
87 signal rstraw : std_ulogic;
88 signal pciclk : std_ulogic;
89 signal sdclkl : std_ulogic;
90 signal sdclkl_DDR2 : std_ulogic;
91 signal cgi : clkgen_in_type;
92 signal cgo : clkgen_out_type;
93
94 --- AHB / APB
95 signal apbi : apb_slv_in_type;
96 signal apbo : apb_slv_out_vector := (others => apb_none);
97 signal ahbsi : ahb_slv_in_type;
98 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
99 signal ahbmi : ahb_mst_in_type;
100 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
101
102 --- MEM CTRLR
103 signal memi : memory_in_type;
104 signal memo : memory_out_type;
105 signal wpo : wprot_out_type;
106 signal sdi : sdctrl_in_type;
107 signal sdo : sdram_out_type;
108
109 --UART
110 signal ahbuarti : uart_in_type;
111 signal ahbuarto : uart_out_type;
112 signal apbuarti : uart_in_type;
113 signal apbuarto : uart_out_type;
114
115 signal led2int : std_logic;
116
117 begin
118
119 DAC_nCLR <= '1';
120 DAC_nCS <= '1';
121 CAL_IN_SCK <= '1';
122 DAC_SDI <= (others =>'1');
123
124 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
125 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
126 --rstn <= reset;
127 --lclk <= clk;
128 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
129
130 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
131 clkgen0 : clkgen -- clock generator
132 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
133 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
134
135 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
136 --sdclk <= sdclkl;
137 sdclk <= sdclkl_DDR2;
138
139 LED(1) <= not cgo.clklock;
140 LED(0) <= cgo.clklock;
141
142 ODDR2_inst : ODDR2
143 generic map(
144 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
145 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
146 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
147 port map (
148 Q => sdclkl_DDR2, -- 1-bit output data
149 C0 => sdclkl, -- 1-bit clock input
150 C1 => not sdclkl, -- 1-bit clock input
151 CE => '1', -- 1-bit clock enable input
152 D0 => '1', -- 1-bit data input (associated with C0)
153 D1 => '0', -- 1-bit data input (associated with C1)
154 R => '0', -- 1-bit reset input
155 S => '0' -- 1-bit set input
156 );
157
158 ----------------------------------------------------------------------
159 --- AHB CONTROLLER -------------------------------------------------
160 ----------------------------------------------------------------------
161
162 ahb0 : ahbctrl -- AHB arbiter/multiplexer
163 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
164 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
165 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
166 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
167
168 ----------------------------------------------------------------------
169 --- AHB UART -------------------------------------------------------
170 ----------------------------------------------------------------------
171
172 dcomgen : if CFG_AHB_UART = 1 generate
173 dcom0: ahbuart -- Debug UART
174 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
175 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
176 ahbuarti.rxd <= RXD;
177 TXD <= ahbuarto.txd;
178 end generate;
179 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
180
181 ----------------------------------------------------------------------
182 --- APB Bridge -----------------------------------------------------
183 ----------------------------------------------------------------------
184
185 apb0 : apbctrl -- AHB/APB bridge
186 generic map (hindex => 1, haddr => CFG_APBADDR)
187 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
188
189 ----------------------------------------------------------------------
190 --- APB UART -------------------------------------------------------
191 ----------------------------------------------------------------------
192
193 ua1 : if CFG_UART1_ENABLE /= 0 generate
194 uart1 : apbuart -- UART 1
195 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
196 fifosize => CFG_UART1_FIFO)
197 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
198 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
199 apbuarti.ctsn <= '0';
200 end generate;
201 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
202
203
204
205
206 --div0: Clk_divider
207 -- generic map( 100000000,1)
208 -- Port map( clkm,rstn,LED(2));
209
210 LED(2) <= led2int;
211
212 process(clkm,rstn)
213 begin
214 if rstn = '0' then
215 led2int <= '0';
216 elsif clkm'event and clkm='1' then
217 led2int <= not led2int;
218 end if;
219 end process;
220
221
222
223
224 memi.writen <= '1';
225 memi.wrn <= "1111";
226 memi.bwidth <= "00";
227 memi.brdyn <= '1';
228 memi.bexcn <= '1';
229
230 mctrl0 : mctrl
231 generic map (
232 hindex => 0,
233 pindex => 0,
234 paddr => 0,
235 srbanks => 1,
236 ram8 => 1,
237 ram16 => 1,
238 sden => 1,
239 invclk => 0,
240 sepbus => 0,
241 pageburst => 0)
242 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
243
244 -- SDRAM controller
245 sdwen_pad : outpad generic map (tech => padtech)
246 port map (sdwen, sdo.sdwen);
247 sdras_pad : outpad generic map (tech => padtech)
248 port map (sdrasn, sdo.rasn);
249 sdcas_pad : outpad generic map (tech => padtech)
250 port map (sdcasn, sdo.casn);
251 sddqm_pad : outpadv generic map (width =>4, tech => padtech)
252 port map (sddqm, sdo.dqm(3 downto 0));
253 sdba <= "00";
254
255 sdcsn_pad : outpad generic map (tech => padtech)
256 port map (sdcsn, sdo.sdcsn(0));
257
258 sdcke_pad : outpad generic map (tech => padtech)
259 port map (sdcke, sdo.sdcke(0));
260
261 addr_pad : outpadv generic map (width => 12, tech => padtech)
262 port map (address, memo.address(11 downto 0));
263
264 bdr : for i in 0 to 3 generate
265 data_pad : iopadv generic map (tech => padtech, width => 8)
266 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
267 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
268 end generate;
269
270
271 end rtl;
272
273
274
Show file before | Show file after | Hide comments
@@ -0,0 +1,117
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:26:29 12/07/2013
6 -- Design Name:
7 -- Module Name: DAC8581 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.numeric_std.all;
23 library LPP;
24 use lpp.lpp_cna.all;
25
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 use IEEE.NUMERIC_STD.ALL;
29
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 --library UNISIM;
33 --use UNISIM.VComponents.all;
34
35 entity DAC8581 is
36 generic(clkfreq : integer := 100);
37 Port ( clk : in STD_LOGIC;
38 rstn : in STD_LOGIC;
39 smpclk : in STD_LOGIC;
40 sclk : out STD_LOGIC;
41 csn : out STD_LOGIC;
42 sdo : out STD_LOGIC;
43 smp_in : in STD_LOGIC_VECTOR (15 downto 0)
44 );
45 end DAC8581;
46
47 architecture Behavioral of DAC8581 is
48
49
50 signal smpclk_reg : std_logic;
51 signal sclk_gen : std_logic_vector(3 downto 0);
52 signal sclk_net : std_logic;
53 signal load : std_logic;
54 signal data_sreg : std_logic_vector(15 downto 0);
55 signal csn_sreg : std_logic_vector(15 downto 0);
56 begin
57
58
59
60 sclk_net <= sclk_gen(1);
61 sclk <= sclk_net;
62
63 process(rstn,clk)
64 begin
65 if rstn ='0' then
66 smpclk_reg <= '0';
67 sclk_gen <= "0000";
68 load <= '0';
69 elsif clk'event and clk = '1' then
70 smpclk_reg <= smpclk;
71 sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1);
72 if smpclk_reg = '0' and smpclk = '1' then
73 load <= '1';
74 else
75 load <= '0';
76 end if;
77
78 end if;
79 end process;
80
81 process(load,sclk_net)
82 begin
83 if load ='1' then
84 data_sreg <= smp_in;
85 csn_sreg <= (others => '0');
86 elsif sclk_net'event and sclk_net = '1' then
87 data_sreg <= data_sreg(14 downto 0) & '1';
88 csn_sreg <= csn_sreg(14 downto 0) & '1';
89 end if;
90 end process;
91
92 process(rstn,sclk_net)
93 begin
94 if rstn ='0' then
95 sdo <= '1';
96 csn <= '1';
97 elsif sclk_net'event and sclk_net = '0' then
98 sdo <= data_sreg(15);
99 csn <= csn_sreg(15);
100 end if;
101 end process;
102
103
104
105 end Behavioral;
106
107
108
109
110
111
112
113
114
115
116
117
Show file before | Show file after | Hide comments
@@ -0,0 +1,106
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:20:11 12/08/2013
6 -- Design Name:
7 -- Module Name: GPMC_SLAVE - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.numeric_std.all;
23 library grlib, techmap;
24 use grlib.stdlib.all;
25 use techmap.gencomp.all;
26 use techmap.allclkgen.all;
27 library lpp;
28 use lpp.general_purpose.all;
29
30 entity GPMC_ASYNC_SLAVE is
31 generic (
32 memtech : integer := 0;
33 padtech : integer := 0
34 );
35 Port (
36 clk : in STD_LOGIC;
37 reset : in STD_LOGIC;
38 GPMC_AD : inout std_logic_vector(15 downto 0);
39 GPMC_A : in std_logic_vector(19 downto 0);
40 GPMC_CLK_MUX0 : in std_ulogic;
41 GPMC_WEN : in std_ulogic;
42 GPMC_OEN_REN : in std_ulogic;
43 GPMC_ADVN_ALE : in std_ulogic;
44 GPMC_CSN : in std_ulogic_vector(2 downto 0);
45 GPMC_BE0N_CLE : in std_ulogic;
46 GPMC_BE1N : in std_ulogic;
47 GPMC_WAIT0 : out std_ulogic;
48 GPMC_WPN : in std_ulogic
49 );
50 end GPMC_ASYNC_SLAVE;
51
52 architecture Behavioral of GPMC_ASYNC_SLAVE is
53 constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
54
55 signal data_out :std_logic_vector(15 downto 0);
56 signal data_in :std_logic_vector(15 downto 0);
57
58 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
59 signal RAMarray : RAMarrayT:=(others => VectInit);
60 signal ramindex : integer range 0 to 255;
61
62 begin
63
64 data_pad : iopadv generic map (tech=> padtech,width => 16)
65 port map (
66 pad => GPMC_AD(15 downto 0),
67 o => data_in(15 downto 0),
68 en => GPMC_OEN_REN,
69 i => data_out(15 downto 0)
70 );
71
72 GPMC_WAIT0 <= '1';
73
74 data_out <= RAMarray(ramindex);
75
76 process(reset,GPMC_CLK_MUX0)
77 begin
78 if reset = '0' then
79 --data_out <= (others => '0');
80 ramindex <= 0;
81 elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
82 if GPMC_ADVN_ALE = '0' then
83 ramindex <= to_integer(unsigned(GPMC_A(19 downto 1)));
84 end if;
85
86 if GPMC_WEN = '0' then
87 RAMarray(ramindex) <= data_in;
88 end if;
89 end if;
90 end process;
91
92 end Behavioral;
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Show file before | Show file after | Hide comments
@@ -0,0 +1,338
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
5 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
10 library gaisler;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
15 library esa;
16 use esa.memoryctrl.all;
17 --use gaisler.sim.all;
18 library lpp;
19 use lpp.lpp_ad_conv.all;
20 use lpp.lpp_amba.all;
21 use lpp.apb_devices_list.all;
22 use lpp.general_purpose.all;
23 use lpp.lpp_cna.all;
24 use lpp.lpp_memory.all;
25
26 Library UNISIM;
27 use UNISIM.vcomponents.all;
28
29 use work.config.all;
30
31 entity beagleSigGen is
32 generic (
33 memtech : integer := CFG_MEMTECH;
34 padtech : integer := CFG_PADTECH;
35 clktech : integer := CFG_CLKTECH
36 );
37 Port (
38 clk : in STD_LOGIC;
39 rstn : in STD_LOGIC;
40 CAL_IN_SCK : out std_ulogic;
41 DAC_nCS : out std_ulogic;
42 DAC_SDI : out std_logic_vector(7 downto 0);
43 address : in std_logic_vector(2 downto 0);
44 DATA : in std_logic_vector(15 downto 0);
45 REN_debug : out std_logic;
46 WEN : in std_logic;
47 FIFO_FULL : out std_logic_vector(7 downto 0);
48 FIFO_EMPTY : out std_logic_vector(7 downto 0)
49 );
50 end beagleSigGen;
51
52 architecture Behavioral of beagleSigGen is
53
54
55 signal FIFO_FULL_net : std_logic_vector(7 downto 0);
56 signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
57 signal FIFO_WEN : std_logic_vector(7 downto 0);
58 signal FIFO_REN : std_logic;
59
60
61 subtype TAB16 is std_logic_vector(15 downto 0);
62 type FIFOout_t is array(7 downto 0) of TAB16;
63
64 signal FIFO_out : FIFOout_t;
65 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
66 signal smpclk : std_logic;
67 signal smpclk_reg : std_logic;
68 signal DAC_SDO : std_logic;
69 signal DATA_reg : std_logic_vector(15 downto 0);
70
71 begin
72
73
74
75 FIFO_FULL <= FIFO_FULL_net;
76 FIFO_EMPTY <= FIFO_EMPTY_net;
77
78 --fron_fifo1: lpp_fifo
79 -- generic map(
80 -- tech => memtech,
81 -- Mem_use => 1, --use RAM not CELS
82 -- DataSz => 16,
83 -- AddrSz => 8
84 -- )
85 -- port map(
86 -- rstn => rstn,
87 -- ReUse => '0',
88 -- rclk => clk,
89 -- ren => FIFO_REN,
90 -- rdata => FIFO_out(0),
91 -- empty => FIFO_EMPTY_net(0),
92 -- raddr => open,
93 -- wclk => clk,
94 -- wen => FIFO_WEN(0),
95 -- wdata => DATA_reg,
96 -- full => FIFO_FULL_net(0),
97 -- waddr => open
98 -- );
99 --fron_fifo2: lpp_fifo
100 -- generic map(
101 -- tech => memtech,
102 -- Mem_use => 1, --use RAM not CELS
103 -- DataSz => 16,
104 -- AddrSz => 8
105 -- )
106 -- port map(
107 -- rstn => rstn,
108 -- ReUse => '0',
109 -- rclk => clk,
110 -- ren => FIFO_REN,
111 -- rdata => FIFO_out(1),
112 -- empty => FIFO_EMPTY_net(1),
113 -- raddr => open,
114 -- wclk => clk,
115 -- wen => FIFO_WEN(1),
116 -- wdata => DATA_reg,
117 -- full => FIFO_FULL_net(1),
118 -- waddr => open
119 -- );
120 --fron_fifo3: lpp_fifo
121 -- generic map(
122 -- tech => memtech,
123 -- Mem_use => 1, --use RAM not CELS
124 -- DataSz => 16,
125 -- AddrSz => 8
126 -- )
127 -- port map(
128 -- rstn => rstn,
129 -- ReUse => '0',
130 -- rclk => clk,
131 -- ren => FIFO_REN,
132 -- rdata => FIFO_out(2),
133 -- empty => FIFO_EMPTY_net(2),
134 -- raddr => open,
135 -- wclk => clk,
136 -- wen => FIFO_WEN(2),
137 -- wdata => DATA_reg,
138 -- full => FIFO_FULL_net(2),
139 -- waddr => open
140 -- );
141 --fron_fifo4: lpp_fifo
142 -- generic map(
143 -- tech => memtech,
144 -- Mem_use => 1, --use RAM not CELS
145 -- DataSz => 16,
146 -- AddrSz => 8
147 -- )
148 -- port map(
149 -- rstn => rstn,
150 -- ReUse => '0',
151 -- rclk => clk,
152 -- ren => FIFO_REN,
153 -- rdata => FIFO_out(3),
154 -- empty => FIFO_EMPTY_net(3),
155 -- raddr => open,
156 -- wclk => clk,
157 -- wen => FIFO_WEN(3),
158 -- wdata => DATA_reg,
159 -- full => FIFO_FULL_net(3),
160 -- waddr => open
161 -- );
162 --fron_fifo5: lpp_fifo
163 -- generic map(
164 -- tech => memtech,
165 -- Mem_use => 1, --use RAM not CELS
166 -- DataSz => 16,
167 -- AddrSz => 8
168 -- )
169 -- port map(
170 -- rstn => rstn,
171 -- ReUse => '0',
172 -- rclk => clk,
173 -- ren => FIFO_REN,
174 -- rdata => FIFO_out(4),
175 -- empty => FIFO_EMPTY_net(4),
176 -- raddr => open,
177 -- wclk => clk,
178 -- wen => FIFO_WEN(4),
179 -- wdata => DATA_reg,
180 -- full => FIFO_FULL_net(4),
181 -- waddr => open
182 -- );
183 --fron_fifo6: lpp_fifo
184 -- generic map(
185 -- tech => memtech,
186 -- Mem_use => 1, --use RAM not CELS
187 -- DataSz => 16,
188 -- AddrSz => 8
189 -- )
190 -- port map(
191 -- rstn => rstn,
192 -- ReUse => '0',
193 -- rclk => clk,
194 -- ren => FIFO_REN,
195 -- rdata => FIFO_out(5),
196 -- empty => FIFO_EMPTY_net(5),
197 -- raddr => open,
198 -- wclk => clk,
199 -- wen => FIFO_WEN(5),
200 -- wdata => DATA_reg,
201 -- full => FIFO_FULL_net(5),
202 -- waddr => open
203 -- );
204 --fron_fifo7: lpp_fifo
205 -- generic map(
206 -- tech => memtech,
207 -- Mem_use => 1, --use RAM not CELS
208 -- DataSz => 16,
209 -- AddrSz => 8
210 -- )
211 -- port map(
212 -- rstn => rstn,
213 -- ReUse => '0',
214 -- rclk => clk,
215 -- ren => FIFO_REN,
216 -- rdata => FIFO_out(6),
217 -- empty => FIFO_EMPTY_net(6),
218 -- raddr => open,
219 -- wclk => clk,
220 -- wen => FIFO_WEN(6),
221 -- wdata => DATA_reg,
222 -- full => FIFO_FULL_net(6),
223 -- waddr => open
224 -- );
225 --fron_fifo8: lpp_fifo
226 -- generic map(
227 -- tech => memtech,
228 -- Mem_use => 1, --use RAM not CELS
229 -- DataSz => 16,
230 -- AddrSz => 8
231 -- )
232 -- port map(
233 -- rstn => rstn,
234 -- ReUse => '0',
235 -- rclk => clk,
236 -- ren => FIFO_REN,
237 -- rdata => FIFO_out(7),
238 -- empty => FIFO_EMPTY_net(7),
239 -- raddr => open,
240 -- wclk => clk,
241 -- wen => FIFO_WEN(7),
242 -- wdata => DATA_reg,
243 -- full => FIFO_FULL_net(7),
244 -- waddr => open
245 -- );
246
247 REN_debug <= FIFO_REN;
248
249 process(clk,rstn)
250 begin
251 if rstn = '0' then
252 DATA_reg <= (others => '0');
253 FIFO_WEN <= (others => '0');
254 elsif clk'event and clk = '1' then
255 if WEN = '0' then
256 DATA_reg <= DATA;
257 case address is
258 when "000"=>
259 FIFO_WEN <= "11111110";
260 FIFO_out(0) <= DATA;
261 when "001"=>
262 FIFO_WEN <= "11111101";
263 FIFO_out(1) <= DATA;
264 when "010"=>
265 FIFO_WEN <= "11111011";
266 FIFO_out(2) <= DATA;
267 when "011"=>
268 FIFO_WEN <= "11110111";
269 FIFO_out(3) <= DATA;
270 when "100"=>
271 FIFO_WEN <= "11101111";
272 FIFO_out(4) <= DATA;
273 when "101"=>
274 FIFO_WEN <= "11011111";
275 FIFO_out(5) <= DATA;
276 when "110"=>
277 FIFO_WEN <= "10111111";
278 FIFO_out(6) <= DATA;
279 when "111"=>
280 FIFO_WEN <= "01111111";
281 FIFO_out(7) <= DATA;
282 when others =>
283 FIFO_WEN <= "11111111";
284 end case;
285 end if;
286 end if;
287 end process;
288
289 all_bits: FOR I in 15 downto 0 GENERATE
290 all_chans: FOR J in 7 downto 0 GENERATE
291 DAC_DATA(J,I) <= FIFO_out(J)(I);
292 end GENERATE;
293 end GENERATE;
294
295
296
297 process(clk,rstn)
298 begin
299 if rstn = '0' then
300 FIFO_REN <= '1';
301 smpclk_reg <= '0';
302 elsif clk'event and clk = '1' then
303 smpclk_reg <= smpclk;
304 if smpclk = '1' and smpclk_reg = '0' then
305 FIFO_REN <= '0';
306 else
307 FIFO_REN <= '1';
308 end if;
309 end if;
310 end process;
311
312
313 DAC0 : DAC8581
314 generic map(150,8)
315 Port map(
316 clk => clk,
317 rstn => rstn,
318 smpclk => smpclk,
319 sclk => CAL_IN_SCK,
320 csn => DAC_nCS,
321 sdo => DAC_SDI,
322 smp_in => DAC_DATA
323 );
324
325
326
327 smpclk0: Clk_divider
328 GENERIC map(OSC_freqHz => 150000000,
329 TargetFreq_Hz => 32000)
330 PORT map(
331 clk => clk,
332 reset => rstn,
333 clk_divided => smpclk
334 );
335
336
337 end Behavioral;
338
Show file before | Show file after | Hide comments
@@ -1,167 +1,168
1 1
2 2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 3 NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
4 4 NET "CLKM" TNM_NET = "clkm_net";
5 TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
6
5 TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 6 ns HIGH 33%;
7 6
8 7 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
9 8 NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
10 9
11 10 NET "DAC_nCLR" LOC = "R11" | IOSTANDARD=LVTTL;
12 11 NET "DAC_nCS" LOC = "T12" | IOSTANDARD=LVTTL;
13 12 NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD=LVTTL;
14 13 NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD=LVTTL;
15 14 NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD=LVTTL;
16 15 NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD=LVTTL;
17 16 NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD=LVTTL;
18 17 NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD=LVTTL;
19 18 NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD=LVTTL;
20 19 NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD=LVTTL;
21 20 NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL;
22 21
23 22
24 23 NET "TXD" LOC = "V22"| slew=FAST | IOSTANDARD=LVTTL;
25 24 NET "RXD" LOC = "U22"| slew=FAST | IOSTANDARD=LVTTL;
26 25 NET "LED(0)" LOC = "AB9"| slew=FAST | IOSTANDARD=LVTTL;
27 26 NET "LED(1)" LOC = "AB8"| slew=FAST | IOSTANDARD=LVTTL;
28 27 NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL;
29 28
30 29 NET "urxd1" LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN
31 30 NET "utxd1" LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN
32 31
33 32 NET "sdcke" LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en
34 33 NET "sdcsn" LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel
35 34 NET "sdwen" LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en
36 35 NET "sdrasn" LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb
37 36 NET "sdcasn" LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb
38 37
39 38 NET "sddqm(3)" LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
40 39 NET "sddqm(2)" LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
41 40 NET "sddqm(1)" LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
42 41 NET "sddqm(0)" LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
43 42
44 43 NET "sdclk" CLOCK_DEDICATED_ROUTE = FALSE;
45 44 NET "sdclk" LOC = "A6" | slew=FAST | IOSTANDARD=LVTTL; # sdram clk output
46 45 NET "sdba(1)" LOC = "J20"| slew=FAST | IOSTANDARD=LVTTL; # bank select address
47 46 NET "sdba(0)" LOC = "G16"| slew=FAST | IOSTANDARD=LVTTL; # bank select address
48 47
49 48 NET "Address(11)" LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
50 49 NET "Address(10)" LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
51 50 NET "Address(9)" LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
52 51 NET "Address(8)" LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
53 52 NET "Address(7)" LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
54 53 NET "Address(6)" LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
55 54 NET "Address(5)" LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
56 55 NET "Address(4)" LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
57 56 NET "Address(3)" LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
58 57 NET "Address(2)" LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
59 58 NET "Address(1)" LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
60 59 NET "Address(0)" LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
61 60
62 61 NET "Data(31)" LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
63 62 NET "Data(30)" LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
64 63 NET "Data(29)" LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
65 64 NET "Data(28)" LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
66 65 NET "Data(27)" LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
67 66 NET "Data(26)" LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
68 67 NET "Data(25)" LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
69 68 NET "Data(24)" LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
70 69 NET "Data(23)" LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
71 70 NET "Data(22)" LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
72 71 NET "Data(21)" LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
73 72 NET "Data(20)" LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
74 73 NET "Data(19)" LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
75 74 NET "Data(18)" LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
76 75 NET "Data(17)" LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
77 76 NET "Data(16)" LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
78 77 NET "Data(15)" LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
79 78 NET "Data(14)" LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
80 79 NET "Data(13)" LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
81 80 NET "Data(12)" LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
82 81 NET "Data(11)" LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
83 82 NET "Data(10)" LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
84 83 NET "Data(9)" LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
85 84 NET "Data(8)" LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
86 85 NET "Data(7)" LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
87 86 NET "Data(6)" LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
88 87 NET "Data(5)" LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
89 88 NET "Data(4)" LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
90 89 NET "Data(3)" LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
91 90 NET "Data(2)" LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
92 91 NET "Data(1)" LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
93 92 NET "Data(0)" LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
94 93
95 94 NET "GPMC_AD(0)" LOC = "M1"| slew=FAST | IOSTANDARD=LVTTL;
96 95 NET "GPMC_AD(1)" LOC = "M2"| slew=FAST | IOSTANDARD=LVTTL;
97 96 NET "GPMC_AD(2)" LOC = "AB3"| slew=FAST | IOSTANDARD=LVTTL;
98 97 NET "GPMC_AD(3)" LOC = "AB2"| slew=FAST | IOSTANDARD=LVTTL;
99 98 NET "GPMC_AD(4)" LOC = "N1"| slew=FAST | IOSTANDARD=LVTTL;
100 99 NET "GPMC_AD(5)" LOC = "N3"| slew=FAST | IOSTANDARD=LVTTL;
101 100 NET "GPMC_AD(6)" LOC = "AB5"| slew=FAST | IOSTANDARD=LVTTL;
102 101 NET "GPMC_AD(7)" LOC = "AB4"| slew=FAST | IOSTANDARD=LVTTL;
103 102 NET "GPMC_AD(8)" LOC = "R1"| slew=FAST | IOSTANDARD=LVTTL;
104 103 NET "GPMC_AD(9)" LOC = "V1"| slew=FAST | IOSTANDARD=LVTTL;
105 104 NET "GPMC_AD(10)" LOC = "U3"| slew=FAST | IOSTANDARD=LVTTL;
106 105 NET "GPMC_AD(11)" LOC = "T1"| slew=FAST | IOSTANDARD=LVTTL;
107 106 NET "GPMC_AD(12)" LOC = "V2"| slew=FAST | IOSTANDARD=LVTTL;
108 107 NET "GPMC_AD(13)" LOC = "W1"| slew=FAST | IOSTANDARD=LVTTL;
109 108 NET "GPMC_AD(14)" LOC = "T2"| slew=FAST | IOSTANDARD=LVTTL;
110 109 NET "GPMC_AD(15)" LOC = "U1"| slew=FAST | IOSTANDARD=LVTTL;
111 110
112 111
113 112
114 113 NET "GPMC_A(0)" LOC = "N4"| slew=FAST | IOSTANDARD=LVTTL;
115 114 NET "GPMC_A(1)" LOC = "N6"| slew=FAST | IOSTANDARD=LVTTL;
116 115 NET "GPMC_A(2)" LOC = "P3"| slew=FAST | IOSTANDARD=LVTTL;
117 116 NET "GPMC_A(3)" LOC = "P4"| slew=FAST | IOSTANDARD=LVTTL;
118 117 NET "GPMC_A(4)" LOC = "R4"| slew=FAST | IOSTANDARD=LVTTL;
119 118 NET "GPMC_A(5)" LOC = "T5"| slew=FAST | IOSTANDARD=LVTTL;
120 119 NET "GPMC_A(6)" LOC = "T6"| slew=FAST | IOSTANDARD=LVTTL;
121 120 NET "GPMC_A(7)" LOC = "T3"| slew=FAST | IOSTANDARD=LVTTL;
122 121 NET "GPMC_A(8)" LOC = "L1"| slew=FAST | IOSTANDARD=LVTTL;
123 122 NET "GPMC_A(9)" LOC = "K1"| slew=FAST | IOSTANDARD=LVTTL;
124 123 NET "GPMC_A(10)" LOC = "L3"| slew=FAST | IOSTANDARD=LVTTL;
125 124 NET "GPMC_A(11)" LOC = "K2"| slew=FAST | IOSTANDARD=LVTTL;
126 125 NET "GPMC_A(12)" LOC = "F1"| slew=FAST | IOSTANDARD=LVTTL;
127 126 NET "GPMC_A(13)" LOC = "F2"| slew=FAST | IOSTANDARD=LVTTL;
128 127 NET "GPMC_A(14)" LOC = "G3"| slew=FAST | IOSTANDARD=LVTTL;
129 128 NET "GPMC_A(15)" LOC = "H2"| slew=FAST | IOSTANDARD=LVTTL;
130 129 NET "GPMC_A(16)" LOC = "G1"| slew=FAST | IOSTANDARD=LVTTL;
131 130 NET "GPMC_A(17)" LOC = "H1"| slew=FAST | IOSTANDARD=LVTTL;
132 131 NET "GPMC_A(18)" LOC = "J1"| slew=FAST | IOSTANDARD=LVTTL;
133 132 NET "GPMC_A(19)" LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL;
134 133
135 134 NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE;
135 NET "GPMC_CLK_MUX0" TNM_NET = "GPMC_CLK_MUX0_net";
136 TIMESPEC "TS_GPMC_CLK_MUX0_net" = PERIOD "GPMC_CLK_MUX0_net" 8 ns HIGH 50%;
136 137 NET "GPMC_CLK_MUX0" LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL;
137 138 NET "GPMC_WEN" LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL;
138 139 NET "GPMC_OEN_REN" LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL;
139 140 NET "GPMC_ADVN_ALE" LOC = "AA2"| slew=FAST | IOSTANDARD=LVTTL;
140 141 NET "GPMC_CSN(0)" LOC = "M3"| slew=FAST | IOSTANDARD=LVTTL;
141 142 NET "GPMC_CSN(1)" LOC = "P1"| slew=FAST | IOSTANDARD=LVTTL;
142 143 NET "GPMC_CSN(2)" LOC = "P2"| slew=FAST | IOSTANDARD=LVTTL;
143 144 NET "GPMC_BE0N_CLE" LOC = "Y1"| slew=FAST | IOSTANDARD=LVTTL;
144 145 NET "GPMC_BE1N" LOC = "AB21"| slew=FAST | IOSTANDARD=LVTTL;
145 146 NET "GPMC_WAIT0" LOC = "AA21"| slew=FAST | IOSTANDARD=LVTTL;
146 147 NET "GPMC_WPN" LOC = "W22"| slew=FAST | IOSTANDARD=LVTTL;
147 148
148 149
149 150
150 151
151 152
152 153
153 154
154 155
155 156
156 157
157 158
158 159
159 160
160 161
161 162
162 163
163 164
164 165
165 166
166 167
167 168
Show file before | Show file after | Hide comments
@@ -1,364 +1,198
1 1 library ieee;
2 2 use ieee.std_logic_1164.all;
3 3 use IEEE.numeric_std.all;
4 4 library grlib, techmap;
5 5 use grlib.amba.all;
6 6 use grlib.amba.all;
7 7 use grlib.stdlib.all;
8 8 use techmap.gencomp.all;
9 9 use techmap.allclkgen.all;
10 10 library gaisler;
11 11 use gaisler.memctrl.all;
12 12 use gaisler.leon3.all;
13 13 use gaisler.uart.all;
14 14 use gaisler.misc.all;
15 15 library esa;
16 16 use esa.memoryctrl.all;
17 17 --use gaisler.sim.all;
18 18 library lpp;
19 19 use lpp.lpp_ad_conv.all;
20 20 use lpp.lpp_amba.all;
21 21 use lpp.apb_devices_list.all;
22 22 use lpp.general_purpose.all;
23 23 use lpp.lpp_cna.all;
24 24
25 25 Library UNISIM;
26 26 use UNISIM.vcomponents.all;
27 27
28 28
29 29 use work.config.all;
30 30 --==================================================================
31 31 --
32 32 --
33 33 -- FPGA FREQ = 100MHz
34 34 --
35 35 --
36 36 --==================================================================
37 37
38 38 entity BeagleSynth is
39 39 generic (
40 40 fabtech : integer := CFG_FABTECH;
41 41 memtech : integer := CFG_MEMTECH;
42 42 padtech : integer := CFG_PADTECH;
43 43 clktech : integer := CFG_CLKTECH
44 44 );
45 45 port (
46 46 reset : in std_ulogic;
47 47 clk : in std_ulogic;
48 48 DAC_nCLR : out std_ulogic;
49 49 DAC_nCS : out std_ulogic;
50 50 CAL_IN_SCK : out std_ulogic;
51 51 DAC_SDI : out std_logic_vector(7 downto 0);
52 52 TXD : out std_ulogic;
53 53 RXD : in std_ulogic;
54 54 urxd1 : in std_ulogic;
55 55 utxd1 : out std_ulogic;
56 56 LED : out std_ulogic_vector(2 downto 0);
57 57 --------------------------------------------------------
58 58 ---- Beaglebone GPMC
59 59 --------------------------------------------------------
60 60 GPMC_AD : inout std_logic_vector(15 downto 0);
61 61 GPMC_A : in std_logic_vector(19 downto 0);
62 GPMC_CLK_MUX0 : in std_ulogic;
63 GPMC_WEN : in std_ulogic;
64 GPMC_OEN_REN : in std_ulogic;
65 GPMC_ADVN_ALE : in std_ulogic;
66 GPMC_CSN : in std_ulogic_vector(2 downto 0);
67 GPMC_BE0N_CLE : in std_ulogic;
68 GPMC_BE1N : in std_ulogic;
69 GPMC_WAIT0 : in std_ulogic;
70 GPMC_WPN : in std_ulogic;
62 GPMC_CLK_MUX0 : in std_logic;
63 GPMC_WEN : in std_logic;
64 GPMC_OEN_REN : in std_logic;
65 GPMC_ADVN_ALE : in std_logic;
66 GPMC_CSN : in std_logic_vector(2 downto 0);
67 GPMC_BE0N_CLE : in std_logic;
68 GPMC_BE1N : in std_logic;
69 GPMC_WAIT0 : out std_logic;
70 GPMC_WPN : in std_logic;
71 71
72 72 --------------------------------------------------------
73 73 ---- SDRAM
74 74 ---- For SDRAM config have a look on leon3-altera-ep1c20
75 75 ---- design from GRLIB, the IS42S32400E is similar to
76 76 ---- MT48LC4M32B2.
77 77 --------------------------------------------------------
78 sdcke : out std_logic; -- clk en
79 sdcsn : out std_logic; -- chip sel
80 sdwen : out std_logic; -- write en
81 sdrasn : out std_logic; -- row addr stb
82 sdcasn : out std_logic; -- col addr stb
83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
84 sdclk : out std_logic; -- sdram clk output
85 sdba : out std_logic_vector (1 downto 0); -- bank select address
86 Address : out std_logic_vector(11 downto 0); -- sdram address
78 sdcke : out std_logic; -- clk en
79 sdcsn : out std_logic; -- chip sel
80 sdwen : out std_logic; -- write en
81 sdrasn : out std_logic; -- row addr stb
82 sdcasn : out std_logic; -- col addr stb
83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
84 sdclk : out std_logic; -- sdram clk output
85 sdba : out std_logic_vector (1 downto 0); -- bank select address
86 Address : out std_logic_vector(11 downto 0); -- sdram address
87 87 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
88 88 );
89 89 end;
90 90
91 91 architecture rtl of BeagleSynth is
92 92 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
93 93 CFG_GRETH+CFG_AHB_JTAG;
94 94 constant maxahbm : integer := maxahbmsp;
95 95 constant IOAEN : integer := CFG_CAN;
96 96 constant boardfreq : integer := 100000;
97 97
98 98 signal clk2x : std_ulogic;
99 99 signal lclk : std_ulogic;
100 100 signal clkm : std_ulogic;
101 101 signal rstn : std_ulogic;
102 102 signal rst : std_ulogic;
103 103 signal rstraw : std_ulogic;
104 104 signal pciclk : std_ulogic;
105 105 signal sdclkl : std_ulogic;
106 106 signal sdclkl_DDR2 : std_ulogic;
107 107 signal cgi : clkgen_in_type;
108 108 signal cgo : clkgen_out_type;
109 109
110 --- AHB / APB
111 signal apbi : apb_slv_in_type;
112 signal apbo : apb_slv_out_vector := (others => apb_none);
113 signal ahbsi : ahb_slv_in_type;
114 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
115 signal ahbmi : ahb_mst_in_type;
116 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
117
118 --- MEM CTRLR
119 signal sdi : sdctrl_in_type;
120 signal sdo : sdctrl_out_type;
121
122 --UART
123 signal ahbuarti : uart_in_type;
124 signal ahbuarto : uart_out_type;
125 signal apbuarti : uart_in_type;
126 signal apbuarto : uart_out_type;
127
128 signal led2int : std_logic;
129
130
131 signal DAC0_DATA : std_logic_vector(15 downto 0);
132 signal DAC1_DATA : std_logic_vector(15 downto 0);
133 signal DAC2_DATA : std_logic_vector(15 downto 0);
134 signal DAC3_DATA : std_logic_vector(15 downto 0);
135 signal DAC4_DATA : std_logic_vector(15 downto 0);
136 signal DAC5_DATA : std_logic_vector(15 downto 0);
137 signal DAC6_DATA : std_logic_vector(15 downto 0);
138 signal DAC7_DATA : std_logic_vector(15 downto 0);
139 110
140 111 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
141 112 signal smpclk : std_logic;
142 113 signal smpclk_reg : std_logic;
143 114 signal DAC_SDO : std_logic;
144 115
116 signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0);
117 signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0);
118 signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0);
119 signal GPMC_SLAVE_WEN : std_logic;
120
145 121 signal gpmc_clk : std_logic;
122
123 attribute keep : boolean;
124 attribute syn_keep : boolean;
125 attribute syn_preserve : boolean;
126 attribute syn_keep of clkm : signal is true;
127 attribute syn_preserve of clkm : signal is true;
128 attribute keep of clkm : signal is true;
146 129 begin
147 130
148 131 DAC_nCLR <= '1';
149 --DAC_nCS <= SYNC;
150 --CAL_IN_SCK <= '1';
151 --DAC_SDI <= (others =>'1');
132
152 133
153 134 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
154 135 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
155 --rstn <= reset;
156 --lclk <= clk;
136
157 137 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
158 138
159 139 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
160 140 clkgen0 : clkgen -- clock generator
161 141 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
162 142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
163 143
164 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
165 --sdclk <= sdclkl;
166 sdclk <= sdclkl_DDR2;
167
168 LED(1) <= not cgo.clklock;
169 LED(0) <= cgo.clklock;
170
171 ODDR2_inst : ODDR2
172 generic map(
173 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
174 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
175 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
176 port map (
177 Q => sdclkl_DDR2, -- 1-bit output data
178 C0 => sdclkl, -- 1-bit clock input
179 C1 => not sdclkl, -- 1-bit clock input
180 CE => '1', -- 1-bit clock enable input
181 D0 => '1', -- 1-bit data input (associated with C0)
182 D1 => '0', -- 1-bit data input (associated with C1)
183 R => '0', -- 1-bit reset input
184 S => '0' -- 1-bit set input
185 );
186
187 ----------------------------------------------------------------------
188 --- AHB CONTROLLER -------------------------------------------------
189 ----------------------------------------------------------------------
190
191 ahb0 : ahbctrl -- AHB arbiter/multiplexer
192 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
193 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
194 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
195 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
196
197 ----------------------------------------------------------------------
198 --- AHB UART -------------------------------------------------------
199 ----------------------------------------------------------------------
200
201 dcomgen : if CFG_AHB_UART = 1 generate
202 dcom0: ahbuart -- Debug UART
203 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
204 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
205 ahbuarti.rxd <= RXD;
206 TXD <= ahbuarto.txd;
207 end generate;
208 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
209
210 ----------------------------------------------------------------------
211 --- APB Bridge -----------------------------------------------------
212 ----------------------------------------------------------------------
213
214 apb0 : apbctrl -- AHB/APB bridge
215 generic map (hindex => 1, haddr => CFG_APBADDR)
216 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
217
218 ----------------------------------------------------------------------
219 --- APB UART -------------------------------------------------------
220 ----------------------------------------------------------------------
221
222 ua1 : if CFG_UART1_ENABLE /= 0 generate
223 uart1 : apbuart -- UART 1
224 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
225 fifosize => CFG_UART1_FIFO)
226 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
227 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
228 apbuarti.ctsn <= '0';
229 end generate;
230 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
231
232
233
234
235 --div0: Clk_divider
236 -- generic map( 100000000,1)
237 -- Port map( clkm,rstn,LED(2));
238
239 LED(2) <= led2int;
240
241 process(clkm,rstn)
242 begin
243 if rstn = '0' then
244 led2int <= '0';
245 elsif clkm'event and clkm='1' then
246 led2int <= not led2int;
247 end if;
248 end process;
249
250 144
251 145
252 146
253 sdc : sdctrl
254 generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
255 invclk => 0,sdbits =>32)
256 port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
257
258
259
260 --Alternative data pad instantiation with vectored bdrive
261 sd_pad : iopadvv generic map (tech=> padtech,width => 32)
262 port map (
263 data(31 downto 0),
264 sdo.data(31 downto 0),
265 sdo.vbdrive(31 downto 0),
266 sdi.data(31 downto 0));
267
268
269 -- connect memory controller outputs to entity output signals
270 Address <= sdo.address(13 downto 2);
271 --sdba <= sdo.address(16 downto 15);
272 sdba <= "00";
273 sdcke <= sdo.sdcke(0);
274 sdwen <= sdo.sdwen;
275 sdcsn <= sdo.sdcsn(0);
276 sdrasn <= sdo.rasn;
277 sdcasn <= sdo.casn;
278 sddqm <= sdo.dqm(3 downto 0);
279
280
281 DAC0 : DAC8581
282 generic map(100,8)
147 DAC0 : entity work.beagleSigGen
148 generic map(
149 memtech,
150 padtech,
151 clktech
152 )
283 153 Port map(
284 clk => clkm,
285 rstn => rstn,
286 smpclk => smpclk,
287 sclk => CAL_IN_SCK,
288 csn => DAC_nCS,
289 sdo => DAC_SDI,
290 smp_in => DAC_DATA
154 clk => clkm,
155 rstn => rstn,
156 CAL_IN_SCK => CAL_IN_SCK,
157 DAC_nCS => DAC_nCS,
158 DAC_SDI => DAC_SDI,
159 address => GPMC_SLAVE_ADDRESS(3 downto 1),
160 DATA => GPMC_SLAVE_DATA,
161 WEN => GPMC_SLAVE_WEN,
162 REN_debug => LED(1),
163 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
164 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
291 165 );
292 166
293
294 167
295 smpclk0: Clk_divider
296 GENERIC map(OSC_freqHz => 50000000,
297 TargetFreq_Hz => 256000)
298 PORT map( clk => clkm,
299 reset => rstn,
300 clk_divided => smpclk
301 );
302
303 all_bits: FOR I in 15 downto 0 GENERATE
304 DAC_DATA(0,I) <= DAC0_DATA(I);
305 DAC_DATA(1,I) <= DAC1_DATA(I);
306 DAC_DATA(2,I) <= DAC2_DATA(I);
307 DAC_DATA(3,I) <= DAC3_DATA(I);
308 DAC_DATA(4,I) <= DAC4_DATA(I);
309 DAC_DATA(5,I) <= DAC5_DATA(I);
310 DAC_DATA(6,I) <= DAC6_DATA(I);
311 DAC_DATA(7,I) <= DAC7_DATA(I);
312 end GENERATE;
313
314 process(clkm,rstn)
315 begin
316 if rstn ='0' then
317 DAC0_DATA <= X"0000";
318 DAC1_DATA <= X"0000";
319 DAC2_DATA <= X"0000";
320 DAC3_DATA <= X"0000";
321 DAC4_DATA <= X"0000";
322 DAC5_DATA <= X"0000";
323 DAC6_DATA <= X"0000";
324 DAC7_DATA <= X"0000";
325 smpclk_reg <= smpclk;
326 elsif clkm'event and clkm = '1' then
327 smpclk_reg <= smpclk;
328 if smpclk_reg = '0' and smpclk = '1' then
329 DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
330 DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
331 DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
332 DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
333 DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
334 DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
335 DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
336 DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
337 -- DAC_DATA <= "0100000000000000";
338 end if;
339 end if;
340 end process;
168
169 LED(0) <= GPMC_SLAVE_WEN;
170 LED(2) <= GPMC_WEN;
341 171
342 172 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
343 173 GPMCS0: entity work.GPMC_SLAVE
344 174 generic map(memtech,padtech)
345 175 Port map(
346 176 clk => clkm,
347 177 reset => rstn,
178 STATUS => GPMC_SLAVE_STATUS,
179 DATA => GPMC_SLAVE_DATA,
180 ADDRESS => GPMC_SLAVE_ADDRESS,
181 WEN => GPMC_SLAVE_WEN,
348 182 GPMC_AD => GPMC_AD,
349 183 GPMC_A => GPMC_A,
350 GPMC_CLK_MUX0 => gpmc_clk,
184 GPMC_CLK => gpmc_clk,
351 185 GPMC_WEN => GPMC_WEN,
352 186 GPMC_OEN_REN => GPMC_OEN_REN,
353 187 GPMC_ADVN_ALE => GPMC_ADVN_ALE,
354 188 GPMC_CSN => GPMC_CSN,
355 189 GPMC_BE0N_CLE => GPMC_BE0N_CLE,
356 190 GPMC_BE1N => GPMC_BE1N,
357 191 GPMC_WAIT0 => GPMC_WAIT0,
358 GPMC_WPN => GPMC_WAIT0
192 GPMC_WPN => GPMC_WPN
359 193 );
360 194
361 195 end rtl;
362 196
363 197
364 198
Show file before | Show file after | Hide comments
@@ -1,100 +1,122
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 15:20:11 12/08/2013
6 6 -- Design Name:
7 7 -- Module Name: GPMC_SLAVE - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 library IEEE;
21 21 use IEEE.STD_LOGIC_1164.ALL;
22 22 use IEEE.numeric_std.all;
23 23 library grlib, techmap;
24 24 use grlib.stdlib.all;
25 25 use techmap.gencomp.all;
26 26 use techmap.allclkgen.all;
27 27 library lpp;
28 28 use lpp.general_purpose.all;
29 29
30 30 entity GPMC_SLAVE is
31 31 generic (
32 32 memtech : integer := 0;
33 33 padtech : integer := 0
34 34 );
35 35 Port (
36 36 clk : in STD_LOGIC;
37 37 reset : in STD_LOGIC;
38 STATUS : in STD_LOGIC_VECTOR(15 downto 0);
39 DATA : out STD_LOGIC_VECTOR(15 downto 0);
40 ADDRESS : out std_logic_vector(19 downto 0);
41 WEN : out STD_LOGIC;
38 42 GPMC_AD : inout std_logic_vector(15 downto 0);
39 43 GPMC_A : in std_logic_vector(19 downto 0);
40 GPMC_CLK_MUX0 : in std_ulogic;
41 GPMC_WEN : in std_ulogic;
42 GPMC_OEN_REN : in std_ulogic;
43 GPMC_ADVN_ALE : in std_ulogic;
44 GPMC_CSN : in std_ulogic_vector(2 downto 0);
45 GPMC_BE0N_CLE : in std_ulogic;
46 GPMC_BE1N : in std_ulogic;
47 GPMC_WAIT0 : in std_ulogic;
48 GPMC_WPN : in std_ulogic
44 GPMC_CLK : in std_logic;
45 GPMC_WEN : in std_logic;
46 GPMC_OEN_REN : in std_logic;
47 GPMC_ADVN_ALE : in std_logic;
48 GPMC_CSN : in std_logic_vector(2 downto 0);
49 GPMC_BE0N_CLE : in std_logic;
50 GPMC_BE1N : in std_logic;
51 GPMC_WAIT0 : out std_logic;
52 GPMC_WPN : in std_logic
49 53 );
50 54 end GPMC_SLAVE;
51 55
52 56 architecture Behavioral of GPMC_SLAVE is
53 constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
57
58 signal data_out : std_logic_vector(15 downto 0) := (others => '0');
59 signal data_in : std_logic_vector(15 downto 0) := (others => '0');
54 60
55 signal data_out :std_logic_vector(15 downto 0);
56 signal data_in :std_logic_vector(15 downto 0);
61 signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0');
62 signal data_r : std_logic_vector(15 downto 0) := (others => '0');
57 63
58 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
59 signal RAMarray : RAMarrayT:=(others => VectInit);
60 signal ramindex : integer range 0 to 255;
64
65 signal outen : std_logic := '0';
66
61 67
62 68 begin
63 69
70 outen <= GPMC_OEN_REN or GPMC_CSN(0);
71 data_out <= STATUS;
72
64 73 data_pad : iopadv generic map (tech=> padtech,width => 16)
65 74 port map (
66 75 pad => GPMC_AD(15 downto 0),
67 76 o => data_in(15 downto 0),
68 en => GPMC_OEN_REN,
77 en => outen,
69 78 i => data_out(15 downto 0)
70 79 );
71 80
72 process(reset,GPMC_CLK_MUX0)
81 GPMC_WAIT0 <= '1';
82
83
84
85 process(reset,clk)
73 86 begin
74 87 if reset = '0' then
75 data_out <= (others => '0');
76 ramindex <= 0;
77 elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
78 ramindex <= to_integer(unsigned(GPMC_A));
79 data_out <= RAMarray(ramindex);
80 if GPMC_WEN = '0' then
81 RAMarray(ramindex) <= data_in;
88 WEN <= '1';
89 GPMC_CLK_reg <= "0000";
90 ADDRESS <= (others => '0');
91 elsif clk'event and clk = '1' then
92 GPMC_CLK_reg(0) <= GPMC_CLK;
93 if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then
94 if GPMC_WEN = '0' then
95 WEN <= '0';
96 DATA <= data_in;
97 end if;
98 if GPMC_ADVN_ALE = '0' then
99 ADDRESS <= GPMC_A;
100 end if;
101 else
102 WEN <= '1';
82 103 end if;
104
83 105 end if;
84 106 end process;
85 107
86 108 end Behavioral;
87 109
88 110
89 111
90 112
91 113
92 114
93 115
94 116
95 117
96 118
97 119
98 120
99 121
100 122
Show file before | Show file after | Hide comments
@@ -1,49 +1,49
1 1 include .config
2 2
3 3 #GRLIB=$(GRLIB)
4 4 TOP=BeagleSynth
5 5 BOARD=BeagleSynth
6 6 #BOARD=SP601
7 7 include ../../boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
10 10 UCF=../../boards/$(BOARD)/default.ucf
11 11 QSF=../../boards/$(BOARD)/$(TOP).qsf
12 12 EFFORT=high
13 13 ISEMAPOPT="-timing"
14 14 XSTOPT=""
15 15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
16 16 VHDLOPTSYNFILES=
17 17
18 18
19 19 VHDLSYNFILES= \
20 config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd
20 config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd beagleSigGen.vhd GPMC_ASYNC_SLAVE.vhd
21 21 #VHDLSIMFILES=testbench.vhd
22 22 #SIMTOP=testbench
23 23 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
24 24 SDCFILE=default.sdc
25 25 BITGEN=../../boards/$(BOARD)/default.ut
26 26 CLEAN=soft-clean
27 27 VCOMOPT=-explicit
28 28 TECHLIBS = secureip unisim
29 29
30 30 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 31 tmtc openchip cypress ihp gleichmann gsi fmf spansion
32 32 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
33 33 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
34 34 ac97 hcan usb
35 35 DIRADD =
36 36 FILEADD =
37 37 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
38 38
39 39 include $(GRLIB)/bin/Makefile
40 40 include $(GRLIB)/software/leon3/Makefile
41 41
42 42
43 43 ################## project specific targets ##########################
44 44
45 45 flash:
46 46 xc3sprog -c ftdi -p 1 BeagleSynth.bit
47 47
48 48 ram:
49 49 xc3sprog -c ftdi -p 0 BeagleSynth.bit
Show file before | Show file after | Hide comments
@@ -1,78 +1,78
1 1
2 2
3 3
4 4 -----------------------------------------------------------------------------
5 5 -- LEON3 Demonstration design test bench configuration
6 6 -- Copyright (C) 2009 Aeroflex Gaisler
7 7 ------------------------------------------------------------------------------
8 8
9 9
10 10 library techmap;
11 11 use techmap.gencomp.all;
12 12 LIBRARY IEEE;
13 13 USE IEEE.numeric_std.ALL;
14 14 USE IEEE.std_logic_1164.ALL;
15 15
16 16
17 17 package config is
18 18 -- Technology and synthesis options
19 19 constant CFG_FABTECH : integer := spartan6;
20 20 constant CFG_MEMTECH : integer := spartan6;
21 21 constant CFG_PADTECH : integer := spartan6;
22 22
23 23 -- Clock generator
24 24 -- ON Spartan 6 VCO freq must be between 400MHz and 1GHz
25 25 constant CFG_CLKTECH : integer := spartan6;
26 26 constant CFG_CLKMUL : integer := (6);
27 constant CFG_CLKDIV : integer := (12);
27 constant CFG_CLKDIV : integer := (4);
28 28 constant CFG_OCLKDIV : integer := (1);
29 29 constant CFG_PCIDLL : integer := 0;
30 30 constant CFG_PCISYSCLK: integer := 0;
31 31 constant CFG_CLK_NOFB : integer := 0;
32 32
33 33 -- AMBA settings
34 34 constant CFG_DEFMST : integer := (0);
35 35 constant CFG_RROBIN : integer := 1;
36 36 constant CFG_SPLIT : integer := 0;
37 37 constant CFG_AHBIO : integer := 16#FFF#;
38 38 constant CFG_APBADDR : integer := 16#800#;
39 39 constant CFG_AHB_MON : integer := 0;
40 40 constant CFG_AHB_MONERR : integer := 0;
41 41 constant CFG_AHB_MONWAR : integer := 0;
42 42
43 43 -- LEON3 processor core
44 44 constant CFG_LEON3 : integer := 0;
45 45 constant CFG_NCPU : integer := (0);
46 46
47 47 -- DSU UART
48 48 constant CFG_AHB_UART : integer := 1;
49 49
50 50 -- JTAG based DSU interface
51 51 constant CFG_AHB_JTAG : integer := 0;
52 52
53 53 -- UART 1
54 54 constant CFG_UART1_ENABLE : integer := 1;
55 55 constant CFG_UART1_FIFO : integer := 1;
56 56
57 57 -- GRLIB debugging
58 58 constant CFG_DUART : integer := 0;
59 59
60 60 -- LEON2 memory controller
61 61 constant CFG_MCTRL_LEON2 : integer := 1;
62 62 constant CFG_MCTRL_RAM8BIT : integer := 1;
63 63 constant CFG_MCTRL_RAM16BIT : integer := 0;
64 64 constant CFG_MCTRL_5CS : integer := 0;
65 65 constant CFG_MCTRL_SDEN : integer := 1;
66 66 constant CFG_MCTRL_SEPBUS : integer := 0;
67 67 constant CFG_MCTRL_INVCLK : integer := 0;
68 68 constant CFG_MCTRL_SD64 : integer := 0;
69 69 constant CFG_MCTRL_PAGE : integer := 1 + 0;
70 70
71 71 -- Gaisler Ethernet core
72 72 constant CFG_GRETH : integer := 0;
73 73
74 74 -- CAN 2.0 interface
75 75 constant CFG_CAN : integer := 0;
76 76
77 77
78 78 end;
Show file before | Show file after | Hide comments
@@ -1,130 +1,155
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 15:26:29 12/07/2013
6 6 -- Design Name:
7 7 -- Module Name: DAC8581 - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 library IEEE;
21 21 use IEEE.STD_LOGIC_1164.ALL;
22 22 use IEEE.numeric_std.all;
23 23 library LPP;
24 24 use lpp.lpp_cna.all;
25 25
26 26 -- Uncomment the following library declaration if using
27 27 -- arithmetic functions with Signed or Unsigned values
28 28 use IEEE.NUMERIC_STD.ALL;
29 29
30 30 -- Uncomment the following library declaration if instantiating
31 31 -- any Xilinx primitives in this code.
32 32 --library UNISIM;
33 33 --use UNISIM.VComponents.all;
34 34
35 35 entity DAC8581 is
36 36 generic(
37 37 clkfreq : integer := 100;
38 38 ChanCount : integer := 8
39 39 );
40 40 Port ( clk : in STD_LOGIC;
41 41 rstn : in STD_LOGIC;
42 42 smpclk : in STD_LOGIC;
43 43 sclk : out STD_LOGIC;
44 44 csn : out STD_LOGIC;
45 45 sdo : out STD_LOGIC_VECTOR (ChanCount-1 downto 0);
46 46 smp_in : in CNA_16bit_T(ChanCount-1 downto 0,15 downto 0)
47 47 );
48 48 end DAC8581;
49 49
50 50 architecture Behavioral of DAC8581 is
51 51
52 52 signal smpclk_reg : std_logic;
53 53 signal sclk_gen : std_logic_vector(3 downto 0);
54 54 signal sclk_net : std_logic;
55 55 signal load : std_logic;
56 signal load_reg : std_logic;
56 57 signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
57 signal csn_sreg : std_logic_vector(15 downto 0);
58 58
59 signal csn_sreg : std_logic;
60 signal shift_counter : integer range 0 to 16;
61 signal sdo_int : STD_LOGIC_VECTOR (ChanCount-1 downto 0);
59 62 begin
60 63
61 64
62 65
63 sclk_net <= sclk_gen(1);
66 sclk_net <= sclk_gen(2);
64 67 sclk <= sclk_net;
65 68
66 69 process(rstn,clk)
67 70 begin
68 71 if rstn ='0' then
69 72 smpclk_reg <= '0';
70 73 sclk_gen <= "0000";
71 74 load <= '0';
72 75 elsif clk'event and clk = '1' then
73 76 smpclk_reg <= smpclk;
74 77 sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1);
75 78 if smpclk_reg = '0' and smpclk = '1' then
76 79 load <= '1';
77 80 else
78 81 load <= '0';
79 82 end if;
80 83
81 84 end if;
82 85 end process;
83 86
84 87 process(load,sclk_net)
85 88 begin
86 89 if load ='1' then
87 data_sreg <= smp_in;
88 csn_sreg <= (others => '0');
89
90 elsif sclk_net'event and sclk_net = '1' then
91 all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
92 all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
93 data_sreg(I,J+1) <= data_sreg(I,J);
94 END LOOP all_bits0;
95 data_sreg(I,0) <= '1';
96 END LOOP all_chanel0;
97 csn_sreg <= csn_sreg(14 downto 0) & '1';
90 load_reg <= '1';
91 elsif sclk_net'event and sclk_net = '1' then
92 load_reg <= '0';
93 end if;
94 end process;
95
96 process(rstn,sclk_net)
97 begin
98 if rstn ='0' then
99 data_sreg <= smp_in;
100 csn_sreg <= '1';
101 elsif sclk_net'event and sclk_net = '1' then
102 if load_reg = '1' then
103 data_sreg <= smp_in;
104 shift_counter <= 0;
105 csn_sreg <= '1';
106 else
107 all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
108 all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
109 data_sreg(I,J+1) <= data_sreg(I,J);
110 END LOOP all_bits0;
111 data_sreg(I,0) <= '1';
112 END LOOP all_chanel0;
113 if shift_counter /= 16 then
114 shift_counter <= shift_counter + 1;
115 csn_sreg <= '0';
116 else
117 csn_sreg <= '1';
118 end if;
119
120 end if;
98 121 end if;
99 122 end process;
100 123
101 124 process(rstn,sclk_net)
102 125 begin
103 126 if rstn ='0' then
104 127 all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
105 sdo(I) <= '1';
128 sdo_int(I) <= '1';
129 sdo(I) <= '1';
106 130 END LOOP all_chanel2;
107 131 csn <= '1';
108 132 elsif sclk_net'event and sclk_net = '0' then
109 133 all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
110 sdo(I) <= data_sreg(I,15);
134 sdo_int(I) <= data_sreg(I,15);
111 135 END LOOP all_chanel1;
112 csn <= csn_sreg(15);
136 sdo <= sdo_int;
137 csn <= csn_sreg;
113 138 end if;
114 139 end process;
115 140
116 141
117 142
118 143 end Behavioral;
119 144
120 145
121 146
122 147
123 148
124 149
125 150
126 151
127 152
128 153
129 154
130 155
Show file before | Show file after | Hide comments
@@ -1,68 +1,73
1 1 echo "======================================================================================="
2 2 echo "---------------------------------------------------------------------------------------"
3 3 echo " LPP's GRLIB GLOBAL PATCHER "
4 4 echo " Copyright (C) 2013 Laboratory of Plasmas Physic. "
5 5 echo "======================================================================================="
6 6 echo '------------------------------------------------------------------------------
7 7 -- This file is a part of the LPP VHDL IP LIBRARY
8 8 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
9 9 --
10 10 -- This program is free software; you can redistribute it and/or modify
11 11 -- it under the terms of the GNU General Public License as published by
12 12 -- the Free Software Foundation; either version 3 of the License, or
13 13 -- (at your option) any later version.
14 14 --
15 15 -- This program is distributed in the hope that it will be useful,
16 16 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
17 17 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 18 -- GNU General Public License for more details.
19 19 --
20 20 -- You should have received a copy of the GNU General Public License
21 21 -- along with this program; if not, write to the Free Software
22 22 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 23 -------------------------------------------------------------------------------'
24 24 echo
25 25 echo
26 26 echo
27 27
28 28
29 29 VHDLIB_LIB_PATH=`pwd -L`
30 30 source $VHDLIB_LIB_PATH/scripts/lpp_bash_functions.sh
31 31 GRLIBPATH=$1
32 32
33 33 if [ -d "$GRLIBPATH" ]; then
34 34 LPP_PATCHPATH=`relpath $GRLIBPATH/lib $VHDLIB_LIB_PATH`
35 35 echo $LPP_PATCHPATH
36 36 if [ -d "$GRLIBPATH/lib" ]; then
37 37 if [ -d "$GRLIBPATH/designs" ]; then
38 38 if [ -d "$GRLIBPATH/boards" ]; then
39 39
40 40 echo "Patch $1/lib/libs.txt..."
41 41 if(grep -q $LPP_PATCHPATH/lib/lpp $1/lib/libs.txt); then
42 42 echo "No need to Patch $1/lib/libs.txt..."
43 43 else
44 44 echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
45 45 fi
46 if(grep -q $LPP_PATCHPATH/lib/staging $1/lib/libs.txt); then
47 echo "No need to Patch $1/lib/libs.txt..."
48 else
49 echo $LPP_PATCHPATH/lib/staging >>$1/lib/libs.txt
50 fi
46 51 echo
47 52 echo
48 53 echo
49 54 else
50 55 echo "I can't find GRLIB in $1"
51 56 fi
52 57
53 58 else
54 59 echo "I can't find GRLIB in $1"
55 60 fi
56 61 else
57 62 echo "I can't find GRLIB in $1"
58 63 fi
59 64
60 65 else
61 66 echo "I can't find GRLIB in $1"
62 67 fi
63 68
64 69
65 70
66 71
67 72
68 73
General Comments 0
You need to be logged in to leave comments. Login now