diff --git a/boards/BeagleSynth/default.ucf b/boards/BeagleSynth/default.ucf
--- a/boards/BeagleSynth/default.ucf
+++ b/boards/BeagleSynth/default.ucf
@@ -2,8 +2,7 @@
 NET "CLK"      CLOCK_DEDICATED_ROUTE = FALSE;
 NET "CLK"              LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
 NET "CLKM" TNM_NET = "clkm_net";
-TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
-
+TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 6 ns HIGH 33%;
 
 NET "RESET"    CLOCK_DEDICATED_ROUTE = FALSE;
 NET "RESET"            LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
@@ -133,6 +132,8 @@ NET "GPMC_A(18)"   LOC = "J1"| slew=FAST
 NET "GPMC_A(19)"   LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL;
 
 NET "GPMC_CLK_MUX0"    CLOCK_DEDICATED_ROUTE = FALSE;
+NET "GPMC_CLK_MUX0" TNM_NET = "GPMC_CLK_MUX0_net";
+TIMESPEC "TS_GPMC_CLK_MUX0_net" = PERIOD "GPMC_CLK_MUX0_net" 8 ns HIGH 50%;
 NET "GPMC_CLK_MUX0"   LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL;
 NET "GPMC_WEN"        LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL;
 NET "GPMC_OEN_REN"    LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL;
diff --git a/designs/BeagleSynth/BeagleSynth.vhd b/designs/BeagleSynth/BeagleSynth.vhd
--- a/designs/BeagleSynth/BeagleSynth.vhd
+++ b/designs/BeagleSynth/BeagleSynth.vhd
@@ -59,15 +59,15 @@ entity BeagleSynth is
 --------------------------------------------------------
         GPMC_AD       : inout std_logic_vector(15 downto 0);
         GPMC_A        : in  std_logic_vector(19 downto 0);
-        GPMC_CLK_MUX0 : in  std_ulogic;
-        GPMC_WEN      : in  std_ulogic;   
-        GPMC_OEN_REN  : in  std_ulogic;  
-        GPMC_ADVN_ALE : in  std_ulogic;   
-        GPMC_CSN      : in  std_ulogic_vector(2 downto 0);
-        GPMC_BE0N_CLE : in  std_ulogic; 
-        GPMC_BE1N     : in  std_ulogic;
-        GPMC_WAIT0    : in  std_ulogic;
-        GPMC_WPN      : in  std_ulogic;
+        GPMC_CLK_MUX0 : in  std_logic;
+        GPMC_WEN      : in  std_logic;   
+        GPMC_OEN_REN  : in  std_logic;  
+        GPMC_ADVN_ALE : in  std_logic;   
+        GPMC_CSN      : in  std_logic_vector(2 downto 0);
+        GPMC_BE0N_CLE : in  std_logic; 
+        GPMC_BE1N     : in  std_logic;
+        GPMC_WAIT0    : out std_logic;
+        GPMC_WPN      : in  std_logic;
 
 --------------------------------------------------------
 ----       SDRAM
@@ -75,15 +75,15 @@ entity BeagleSynth is
 ---- design from GRLIB, the  IS42S32400E is similar to
 ---- MT48LC4M32B2.     
 --------------------------------------------------------
-	 sdcke         : out std_logic; -- clk en
-	 sdcsn         : out std_logic; -- chip sel
-	 sdwen         : out std_logic;                      -- write en 
-	 sdrasn        : out std_logic;                      -- row addr stb
-	 sdcasn        : out std_logic;                      -- col addr stb
-	 sddqm         : out std_logic_vector (3 downto 0);  -- data i/o mask
-	 sdclk         : out std_logic;                      -- sdram clk output
-	 sdba          : out std_logic_vector (1 downto 0);  -- bank select address
-	 Address       : out std_logic_vector(11 downto 0);  -- sdram address
+	 sdcke         : out   std_logic; -- clk en
+	 sdcsn         : out   std_logic; -- chip sel
+	 sdwen         : out   std_logic;                      -- write en 
+	 sdrasn        : out   std_logic;                      -- row addr stb
+	 sdcasn        : out   std_logic;                      -- col addr stb
+	 sddqm         : out   std_logic_vector (3 downto 0);  -- data i/o mask
+	 sdclk         : out   std_logic;                      -- sdram clk output
+	 sdba          : out   std_logic_vector (1 downto 0);  -- bank select address
+	 Address       : out   std_logic_vector(11 downto 0);  -- sdram address
 	 Data          : inout std_logic_vector(31 downto 0) -- optional sdram data
 	 );
 end;
@@ -107,53 +107,33 @@ signal sdclkl_DDR2   : std_ulogic;
 signal cgi      : clkgen_in_type;
 signal cgo      : clkgen_out_type;
 
---- AHB / APB
-signal apbi     : apb_slv_in_type;
-signal apbo     : apb_slv_out_vector := (others => apb_none);
-signal ahbsi    : ahb_slv_in_type;
-signal ahbso    : ahb_slv_out_vector := (others => ahbs_none);
-signal ahbmi    : ahb_mst_in_type;
-signal ahbmo    : ahb_mst_out_vector := (others => ahbm_none);
-
---- MEM CTRLR
-signal sdi : sdctrl_in_type;
-signal sdo : sdctrl_out_type;
-
---UART
-signal ahbuarti : uart_in_type;
-signal ahbuarto : uart_out_type;
-signal apbuarti : uart_in_type;
-signal apbuarto : uart_out_type;
-
-signal led2int  : std_logic;
-
-
-signal DAC0_DATA	 : std_logic_vector(15 downto 0);
-signal DAC1_DATA	 : std_logic_vector(15 downto 0);
-signal DAC2_DATA	 : std_logic_vector(15 downto 0);
-signal DAC3_DATA	 : std_logic_vector(15 downto 0);
-signal DAC4_DATA	 : std_logic_vector(15 downto 0);
-signal DAC5_DATA	 : std_logic_vector(15 downto 0);
-signal DAC6_DATA	 : std_logic_vector(15 downto 0);
-signal DAC7_DATA	 : std_logic_vector(15 downto 0);
 
 signal DAC_DATA    : CNA_16bit_T(7 downto 0,15 downto 0);
 signal smpclk      : std_logic;
 signal smpclk_reg  : std_logic;
 signal DAC_SDO	    : std_logic;
 
+signal GPMC_SLAVE_STATUS      : std_logic_vector(15 downto 0);
+signal GPMC_SLAVE_DATA        : std_logic_vector(15 downto 0);
+signal GPMC_SLAVE_ADDRESS     : std_logic_vector(19 downto 0);
+signal GPMC_SLAVE_WEN	       : std_logic;
+
 signal gpmc_clk    : std_logic;
+
+attribute keep                     : boolean;
+attribute syn_keep                 : boolean;
+attribute syn_preserve             : boolean;
+attribute syn_keep of clkm         : signal is true;
+attribute syn_preserve of clkm     : signal is true;
+attribute keep of clkm             : signal is true;
 begin
 
 DAC_nCLR		<= '1';
---DAC_nCS     <= SYNC;
---CAL_IN_SCK  <= '1';
---DAC_SDI		<= (others =>'1');
+
 
 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
   rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
-  --rstn	<= reset;
-  --lclk <= clk;
+
   clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
 
   cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
@@ -161,183 +141,33 @@ resetn_pad : inpad generic map (tech => 
     generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
     port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
 
---  sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
---sdclk <= sdclkl;
-sdclk <= sdclkl_DDR2;
-
-LED(1)  <= not cgo.clklock;
-LED(0)  <= cgo.clklock;
-
-ODDR2_inst : ODDR2
-   generic map(
-      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
-      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
-      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
-   port map (
-      Q => sdclkl_DDR2, -- 1-bit output data
-      C0 => sdclkl, -- 1-bit clock input
-      C1 => not sdclkl, -- 1-bit clock input
-      CE => '1',  -- 1-bit clock enable input
-      D0 => '1',   -- 1-bit data input (associated with C0)
-      D1 => '0',   -- 1-bit data input (associated with C1)
-      R =>  '0',    -- 1-bit reset input
-      S => '0'     -- 1-bit set input
-   );
-
-----------------------------------------------------------------------
----  AHB CONTROLLER  -------------------------------------------------
-----------------------------------------------------------------------
-
-  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
-  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, 
-	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
-	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
-  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
-
-----------------------------------------------------------------------
----  AHB UART  -------------------------------------------------------
-----------------------------------------------------------------------
-
-  dcomgen : if CFG_AHB_UART = 1 generate
-    dcom0: ahbuart		-- Debug UART
-    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
-    port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
-    ahbuarti.rxd  <= RXD; 
-    TXD           <= ahbuarto.txd;
-  end generate;
-  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
-
-----------------------------------------------------------------------
----  APB Bridge  -----------------------------------------------------
-----------------------------------------------------------------------
-
-  apb0 : apbctrl				-- AHB/APB bridge
-  generic map (hindex => 1, haddr => CFG_APBADDR)
-  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
-  
-----------------------------------------------------------------------
----  APB UART  -------------------------------------------------------
-----------------------------------------------------------------------
-
-  ua1 : if CFG_UART1_ENABLE /= 0 generate
-    uart1 : apbuart			-- UART 1
-    generic map (pindex => 1, paddr => 1,  pirq => 2, console => CFG_DUART,
-	fifosize => CFG_UART1_FIFO)
-    port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
-    apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
-    apbuarti.ctsn <= '0';
-  end generate;
-  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-
-
-
-
---div0: Clk_divider 
---	 generic map( 100000000,1)
---    Port map( clkm,rstn,LED(2));
-
-LED(2) <= led2int;
-
-process(clkm,rstn)
-begin
-	if rstn = '0' then
-		led2int <= '0';
-	elsif clkm'event and clkm='1' then
-		led2int <= not led2int;
-	end if;
-end process;
-
 
 
 
-sdc : sdctrl 
-   generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0, 
-	invclk => 0,sdbits =>32)
-	port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
-	
-  
-  
---Alternative data pad instantiation with vectored bdrive
-sd_pad : iopadvv generic map (tech=> padtech,width => 32)
-port map (
-  data(31 downto 0), 
-  sdo.data(31 downto 0), 
-  sdo.vbdrive(31 downto 0), 
-  sdi.data(31 downto 0));
-
-
--- connect memory controller outputs to entity output signals
-Address <= sdo.address(13 downto 2);
---sdba	  <= sdo.address(16 downto 15);
-sdba	  <= "00";
-sdcke <= sdo.sdcke(0); 
-sdwen <= sdo.sdwen; 
-sdcsn <= sdo.sdcsn(0);
-sdrasn <= sdo.rasn; 
-sdcasn <= sdo.casn; 
-sddqm <= sdo.dqm(3 downto 0);
-
-
-DAC0 :  DAC8581 
-    generic map(100,8)
+DAC0 :  entity work.beagleSigGen 
+	generic map(
+			memtech,
+			padtech,
+			clktech
+			)
     Port map( 
-	        clk =>      clkm,
-           rstn =>     rstn,
-           smpclk =>   smpclk,
-           sclk =>     CAL_IN_SCK,
-           csn =>		  DAC_nCS,
-           sdo =>      DAC_SDI,
-           smp_in =>   DAC_DATA
+	        clk          => clkm,
+           rstn         => rstn,
+			  CAL_IN_SCK   => CAL_IN_SCK,
+			  DAC_nCS      => DAC_nCS,
+           DAC_SDI      => DAC_SDI,
+			  address      => GPMC_SLAVE_ADDRESS(3 downto 1),
+			  DATA   	   => GPMC_SLAVE_DATA,
+			  WEN				=> GPMC_SLAVE_WEN,
+			  REN_debug    => LED(1),
+			  FIFO_FULL	   => GPMC_SLAVE_STATUS(7 downto 0),
+			  FIFO_EMPTY	=> GPMC_SLAVE_STATUS(15 downto 8)
 			  );
 
-	 
 
-  smpclk0: Clk_divider 
-    GENERIC map(OSC_freqHz  => 50000000,
-            TargetFreq_Hz   => 256000)
-    PORT map( clk          =>  clkm,
-           reset        =>  rstn,
-           clk_divided  =>  smpclk 
-			  );
-
-all_bits: FOR I in 15 downto 0 GENERATE
-	DAC_DATA(0,I) <= DAC0_DATA(I);
-	DAC_DATA(1,I) <= DAC1_DATA(I);
-	DAC_DATA(2,I) <= DAC2_DATA(I);
-	DAC_DATA(3,I) <= DAC3_DATA(I);
-	DAC_DATA(4,I) <= DAC4_DATA(I);
-	DAC_DATA(5,I) <= DAC5_DATA(I);
-	DAC_DATA(6,I) <= DAC6_DATA(I);
-	DAC_DATA(7,I) <= DAC7_DATA(I);
-end GENERATE;
-
-process(clkm,rstn)
-begin
-if rstn ='0' then
-	DAC0_DATA	<= X"0000";
-	DAC1_DATA	<= X"0000";
-	DAC2_DATA	<= X"0000";
-	DAC3_DATA	<= X"0000";
-	DAC4_DATA	<= X"0000";
-	DAC5_DATA	<= X"0000";
-	DAC6_DATA	<= X"0000";
-	DAC7_DATA	<= X"0000";
-	smpclk_reg	<= smpclk;
-elsif clkm'event and clkm = '1' then 
-	smpclk_reg <= smpclk;
-	if smpclk_reg = '0' and smpclk = '1' then
-		DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1);
-		DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2);
-		DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3);
-		DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4);
-		DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5);
-		DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6);
-		DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7);
-		DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8);
---		DAC_DATA <= "0100000000000000";
-	end if;
-end if;
-end process;
+	
+LED(0)	<= GPMC_SLAVE_WEN;
+LED(2)	<= GPMC_WEN;
 
 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
 GPMCS0: entity work.GPMC_SLAVE
@@ -345,9 +175,13 @@ GPMCS0: entity work.GPMC_SLAVE
     Port map( 
 	     clk           => clkm,
         reset         => rstn,
+		  STATUS        => GPMC_SLAVE_STATUS,
+		  DATA          => GPMC_SLAVE_DATA,
+		  ADDRESS       => GPMC_SLAVE_ADDRESS,
+		  WEN	          => GPMC_SLAVE_WEN,
         GPMC_AD       => GPMC_AD,
         GPMC_A        => GPMC_A,
-        GPMC_CLK_MUX0 => gpmc_clk,
+        GPMC_CLK      => gpmc_clk,
         GPMC_WEN      => GPMC_WEN,
         GPMC_OEN_REN  => GPMC_OEN_REN,
         GPMC_ADVN_ALE => GPMC_ADVN_ALE,
@@ -355,7 +189,7 @@ GPMCS0: entity work.GPMC_SLAVE
         GPMC_BE0N_CLE => GPMC_BE0N_CLE,
         GPMC_BE1N     => GPMC_BE1N,
         GPMC_WAIT0    => GPMC_WAIT0,
-        GPMC_WPN      => GPMC_WAIT0
+        GPMC_WPN      => GPMC_WPN
 		  );
 
 end rtl;
diff --git a/designs/BeagleSynth/BeagleSynth_MCTRL.vhd b/designs/BeagleSynth/BeagleSynth_MCTRL.vhd
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/BeagleSynth_MCTRL.vhd
@@ -0,0 +1,274 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library grlib, techmap;
+use grlib.amba.all;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+library esa;
+use esa.memoryctrl.all;
+--use gaisler.sim.all;
+library lpp;
+use lpp.lpp_ad_conv.all;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+use lpp.general_purpose.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+use work.config.all;
+--==================================================================
+--
+--
+--			FPGA FREQ = 100MHz
+--
+--
+--==================================================================
+
+entity BeagleSynth_MCTRL is
+  generic (
+    fabtech       : integer := CFG_FABTECH;
+    memtech       : integer := CFG_MEMTECH;
+    padtech       : integer := CFG_PADTECH;
+    clktech       : integer := CFG_CLKTECH
+  );
+  port (
+    reset         : in  std_ulogic;
+    clk           : in  std_ulogic;
+	 DAC_nCLR		: out std_ulogic;
+	 DAC_nCS       : out std_ulogic;
+	 CAL_IN_SCK		: out std_ulogic;
+	 DAC_SDI			: out std_ulogic_vector(7 downto 0);
+	 TXD				: out std_ulogic;
+	 RXD				: in  std_ulogic;
+	 urxd1	      : in  std_ulogic;
+	 utxd1         : out std_ulogic;
+	 LED				: out std_ulogic_vector(2 downto 0);
+--------------------------------------------------------
+----       SDRAM
+---- For SDRAM config have a look on leon3-altera-ep1c20
+---- design from GRLIB, the  IS42S32400E is similar to
+---- MT48LC4M32B2.     
+--------------------------------------------------------
+	 sdcke         : out std_logic; -- clk en
+	 sdcsn         : out std_logic; -- chip sel
+	 sdwen         : out std_logic;                      -- write en 
+	 sdrasn        : out std_logic;                      -- row addr stb
+	 sdcasn        : out std_logic;                      -- col addr stb
+	 sddqm         : out std_logic_vector (3 downto 0);  -- data i/o mask
+	 sdclk         : out std_logic;                      -- sdram clk output
+	 sdba          : out std_logic_vector (1 downto 0);  -- bank select address
+	 Address       : out std_logic_vector(11 downto 0);  -- sdram address
+	 Data          : inout std_logic_vector(31 downto 0) -- optional sdram data
+	 );
+end;
+
+architecture rtl of BeagleSynth_MCTRL is
+constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
+	CFG_GRETH+CFG_AHB_JTAG;
+constant maxahbm : integer := maxahbmsp;
+constant IOAEN  : integer := CFG_CAN;
+constant boardfreq : integer := 100000;
+
+signal clk2x    : std_ulogic;
+signal lclk     : std_ulogic;
+signal clkm     : std_ulogic;
+signal rstn     : std_ulogic;
+signal rst      : std_ulogic;
+signal rstraw   : std_ulogic;
+signal pciclk   : std_ulogic;
+signal sdclkl   : std_ulogic;
+signal sdclkl_DDR2   : std_ulogic;
+signal cgi      : clkgen_in_type;
+signal cgo      : clkgen_out_type;
+
+--- AHB / APB
+signal apbi     : apb_slv_in_type;
+signal apbo     : apb_slv_out_vector := (others => apb_none);
+signal ahbsi    : ahb_slv_in_type;
+signal ahbso    : ahb_slv_out_vector := (others => ahbs_none);
+signal ahbmi    : ahb_mst_in_type;
+signal ahbmo    : ahb_mst_out_vector := (others => ahbm_none);
+
+--- MEM CTRLR
+signal memi  : memory_in_type;
+signal memo  : memory_out_type;
+signal wpo   : wprot_out_type;
+signal sdi   : sdctrl_in_type;
+signal sdo   : sdram_out_type;
+
+--UART
+signal ahbuarti : uart_in_type;
+signal ahbuarto : uart_out_type;
+signal apbuarti : uart_in_type;
+signal apbuarto : uart_out_type;
+
+signal led2int  : std_logic;
+
+begin
+
+DAC_nCLR		<= '1';
+DAC_nCS     <= '1';
+CAL_IN_SCK  <= '1';
+DAC_SDI		<= (others =>'1');
+
+resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
+  rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
+  --rstn	<= reset;
+  --lclk <= clk;
+  clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
+
+  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
+  clkgen0 : clkgen  		-- clock generator
+    generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
+    port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
+
+--  sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
+--sdclk <= sdclkl;
+sdclk <= sdclkl_DDR2;
+
+LED(1)  <= not cgo.clklock;
+LED(0)  <= cgo.clklock;
+
+ODDR2_inst : ODDR2
+   generic map(
+      DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
+      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
+      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+   port map (
+      Q => sdclkl_DDR2, -- 1-bit output data
+      C0 => sdclkl, -- 1-bit clock input
+      C1 => not sdclkl, -- 1-bit clock input
+      CE => '1',  -- 1-bit clock enable input
+      D0 => '1',   -- 1-bit data input (associated with C0)
+      D1 => '0',   -- 1-bit data input (associated with C1)
+      R =>  '0',    -- 1-bit reset input
+      S => '0'     -- 1-bit set input
+   );
+
+----------------------------------------------------------------------
+---  AHB CONTROLLER  -------------------------------------------------
+----------------------------------------------------------------------
+
+  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer
+  generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, 
+	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
+	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
+  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
+
+----------------------------------------------------------------------
+---  AHB UART  -------------------------------------------------------
+----------------------------------------------------------------------
+
+  dcomgen : if CFG_AHB_UART = 1 generate
+    dcom0: ahbuart		-- Debug UART
+    generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
+    port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
+    ahbuarti.rxd  <= RXD; 
+    TXD           <= ahbuarto.txd;
+  end generate;
+  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
+
+----------------------------------------------------------------------
+---  APB Bridge  -----------------------------------------------------
+----------------------------------------------------------------------
+
+  apb0 : apbctrl				-- AHB/APB bridge
+  generic map (hindex => 1, haddr => CFG_APBADDR)
+  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
+  
+----------------------------------------------------------------------
+---  APB UART  -------------------------------------------------------
+----------------------------------------------------------------------
+
+  ua1 : if CFG_UART1_ENABLE /= 0 generate
+    uart1 : apbuart			-- UART 1
+    generic map (pindex => 1, paddr => 1,  pirq => 2, console => CFG_DUART,
+	fifosize => CFG_UART1_FIFO)
+    port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
+    apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
+    apbuarti.ctsn <= '0';
+  end generate;
+  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
+
+
+
+
+--div0: Clk_divider 
+--	 generic map( 100000000,1)
+--    Port map( clkm,rstn,LED(2));
+
+LED(2) <= led2int;
+
+process(clkm,rstn)
+begin
+	if rstn = '0' then
+		led2int <= '0';
+	elsif clkm'event and clkm='1' then
+		led2int <= not led2int;
+	end if;
+end process;
+
+
+
+
+  memi.writen <= '1'; 
+  memi.wrn <= "1111"; 
+  memi.bwidth <= "00";
+  memi.brdyn <= '1';
+  memi.bexcn <= '1';
+
+  mctrl0 : mctrl 
+  generic map (
+   hindex => 0, 
+   pindex => 0,
+	paddr => 0, 
+	srbanks => 1, 
+	ram8 => 1, 
+	ram16 => 1, 
+	sden => 1, 
+	invclk => 0, 
+	sepbus => 0,
+	pageburst => 0)
+  port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
+  
+-- SDRAM controller
+      sdwen_pad : outpad generic map (tech => padtech) 
+	   port map (sdwen, sdo.sdwen);
+      sdras_pad : outpad generic map (tech => padtech) 
+	   port map (sdrasn, sdo.rasn);
+      sdcas_pad : outpad generic map (tech => padtech) 
+	   port map (sdcasn, sdo.casn);
+      sddqm_pad : outpadv generic map (width =>4, tech => padtech) 
+	   port map (sddqm, sdo.dqm(3 downto 0));
+  sdba <= "00";
+  
+  sdcsn_pad : outpad generic map (tech => padtech) 
+	   port map (sdcsn, sdo.sdcsn(0));
+		
+  sdcke_pad : outpad generic map (tech => padtech) 
+      port map (sdcke, sdo.sdcke(0));
+  
+  addr_pad : outpadv generic map (width => 12, tech => padtech) 
+	port map (address, memo.address(11 downto 0)); 
+	
+  bdr : for i in 0 to 3 generate
+      data_pad : iopadv generic map (tech => padtech, width => 8)
+      port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
+	memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
+  end generate;
+
+
+end rtl;
+
+
+ 
diff --git a/designs/BeagleSynth/DAC8581.vhd b/designs/BeagleSynth/DAC8581.vhd
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/DAC8581.vhd
@@ -0,0 +1,117 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    15:26:29 12/07/2013 
+-- Design Name: 
+-- Module Name:    DAC8581 - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+library LPP;
+use lpp.lpp_cna.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity DAC8581 is
+    generic(clkfreq : integer := 100);
+    Port ( clk : in  STD_LOGIC;
+           rstn : in  STD_LOGIC;
+           smpclk : in  STD_LOGIC;
+           sclk : out  STD_LOGIC;
+           csn : out  STD_LOGIC;
+           sdo : out  STD_LOGIC;
+           smp_in : in  STD_LOGIC_VECTOR (15 downto 0)
+			  );
+end DAC8581;
+
+architecture Behavioral of DAC8581 is
+
+
+signal smpclk_reg   : std_logic;
+signal sclk_gen     : std_logic_vector(3 downto 0);
+signal sclk_net     : std_logic;
+signal load         : std_logic;
+signal data_sreg	  : std_logic_vector(15 downto 0);
+signal csn_sreg     : std_logic_vector(15 downto 0);
+begin
+
+	 
+	 
+sclk_net  <= sclk_gen(1);
+sclk		 <= sclk_net;
+
+process(rstn,clk)
+begin
+if rstn ='0' then
+	smpclk_reg	<= '0';
+	sclk_gen		<= "0000";
+	load        <= '0';
+elsif clk'event and clk = '1' then 
+	smpclk_reg	<= smpclk;
+	sclk_gen  <= std_logic_vector(unsigned(sclk_gen) + 1);
+	if smpclk_reg = '0' and smpclk = '1' then
+		load <= '1';
+	else
+		load <= '0';
+	end if;
+	
+end if;
+end process;
+
+process(load,sclk_net)
+begin
+if load ='1' then
+	data_sreg	  <= smp_in;
+   csn_sreg      <= (others => '0');
+elsif sclk_net'event and sclk_net = '1' then 
+	data_sreg   <= data_sreg(14 downto 0) & '1';
+	csn_sreg    <= csn_sreg(14 downto 0) & '1';
+end if;
+end process;
+
+process(rstn,sclk_net)
+begin
+if rstn ='0' then
+	sdo	  <= '1';
+   csn     <= '1';
+elsif sclk_net'event and sclk_net = '0' then 
+	sdo <= data_sreg(15);
+	csn <= csn_sreg(15);
+end if;
+end process;
+
+
+
+end Behavioral;
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/designs/BeagleSynth/GPMC_ASYNC_SLAVE.vhd b/designs/BeagleSynth/GPMC_ASYNC_SLAVE.vhd
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/GPMC_ASYNC_SLAVE.vhd
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    15:20:11 12/08/2013 
+-- Design Name: 
+-- Module Name:    GPMC_SLAVE - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+library grlib, techmap;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library lpp;
+use lpp.general_purpose.all;
+
+entity GPMC_ASYNC_SLAVE is
+  generic (
+    memtech       : integer := 0;
+    padtech       : integer := 0
+  );
+    Port ( 
+	     clk           : in  STD_LOGIC;
+        reset         : in  STD_LOGIC;
+        GPMC_AD       : inout std_logic_vector(15 downto 0);
+        GPMC_A        : in  std_logic_vector(19 downto 0);
+        GPMC_CLK_MUX0 : in  std_ulogic;
+        GPMC_WEN      : in  std_ulogic;   
+        GPMC_OEN_REN  : in  std_ulogic;  
+        GPMC_ADVN_ALE : in  std_ulogic;   
+        GPMC_CSN      : in  std_ulogic_vector(2 downto 0);
+        GPMC_BE0N_CLE : in  std_ulogic; 
+        GPMC_BE1N     : in  std_ulogic;
+        GPMC_WAIT0    : out std_ulogic;
+        GPMC_WPN      : in  std_ulogic
+		  );
+end GPMC_ASYNC_SLAVE;
+
+architecture Behavioral of GPMC_ASYNC_SLAVE is
+constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
+
+signal data_out :std_logic_vector(15 downto 0);
+signal data_in  :std_logic_vector(15 downto 0);
+
+type    RAMarrayT   is array (0 to 255) of std_logic_vector(15 downto 0);
+signal  RAMarray           :   RAMarrayT:=(others => VectInit);
+signal  ramindex         : integer range 0 to 255;
+
+begin
+
+data_pad : iopadv generic map (tech=> padtech,width => 16)
+port map (
+   pad => GPMC_AD(15 downto 0),
+   o   => data_in(15 downto 0),
+   en  => GPMC_OEN_REN,
+   i   => data_out(15 downto 0)
+);
+
+GPMC_WAIT0  <=  '1';
+
+data_out <= RAMarray(ramindex);
+
+process(reset,GPMC_CLK_MUX0)
+begin
+if reset = '0' then
+	--data_out	<= (others => '0');
+	ramindex <= 0;
+elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
+	if GPMC_ADVN_ALE = '0' then
+		ramindex <= to_integer(unsigned(GPMC_A(19 downto 1)));
+	end if;
+
+	if GPMC_WEN = '0' then 
+		RAMarray(ramindex) <= data_in; 
+	end if;
+end if;
+end process;
+
+end Behavioral;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/designs/BeagleSynth/GPMC_SLAVE.vhd b/designs/BeagleSynth/GPMC_SLAVE.vhd
--- a/designs/BeagleSynth/GPMC_SLAVE.vhd
+++ b/designs/BeagleSynth/GPMC_SLAVE.vhd
@@ -35,51 +35,73 @@ entity GPMC_SLAVE is
     Port ( 
 	     clk           : in  STD_LOGIC;
         reset         : in  STD_LOGIC;
+		  STATUS        : in  STD_LOGIC_VECTOR(15 downto 0);
+		  DATA          : out STD_LOGIC_VECTOR(15 downto 0);
+		  ADDRESS       : out std_logic_vector(19 downto 0);
+		  WEN	          : out STD_LOGIC;
         GPMC_AD       : inout std_logic_vector(15 downto 0);
         GPMC_A        : in  std_logic_vector(19 downto 0);
-        GPMC_CLK_MUX0 : in  std_ulogic;
-        GPMC_WEN      : in  std_ulogic;   
-        GPMC_OEN_REN  : in  std_ulogic;  
-        GPMC_ADVN_ALE : in  std_ulogic;   
-        GPMC_CSN      : in  std_ulogic_vector(2 downto 0);
-        GPMC_BE0N_CLE : in  std_ulogic; 
-        GPMC_BE1N     : in  std_ulogic;
-        GPMC_WAIT0    : in  std_ulogic;
-        GPMC_WPN      : in  std_ulogic
+        GPMC_CLK      : in  std_logic;
+        GPMC_WEN      : in  std_logic;   
+        GPMC_OEN_REN  : in  std_logic;  
+        GPMC_ADVN_ALE : in  std_logic;   
+        GPMC_CSN      : in  std_logic_vector(2 downto 0);
+        GPMC_BE0N_CLE : in  std_logic; 
+        GPMC_BE1N     : in  std_logic;
+        GPMC_WAIT0    : out std_logic;
+        GPMC_WPN      : in  std_logic
 		  );
 end GPMC_SLAVE;
 
 architecture Behavioral of GPMC_SLAVE is
-constant VectInit : std_logic_vector(15 downto 0):=(others => '0');
+
+signal data_out : std_logic_vector(15 downto 0) := (others => '0');
+signal data_in  : std_logic_vector(15 downto 0) := (others => '0');
 
-signal data_out :std_logic_vector(15 downto 0);
-signal data_in  :std_logic_vector(15 downto 0);
+signal GPMC_CLK_reg : std_logic_vector(3 downto 0)  := (others => '0');
+signal data_r       : std_logic_vector(15 downto 0) := (others => '0');
 
-type    RAMarrayT   is array (0 to 255) of std_logic_vector(15 downto 0);
-signal  RAMarray           :   RAMarrayT:=(others => VectInit);
-signal  ramindex         : integer range 0 to 255;
+
+signal outen       : std_logic := '0';
+
 
 begin
 
+outen    <= GPMC_OEN_REN or GPMC_CSN(0);
+data_out <= STATUS;
+
 data_pad : iopadv generic map (tech=> padtech,width => 16)
 port map (
    pad => GPMC_AD(15 downto 0),
    o   => data_in(15 downto 0),
-   en  => GPMC_OEN_REN,
+   en  => outen,
    i   => data_out(15 downto 0)
 );
 
-process(reset,GPMC_CLK_MUX0)
+GPMC_WAIT0  <=  '1';
+
+
+
+process(reset,clk)
 begin
 if reset = '0' then
-	data_out	<= (others => '0');
-	ramindex <= 0;
-elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then
-	ramindex <= to_integer(unsigned(GPMC_A));
-	data_out <= RAMarray(ramindex);
-	if GPMC_WEN = '0' then 
-		RAMarray(ramindex) <= data_in; 
+	WEN	<= '1';
+	GPMC_CLK_reg <= "0000";
+	ADDRESS		<=  (others => '0');
+elsif clk'event and clk = '1' then
+	GPMC_CLK_reg(0) <= GPMC_CLK;
+	if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then
+	   if GPMC_WEN = '0' then
+	      WEN  <= '0';
+		   DATA <= data_in;
+	    end if;
+	    if GPMC_ADVN_ALE = '0' then
+          ADDRESS  <= GPMC_A;
+	    end if;		
+	else
+	    WEN <= '1';
 	end if;
+	
 end if;
 end process;
 
diff --git a/designs/BeagleSynth/Makefile b/designs/BeagleSynth/Makefile
--- a/designs/BeagleSynth/Makefile
+++ b/designs/BeagleSynth/Makefile
@@ -17,7 +17,7 @@ VHDLOPTSYNFILES=
 
 
 VHDLSYNFILES= \
-	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd
+	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd beagleSigGen.vhd GPMC_ASYNC_SLAVE.vhd
 #VHDLSIMFILES=testbench.vhd
 #SIMTOP=testbench
 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
diff --git a/designs/BeagleSynth/beagleSigGen.vhd b/designs/BeagleSynth/beagleSigGen.vhd
new file mode 100644
--- /dev/null
+++ b/designs/BeagleSynth/beagleSigGen.vhd
@@ -0,0 +1,338 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.numeric_std.all;
+library grlib, techmap;
+use grlib.amba.all;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use techmap.gencomp.all;
+use techmap.allclkgen.all;
+library gaisler;
+use gaisler.memctrl.all;
+use gaisler.leon3.all;
+use gaisler.uart.all;
+use gaisler.misc.all;
+library esa;
+use esa.memoryctrl.all;
+--use gaisler.sim.all;
+library lpp;
+use lpp.lpp_ad_conv.all;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+use lpp.general_purpose.all;
+use lpp.lpp_cna.all;
+use lpp.lpp_memory.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+use work.config.all;
+
+entity beagleSigGen is
+	generic (
+			memtech       : integer := CFG_MEMTECH;
+			padtech       : integer := CFG_PADTECH;
+			clktech       : integer := CFG_CLKTECH
+			);
+    Port ( 
+	        clk          : in  STD_LOGIC;
+           rstn         : in  STD_LOGIC;
+			  CAL_IN_SCK   : out std_ulogic;
+			  DAC_nCS      : out std_ulogic;
+           DAC_SDI      : out std_logic_vector(7 downto 0);
+			  address      : in  std_logic_vector(2 downto 0);
+			  DATA   	   : in  std_logic_vector(15 downto 0);
+			  REN_debug  	: out std_logic;
+			  WEN				: in  std_logic;
+			  FIFO_FULL	   : out std_logic_vector(7 downto 0);
+			  FIFO_EMPTY	: out std_logic_vector(7 downto 0)
+			  );
+end beagleSigGen;
+
+architecture Behavioral of beagleSigGen is
+
+
+signal FIFO_FULL_net	    : std_logic_vector(7 downto 0);
+signal FIFO_EMPTY_net 	 : std_logic_vector(7 downto 0);
+signal FIFO_WEN 	 : std_logic_vector(7 downto 0);
+signal FIFO_REN 	 : std_logic;
+
+
+subtype TAB16  is std_logic_vector(15 downto 0);
+type FIFOout_t is array(7 downto 0) of TAB16;
+
+signal FIFO_out    : FIFOout_t;
+signal DAC_DATA    : CNA_16bit_T(7 downto 0,15 downto 0);
+signal smpclk      : std_logic;
+signal smpclk_reg  : std_logic;
+signal DAC_SDO	    : std_logic;
+signal DATA_reg    : std_logic_vector(15 downto 0);
+
+begin
+
+
+
+FIFO_FULL	 <= FIFO_FULL_net;
+FIFO_EMPTY	 <= FIFO_EMPTY_net;
+
+--fron_fifo1: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(0),
+--		 empty   => FIFO_EMPTY_net(0),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(0),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(0),
+--		 waddr   => open
+--	);
+--fron_fifo2: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(1),
+--		 empty   => FIFO_EMPTY_net(1),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(1),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(1),
+--		 waddr   => open
+--	);
+--fron_fifo3: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(2),
+--		 empty   => FIFO_EMPTY_net(2),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(2),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(2),
+--		 waddr   => open
+--	);
+--fron_fifo4: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(3),
+--		 empty   => FIFO_EMPTY_net(3),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(3),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(3),
+--		 waddr   => open
+--	);
+--fron_fifo5: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(4),
+--		 empty   => FIFO_EMPTY_net(4),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(4),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(4),
+--		 waddr   => open
+--	);
+--fron_fifo6: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(5),
+--		 empty   => FIFO_EMPTY_net(5),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(5),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(5),
+--		 waddr   => open
+--	);
+--fron_fifo7: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(6),
+--		 empty   => FIFO_EMPTY_net(6),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(6),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(6),
+--		 waddr   => open
+--	);
+--fron_fifo8: lpp_fifo
+--	generic map(
+--		 tech          =>  memtech,
+--		 Mem_use       =>  1, --use RAM not CELS
+--		 DataSz        =>  16,
+--		 AddrSz        =>  8
+--		 )
+--	port map(
+--		 rstn    => rstn,
+--		 ReUse   => '0',
+--		 rclk    => clk,
+--		 ren     => FIFO_REN,
+--		 rdata   => FIFO_out(7),
+--		 empty   => FIFO_EMPTY_net(7),
+--		 raddr   => open,
+--		 wclk    => clk,
+--		 wen     => FIFO_WEN(7),
+--		 wdata   => DATA_reg,
+--		 full    => FIFO_FULL_net(7),
+--		 waddr   => open
+--	);
+
+REN_debug	<= FIFO_REN;
+
+process(clk,rstn)
+begin
+	if rstn = '0' then
+		DATA_reg  <= (others => '0');
+		FIFO_WEN  <= (others => '0');
+	elsif clk'event and clk = '1' then
+		if WEN = '0' then
+			DATA_reg <= DATA;
+			case address is 
+				when "000"=>
+					FIFO_WEN <= "11111110";
+					FIFO_out(0) <= DATA;
+				when "001"=>
+				   FIFO_WEN <= "11111101";
+					FIFO_out(1) <= DATA;
+				when "010"=>
+				   FIFO_WEN <= "11111011";
+					FIFO_out(2) <= DATA;
+				when "011"=>
+				   FIFO_WEN <= "11110111";
+					FIFO_out(3) <= DATA;
+				when "100"=>
+				   FIFO_WEN <= "11101111";
+					FIFO_out(4) <= DATA;
+				when "101"=>
+				   FIFO_WEN <= "11011111";
+					FIFO_out(5) <= DATA;
+				when "110"=>
+				   FIFO_WEN <= "10111111";
+					FIFO_out(6) <= DATA;
+				when "111"=>
+ 				   FIFO_WEN <= "01111111";
+					FIFO_out(7) <= DATA;
+				when others =>
+				   FIFO_WEN <= "11111111";
+			end case;
+		end if;
+	end if;
+end process;
+
+all_bits: FOR I in 15 downto 0 GENERATE
+  all_chans: FOR J in 7 downto 0 GENERATE
+	  DAC_DATA(J,I) <= FIFO_out(J)(I);
+  end GENERATE;
+end GENERATE;
+
+
+
+process(clk,rstn)
+begin
+	if rstn = '0' then
+		FIFO_REN	<= '1';
+		smpclk_reg <= '0';
+	elsif clk'event and clk = '1' then
+		smpclk_reg <= smpclk;
+		if smpclk = '1' and smpclk_reg = '0' then
+			FIFO_REN <= '0';
+		else 
+			FIFO_REN <= '1';
+		end if;
+	end if;
+end process;
+
+
+DAC0 :  DAC8581 
+    generic map(150,8)
+    Port map( 
+	        clk =>      clk,
+           rstn =>     rstn,
+           smpclk =>   smpclk,
+           sclk =>     CAL_IN_SCK,
+           csn =>		  DAC_nCS,
+           sdo =>      DAC_SDI,
+           smp_in =>   DAC_DATA
+			  );
+
+	 
+
+smpclk0: Clk_divider 
+    GENERIC map(OSC_freqHz  => 150000000,
+            TargetFreq_Hz   => 32000)
+    PORT map( 
+			  clk          =>  clk,
+           reset        =>  rstn,
+           clk_divided  =>  smpclk 
+			  );
+
+
+end Behavioral;
+
diff --git a/designs/BeagleSynth/config.vhd b/designs/BeagleSynth/config.vhd
--- a/designs/BeagleSynth/config.vhd
+++ b/designs/BeagleSynth/config.vhd
@@ -24,7 +24,7 @@ package config is
 --  ON Spartan 6 VCO freq must be between 400MHz and 1GHz
   constant CFG_CLKTECH : integer := spartan6;
   constant CFG_CLKMUL : integer := (6);
-  constant CFG_CLKDIV : integer := (12);
+  constant CFG_CLKDIV : integer := (4);
   constant CFG_OCLKDIV : integer := (1);
   constant CFG_PCIDLL : integer := 0;
   constant CFG_PCISYSCLK: integer := 0;
diff --git a/lib/lpp/lpp_cna/DAC8581.vhd b/lib/lpp/lpp_cna/DAC8581.vhd
--- a/lib/lpp/lpp_cna/DAC8581.vhd
+++ b/lib/lpp/lpp_cna/DAC8581.vhd
@@ -53,14 +53,17 @@ signal smpclk_reg   : std_logic;
 signal sclk_gen     : std_logic_vector(3 downto 0);
 signal sclk_net     : std_logic;
 signal load         : std_logic;
+signal load_reg     : std_logic;
 signal data_sreg	  : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0);
-signal csn_sreg     : std_logic_vector(15 downto 0);
 
+signal csn_sreg     : std_logic;
+signal shift_counter : integer range 0 to 16;
+signal sdo_int : STD_LOGIC_VECTOR (ChanCount-1 downto 0);
 begin
 
 	 
 	 
-sclk_net  <= sclk_gen(1);
+sclk_net  <= sclk_gen(2);
 sclk		 <= sclk_net;
 
 process(rstn,clk)
@@ -84,17 +87,37 @@ end process;
 process(load,sclk_net)
 begin
 if load ='1' then
-	data_sreg   <= smp_in;
-   csn_sreg      <= (others => '0');
-	
-elsif sclk_net'event and sclk_net = '1' then 
-   all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
-		all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
-			data_sreg(I,J+1)   <= data_sreg(I,J);
-		END LOOP all_bits0;
-			data_sreg(I,0)   <= '1';
-   END LOOP all_chanel0;
-	csn_sreg    <= csn_sreg(14 downto 0) & '1';
+	load_reg     <= '1';
+elsif sclk_net'event and sclk_net = '1' then
+   load_reg     <= '0';
+end if;
+end process;
+
+process(rstn,sclk_net)
+begin
+if rstn ='0' then
+	data_sreg     <= smp_in;
+   csn_sreg      <= '1';
+elsif sclk_net'event and sclk_net = '1' then
+   if load_reg = '1' then
+		data_sreg     <= smp_in;
+      shift_counter <= 0;
+		csn_sreg      <= '1';
+   else
+		all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
+			all_bits0 : FOR J IN 14 DOWNTO 0 LOOP
+				data_sreg(I,J+1)   <= data_sreg(I,J);
+			END LOOP all_bits0;
+				data_sreg(I,0)   <= '1';
+		END LOOP all_chanel0;
+		if shift_counter /= 16 then
+			shift_counter    <= shift_counter + 1;
+			csn_sreg         <= '0';
+		else 
+			csn_sreg	        <= '1';
+		end if;
+		
+   end if;
 end if;
 end process;
 
@@ -102,14 +125,16 @@ process(rstn,sclk_net)
 begin
 if rstn ='0' then
 	all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
-      sdo(I) <= '1';
+      sdo_int(I) <= '1';
+		sdo(I) <= '1';
    END LOOP all_chanel2;
    csn     <= '1';
 elsif sclk_net'event and sclk_net = '0' then 
    all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP
-      sdo(I) <= data_sreg(I,15);
+      sdo_int(I) <= data_sreg(I,15);
    END LOOP all_chanel1;
-	csn <= csn_sreg(15);
+	sdo <= sdo_int;
+	csn <= csn_sreg;
 end if;
 end process;
 
diff --git a/scripts/linklibs.sh b/scripts/linklibs.sh
--- a/scripts/linklibs.sh
+++ b/scripts/linklibs.sh
@@ -43,6 +43,11 @@ if [ -d "$GRLIBPATH" ]; then
 				else
 					echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
 				fi
+				if(grep -q $LPP_PATCHPATH/lib/staging $1/lib/libs.txt); then
+					echo "No need to Patch $1/lib/libs.txt..."
+				else
+					echo $LPP_PATCHPATH/lib/staging >>$1/lib/libs.txt
+				fi
 				echo
 				echo
 				echo