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1 | library ieee; | |
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2 | use ieee.std_logic_1164.all; | |
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3 | use IEEE.numeric_std.all; | |
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4 | library grlib, techmap; | |
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5 | use grlib.amba.all; | |
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6 | use grlib.amba.all; | |
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7 | use grlib.stdlib.all; | |
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8 | use techmap.gencomp.all; | |
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9 | use techmap.allclkgen.all; | |
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10 | library gaisler; | |
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11 | use gaisler.memctrl.all; | |
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12 | use gaisler.leon3.all; | |
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13 | use gaisler.uart.all; | |
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14 | use gaisler.misc.all; | |
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15 | library esa; | |
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16 | use esa.memoryctrl.all; | |
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17 | --use gaisler.sim.all; | |
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18 | library lpp; | |
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19 | use lpp.lpp_ad_conv.all; | |
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20 | use lpp.lpp_amba.all; | |
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21 | use lpp.apb_devices_list.all; | |
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22 | use lpp.general_purpose.all; | |
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23 | ||
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24 | Library UNISIM; | |
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25 | use UNISIM.vcomponents.all; | |
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26 | ||
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27 | ||
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28 | use work.config.all; | |
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29 | --================================================================== | |
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30 | -- | |
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31 | -- | |
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32 | -- FPGA FREQ = 100MHz | |
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33 | -- | |
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34 | -- | |
|
35 | --================================================================== | |
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36 | ||
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37 | entity BeagleSynth_MCTRL is | |
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38 | generic ( | |
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39 | fabtech : integer := CFG_FABTECH; | |
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40 | memtech : integer := CFG_MEMTECH; | |
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41 | padtech : integer := CFG_PADTECH; | |
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42 | clktech : integer := CFG_CLKTECH | |
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43 | ); | |
|
44 | port ( | |
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45 | reset : in std_ulogic; | |
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46 | clk : in std_ulogic; | |
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47 | DAC_nCLR : out std_ulogic; | |
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48 | DAC_nCS : out std_ulogic; | |
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49 | CAL_IN_SCK : out std_ulogic; | |
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50 | DAC_SDI : out std_ulogic_vector(7 downto 0); | |
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51 | TXD : out std_ulogic; | |
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52 | RXD : in std_ulogic; | |
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53 | urxd1 : in std_ulogic; | |
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54 | utxd1 : out std_ulogic; | |
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55 | LED : out std_ulogic_vector(2 downto 0); | |
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56 | -------------------------------------------------------- | |
|
57 | ---- SDRAM | |
|
58 | ---- For SDRAM config have a look on leon3-altera-ep1c20 | |
|
59 | ---- design from GRLIB, the IS42S32400E is similar to | |
|
60 | ---- MT48LC4M32B2. | |
|
61 | -------------------------------------------------------- | |
|
62 | sdcke : out std_logic; -- clk en | |
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63 | sdcsn : out std_logic; -- chip sel | |
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64 | sdwen : out std_logic; -- write en | |
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65 | sdrasn : out std_logic; -- row addr stb | |
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66 | sdcasn : out std_logic; -- col addr stb | |
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67 | sddqm : out std_logic_vector (3 downto 0); -- data i/o mask | |
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68 | sdclk : out std_logic; -- sdram clk output | |
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69 | sdba : out std_logic_vector (1 downto 0); -- bank select address | |
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70 | Address : out std_logic_vector(11 downto 0); -- sdram address | |
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71 | Data : inout std_logic_vector(31 downto 0) -- optional sdram data | |
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72 | ); | |
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73 | end; | |
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74 | ||
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75 | architecture rtl of BeagleSynth_MCTRL is | |
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76 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ | |
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77 | CFG_GRETH+CFG_AHB_JTAG; | |
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78 | constant maxahbm : integer := maxahbmsp; | |
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79 | constant IOAEN : integer := CFG_CAN; | |
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80 | constant boardfreq : integer := 100000; | |
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81 | ||
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82 | signal clk2x : std_ulogic; | |
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83 | signal lclk : std_ulogic; | |
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84 | signal clkm : std_ulogic; | |
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85 | signal rstn : std_ulogic; | |
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86 | signal rst : std_ulogic; | |
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87 | signal rstraw : std_ulogic; | |
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88 | signal pciclk : std_ulogic; | |
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89 | signal sdclkl : std_ulogic; | |
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90 | signal sdclkl_DDR2 : std_ulogic; | |
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91 | signal cgi : clkgen_in_type; | |
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92 | signal cgo : clkgen_out_type; | |
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93 | ||
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94 | --- AHB / APB | |
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95 | signal apbi : apb_slv_in_type; | |
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96 | signal apbo : apb_slv_out_vector := (others => apb_none); | |
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97 | signal ahbsi : ahb_slv_in_type; | |
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98 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | |
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99 | signal ahbmi : ahb_mst_in_type; | |
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100 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | |
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101 | ||
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102 | --- MEM CTRLR | |
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103 | signal memi : memory_in_type; | |
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104 | signal memo : memory_out_type; | |
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105 | signal wpo : wprot_out_type; | |
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106 | signal sdi : sdctrl_in_type; | |
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107 | signal sdo : sdram_out_type; | |
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108 | ||
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109 | --UART | |
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110 | signal ahbuarti : uart_in_type; | |
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111 | signal ahbuarto : uart_out_type; | |
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112 | signal apbuarti : uart_in_type; | |
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113 | signal apbuarto : uart_out_type; | |
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114 | ||
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115 | signal led2int : std_logic; | |
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116 | ||
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117 | begin | |
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118 | ||
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119 | DAC_nCLR <= '1'; | |
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120 | DAC_nCS <= '1'; | |
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121 | CAL_IN_SCK <= '1'; | |
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122 | DAC_SDI <= (others =>'1'); | |
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123 | ||
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124 | resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); | |
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125 | rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); | |
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126 | --rstn <= reset; | |
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127 | --lclk <= clk; | |
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128 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); | |
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129 | ||
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130 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; | |
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131 | clkgen0 : clkgen -- clock generator | |
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132 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) | |
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133 | port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); | |
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134 | ||
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135 | -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2); | |
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136 | --sdclk <= sdclkl; | |
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137 | sdclk <= sdclkl_DDR2; | |
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138 | ||
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139 | LED(1) <= not cgo.clklock; | |
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140 | LED(0) <= cgo.clklock; | |
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141 | ||
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142 | ODDR2_inst : ODDR2 | |
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143 | generic map( | |
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144 | DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" | |
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145 | INIT => '0', -- Sets initial state of the Q output to '0' or '1' | |
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146 | SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset | |
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147 | port map ( | |
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148 | Q => sdclkl_DDR2, -- 1-bit output data | |
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149 | C0 => sdclkl, -- 1-bit clock input | |
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150 | C1 => not sdclkl, -- 1-bit clock input | |
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151 | CE => '1', -- 1-bit clock enable input | |
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152 | D0 => '1', -- 1-bit data input (associated with C0) | |
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153 | D1 => '0', -- 1-bit data input (associated with C1) | |
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154 | R => '0', -- 1-bit reset input | |
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155 | S => '0' -- 1-bit set input | |
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156 | ); | |
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157 | ||
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158 | ---------------------------------------------------------------------- | |
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159 | --- AHB CONTROLLER ------------------------------------------------- | |
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160 | ---------------------------------------------------------------------- | |
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161 | ||
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162 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
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163 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
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164 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
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165 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
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166 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
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167 | ||
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168 | ---------------------------------------------------------------------- | |
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169 | --- AHB UART ------------------------------------------------------- | |
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170 | ---------------------------------------------------------------------- | |
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171 | ||
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172 | dcomgen : if CFG_AHB_UART = 1 generate | |
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173 | dcom0: ahbuart -- Debug UART | |
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174 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | |
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175 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | |
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176 | ahbuarti.rxd <= RXD; | |
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177 | TXD <= ahbuarto.txd; | |
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178 | end generate; | |
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179 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | |
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180 | ||
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181 | ---------------------------------------------------------------------- | |
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182 | --- APB Bridge ----------------------------------------------------- | |
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183 | ---------------------------------------------------------------------- | |
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184 | ||
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185 | apb0 : apbctrl -- AHB/APB bridge | |
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186 | generic map (hindex => 1, haddr => CFG_APBADDR) | |
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187 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | |
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188 | ||
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189 | ---------------------------------------------------------------------- | |
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190 | --- APB UART ------------------------------------------------------- | |
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191 | ---------------------------------------------------------------------- | |
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192 | ||
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193 | ua1 : if CFG_UART1_ENABLE /= 0 generate | |
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194 | uart1 : apbuart -- UART 1 | |
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195 | generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, | |
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196 | fifosize => CFG_UART1_FIFO) | |
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197 | port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
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198 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | |
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199 | apbuarti.ctsn <= '0'; | |
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200 | end generate; | |
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201 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | |
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202 | ||
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203 | ||
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204 | ||
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205 | ||
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206 | --div0: Clk_divider | |
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207 | -- generic map( 100000000,1) | |
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208 | -- Port map( clkm,rstn,LED(2)); | |
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209 | ||
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210 | LED(2) <= led2int; | |
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211 | ||
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212 | process(clkm,rstn) | |
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213 | begin | |
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214 | if rstn = '0' then | |
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215 | led2int <= '0'; | |
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216 | elsif clkm'event and clkm='1' then | |
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217 | led2int <= not led2int; | |
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218 | end if; | |
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219 | end process; | |
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220 | ||
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221 | ||
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222 | ||
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223 | ||
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224 | memi.writen <= '1'; | |
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225 | memi.wrn <= "1111"; | |
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226 | memi.bwidth <= "00"; | |
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227 | memi.brdyn <= '1'; | |
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228 | memi.bexcn <= '1'; | |
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229 | ||
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230 | mctrl0 : mctrl | |
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231 | generic map ( | |
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232 | hindex => 0, | |
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233 | pindex => 0, | |
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234 | paddr => 0, | |
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235 | srbanks => 1, | |
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236 | ram8 => 1, | |
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237 | ram16 => 1, | |
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238 | sden => 1, | |
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239 | invclk => 0, | |
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240 | sepbus => 0, | |
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241 | pageburst => 0) | |
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242 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
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243 | ||
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244 | -- SDRAM controller | |
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245 | sdwen_pad : outpad generic map (tech => padtech) | |
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246 | port map (sdwen, sdo.sdwen); | |
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247 | sdras_pad : outpad generic map (tech => padtech) | |
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248 | port map (sdrasn, sdo.rasn); | |
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249 | sdcas_pad : outpad generic map (tech => padtech) | |
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250 | port map (sdcasn, sdo.casn); | |
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251 | sddqm_pad : outpadv generic map (width =>4, tech => padtech) | |
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252 | port map (sddqm, sdo.dqm(3 downto 0)); | |
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253 | sdba <= "00"; | |
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254 | ||
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255 | sdcsn_pad : outpad generic map (tech => padtech) | |
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256 | port map (sdcsn, sdo.sdcsn(0)); | |
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257 | ||
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258 | sdcke_pad : outpad generic map (tech => padtech) | |
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259 | port map (sdcke, sdo.sdcke(0)); | |
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260 | ||
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261 | addr_pad : outpadv generic map (width => 12, tech => padtech) | |
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262 | port map (address, memo.address(11 downto 0)); | |
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263 | ||
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264 | bdr : for i in 0 to 3 generate | |
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265 | data_pad : iopadv generic map (tech => padtech, width => 8) | |
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266 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), | |
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267 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); | |
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268 | end generate; | |
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269 | ||
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270 | ||
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271 | end rtl; | |
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272 | ||
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273 | ||
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274 |
@@ -0,0 +1,117 | |||
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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
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3 | -- Engineer: | |
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4 | -- | |
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5 | -- Create Date: 15:26:29 12/07/2013 | |
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6 | -- Design Name: | |
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7 | -- Module Name: DAC8581 - Behavioral | |
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8 | -- Project Name: | |
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9 | -- Target Devices: | |
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10 | -- Tool versions: | |
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11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | use IEEE.numeric_std.all; | |
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23 | library LPP; | |
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24 | use lpp.lpp_cna.all; | |
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25 | ||
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26 | -- Uncomment the following library declaration if using | |
|
27 | -- arithmetic functions with Signed or Unsigned values | |
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28 | use IEEE.NUMERIC_STD.ALL; | |
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29 | ||
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30 | -- Uncomment the following library declaration if instantiating | |
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31 | -- any Xilinx primitives in this code. | |
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32 | --library UNISIM; | |
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33 | --use UNISIM.VComponents.all; | |
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34 | ||
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35 | entity DAC8581 is | |
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36 | generic(clkfreq : integer := 100); | |
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37 | Port ( clk : in STD_LOGIC; | |
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38 | rstn : in STD_LOGIC; | |
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39 | smpclk : in STD_LOGIC; | |
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40 | sclk : out STD_LOGIC; | |
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41 | csn : out STD_LOGIC; | |
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42 | sdo : out STD_LOGIC; | |
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43 | smp_in : in STD_LOGIC_VECTOR (15 downto 0) | |
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44 | ); | |
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45 | end DAC8581; | |
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46 | ||
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47 | architecture Behavioral of DAC8581 is | |
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48 | ||
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49 | ||
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50 | signal smpclk_reg : std_logic; | |
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51 | signal sclk_gen : std_logic_vector(3 downto 0); | |
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52 | signal sclk_net : std_logic; | |
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53 | signal load : std_logic; | |
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54 | signal data_sreg : std_logic_vector(15 downto 0); | |
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55 | signal csn_sreg : std_logic_vector(15 downto 0); | |
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56 | begin | |
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57 | ||
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58 | ||
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59 | ||
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60 | sclk_net <= sclk_gen(1); | |
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61 | sclk <= sclk_net; | |
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62 | ||
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63 | process(rstn,clk) | |
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64 | begin | |
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65 | if rstn ='0' then | |
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66 | smpclk_reg <= '0'; | |
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67 | sclk_gen <= "0000"; | |
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68 | load <= '0'; | |
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69 | elsif clk'event and clk = '1' then | |
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70 | smpclk_reg <= smpclk; | |
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71 | sclk_gen <= std_logic_vector(unsigned(sclk_gen) + 1); | |
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72 | if smpclk_reg = '0' and smpclk = '1' then | |
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73 | load <= '1'; | |
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74 | else | |
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75 | load <= '0'; | |
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76 | end if; | |
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77 | ||
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78 | end if; | |
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79 | end process; | |
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80 | ||
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81 | process(load,sclk_net) | |
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82 | begin | |
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83 | if load ='1' then | |
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84 | data_sreg <= smp_in; | |
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85 | csn_sreg <= (others => '0'); | |
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86 | elsif sclk_net'event and sclk_net = '1' then | |
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87 | data_sreg <= data_sreg(14 downto 0) & '1'; | |
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88 | csn_sreg <= csn_sreg(14 downto 0) & '1'; | |
|
89 | end if; | |
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90 | end process; | |
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91 | ||
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92 | process(rstn,sclk_net) | |
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93 | begin | |
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94 | if rstn ='0' then | |
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95 | sdo <= '1'; | |
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96 | csn <= '1'; | |
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97 | elsif sclk_net'event and sclk_net = '0' then | |
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98 | sdo <= data_sreg(15); | |
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99 | csn <= csn_sreg(15); | |
|
100 | end if; | |
|
101 | end process; | |
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102 | ||
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103 | ||
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104 | ||
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105 | end Behavioral; | |
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106 | ||
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107 | ||
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108 | ||
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109 | ||
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110 | ||
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111 | ||
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112 | ||
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113 | ||
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114 | ||
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115 | ||
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116 | ||
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117 |
@@ -0,0 +1,106 | |||
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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
|
3 | -- Engineer: | |
|
4 | -- | |
|
5 | -- Create Date: 15:20:11 12/08/2013 | |
|
6 | -- Design Name: | |
|
7 | -- Module Name: GPMC_SLAVE - Behavioral | |
|
8 | -- Project Name: | |
|
9 | -- Target Devices: | |
|
10 | -- Tool versions: | |
|
11 | -- Description: | |
|
12 | -- | |
|
13 | -- Dependencies: | |
|
14 | -- | |
|
15 | -- Revision: | |
|
16 | -- Revision 0.01 - File Created | |
|
17 | -- Additional Comments: | |
|
18 | -- | |
|
19 | ---------------------------------------------------------------------------------- | |
|
20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | use IEEE.numeric_std.all; | |
|
23 | library grlib, techmap; | |
|
24 | use grlib.stdlib.all; | |
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25 | use techmap.gencomp.all; | |
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26 | use techmap.allclkgen.all; | |
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27 | library lpp; | |
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28 | use lpp.general_purpose.all; | |
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29 | ||
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30 | entity GPMC_ASYNC_SLAVE is | |
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31 | generic ( | |
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32 | memtech : integer := 0; | |
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33 | padtech : integer := 0 | |
|
34 | ); | |
|
35 | Port ( | |
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36 | clk : in STD_LOGIC; | |
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37 | reset : in STD_LOGIC; | |
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38 | GPMC_AD : inout std_logic_vector(15 downto 0); | |
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39 | GPMC_A : in std_logic_vector(19 downto 0); | |
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40 | GPMC_CLK_MUX0 : in std_ulogic; | |
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41 | GPMC_WEN : in std_ulogic; | |
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42 | GPMC_OEN_REN : in std_ulogic; | |
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43 | GPMC_ADVN_ALE : in std_ulogic; | |
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44 | GPMC_CSN : in std_ulogic_vector(2 downto 0); | |
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45 | GPMC_BE0N_CLE : in std_ulogic; | |
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46 | GPMC_BE1N : in std_ulogic; | |
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47 | GPMC_WAIT0 : out std_ulogic; | |
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48 | GPMC_WPN : in std_ulogic | |
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49 | ); | |
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50 | end GPMC_ASYNC_SLAVE; | |
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51 | ||
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52 | architecture Behavioral of GPMC_ASYNC_SLAVE is | |
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53 | constant VectInit : std_logic_vector(15 downto 0):=(others => '0'); | |
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54 | ||
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55 | signal data_out :std_logic_vector(15 downto 0); | |
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56 | signal data_in :std_logic_vector(15 downto 0); | |
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57 | ||
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58 | type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0); | |
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59 | signal RAMarray : RAMarrayT:=(others => VectInit); | |
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60 | signal ramindex : integer range 0 to 255; | |
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61 | ||
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62 | begin | |
|
63 | ||
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64 | data_pad : iopadv generic map (tech=> padtech,width => 16) | |
|
65 | port map ( | |
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66 | pad => GPMC_AD(15 downto 0), | |
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67 | o => data_in(15 downto 0), | |
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68 | en => GPMC_OEN_REN, | |
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69 | i => data_out(15 downto 0) | |
|
70 | ); | |
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71 | ||
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72 | GPMC_WAIT0 <= '1'; | |
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73 | ||
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74 | data_out <= RAMarray(ramindex); | |
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75 | ||
|
76 | process(reset,GPMC_CLK_MUX0) | |
|
77 | begin | |
|
78 | if reset = '0' then | |
|
79 | --data_out <= (others => '0'); | |
|
80 | ramindex <= 0; | |
|
81 | elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then | |
|
82 | if GPMC_ADVN_ALE = '0' then | |
|
83 | ramindex <= to_integer(unsigned(GPMC_A(19 downto 1))); | |
|
84 | end if; | |
|
85 | ||
|
86 | if GPMC_WEN = '0' then | |
|
87 | RAMarray(ramindex) <= data_in; | |
|
88 | end if; | |
|
89 | end if; | |
|
90 | end process; | |
|
91 | ||
|
92 | end Behavioral; | |
|
93 | ||
|
94 | ||
|
95 | ||
|
96 | ||
|
97 | ||
|
98 | ||
|
99 | ||
|
100 | ||
|
101 | ||
|
102 | ||
|
103 | ||
|
104 | ||
|
105 | ||
|
106 |
@@ -0,0 +1,338 | |||
|
1 | library ieee; | |
|
2 | use ieee.std_logic_1164.all; | |
|
3 | use IEEE.numeric_std.all; | |
|
4 | library grlib, techmap; | |
|
5 | use grlib.amba.all; | |
|
6 | use grlib.amba.all; | |
|
7 | use grlib.stdlib.all; | |
|
8 | use techmap.gencomp.all; | |
|
9 | use techmap.allclkgen.all; | |
|
10 | library gaisler; | |
|
11 | use gaisler.memctrl.all; | |
|
12 | use gaisler.leon3.all; | |
|
13 | use gaisler.uart.all; | |
|
14 | use gaisler.misc.all; | |
|
15 | library esa; | |
|
16 | use esa.memoryctrl.all; | |
|
17 | --use gaisler.sim.all; | |
|
18 | library lpp; | |
|
19 | use lpp.lpp_ad_conv.all; | |
|
20 | use lpp.lpp_amba.all; | |
|
21 | use lpp.apb_devices_list.all; | |
|
22 | use lpp.general_purpose.all; | |
|
23 | use lpp.lpp_cna.all; | |
|
24 | use lpp.lpp_memory.all; | |
|
25 | ||
|
26 | Library UNISIM; | |
|
27 | use UNISIM.vcomponents.all; | |
|
28 | ||
|
29 | use work.config.all; | |
|
30 | ||
|
31 | entity beagleSigGen is | |
|
32 | generic ( | |
|
33 | memtech : integer := CFG_MEMTECH; | |
|
34 | padtech : integer := CFG_PADTECH; | |
|
35 | clktech : integer := CFG_CLKTECH | |
|
36 | ); | |
|
37 | Port ( | |
|
38 | clk : in STD_LOGIC; | |
|
39 | rstn : in STD_LOGIC; | |
|
40 | CAL_IN_SCK : out std_ulogic; | |
|
41 | DAC_nCS : out std_ulogic; | |
|
42 | DAC_SDI : out std_logic_vector(7 downto 0); | |
|
43 | address : in std_logic_vector(2 downto 0); | |
|
44 | DATA : in std_logic_vector(15 downto 0); | |
|
45 | REN_debug : out std_logic; | |
|
46 | WEN : in std_logic; | |
|
47 | FIFO_FULL : out std_logic_vector(7 downto 0); | |
|
48 | FIFO_EMPTY : out std_logic_vector(7 downto 0) | |
|
49 | ); | |
|
50 | end beagleSigGen; | |
|
51 | ||
|
52 | architecture Behavioral of beagleSigGen is | |
|
53 | ||
|
54 | ||
|
55 | signal FIFO_FULL_net : std_logic_vector(7 downto 0); | |
|
56 | signal FIFO_EMPTY_net : std_logic_vector(7 downto 0); | |
|
57 | signal FIFO_WEN : std_logic_vector(7 downto 0); | |
|
58 | signal FIFO_REN : std_logic; | |
|
59 | ||
|
60 | ||
|
61 | subtype TAB16 is std_logic_vector(15 downto 0); | |
|
62 | type FIFOout_t is array(7 downto 0) of TAB16; | |
|
63 | ||
|
64 | signal FIFO_out : FIFOout_t; | |
|
65 | signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); | |
|
66 | signal smpclk : std_logic; | |
|
67 | signal smpclk_reg : std_logic; | |
|
68 | signal DAC_SDO : std_logic; | |
|
69 | signal DATA_reg : std_logic_vector(15 downto 0); | |
|
70 | ||
|
71 | begin | |
|
72 | ||
|
73 | ||
|
74 | ||
|
75 | FIFO_FULL <= FIFO_FULL_net; | |
|
76 | FIFO_EMPTY <= FIFO_EMPTY_net; | |
|
77 | ||
|
78 | --fron_fifo1: lpp_fifo | |
|
79 | -- generic map( | |
|
80 | -- tech => memtech, | |
|
81 | -- Mem_use => 1, --use RAM not CELS | |
|
82 | -- DataSz => 16, | |
|
83 | -- AddrSz => 8 | |
|
84 | -- ) | |
|
85 | -- port map( | |
|
86 | -- rstn => rstn, | |
|
87 | -- ReUse => '0', | |
|
88 | -- rclk => clk, | |
|
89 | -- ren => FIFO_REN, | |
|
90 | -- rdata => FIFO_out(0), | |
|
91 | -- empty => FIFO_EMPTY_net(0), | |
|
92 | -- raddr => open, | |
|
93 | -- wclk => clk, | |
|
94 | -- wen => FIFO_WEN(0), | |
|
95 | -- wdata => DATA_reg, | |
|
96 | -- full => FIFO_FULL_net(0), | |
|
97 | -- waddr => open | |
|
98 | -- ); | |
|
99 | --fron_fifo2: lpp_fifo | |
|
100 | -- generic map( | |
|
101 | -- tech => memtech, | |
|
102 | -- Mem_use => 1, --use RAM not CELS | |
|
103 | -- DataSz => 16, | |
|
104 | -- AddrSz => 8 | |
|
105 | -- ) | |
|
106 | -- port map( | |
|
107 | -- rstn => rstn, | |
|
108 | -- ReUse => '0', | |
|
109 | -- rclk => clk, | |
|
110 | -- ren => FIFO_REN, | |
|
111 | -- rdata => FIFO_out(1), | |
|
112 | -- empty => FIFO_EMPTY_net(1), | |
|
113 | -- raddr => open, | |
|
114 | -- wclk => clk, | |
|
115 | -- wen => FIFO_WEN(1), | |
|
116 | -- wdata => DATA_reg, | |
|
117 | -- full => FIFO_FULL_net(1), | |
|
118 | -- waddr => open | |
|
119 | -- ); | |
|
120 | --fron_fifo3: lpp_fifo | |
|
121 | -- generic map( | |
|
122 | -- tech => memtech, | |
|
123 | -- Mem_use => 1, --use RAM not CELS | |
|
124 | -- DataSz => 16, | |
|
125 | -- AddrSz => 8 | |
|
126 | -- ) | |
|
127 | -- port map( | |
|
128 | -- rstn => rstn, | |
|
129 | -- ReUse => '0', | |
|
130 | -- rclk => clk, | |
|
131 | -- ren => FIFO_REN, | |
|
132 | -- rdata => FIFO_out(2), | |
|
133 | -- empty => FIFO_EMPTY_net(2), | |
|
134 | -- raddr => open, | |
|
135 | -- wclk => clk, | |
|
136 | -- wen => FIFO_WEN(2), | |
|
137 | -- wdata => DATA_reg, | |
|
138 | -- full => FIFO_FULL_net(2), | |
|
139 | -- waddr => open | |
|
140 | -- ); | |
|
141 | --fron_fifo4: lpp_fifo | |
|
142 | -- generic map( | |
|
143 | -- tech => memtech, | |
|
144 | -- Mem_use => 1, --use RAM not CELS | |
|
145 | -- DataSz => 16, | |
|
146 | -- AddrSz => 8 | |
|
147 | -- ) | |
|
148 | -- port map( | |
|
149 | -- rstn => rstn, | |
|
150 | -- ReUse => '0', | |
|
151 | -- rclk => clk, | |
|
152 | -- ren => FIFO_REN, | |
|
153 | -- rdata => FIFO_out(3), | |
|
154 | -- empty => FIFO_EMPTY_net(3), | |
|
155 | -- raddr => open, | |
|
156 | -- wclk => clk, | |
|
157 | -- wen => FIFO_WEN(3), | |
|
158 | -- wdata => DATA_reg, | |
|
159 | -- full => FIFO_FULL_net(3), | |
|
160 | -- waddr => open | |
|
161 | -- ); | |
|
162 | --fron_fifo5: lpp_fifo | |
|
163 | -- generic map( | |
|
164 | -- tech => memtech, | |
|
165 | -- Mem_use => 1, --use RAM not CELS | |
|
166 | -- DataSz => 16, | |
|
167 | -- AddrSz => 8 | |
|
168 | -- ) | |
|
169 | -- port map( | |
|
170 | -- rstn => rstn, | |
|
171 | -- ReUse => '0', | |
|
172 | -- rclk => clk, | |
|
173 | -- ren => FIFO_REN, | |
|
174 | -- rdata => FIFO_out(4), | |
|
175 | -- empty => FIFO_EMPTY_net(4), | |
|
176 | -- raddr => open, | |
|
177 | -- wclk => clk, | |
|
178 | -- wen => FIFO_WEN(4), | |
|
179 | -- wdata => DATA_reg, | |
|
180 | -- full => FIFO_FULL_net(4), | |
|
181 | -- waddr => open | |
|
182 | -- ); | |
|
183 | --fron_fifo6: lpp_fifo | |
|
184 | -- generic map( | |
|
185 | -- tech => memtech, | |
|
186 | -- Mem_use => 1, --use RAM not CELS | |
|
187 | -- DataSz => 16, | |
|
188 | -- AddrSz => 8 | |
|
189 | -- ) | |
|
190 | -- port map( | |
|
191 | -- rstn => rstn, | |
|
192 | -- ReUse => '0', | |
|
193 | -- rclk => clk, | |
|
194 | -- ren => FIFO_REN, | |
|
195 | -- rdata => FIFO_out(5), | |
|
196 | -- empty => FIFO_EMPTY_net(5), | |
|
197 | -- raddr => open, | |
|
198 | -- wclk => clk, | |
|
199 | -- wen => FIFO_WEN(5), | |
|
200 | -- wdata => DATA_reg, | |
|
201 | -- full => FIFO_FULL_net(5), | |
|
202 | -- waddr => open | |
|
203 | -- ); | |
|
204 | --fron_fifo7: lpp_fifo | |
|
205 | -- generic map( | |
|
206 | -- tech => memtech, | |
|
207 | -- Mem_use => 1, --use RAM not CELS | |
|
208 | -- DataSz => 16, | |
|
209 | -- AddrSz => 8 | |
|
210 | -- ) | |
|
211 | -- port map( | |
|
212 | -- rstn => rstn, | |
|
213 | -- ReUse => '0', | |
|
214 | -- rclk => clk, | |
|
215 | -- ren => FIFO_REN, | |
|
216 | -- rdata => FIFO_out(6), | |
|
217 | -- empty => FIFO_EMPTY_net(6), | |
|
218 | -- raddr => open, | |
|
219 | -- wclk => clk, | |
|
220 | -- wen => FIFO_WEN(6), | |
|
221 | -- wdata => DATA_reg, | |
|
222 | -- full => FIFO_FULL_net(6), | |
|
223 | -- waddr => open | |
|
224 | -- ); | |
|
225 | --fron_fifo8: lpp_fifo | |
|
226 | -- generic map( | |
|
227 | -- tech => memtech, | |
|
228 | -- Mem_use => 1, --use RAM not CELS | |
|
229 | -- DataSz => 16, | |
|
230 | -- AddrSz => 8 | |
|
231 | -- ) | |
|
232 | -- port map( | |
|
233 | -- rstn => rstn, | |
|
234 | -- ReUse => '0', | |
|
235 | -- rclk => clk, | |
|
236 | -- ren => FIFO_REN, | |
|
237 | -- rdata => FIFO_out(7), | |
|
238 | -- empty => FIFO_EMPTY_net(7), | |
|
239 | -- raddr => open, | |
|
240 | -- wclk => clk, | |
|
241 | -- wen => FIFO_WEN(7), | |
|
242 | -- wdata => DATA_reg, | |
|
243 | -- full => FIFO_FULL_net(7), | |
|
244 | -- waddr => open | |
|
245 | -- ); | |
|
246 | ||
|
247 | REN_debug <= FIFO_REN; | |
|
248 | ||
|
249 | process(clk,rstn) | |
|
250 | begin | |
|
251 | if rstn = '0' then | |
|
252 | DATA_reg <= (others => '0'); | |
|
253 | FIFO_WEN <= (others => '0'); | |
|
254 | elsif clk'event and clk = '1' then | |
|
255 | if WEN = '0' then | |
|
256 | DATA_reg <= DATA; | |
|
257 | case address is | |
|
258 | when "000"=> | |
|
259 | FIFO_WEN <= "11111110"; | |
|
260 | FIFO_out(0) <= DATA; | |
|
261 | when "001"=> | |
|
262 | FIFO_WEN <= "11111101"; | |
|
263 | FIFO_out(1) <= DATA; | |
|
264 | when "010"=> | |
|
265 | FIFO_WEN <= "11111011"; | |
|
266 | FIFO_out(2) <= DATA; | |
|
267 | when "011"=> | |
|
268 | FIFO_WEN <= "11110111"; | |
|
269 | FIFO_out(3) <= DATA; | |
|
270 | when "100"=> | |
|
271 | FIFO_WEN <= "11101111"; | |
|
272 | FIFO_out(4) <= DATA; | |
|
273 | when "101"=> | |
|
274 | FIFO_WEN <= "11011111"; | |
|
275 | FIFO_out(5) <= DATA; | |
|
276 | when "110"=> | |
|
277 | FIFO_WEN <= "10111111"; | |
|
278 | FIFO_out(6) <= DATA; | |
|
279 | when "111"=> | |
|
280 | FIFO_WEN <= "01111111"; | |
|
281 | FIFO_out(7) <= DATA; | |
|
282 | when others => | |
|
283 | FIFO_WEN <= "11111111"; | |
|
284 | end case; | |
|
285 | end if; | |
|
286 | end if; | |
|
287 | end process; | |
|
288 | ||
|
289 | all_bits: FOR I in 15 downto 0 GENERATE | |
|
290 | all_chans: FOR J in 7 downto 0 GENERATE | |
|
291 | DAC_DATA(J,I) <= FIFO_out(J)(I); | |
|
292 | end GENERATE; | |
|
293 | end GENERATE; | |
|
294 | ||
|
295 | ||
|
296 | ||
|
297 | process(clk,rstn) | |
|
298 | begin | |
|
299 | if rstn = '0' then | |
|
300 | FIFO_REN <= '1'; | |
|
301 | smpclk_reg <= '0'; | |
|
302 | elsif clk'event and clk = '1' then | |
|
303 | smpclk_reg <= smpclk; | |
|
304 | if smpclk = '1' and smpclk_reg = '0' then | |
|
305 | FIFO_REN <= '0'; | |
|
306 | else | |
|
307 | FIFO_REN <= '1'; | |
|
308 | end if; | |
|
309 | end if; | |
|
310 | end process; | |
|
311 | ||
|
312 | ||
|
313 | DAC0 : DAC8581 | |
|
314 | generic map(150,8) | |
|
315 | Port map( | |
|
316 | clk => clk, | |
|
317 | rstn => rstn, | |
|
318 | smpclk => smpclk, | |
|
319 | sclk => CAL_IN_SCK, | |
|
320 | csn => DAC_nCS, | |
|
321 | sdo => DAC_SDI, | |
|
322 | smp_in => DAC_DATA | |
|
323 | ); | |
|
324 | ||
|
325 | ||
|
326 | ||
|
327 | smpclk0: Clk_divider | |
|
328 | GENERIC map(OSC_freqHz => 150000000, | |
|
329 | TargetFreq_Hz => 32000) | |
|
330 | PORT map( | |
|
331 | clk => clk, | |
|
332 | reset => rstn, | |
|
333 | clk_divided => smpclk | |
|
334 | ); | |
|
335 | ||
|
336 | ||
|
337 | end Behavioral; | |
|
338 |
@@ -2,8 +2,7 | |||
|
2 | 2 | NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE; |
|
3 | 3 | NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL; |
|
4 | 4 | NET "CLKM" TNM_NET = "clkm_net"; |
|
5 |
TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" |
|
|
6 | ||
|
5 | TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 6 ns HIGH 33%; | |
|
7 | 6 | |
|
8 | 7 | NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; |
|
9 | 8 | NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL; |
@@ -133,6 +132,8 NET "GPMC_A(18)" LOC = "J1"| slew=FAST | |||
|
133 | 132 | NET "GPMC_A(19)" LOC = "J3"| slew=FAST | IOSTANDARD=LVTTL; |
|
134 | 133 | |
|
135 | 134 | NET "GPMC_CLK_MUX0" CLOCK_DEDICATED_ROUTE = FALSE; |
|
135 | NET "GPMC_CLK_MUX0" TNM_NET = "GPMC_CLK_MUX0_net"; | |
|
136 | TIMESPEC "TS_GPMC_CLK_MUX0_net" = PERIOD "GPMC_CLK_MUX0_net" 8 ns HIGH 50%; | |
|
136 | 137 | NET "GPMC_CLK_MUX0" LOC = "R3"| slew=FAST | IOSTANDARD=LVTTL; |
|
137 | 138 | NET "GPMC_WEN" LOC = "W3"| slew=FAST | IOSTANDARD=LVTTL; |
|
138 | 139 | NET "GPMC_OEN_REN" LOC = "Y2"| slew=FAST | IOSTANDARD=LVTTL; |
@@ -59,15 +59,15 entity BeagleSynth is | |||
|
59 | 59 | -------------------------------------------------------- |
|
60 | 60 | GPMC_AD : inout std_logic_vector(15 downto 0); |
|
61 | 61 | GPMC_A : in std_logic_vector(19 downto 0); |
|
62 |
GPMC_CLK_MUX0 : in std_ |
|
|
63 |
GPMC_WEN : in std_ |
|
|
64 |
GPMC_OEN_REN : in std_ |
|
|
65 |
GPMC_ADVN_ALE : in std_ |
|
|
66 |
GPMC_CSN : in std_ |
|
|
67 |
GPMC_BE0N_CLE : in std_ |
|
|
68 |
GPMC_BE1N : in std_ |
|
|
69 |
GPMC_WAIT0 : |
|
|
70 |
GPMC_WPN : in std_ |
|
|
62 | GPMC_CLK_MUX0 : in std_logic; | |
|
63 | GPMC_WEN : in std_logic; | |
|
64 | GPMC_OEN_REN : in std_logic; | |
|
65 | GPMC_ADVN_ALE : in std_logic; | |
|
66 | GPMC_CSN : in std_logic_vector(2 downto 0); | |
|
67 | GPMC_BE0N_CLE : in std_logic; | |
|
68 | GPMC_BE1N : in std_logic; | |
|
69 | GPMC_WAIT0 : out std_logic; | |
|
70 | GPMC_WPN : in std_logic; | |
|
71 | 71 | |
|
72 | 72 | -------------------------------------------------------- |
|
73 | 73 | ---- SDRAM |
@@ -75,15 +75,15 entity BeagleSynth is | |||
|
75 | 75 | ---- design from GRLIB, the IS42S32400E is similar to |
|
76 | 76 | ---- MT48LC4M32B2. |
|
77 | 77 | -------------------------------------------------------- |
|
78 | sdcke : out std_logic; -- clk en | |
|
79 | sdcsn : out std_logic; -- chip sel | |
|
80 | sdwen : out std_logic; -- write en | |
|
81 | sdrasn : out std_logic; -- row addr stb | |
|
82 | sdcasn : out std_logic; -- col addr stb | |
|
83 | sddqm : out std_logic_vector (3 downto 0); -- data i/o mask | |
|
84 | sdclk : out std_logic; -- sdram clk output | |
|
85 | sdba : out std_logic_vector (1 downto 0); -- bank select address | |
|
86 | Address : out std_logic_vector(11 downto 0); -- sdram address | |
|
78 | sdcke : out std_logic; -- clk en | |
|
79 | sdcsn : out std_logic; -- chip sel | |
|
80 | sdwen : out std_logic; -- write en | |
|
81 | sdrasn : out std_logic; -- row addr stb | |
|
82 | sdcasn : out std_logic; -- col addr stb | |
|
83 | sddqm : out std_logic_vector (3 downto 0); -- data i/o mask | |
|
84 | sdclk : out std_logic; -- sdram clk output | |
|
85 | sdba : out std_logic_vector (1 downto 0); -- bank select address | |
|
86 | Address : out std_logic_vector(11 downto 0); -- sdram address | |
|
87 | 87 | Data : inout std_logic_vector(31 downto 0) -- optional sdram data |
|
88 | 88 | ); |
|
89 | 89 | end; |
@@ -107,53 +107,33 signal sdclkl_DDR2 : std_ulogic; | |||
|
107 | 107 | signal cgi : clkgen_in_type; |
|
108 | 108 | signal cgo : clkgen_out_type; |
|
109 | 109 | |
|
110 | --- AHB / APB | |
|
111 | signal apbi : apb_slv_in_type; | |
|
112 | signal apbo : apb_slv_out_vector := (others => apb_none); | |
|
113 | signal ahbsi : ahb_slv_in_type; | |
|
114 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); | |
|
115 | signal ahbmi : ahb_mst_in_type; | |
|
116 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); | |
|
117 | ||
|
118 | --- MEM CTRLR | |
|
119 | signal sdi : sdctrl_in_type; | |
|
120 | signal sdo : sdctrl_out_type; | |
|
121 | ||
|
122 | --UART | |
|
123 | signal ahbuarti : uart_in_type; | |
|
124 | signal ahbuarto : uart_out_type; | |
|
125 | signal apbuarti : uart_in_type; | |
|
126 | signal apbuarto : uart_out_type; | |
|
127 | ||
|
128 | signal led2int : std_logic; | |
|
129 | ||
|
130 | ||
|
131 | signal DAC0_DATA : std_logic_vector(15 downto 0); | |
|
132 | signal DAC1_DATA : std_logic_vector(15 downto 0); | |
|
133 | signal DAC2_DATA : std_logic_vector(15 downto 0); | |
|
134 | signal DAC3_DATA : std_logic_vector(15 downto 0); | |
|
135 | signal DAC4_DATA : std_logic_vector(15 downto 0); | |
|
136 | signal DAC5_DATA : std_logic_vector(15 downto 0); | |
|
137 | signal DAC6_DATA : std_logic_vector(15 downto 0); | |
|
138 | signal DAC7_DATA : std_logic_vector(15 downto 0); | |
|
139 | 110 | |
|
140 | 111 | signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); |
|
141 | 112 | signal smpclk : std_logic; |
|
142 | 113 | signal smpclk_reg : std_logic; |
|
143 | 114 | signal DAC_SDO : std_logic; |
|
144 | 115 | |
|
116 | signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0); | |
|
117 | signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0); | |
|
118 | signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0); | |
|
119 | signal GPMC_SLAVE_WEN : std_logic; | |
|
120 | ||
|
145 | 121 | signal gpmc_clk : std_logic; |
|
122 | ||
|
123 | attribute keep : boolean; | |
|
124 | attribute syn_keep : boolean; | |
|
125 | attribute syn_preserve : boolean; | |
|
126 | attribute syn_keep of clkm : signal is true; | |
|
127 | attribute syn_preserve of clkm : signal is true; | |
|
128 | attribute keep of clkm : signal is true; | |
|
146 | 129 | begin |
|
147 | 130 | |
|
148 | 131 | DAC_nCLR <= '1'; |
|
149 | --DAC_nCS <= SYNC; | |
|
150 | --CAL_IN_SCK <= '1'; | |
|
151 | --DAC_SDI <= (others =>'1'); | |
|
132 | ||
|
152 | 133 | |
|
153 | 134 | resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); |
|
154 | 135 | rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); |
|
155 | --rstn <= reset; | |
|
156 | --lclk <= clk; | |
|
136 | ||
|
157 | 137 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); |
|
158 | 138 | |
|
159 | 139 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
@@ -161,183 +141,33 resetn_pad : inpad generic map (tech => | |||
|
161 | 141 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) |
|
162 | 142 | port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); |
|
163 | 143 | |
|
164 | -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2); | |
|
165 | --sdclk <= sdclkl; | |
|
166 | sdclk <= sdclkl_DDR2; | |
|
167 | ||
|
168 | LED(1) <= not cgo.clklock; | |
|
169 | LED(0) <= cgo.clklock; | |
|
170 | ||
|
171 | ODDR2_inst : ODDR2 | |
|
172 | generic map( | |
|
173 | DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" | |
|
174 | INIT => '0', -- Sets initial state of the Q output to '0' or '1' | |
|
175 | SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset | |
|
176 | port map ( | |
|
177 | Q => sdclkl_DDR2, -- 1-bit output data | |
|
178 | C0 => sdclkl, -- 1-bit clock input | |
|
179 | C1 => not sdclkl, -- 1-bit clock input | |
|
180 | CE => '1', -- 1-bit clock enable input | |
|
181 | D0 => '1', -- 1-bit data input (associated with C0) | |
|
182 | D1 => '0', -- 1-bit data input (associated with C1) | |
|
183 | R => '0', -- 1-bit reset input | |
|
184 | S => '0' -- 1-bit set input | |
|
185 | ); | |
|
186 | ||
|
187 | ---------------------------------------------------------------------- | |
|
188 | --- AHB CONTROLLER ------------------------------------------------- | |
|
189 | ---------------------------------------------------------------------- | |
|
190 | ||
|
191 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
|
192 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
|
193 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
|
194 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) | |
|
195 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
|
196 | ||
|
197 | ---------------------------------------------------------------------- | |
|
198 | --- AHB UART ------------------------------------------------------- | |
|
199 | ---------------------------------------------------------------------- | |
|
200 | ||
|
201 | dcomgen : if CFG_AHB_UART = 1 generate | |
|
202 | dcom0: ahbuart -- Debug UART | |
|
203 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) | |
|
204 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); | |
|
205 | ahbuarti.rxd <= RXD; | |
|
206 | TXD <= ahbuarto.txd; | |
|
207 | end generate; | |
|
208 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; | |
|
209 | ||
|
210 | ---------------------------------------------------------------------- | |
|
211 | --- APB Bridge ----------------------------------------------------- | |
|
212 | ---------------------------------------------------------------------- | |
|
213 | ||
|
214 | apb0 : apbctrl -- AHB/APB bridge | |
|
215 | generic map (hindex => 1, haddr => CFG_APBADDR) | |
|
216 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); | |
|
217 | ||
|
218 | ---------------------------------------------------------------------- | |
|
219 | --- APB UART ------------------------------------------------------- | |
|
220 | ---------------------------------------------------------------------- | |
|
221 | ||
|
222 | ua1 : if CFG_UART1_ENABLE /= 0 generate | |
|
223 | uart1 : apbuart -- UART 1 | |
|
224 | generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART, | |
|
225 | fifosize => CFG_UART1_FIFO) | |
|
226 | port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
|
227 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; | |
|
228 | apbuarti.ctsn <= '0'; | |
|
229 | end generate; | |
|
230 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; | |
|
231 | ||
|
232 | ||
|
233 | ||
|
234 | ||
|
235 | --div0: Clk_divider | |
|
236 | -- generic map( 100000000,1) | |
|
237 | -- Port map( clkm,rstn,LED(2)); | |
|
238 | ||
|
239 | LED(2) <= led2int; | |
|
240 | ||
|
241 | process(clkm,rstn) | |
|
242 | begin | |
|
243 | if rstn = '0' then | |
|
244 | led2int <= '0'; | |
|
245 | elsif clkm'event and clkm='1' then | |
|
246 | led2int <= not led2int; | |
|
247 | end if; | |
|
248 | end process; | |
|
249 | ||
|
250 | 144 | |
|
251 | 145 | |
|
252 | 146 | |
|
253 | sdc : sdctrl | |
|
254 | generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0, | |
|
255 | invclk => 0,sdbits =>32) | |
|
256 | port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo); | |
|
257 | ||
|
258 | ||
|
259 | ||
|
260 | --Alternative data pad instantiation with vectored bdrive | |
|
261 | sd_pad : iopadvv generic map (tech=> padtech,width => 32) | |
|
262 | port map ( | |
|
263 | data(31 downto 0), | |
|
264 | sdo.data(31 downto 0), | |
|
265 | sdo.vbdrive(31 downto 0), | |
|
266 | sdi.data(31 downto 0)); | |
|
267 | ||
|
268 | ||
|
269 | -- connect memory controller outputs to entity output signals | |
|
270 | Address <= sdo.address(13 downto 2); | |
|
271 | --sdba <= sdo.address(16 downto 15); | |
|
272 | sdba <= "00"; | |
|
273 | sdcke <= sdo.sdcke(0); | |
|
274 | sdwen <= sdo.sdwen; | |
|
275 | sdcsn <= sdo.sdcsn(0); | |
|
276 | sdrasn <= sdo.rasn; | |
|
277 | sdcasn <= sdo.casn; | |
|
278 | sddqm <= sdo.dqm(3 downto 0); | |
|
279 | ||
|
280 | ||
|
281 | DAC0 : DAC8581 | |
|
282 | generic map(100,8) | |
|
147 | DAC0 : entity work.beagleSigGen | |
|
148 | generic map( | |
|
149 | memtech, | |
|
150 | padtech, | |
|
151 | clktech | |
|
152 | ) | |
|
283 | 153 | Port map( |
|
284 |
clk => |
|
|
285 |
rstn => |
|
|
286 | smpclk => smpclk, | |
|
287 | sclk => CAL_IN_SCK, | |
|
288 |
|
|
|
289 | sdo => DAC_SDI, | |
|
290 | smp_in => DAC_DATA | |
|
154 | clk => clkm, | |
|
155 | rstn => rstn, | |
|
156 | CAL_IN_SCK => CAL_IN_SCK, | |
|
157 | DAC_nCS => DAC_nCS, | |
|
158 | DAC_SDI => DAC_SDI, | |
|
159 | address => GPMC_SLAVE_ADDRESS(3 downto 1), | |
|
160 | DATA => GPMC_SLAVE_DATA, | |
|
161 | WEN => GPMC_SLAVE_WEN, | |
|
162 | REN_debug => LED(1), | |
|
163 | FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0), | |
|
164 | FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8) | |
|
291 | 165 | ); |
|
292 | 166 | |
|
293 | ||
|
294 | 167 | |
|
295 | smpclk0: Clk_divider | |
|
296 | GENERIC map(OSC_freqHz => 50000000, | |
|
297 | TargetFreq_Hz => 256000) | |
|
298 | PORT map( clk => clkm, | |
|
299 | reset => rstn, | |
|
300 | clk_divided => smpclk | |
|
301 | ); | |
|
302 | ||
|
303 | all_bits: FOR I in 15 downto 0 GENERATE | |
|
304 | DAC_DATA(0,I) <= DAC0_DATA(I); | |
|
305 | DAC_DATA(1,I) <= DAC1_DATA(I); | |
|
306 | DAC_DATA(2,I) <= DAC2_DATA(I); | |
|
307 | DAC_DATA(3,I) <= DAC3_DATA(I); | |
|
308 | DAC_DATA(4,I) <= DAC4_DATA(I); | |
|
309 | DAC_DATA(5,I) <= DAC5_DATA(I); | |
|
310 | DAC_DATA(6,I) <= DAC6_DATA(I); | |
|
311 | DAC_DATA(7,I) <= DAC7_DATA(I); | |
|
312 | end GENERATE; | |
|
313 | ||
|
314 | process(clkm,rstn) | |
|
315 | begin | |
|
316 | if rstn ='0' then | |
|
317 | DAC0_DATA <= X"0000"; | |
|
318 | DAC1_DATA <= X"0000"; | |
|
319 | DAC2_DATA <= X"0000"; | |
|
320 | DAC3_DATA <= X"0000"; | |
|
321 | DAC4_DATA <= X"0000"; | |
|
322 | DAC5_DATA <= X"0000"; | |
|
323 | DAC6_DATA <= X"0000"; | |
|
324 | DAC7_DATA <= X"0000"; | |
|
325 | smpclk_reg <= smpclk; | |
|
326 | elsif clkm'event and clkm = '1' then | |
|
327 | smpclk_reg <= smpclk; | |
|
328 | if smpclk_reg = '0' and smpclk = '1' then | |
|
329 | DAC0_DATA <= std_logic_vector( UNSIGNED(DAC0_DATA) +1); | |
|
330 | DAC1_DATA <= std_logic_vector( UNSIGNED(DAC1_DATA) +2); | |
|
331 | DAC2_DATA <= std_logic_vector( UNSIGNED(DAC2_DATA) +3); | |
|
332 | DAC3_DATA <= std_logic_vector( UNSIGNED(DAC3_DATA) +4); | |
|
333 | DAC4_DATA <= std_logic_vector( UNSIGNED(DAC4_DATA) +5); | |
|
334 | DAC5_DATA <= std_logic_vector( UNSIGNED(DAC5_DATA) +6); | |
|
335 | DAC6_DATA <= std_logic_vector( UNSIGNED(DAC6_DATA) +7); | |
|
336 | DAC7_DATA <= std_logic_vector( UNSIGNED(DAC7_DATA) +8); | |
|
337 | -- DAC_DATA <= "0100000000000000"; | |
|
338 | end if; | |
|
339 | end if; | |
|
340 | end process; | |
|
168 | ||
|
169 | LED(0) <= GPMC_SLAVE_WEN; | |
|
170 | LED(2) <= GPMC_WEN; | |
|
341 | 171 | |
|
342 | 172 | gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); |
|
343 | 173 | GPMCS0: entity work.GPMC_SLAVE |
@@ -345,9 +175,13 GPMCS0: entity work.GPMC_SLAVE | |||
|
345 | 175 | Port map( |
|
346 | 176 | clk => clkm, |
|
347 | 177 | reset => rstn, |
|
178 | STATUS => GPMC_SLAVE_STATUS, | |
|
179 | DATA => GPMC_SLAVE_DATA, | |
|
180 | ADDRESS => GPMC_SLAVE_ADDRESS, | |
|
181 | WEN => GPMC_SLAVE_WEN, | |
|
348 | 182 | GPMC_AD => GPMC_AD, |
|
349 | 183 | GPMC_A => GPMC_A, |
|
350 |
GPMC_CLK |
|
|
184 | GPMC_CLK => gpmc_clk, | |
|
351 | 185 | GPMC_WEN => GPMC_WEN, |
|
352 | 186 | GPMC_OEN_REN => GPMC_OEN_REN, |
|
353 | 187 | GPMC_ADVN_ALE => GPMC_ADVN_ALE, |
@@ -355,7 +189,7 GPMCS0: entity work.GPMC_SLAVE | |||
|
355 | 189 | GPMC_BE0N_CLE => GPMC_BE0N_CLE, |
|
356 | 190 | GPMC_BE1N => GPMC_BE1N, |
|
357 | 191 | GPMC_WAIT0 => GPMC_WAIT0, |
|
358 |
GPMC_WPN => GPMC_W |
|
|
192 | GPMC_WPN => GPMC_WPN | |
|
359 | 193 | ); |
|
360 | 194 | |
|
361 | 195 | end rtl; |
@@ -35,51 +35,73 entity GPMC_SLAVE is | |||
|
35 | 35 | Port ( |
|
36 | 36 | clk : in STD_LOGIC; |
|
37 | 37 | reset : in STD_LOGIC; |
|
38 | STATUS : in STD_LOGIC_VECTOR(15 downto 0); | |
|
39 | DATA : out STD_LOGIC_VECTOR(15 downto 0); | |
|
40 | ADDRESS : out std_logic_vector(19 downto 0); | |
|
41 | WEN : out STD_LOGIC; | |
|
38 | 42 | GPMC_AD : inout std_logic_vector(15 downto 0); |
|
39 | 43 | GPMC_A : in std_logic_vector(19 downto 0); |
|
40 |
GPMC_CLK |
|
|
41 |
GPMC_WEN : in std_ |
|
|
42 |
GPMC_OEN_REN : in std_ |
|
|
43 |
GPMC_ADVN_ALE : in std_ |
|
|
44 |
GPMC_CSN : in std_ |
|
|
45 |
GPMC_BE0N_CLE : in std_ |
|
|
46 |
GPMC_BE1N : in std_ |
|
|
47 |
GPMC_WAIT0 : |
|
|
48 |
GPMC_WPN : in std_ |
|
|
44 | GPMC_CLK : in std_logic; | |
|
45 | GPMC_WEN : in std_logic; | |
|
46 | GPMC_OEN_REN : in std_logic; | |
|
47 | GPMC_ADVN_ALE : in std_logic; | |
|
48 | GPMC_CSN : in std_logic_vector(2 downto 0); | |
|
49 | GPMC_BE0N_CLE : in std_logic; | |
|
50 | GPMC_BE1N : in std_logic; | |
|
51 | GPMC_WAIT0 : out std_logic; | |
|
52 | GPMC_WPN : in std_logic | |
|
49 | 53 | ); |
|
50 | 54 | end GPMC_SLAVE; |
|
51 | 55 | |
|
52 | 56 | architecture Behavioral of GPMC_SLAVE is |
|
53 | constant VectInit : std_logic_vector(15 downto 0):=(others => '0'); | |
|
57 | ||
|
58 | signal data_out : std_logic_vector(15 downto 0) := (others => '0'); | |
|
59 | signal data_in : std_logic_vector(15 downto 0) := (others => '0'); | |
|
54 | 60 | |
|
55 |
signal |
|
|
56 |
signal data_ |
|
|
61 | signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0'); | |
|
62 | signal data_r : std_logic_vector(15 downto 0) := (others => '0'); | |
|
57 | 63 | |
|
58 | type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0); | |
|
59 | signal RAMarray : RAMarrayT:=(others => VectInit); | |
|
60 | signal ramindex : integer range 0 to 255; | |
|
64 | ||
|
65 | signal outen : std_logic := '0'; | |
|
66 | ||
|
61 | 67 | |
|
62 | 68 | begin |
|
63 | 69 | |
|
70 | outen <= GPMC_OEN_REN or GPMC_CSN(0); | |
|
71 | data_out <= STATUS; | |
|
72 | ||
|
64 | 73 | data_pad : iopadv generic map (tech=> padtech,width => 16) |
|
65 | 74 | port map ( |
|
66 | 75 | pad => GPMC_AD(15 downto 0), |
|
67 | 76 | o => data_in(15 downto 0), |
|
68 | en => GPMC_OEN_REN, | |
|
77 | en => outen, | |
|
69 | 78 | i => data_out(15 downto 0) |
|
70 | 79 | ); |
|
71 | 80 | |
|
72 | process(reset,GPMC_CLK_MUX0) | |
|
81 | GPMC_WAIT0 <= '1'; | |
|
82 | ||
|
83 | ||
|
84 | ||
|
85 | process(reset,clk) | |
|
73 | 86 | begin |
|
74 | 87 | if reset = '0' then |
|
75 | data_out <= (others => '0'); | |
|
76 | ramindex <= 0; | |
|
77 | elsif GPMC_CLK_MUX0'event and GPMC_CLK_MUX0 = '1' then | |
|
78 | ramindex <= to_integer(unsigned(GPMC_A)); | |
|
79 | data_out <= RAMarray(ramindex); | |
|
80 | if GPMC_WEN = '0' then | |
|
81 | RAMarray(ramindex) <= data_in; | |
|
88 | WEN <= '1'; | |
|
89 | GPMC_CLK_reg <= "0000"; | |
|
90 | ADDRESS <= (others => '0'); | |
|
91 | elsif clk'event and clk = '1' then | |
|
92 | GPMC_CLK_reg(0) <= GPMC_CLK; | |
|
93 | if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then | |
|
94 | if GPMC_WEN = '0' then | |
|
95 | WEN <= '0'; | |
|
96 | DATA <= data_in; | |
|
97 | end if; | |
|
98 | if GPMC_ADVN_ALE = '0' then | |
|
99 | ADDRESS <= GPMC_A; | |
|
100 | end if; | |
|
101 | else | |
|
102 | WEN <= '1'; | |
|
82 | 103 | end if; |
|
104 | ||
|
83 | 105 | end if; |
|
84 | 106 | end process; |
|
85 | 107 |
@@ -17,7 +17,7 VHDLOPTSYNFILES= | |||
|
17 | 17 | |
|
18 | 18 | |
|
19 | 19 | VHDLSYNFILES= \ |
|
20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd | |
|
20 | config.vhd BeagleSynth.vhd BeagleSynth_MCTRL.vhd GPMC_SLAVE.vhd beagleSigGen.vhd GPMC_ASYNC_SLAVE.vhd | |
|
21 | 21 | #VHDLSIMFILES=testbench.vhd |
|
22 | 22 | #SIMTOP=testbench |
|
23 | 23 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc |
@@ -24,7 +24,7 package config is | |||
|
24 | 24 | -- ON Spartan 6 VCO freq must be between 400MHz and 1GHz |
|
25 | 25 | constant CFG_CLKTECH : integer := spartan6; |
|
26 | 26 | constant CFG_CLKMUL : integer := (6); |
|
27 |
constant CFG_CLKDIV : integer := ( |
|
|
27 | constant CFG_CLKDIV : integer := (4); | |
|
28 | 28 | constant CFG_OCLKDIV : integer := (1); |
|
29 | 29 | constant CFG_PCIDLL : integer := 0; |
|
30 | 30 | constant CFG_PCISYSCLK: integer := 0; |
@@ -53,14 +53,17 signal smpclk_reg : std_logic; | |||
|
53 | 53 | signal sclk_gen : std_logic_vector(3 downto 0); |
|
54 | 54 | signal sclk_net : std_logic; |
|
55 | 55 | signal load : std_logic; |
|
56 | signal load_reg : std_logic; | |
|
56 | 57 | signal data_sreg : CNA_16bit_T(ChanCount-1 downto 0,15 downto 0); |
|
57 | signal csn_sreg : std_logic_vector(15 downto 0); | |
|
58 | 58 | |
|
59 | signal csn_sreg : std_logic; | |
|
60 | signal shift_counter : integer range 0 to 16; | |
|
61 | signal sdo_int : STD_LOGIC_VECTOR (ChanCount-1 downto 0); | |
|
59 | 62 | begin |
|
60 | 63 | |
|
61 | 64 | |
|
62 | 65 | |
|
63 |
sclk_net <= sclk_gen( |
|
|
66 | sclk_net <= sclk_gen(2); | |
|
64 | 67 | sclk <= sclk_net; |
|
65 | 68 | |
|
66 | 69 | process(rstn,clk) |
@@ -84,17 +87,37 end process; | |||
|
84 | 87 | process(load,sclk_net) |
|
85 | 88 | begin |
|
86 | 89 | if load ='1' then |
|
87 | data_sreg <= smp_in; | |
|
88 | csn_sreg <= (others => '0'); | |
|
89 | ||
|
90 | elsif sclk_net'event and sclk_net = '1' then | |
|
91 | all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP | |
|
92 | all_bits0 : FOR J IN 14 DOWNTO 0 LOOP | |
|
93 | data_sreg(I,J+1) <= data_sreg(I,J); | |
|
94 | END LOOP all_bits0; | |
|
95 | data_sreg(I,0) <= '1'; | |
|
96 | END LOOP all_chanel0; | |
|
97 | csn_sreg <= csn_sreg(14 downto 0) & '1'; | |
|
90 | load_reg <= '1'; | |
|
91 | elsif sclk_net'event and sclk_net = '1' then | |
|
92 | load_reg <= '0'; | |
|
93 | end if; | |
|
94 | end process; | |
|
95 | ||
|
96 | process(rstn,sclk_net) | |
|
97 | begin | |
|
98 | if rstn ='0' then | |
|
99 | data_sreg <= smp_in; | |
|
100 | csn_sreg <= '1'; | |
|
101 | elsif sclk_net'event and sclk_net = '1' then | |
|
102 | if load_reg = '1' then | |
|
103 | data_sreg <= smp_in; | |
|
104 | shift_counter <= 0; | |
|
105 | csn_sreg <= '1'; | |
|
106 | else | |
|
107 | all_chanel0 : FOR I IN ChanCount-1 DOWNTO 0 LOOP | |
|
108 | all_bits0 : FOR J IN 14 DOWNTO 0 LOOP | |
|
109 | data_sreg(I,J+1) <= data_sreg(I,J); | |
|
110 | END LOOP all_bits0; | |
|
111 | data_sreg(I,0) <= '1'; | |
|
112 | END LOOP all_chanel0; | |
|
113 | if shift_counter /= 16 then | |
|
114 | shift_counter <= shift_counter + 1; | |
|
115 | csn_sreg <= '0'; | |
|
116 | else | |
|
117 | csn_sreg <= '1'; | |
|
118 | end if; | |
|
119 | ||
|
120 | end if; | |
|
98 | 121 | end if; |
|
99 | 122 | end process; |
|
100 | 123 | |
@@ -102,14 +125,16 process(rstn,sclk_net) | |||
|
102 | 125 | begin |
|
103 | 126 | if rstn ='0' then |
|
104 | 127 | all_chanel2 : FOR I IN ChanCount-1 DOWNTO 0 LOOP |
|
105 | sdo(I) <= '1'; | |
|
128 | sdo_int(I) <= '1'; | |
|
129 | sdo(I) <= '1'; | |
|
106 | 130 | END LOOP all_chanel2; |
|
107 | 131 | csn <= '1'; |
|
108 | 132 | elsif sclk_net'event and sclk_net = '0' then |
|
109 | 133 | all_chanel1 : FOR I IN ChanCount-1 DOWNTO 0 LOOP |
|
110 | sdo(I) <= data_sreg(I,15); | |
|
134 | sdo_int(I) <= data_sreg(I,15); | |
|
111 | 135 | END LOOP all_chanel1; |
|
112 | csn <= csn_sreg(15); | |
|
136 | sdo <= sdo_int; | |
|
137 | csn <= csn_sreg; | |
|
113 | 138 | end if; |
|
114 | 139 | end process; |
|
115 | 140 |
@@ -43,6 +43,11 if [ -d "$GRLIBPATH" ]; then | |||
|
43 | 43 | else |
|
44 | 44 | echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt |
|
45 | 45 | fi |
|
46 | if(grep -q $LPP_PATCHPATH/lib/staging $1/lib/libs.txt); then | |
|
47 | echo "No need to Patch $1/lib/libs.txt..." | |
|
48 | else | |
|
49 | echo $LPP_PATCHPATH/lib/staging >>$1/lib/libs.txt | |
|
50 | fi | |
|
46 | 51 | echo |
|
47 | 52 | echo |
|
48 | 53 | echo |
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