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Change ncycle_cnv param of top_ad_conv_ADS7886_v2 (ADC driver) from 250 to 249
pellion -
r308:2932b543c3ab (MINI-LFR) WFP_MS-0-1-2 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_val : STD_LOGIC;
167 167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 170
171 171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 172
173 173 -----------------------------------------------------------------------------
174 174
175 175 BEGIN -- beh
176 176
177 177 -----------------------------------------------------------------------------
178 178 -- CLK
179 179 -----------------------------------------------------------------------------
180 180
181 181 PROCESS(clk_50)
182 182 BEGIN
183 183 IF clk_50'EVENT AND clk_50 = '1' THEN
184 184 clk_50_s <= NOT clk_50_s;
185 185 END IF;
186 186 END PROCESS;
187 187
188 188 PROCESS(clk_50_s)
189 189 BEGIN
190 190 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 191 clk_25 <= NOT clk_25;
192 192 END IF;
193 193 END PROCESS;
194 194
195 195 PROCESS(clk_49)
196 196 BEGIN
197 197 IF clk_49'EVENT AND clk_49 = '1' THEN
198 198 clk_24 <= NOT clk_24;
199 199 END IF;
200 200 END PROCESS;
201 201
202 202 -----------------------------------------------------------------------------
203 203
204 204 PROCESS (clk_25, reset)
205 205 BEGIN -- PROCESS
206 206 IF reset = '0' THEN -- asynchronous reset (active low)
207 207 LED0 <= '0';
208 208 LED1 <= '0';
209 209 LED2 <= '0';
210 210 --IO1 <= '0';
211 211 --IO2 <= '1';
212 212 --IO3 <= '0';
213 213 --IO4 <= '0';
214 214 --IO5 <= '0';
215 215 --IO6 <= '0';
216 216 --IO7 <= '0';
217 217 --IO8 <= '0';
218 218 --IO9 <= '0';
219 219 --IO10 <= '0';
220 220 --IO11 <= '0';
221 221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 222 LED0 <= '0';
223 223 LED1 <= '1';
224 224 LED2 <= BP0;
225 225 --IO1 <= '1';
226 226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 227 --IO3 <= ADC_SDO(0);
228 228 --IO4 <= ADC_SDO(1);
229 229 --IO5 <= ADC_SDO(2);
230 230 --IO6 <= ADC_SDO(3);
231 231 --IO7 <= ADC_SDO(4);
232 232 --IO8 <= ADC_SDO(5);
233 233 --IO9 <= ADC_SDO(6);
234 234 --IO10 <= ADC_SDO(7);
235 235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 236 END IF;
237 237 END PROCESS;
238 238
239 239 PROCESS (clk_24, reset)
240 240 BEGIN -- PROCESS
241 241 IF reset = '0' THEN -- asynchronous reset (active low)
242 242 I00_s <= '0';
243 243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 244 I00_s <= NOT I00_s;
245 245 END IF;
246 246 END PROCESS;
247 247 -- IO0 <= I00_s;
248 248
249 249 --UARTs
250 250 nCTS1 <= '1';
251 251 nCTS2 <= '1';
252 252 nDCD2 <= '1';
253 253
254 254 --EXT CONNECTOR
255 255
256 256 --SPACE WIRE
257 257
258 258 leon3_soc_1 : leon3_soc
259 259 GENERIC MAP (
260 260 fabtech => apa3e,
261 261 memtech => apa3e,
262 262 padtech => inferred,
263 263 clktech => inferred,
264 264 disas => 0,
265 265 dbguart => 0,
266 266 pclow => 2,
267 267 clk_freq => 25000,
268 268 NB_CPU => 1,
269 269 ENABLE_FPU => 1,
270 270 FPU_NETLIST => 0,
271 271 ENABLE_DSU => 1,
272 272 ENABLE_AHB_UART => 1,
273 273 ENABLE_APB_UART => 1,
274 274 ENABLE_IRQMP => 1,
275 275 ENABLE_GPT => 1,
276 276 NB_AHB_MASTER => NB_AHB_MASTER,
277 277 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 278 NB_APB_SLAVE => NB_APB_SLAVE)
279 279 PORT MAP (
280 280 clk => clk_25,
281 281 reset => reset,
282 282 errorn => errorn,
283 283 ahbrxd => TXD1,
284 284 ahbtxd => RXD1,
285 285 urxd1 => TXD2,
286 286 utxd1 => RXD2,
287 287 address => SRAM_A,
288 288 data => SRAM_DQ,
289 289 nSRAM_BE0 => SRAM_nBE(0),
290 290 nSRAM_BE1 => SRAM_nBE(1),
291 291 nSRAM_BE2 => SRAM_nBE(2),
292 292 nSRAM_BE3 => SRAM_nBE(3),
293 293 nSRAM_WE => SRAM_nWE,
294 294 nSRAM_CE => SRAM_CE,
295 295 nSRAM_OE => SRAM_nOE,
296 296
297 297 apbi_ext => apbi_ext,
298 298 apbo_ext => apbo_ext,
299 299 ahbi_s_ext => ahbi_s_ext,
300 300 ahbo_s_ext => ahbo_s_ext,
301 301 ahbi_m_ext => ahbi_m_ext,
302 302 ahbo_m_ext => ahbo_m_ext);
303 303
304 304 -------------------------------------------------------------------------------
305 305 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 306 -------------------------------------------------------------------------------
307 307 apb_lfr_time_management_1 : apb_lfr_time_management
308 308 GENERIC MAP (
309 309 pindex => 6,
310 310 paddr => 6,
311 311 pmask => 16#fff#,
312 312 pirq => 12,
313 313 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 314 PORT MAP (
315 315 clk25MHz => clk_25,
316 316 clk49_152MHz => clk_24, -- 49.152MHz/2
317 317 resetn => reset,
318 318 grspw_tick => swno.tickout,
319 319 apbi => apbi_ext,
320 320 apbo => apbo_ext(6),
321 321 coarse_time => coarse_time,
322 322 fine_time => fine_time);
323 323
324 324 -----------------------------------------------------------------------
325 325 --- SpaceWire --------------------------------------------------------
326 326 -----------------------------------------------------------------------
327 327
328 328 SPW_EN <= '1';
329 329
330 330 spw_clk <= clk_50_s;
331 331 spw_rxtxclk <= spw_clk;
332 332 spw_rxclkn <= NOT spw_rxtxclk;
333 333
334 334 -- PADS for SPW1
335 335 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 336 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 337 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 338 PORT MAP (SPW_NOM_SIN, stmp(0));
339 339 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 341 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 342 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 343 -- PADS FOR SPW2
344 344 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 345 PORT MAP (SPW_RED_SIN, dtmp(1));
346 346 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 347 PORT MAP (SPW_RED_DIN, stmp(1));
348 348 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 349 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 350 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 351 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 352
353 353 -- GRSPW PHY
354 354 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 355 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 356 spw_phy0 : grspw_phy
357 357 GENERIC MAP(
358 358 tech => apa3e,
359 359 rxclkbuftype => 1,
360 360 scantest => 0)
361 361 PORT MAP(
362 362 rxrst => swno.rxrst,
363 363 di => dtmp(j),
364 364 si => stmp(j),
365 365 rxclko => spw_rxclk(j),
366 366 do => swni.d(j),
367 367 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 368 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 369 END GENERATE spw_inputloop;
370 370
371 371 -- SPW core
372 372 sw0 : grspwm GENERIC MAP(
373 373 tech => apa3e,
374 374 hindex => 1,
375 375 pindex => 5,
376 376 paddr => 5,
377 377 pirq => 11,
378 378 sysfreq => 25000, -- CPU_FREQ
379 379 rmap => 1,
380 380 rmapcrc => 1,
381 381 fifosize1 => 16,
382 382 fifosize2 => 16,
383 383 rxclkbuftype => 1,
384 384 rxunaligned => 0,
385 385 rmapbufs => 4,
386 386 ft => 0,
387 387 netlist => 0,
388 388 ports => 2,
389 389 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 390 memtech => apa3e,
391 391 destkey => 2,
392 392 spwcore => 1
393 393 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 394 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 395 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 396 )
397 397 PORT MAP(reset, clk_25, spw_rxclk(0),
398 398 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 399 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 400 swni, swno);
401 401
402 402 swni.tickin <= '0';
403 403 swni.rmapen <= '1';
404 404 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 405 swni.tickinraw <= '0';
406 406 swni.timein <= (OTHERS => '0');
407 407 swni.dcrstval <= (OTHERS => '0');
408 408 swni.timerrstval <= (OTHERS => '0');
409 409
410 410 -------------------------------------------------------------------------------
411 411 -- LFR ------------------------------------------------------------------------
412 412 -------------------------------------------------------------------------------
413 413 lpp_lfr_1 : lpp_lfr
414 414 GENERIC MAP (
415 415 Mem_use => use_RAM,
416 416 nb_data_by_buffer_size => 32,
417 417 nb_word_by_buffer_size => 30,
418 418 nb_snapshot_param_size => 32,
419 419 delta_vector_size => 32,
420 420 delta_vector_size_f0_2 => 7, -- log2(96)
421 421 pindex => 15,
422 422 paddr => 15,
423 423 pmask => 16#fff#,
424 424 pirq_ms => 6,
425 425 pirq_wfp => 14,
426 426 hindex => 2,
427 top_lfr_version => X"000101") -- aa.bb.cc version
427 top_lfr_version => X"000102") -- aa.bb.cc version
428 428 PORT MAP (
429 429 clk => clk_25,
430 430 rstn => reset,
431 431 sample_B => sample(2 DOWNTO 0),
432 432 sample_E => sample(7 DOWNTO 3),
433 433 sample_val => sample_val,
434 434 apbi => apbi_ext,
435 435 apbo => apbo_ext(15),
436 436 ahbi => ahbi_m_ext,
437 437 ahbo => ahbo_m_ext(2),
438 438 coarse_time => coarse_time,
439 439 fine_time => fine_time,
440 440 data_shaping_BW => bias_fail_sw_sig);
441 441
442 442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
443 443 GENERIC MAP(
444 444 ChannelCount => 8,
445 445 SampleNbBits => 14,
446 446 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
447 ncycle_cnv => 250) -- 49 152 000 / 98304 /2
447 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
448 448 PORT MAP (
449 449 -- CONV
450 450 cnv_clk => clk_24,
451 451 cnv_rstn => reset,
452 452 cnv => ADC_nCS_sig,
453 453 -- DATA
454 454 clk => clk_25,
455 455 rstn => reset,
456 456 sck => ADC_CLK_sig,
457 457 sdo => ADC_SDO_sig,
458 458 -- SAMPLE
459 459 sample => sample,
460 460 sample_val => sample_val);
461 461
462 462 IO10 <= ADC_SDO_sig(5);
463 463 IO9 <= ADC_SDO_sig(4);
464 464 IO8 <= ADC_SDO_sig(3);
465 465
466 466 ADC_nCS <= ADC_nCS_sig;
467 467 ADC_CLK <= ADC_CLK_sig;
468 468 ADC_SDO_sig <= ADC_SDO;
469 469
470 470 ----------------------------------------------------------------------
471 471 --- GPIO -----------------------------------------------------------
472 472 ----------------------------------------------------------------------
473 473
474 474 grgpio0 : grgpio
475 475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
476 476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
477 477
478 478 pio_pad_0 : iopad
479 479 GENERIC MAP (tech => CFG_PADTECH)
480 480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
481 481 pio_pad_1 : iopad
482 482 GENERIC MAP (tech => CFG_PADTECH)
483 483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
484 484 pio_pad_2 : iopad
485 485 GENERIC MAP (tech => CFG_PADTECH)
486 486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
487 487 pio_pad_3 : iopad
488 488 GENERIC MAP (tech => CFG_PADTECH)
489 489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
490 490 pio_pad_4 : iopad
491 491 GENERIC MAP (tech => CFG_PADTECH)
492 492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
493 493 pio_pad_5 : iopad
494 494 GENERIC MAP (tech => CFG_PADTECH)
495 495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
496 496 pio_pad_6 : iopad
497 497 GENERIC MAP (tech => CFG_PADTECH)
498 498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
499 499 pio_pad_7 : iopad
500 500 GENERIC MAP (tech => CFG_PADTECH)
501 501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
502 502
503 503 END beh;
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