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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe Pellion | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | ||
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23 | LIBRARY ieee; | |
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24 | USE ieee.std_logic_1164.ALL; | |
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25 | USE ieee.numeric_std.ALL; | |
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26 | LIBRARY grlib; | |
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27 | USE grlib.stdlib.ALL; | |
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28 | LIBRARY gaisler; | |
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29 | USE gaisler.libdcom.ALL; | |
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30 | USE gaisler.sim.ALL; | |
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31 | USE gaisler.jtagtst.ALL; | |
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32 | LIBRARY techmap; | |
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33 | USE techmap.gencomp.ALL; | |
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34 | LIBRARY lpp; | |
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35 | USE lpp.lpp_sim_pkg.ALL; | |
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36 | USE lpp.lpp_lfr_apbreg_pkg.ALL; | |
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37 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; | |
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38 | ||
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39 | PACKAGE lpp_lfr_sim_pkg IS | |
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40 | ||
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41 | PROCEDURE UNRESET_LFR ( | |
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42 | SIGNAL TX : OUT STD_LOGIC; | |
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43 | CONSTANT tx_period : IN TIME; | |
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44 | CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8) | |
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45 | ); | |
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46 | ||
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47 | PROCEDURE LAUNCH_SPECTRAL_MATRIX( | |
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48 | SIGNAL TX : OUT STD_LOGIC; | |
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49 | SIGNAL RX : IN STD_LOGIC; | |
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50 | CONSTANT tx_period : IN TIME; | |
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51 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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52 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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53 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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54 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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55 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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56 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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57 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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58 | ); | |
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59 | ||
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60 | ----------------------------------------------------------------------------- | |
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61 | -- SM function | |
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62 | ----------------------------------------------------------------------------- | |
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63 | ||
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64 | PROCEDURE RESET_SPECTRAL_MATRIX_REGS( | |
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65 | SIGNAL TX : OUT STD_LOGIC; | |
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66 | SIGNAL RX : IN STD_LOGIC; | |
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67 | CONSTANT tx_period : IN TIME; | |
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68 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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69 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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70 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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71 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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72 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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73 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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74 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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75 | ); | |
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76 | ||
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77 | PROCEDURE SET_SM_IRQ_onNewMatrix( | |
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78 | SIGNAL TX : OUT STD_LOGIC; | |
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79 | SIGNAL RX : IN STD_LOGIC; | |
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80 | CONSTANT tx_period : IN TIME; | |
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81 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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82 | CONSTANT PARAM_value : IN STD_LOGIC | |
|
83 | ); | |
|
84 | ||
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85 | PROCEDURE SET_SM_IRQ_ERROR( | |
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86 | SIGNAL TX : OUT STD_LOGIC; | |
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87 | SIGNAL RX : IN STD_LOGIC; | |
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88 | CONSTANT tx_period : IN TIME; | |
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89 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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90 | CONSTANT PARAM_value : IN STD_LOGIC | |
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91 | ); | |
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92 | ||
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93 | PROCEDURE RESET_SM_STATUS( | |
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94 | SIGNAL TX : OUT STD_LOGIC; | |
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95 | SIGNAL RX : IN STD_LOGIC; | |
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96 | CONSTANT tx_period : IN TIME; | |
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97 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) | |
|
98 | ); | |
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99 | ||
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100 | END lpp_lfr_sim_pkg; | |
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101 | ||
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102 | ||
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103 | ||
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104 | PACKAGE BODY lpp_lfr_sim_pkg IS | |
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105 | ||
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106 | PROCEDURE UNRESET_LFR ( | |
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107 | SIGNAL TX : OUT STD_LOGIC; | |
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108 | CONSTANT tx_period : IN TIME; | |
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109 | CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)) | |
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110 | IS | |
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111 | BEGIN | |
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112 | UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); | |
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113 | UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); | |
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114 | END; | |
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115 | ||
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116 | PROCEDURE LAUNCH_SPECTRAL_MATRIX( | |
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117 | SIGNAL TX : OUT STD_LOGIC; | |
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118 | SIGNAL RX : IN STD_LOGIC; | |
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119 | CONSTANT tx_period : IN TIME; | |
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120 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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121 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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122 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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123 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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124 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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125 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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126 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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127 | ) | |
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128 | IS | |
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129 | BEGIN | |
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130 | RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR, | |
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131 | PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr, | |
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132 | PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr); | |
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133 | SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR, | |
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134 | '1'); | |
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135 | END; | |
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136 | ||
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137 | ----------------------------------------------------------------------------- | |
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138 | -- SM function | |
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139 | ----------------------------------------------------------------------------- | |
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140 | PROCEDURE RESET_SPECTRAL_MATRIX_REGS( | |
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141 | SIGNAL TX : OUT STD_LOGIC; | |
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142 | SIGNAL RX : IN STD_LOGIC; | |
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143 | CONSTANT tx_period : IN TIME; | |
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144 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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145 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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146 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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147 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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148 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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149 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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150 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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151 | ) | |
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152 | IS | |
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153 | BEGIN | |
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154 | SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0'); | |
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155 | SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0'); | |
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156 | RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR); | |
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157 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr); | |
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158 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr); | |
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159 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr); | |
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160 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr); | |
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161 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr); | |
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162 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr); | |
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163 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8"); | |
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164 | END; | |
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165 | ||
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166 | PROCEDURE SET_SM_IRQ_onNewMatrix( | |
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167 | SIGNAL TX : OUT STD_LOGIC; | |
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168 | SIGNAL RX : IN STD_LOGIC; | |
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169 | CONSTANT tx_period : IN TIME; | |
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170 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ; | |
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171 | CONSTANT PARAM_value : IN STD_LOGIC | |
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172 | ) | |
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173 | IS | |
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174 | VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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175 | BEGIN | |
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176 | UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read); | |
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177 | IF PARAM_value = '1' THEN | |
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178 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' ); | |
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179 | ELSE | |
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180 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' ); | |
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181 | END IF; | |
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182 | END; | |
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183 | ||
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184 | PROCEDURE SET_SM_IRQ_ERROR( | |
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185 | SIGNAL TX : OUT STD_LOGIC; | |
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186 | SIGNAL RX : IN STD_LOGIC; | |
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187 | CONSTANT tx_period : IN TIME; | |
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188 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ; | |
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189 | CONSTANT PARAM_value : IN STD_LOGIC | |
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190 | ) | |
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191 | IS | |
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192 | VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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193 | BEGIN | |
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194 | UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read); | |
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195 | IF PARAM_value = '1' THEN | |
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196 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) ); | |
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197 | ELSE | |
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198 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) ); | |
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199 | END IF; | |
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200 | END; | |
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201 | ||
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202 | PROCEDURE RESET_SM_STATUS( | |
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203 | SIGNAL TX : OUT STD_LOGIC; | |
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204 | SIGNAL RX : IN STD_LOGIC; | |
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205 | CONSTANT tx_period : IN TIME; | |
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206 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) | |
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207 | ) | |
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208 | IS | |
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209 | BEGIN | |
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210 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF"); | |
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211 | END; | |
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212 | ||
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213 | END lpp_lfr_sim_pkg; |
@@ -1,280 +1,297 | |||
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1 | 1 | LIBRARY ieee; |
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2 | 2 | USE ieee.std_logic_1164.ALL; |
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3 | 3 | USE ieee.numeric_std.ALL; |
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4 | 4 | use IEEE.std_logic_textio.all; |
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5 | 5 | LIBRARY STD; |
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6 | 6 | use std.textio.all; |
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7 | 7 | |
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8 | 8 | LIBRARY grlib; |
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9 | 9 | USE grlib.stdlib.ALL; |
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10 | 10 | LIBRARY gaisler; |
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11 | 11 | USE gaisler.libdcom.ALL; |
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12 | 12 | USE gaisler.sim.ALL; |
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13 | 13 | USE gaisler.jtagtst.ALL; |
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14 | 14 | LIBRARY techmap; |
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15 | 15 | USE techmap.gencomp.ALL; |
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16 | 16 | |
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17 | 17 | LIBRARY lpp; |
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18 | 18 | USE lpp.lpp_sim_pkg.ALL; |
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19 | 19 | USE lpp.lpp_lfr_sim_pkg.ALL; |
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20 | 20 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
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21 | 21 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; |
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22 | 22 | |
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23 | 23 | |
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24 | 24 | ENTITY testbench IS |
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25 | 25 | END; |
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26 | 26 | |
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27 | 27 | ARCHITECTURE behav OF testbench IS |
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28 | 28 | |
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29 | 29 | COMPONENT MINI_LFR_top |
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30 | 30 | PORT ( |
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31 | 31 | clk_50 : IN STD_LOGIC; |
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32 | 32 | clk_49 : IN STD_LOGIC; |
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33 | 33 | reset : IN STD_LOGIC; |
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34 | 34 | BP0 : IN STD_LOGIC; |
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35 | 35 | BP1 : IN STD_LOGIC; |
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36 | 36 | LED0 : OUT STD_LOGIC; |
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37 | 37 | LED1 : OUT STD_LOGIC; |
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38 | 38 | LED2 : OUT STD_LOGIC; |
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39 | 39 | TXD1 : IN STD_LOGIC; |
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40 | 40 | RXD1 : OUT STD_LOGIC; |
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41 | 41 | nCTS1 : OUT STD_LOGIC; |
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42 | 42 | nRTS1 : IN STD_LOGIC; |
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43 | 43 | TXD2 : IN STD_LOGIC; |
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44 | 44 | RXD2 : OUT STD_LOGIC; |
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45 | 45 | nCTS2 : OUT STD_LOGIC; |
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46 | 46 | nDTR2 : IN STD_LOGIC; |
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47 | 47 | nRTS2 : IN STD_LOGIC; |
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48 | 48 | nDCD2 : OUT STD_LOGIC; |
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49 | 49 | IO0 : INOUT STD_LOGIC; |
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50 | 50 | IO1 : INOUT STD_LOGIC; |
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51 | 51 | IO2 : INOUT STD_LOGIC; |
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52 | 52 | IO3 : INOUT STD_LOGIC; |
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53 | 53 | IO4 : INOUT STD_LOGIC; |
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54 | 54 | IO5 : INOUT STD_LOGIC; |
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55 | 55 | IO6 : INOUT STD_LOGIC; |
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56 | 56 | IO7 : INOUT STD_LOGIC; |
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57 | 57 | IO8 : INOUT STD_LOGIC; |
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58 | 58 | IO9 : INOUT STD_LOGIC; |
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59 | 59 | IO10 : INOUT STD_LOGIC; |
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60 | 60 | IO11 : INOUT STD_LOGIC; |
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61 | 61 | SPW_EN : OUT STD_LOGIC; |
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62 | 62 | SPW_NOM_DIN : IN STD_LOGIC; |
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63 | 63 | SPW_NOM_SIN : IN STD_LOGIC; |
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64 | 64 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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65 | 65 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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66 | 66 | SPW_RED_DIN : IN STD_LOGIC; |
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67 | 67 | SPW_RED_SIN : IN STD_LOGIC; |
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68 | 68 | SPW_RED_DOUT : OUT STD_LOGIC; |
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69 | 69 | SPW_RED_SOUT : OUT STD_LOGIC; |
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70 | 70 | ADC_nCS : OUT STD_LOGIC; |
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71 | 71 | ADC_CLK : OUT STD_LOGIC; |
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72 | 72 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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73 | 73 | SRAM_nWE : OUT STD_LOGIC; |
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74 | 74 | SRAM_CE : OUT STD_LOGIC; |
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75 | 75 | SRAM_nOE : OUT STD_LOGIC; |
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76 | 76 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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77 | 77 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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78 | 78 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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79 | 79 | END COMPONENT; |
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80 | 80 | |
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81 | 81 | ----------------------------------------------------------------------------- |
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82 | 82 | SIGNAL clk_50 : STD_LOGIC := '0'; |
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83 | 83 | SIGNAL clk_49 : STD_LOGIC := '0'; |
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84 | 84 | SIGNAL reset : STD_LOGIC; |
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85 | 85 | SIGNAL BP0 : STD_LOGIC; |
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86 | 86 | SIGNAL BP1 : STD_LOGIC; |
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87 | 87 | SIGNAL LED0 : STD_LOGIC; |
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88 | 88 | SIGNAL LED1 : STD_LOGIC; |
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89 | 89 | SIGNAL LED2 : STD_LOGIC; |
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90 | 90 | SIGNAL TXD1 : STD_LOGIC; |
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91 | 91 | SIGNAL RXD1 : STD_LOGIC; |
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92 | 92 | SIGNAL nCTS1 : STD_LOGIC; |
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93 | 93 | SIGNAL nRTS1 : STD_LOGIC; |
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94 | 94 | SIGNAL TXD2 : STD_LOGIC; |
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95 | 95 | SIGNAL RXD2 : STD_LOGIC; |
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96 | 96 | SIGNAL nCTS2 : STD_LOGIC; |
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97 | 97 | SIGNAL nDTR2 : STD_LOGIC; |
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98 | 98 | SIGNAL nRTS2 : STD_LOGIC; |
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99 | 99 | SIGNAL nDCD2 : STD_LOGIC; |
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100 | 100 | SIGNAL IO0 : STD_LOGIC; |
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101 | 101 | SIGNAL IO1 : STD_LOGIC; |
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102 | 102 | SIGNAL IO2 : STD_LOGIC; |
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103 | 103 | SIGNAL IO3 : STD_LOGIC; |
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104 | 104 | SIGNAL IO4 : STD_LOGIC; |
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105 | 105 | SIGNAL IO5 : STD_LOGIC; |
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106 | 106 | SIGNAL IO6 : STD_LOGIC; |
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107 | 107 | SIGNAL IO7 : STD_LOGIC; |
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108 | 108 | SIGNAL IO8 : STD_LOGIC; |
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109 | 109 | SIGNAL IO9 : STD_LOGIC; |
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110 | 110 | SIGNAL IO10 : STD_LOGIC; |
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111 | 111 | SIGNAL IO11 : STD_LOGIC; |
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112 | 112 | SIGNAL SPW_EN : STD_LOGIC; |
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113 | 113 | SIGNAL SPW_NOM_DIN : STD_LOGIC; |
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114 | 114 | SIGNAL SPW_NOM_SIN : STD_LOGIC; |
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115 | 115 | SIGNAL SPW_NOM_DOUT : STD_LOGIC; |
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116 | 116 | SIGNAL SPW_NOM_SOUT : STD_LOGIC; |
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117 | 117 | SIGNAL SPW_RED_DIN : STD_LOGIC; |
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118 | 118 | SIGNAL SPW_RED_SIN : STD_LOGIC; |
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119 | 119 | SIGNAL SPW_RED_DOUT : STD_LOGIC; |
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120 | 120 | SIGNAL SPW_RED_SOUT : STD_LOGIC; |
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121 | 121 | SIGNAL ADC_nCS : STD_LOGIC; |
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122 | 122 | SIGNAL ADC_CLK : STD_LOGIC; |
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123 | 123 | SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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124 | 124 | SIGNAL SRAM_nWE : STD_LOGIC; |
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125 | 125 | SIGNAL SRAM_CE : STD_LOGIC; |
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126 | 126 | SIGNAL SRAM_nOE : STD_LOGIC; |
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127 | 127 | SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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128 | 128 | SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); |
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129 | 129 | SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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130 | 130 | ----------------------------------------------------------------------------- |
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131 | 131 | |
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132 | 132 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; |
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133 | 133 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; |
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134 | 134 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; |
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135 | 135 | |
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136 | 136 | |
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137 | 137 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; |
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138 | 138 | |
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139 | 139 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; |
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140 | 140 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); |
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141 | 141 | |
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142 | 142 | BEGIN |
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143 | 143 | |
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144 | 144 | ----------------------------------------------------------------------------- |
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145 | 145 | -- TB |
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146 | 146 | ----------------------------------------------------------------------------- |
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147 | 147 | PROCESS |
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148 | 148 | CONSTANT txp : TIME := 320 ns; |
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149 | 149 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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150 | 150 | BEGIN -- PROCESS |
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151 | 151 | TXD1 <= '1'; |
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152 | 152 | reset <= '0'; |
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153 | 153 | WAIT FOR 500 ns; |
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154 | 154 | reset <= '1'; |
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155 | 155 | WAIT FOR 10000 ns; |
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156 | 156 | message_simu <= "0 - UART init "; |
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157 | 157 | UART_INIT(TXD1,txp); |
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158 | 158 | |
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159 | 159 | message_simu <= "1 - UART test "; |
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160 | 160 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); |
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161 | 161 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); |
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162 | 162 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); |
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163 | 163 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); |
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164 | 164 | data_read <= data_read_v; |
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165 | 165 | data_message <= "GPIO_data_write"; |
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166 | 166 | |
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167 | 167 | -- UNSET the LFR reset |
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168 | 168 | message_simu <= "2 - LFR UNRESET"; |
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169 | 169 | UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); |
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170 | 170 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); |
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171 | 171 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); |
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172 | 172 | -- |
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173 | 173 | message_simu <= "3 - LFR CONFIG "; |
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174 | UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); | |
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174 | --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); | |
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175 | LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, | |
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176 | X"40000000", | |
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177 | X"40001000", | |
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178 | X"40002000", | |
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179 | X"40003000", | |
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180 | X"40004000", | |
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181 | X"40005000"); | |
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182 | message_simu <= "4 - GO GO GO !!"; | |
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183 | UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); | |
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184 | ||
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185 | READ_STATUS: LOOP | |
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186 | WAIT FOR 2 ms; | |
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187 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); | |
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188 | data_read <= data_read_v; | |
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189 | data_message <= "READ_NEW_STATUS"; | |
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190 | UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); | |
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191 | END LOOP READ_STATUS; | |
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175 | 192 | |
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176 | 193 | WAIT; |
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177 | 194 | END PROCESS; |
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178 | 195 | |
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179 | 196 | ----------------------------------------------------------------------------- |
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180 | 197 | -- CLOCK |
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181 | 198 | ----------------------------------------------------------------------------- |
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182 | 199 | clk_50 <= NOT clk_50 AFTER 5 ns; |
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183 | 200 | clk_49 <= NOT clk_49 AFTER 10172 ps; |
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184 | 201 | |
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185 | 202 | ----------------------------------------------------------------------------- |
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186 | 203 | -- DON'T CARE |
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187 | 204 | ----------------------------------------------------------------------------- |
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188 | 205 | BP0 <= '0'; |
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189 | 206 | BP1 <= '0'; |
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190 | 207 | nRTS1 <= '0' ; |
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191 | 208 | |
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192 | 209 | TXD2 <= '1'; |
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193 | 210 | nRTS2 <= '1'; |
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194 | 211 | nDTR2 <= '1'; |
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195 | 212 | |
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196 | 213 | SPW_NOM_DIN <= '1'; |
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197 | 214 | SPW_NOM_SIN <= '1'; |
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198 | 215 | SPW_RED_DIN <= '1'; |
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199 | 216 | SPW_RED_SIN <= '1'; |
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200 | 217 | |
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201 | 218 | ADC_SDO <= x"AA"; |
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202 | 219 | |
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203 | 220 | SRAM_DQ <= (OTHERS => 'Z'); |
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204 | 221 | --IO0 <= 'Z'; |
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205 | 222 | --IO1 <= 'Z'; |
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206 | 223 | --IO2 <= 'Z'; |
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207 | 224 | --IO3 <= 'Z'; |
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208 | 225 | --IO4 <= 'Z'; |
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209 | 226 | --IO5 <= 'Z'; |
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210 | 227 | --IO6 <= 'Z'; |
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211 | 228 | --IO7 <= 'Z'; |
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212 | 229 | --IO8 <= 'Z'; |
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213 | 230 | --IO9 <= 'Z'; |
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214 | 231 | --IO10 <= 'Z'; |
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215 | 232 | --IO11 <= 'Z'; |
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216 | 233 | |
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217 | 234 | ----------------------------------------------------------------------------- |
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218 | 235 | -- DUT |
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219 | 236 | ----------------------------------------------------------------------------- |
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220 | 237 | MINI_LFR_top_1: MINI_LFR_top |
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221 | 238 | PORT MAP ( |
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222 | 239 | clk_50 => clk_50, |
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223 | 240 | clk_49 => clk_49, |
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224 | 241 | reset => reset, |
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225 | 242 | |
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226 | 243 | BP0 => BP0, |
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227 | 244 | BP1 => BP1, |
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228 | 245 | |
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229 | 246 | LED0 => LED0, |
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230 | 247 | LED1 => LED1, |
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231 | 248 | LED2 => LED2, |
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232 | 249 | |
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233 | 250 | TXD1 => TXD1, |
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234 | 251 | RXD1 => RXD1, |
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235 | 252 | nCTS1 => nCTS1, |
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236 | 253 | nRTS1 => nRTS1, |
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237 | 254 | |
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238 | 255 | TXD2 => TXD2, |
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239 | 256 | RXD2 => RXD2, |
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240 | 257 | nCTS2 => nCTS2, |
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241 | 258 | nDTR2 => nDTR2, |
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242 | 259 | nRTS2 => nRTS2, |
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243 | 260 | nDCD2 => nDCD2, |
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244 | 261 | |
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245 | 262 | IO0 => IO0, |
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246 | 263 | IO1 => IO1, |
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247 | 264 | IO2 => IO2, |
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248 | 265 | IO3 => IO3, |
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249 | 266 | IO4 => IO4, |
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250 | 267 | IO5 => IO5, |
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251 | 268 | IO6 => IO6, |
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252 | 269 | IO7 => IO7, |
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253 | 270 | IO8 => IO8, |
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254 | 271 | IO9 => IO9, |
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255 | 272 | IO10 => IO10, |
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256 | 273 | IO11 => IO11, |
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257 | 274 | |
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258 | 275 | SPW_EN => SPW_EN, |
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259 | 276 | SPW_NOM_DIN => SPW_NOM_DIN, |
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260 | 277 | SPW_NOM_SIN => SPW_NOM_SIN, |
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261 | 278 | SPW_NOM_DOUT => SPW_NOM_DOUT, |
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262 | 279 | SPW_NOM_SOUT => SPW_NOM_SOUT, |
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263 | 280 | SPW_RED_DIN => SPW_RED_DIN, |
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264 | 281 | SPW_RED_SIN => SPW_RED_SIN, |
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265 | 282 | SPW_RED_DOUT => SPW_RED_DOUT, |
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266 | 283 | SPW_RED_SOUT => SPW_RED_SOUT, |
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267 | 284 | |
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268 | 285 | ADC_nCS => ADC_nCS, |
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269 | 286 | ADC_CLK => ADC_CLK, |
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270 | 287 | ADC_SDO => ADC_SDO, |
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271 | 288 | |
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272 | 289 | SRAM_nWE => SRAM_nWE, |
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273 | 290 | SRAM_CE => SRAM_CE, |
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274 | 291 | SRAM_nOE => SRAM_nOE, |
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275 | 292 | SRAM_nBE => SRAM_nBE, |
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276 | 293 | SRAM_A => SRAM_A, |
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277 | 294 | SRAM_DQ => SRAM_DQ); |
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278 | 295 | |
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279 | 296 | |
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280 | 297 | END; |
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