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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
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14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
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16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe Pellion | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | ||
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23 | LIBRARY ieee; | |
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24 | USE ieee.std_logic_1164.ALL; | |
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25 | USE ieee.numeric_std.ALL; | |
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26 | LIBRARY grlib; | |
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27 | USE grlib.stdlib.ALL; | |
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28 | LIBRARY gaisler; | |
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29 | USE gaisler.libdcom.ALL; | |
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30 | USE gaisler.sim.ALL; | |
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31 | USE gaisler.jtagtst.ALL; | |
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32 | LIBRARY techmap; | |
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33 | USE techmap.gencomp.ALL; | |
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34 | LIBRARY lpp; | |
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35 | USE lpp.lpp_sim_pkg.ALL; | |
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36 | USE lpp.lpp_lfr_apbreg_pkg.ALL; | |
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37 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; | |
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38 | ||
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39 | PACKAGE lpp_lfr_sim_pkg IS | |
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40 | ||
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41 | PROCEDURE UNRESET_LFR ( | |
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42 | SIGNAL TX : OUT STD_LOGIC; | |
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43 | CONSTANT tx_period : IN TIME; | |
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44 | CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8) | |
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45 | ); | |
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46 | ||
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47 | PROCEDURE LAUNCH_SPECTRAL_MATRIX( | |
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48 | SIGNAL TX : OUT STD_LOGIC; | |
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49 | SIGNAL RX : IN STD_LOGIC; | |
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50 | CONSTANT tx_period : IN TIME; | |
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51 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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52 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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53 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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54 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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55 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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56 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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57 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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58 | ); | |
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59 | ||
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60 | ----------------------------------------------------------------------------- | |
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61 | -- SM function | |
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62 | ----------------------------------------------------------------------------- | |
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63 | ||
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64 | PROCEDURE RESET_SPECTRAL_MATRIX_REGS( | |
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65 | SIGNAL TX : OUT STD_LOGIC; | |
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66 | SIGNAL RX : IN STD_LOGIC; | |
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67 | CONSTANT tx_period : IN TIME; | |
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68 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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69 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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70 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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71 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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72 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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73 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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74 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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75 | ); | |
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76 | ||
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77 | PROCEDURE SET_SM_IRQ_onNewMatrix( | |
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78 | SIGNAL TX : OUT STD_LOGIC; | |
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79 | SIGNAL RX : IN STD_LOGIC; | |
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80 | CONSTANT tx_period : IN TIME; | |
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81 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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82 | CONSTANT PARAM_value : IN STD_LOGIC | |
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83 | ); | |
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84 | ||
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85 | PROCEDURE SET_SM_IRQ_ERROR( | |
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86 | SIGNAL TX : OUT STD_LOGIC; | |
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87 | SIGNAL RX : IN STD_LOGIC; | |
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88 | CONSTANT tx_period : IN TIME; | |
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89 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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90 | CONSTANT PARAM_value : IN STD_LOGIC | |
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91 | ); | |
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92 | ||
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93 | PROCEDURE RESET_SM_STATUS( | |
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94 | SIGNAL TX : OUT STD_LOGIC; | |
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95 | SIGNAL RX : IN STD_LOGIC; | |
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96 | CONSTANT tx_period : IN TIME; | |
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97 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) | |
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98 | ); | |
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99 | ||
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100 | END lpp_lfr_sim_pkg; | |
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101 | ||
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102 | ||
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103 | ||
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104 | PACKAGE BODY lpp_lfr_sim_pkg IS | |
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105 | ||
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106 | PROCEDURE UNRESET_LFR ( | |
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107 | SIGNAL TX : OUT STD_LOGIC; | |
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108 | CONSTANT tx_period : IN TIME; | |
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109 | CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)) | |
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110 | IS | |
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111 | BEGIN | |
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112 | UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); | |
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113 | UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); | |
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114 | END; | |
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115 | ||
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116 | PROCEDURE LAUNCH_SPECTRAL_MATRIX( | |
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117 | SIGNAL TX : OUT STD_LOGIC; | |
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118 | SIGNAL RX : IN STD_LOGIC; | |
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119 | CONSTANT tx_period : IN TIME; | |
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120 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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121 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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122 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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123 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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124 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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125 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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126 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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127 | ) | |
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128 | IS | |
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129 | BEGIN | |
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130 | RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR, | |
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131 | PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr, | |
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132 | PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr); | |
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133 | SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR, | |
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134 | '1'); | |
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135 | END; | |
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136 | ||
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137 | ----------------------------------------------------------------------------- | |
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138 | -- SM function | |
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139 | ----------------------------------------------------------------------------- | |
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140 | PROCEDURE RESET_SPECTRAL_MATRIX_REGS( | |
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141 | SIGNAL TX : OUT STD_LOGIC; | |
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142 | SIGNAL RX : IN STD_LOGIC; | |
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143 | CONSTANT tx_period : IN TIME; | |
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144 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8); | |
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145 | CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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146 | CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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147 | CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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148 | CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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149 | CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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150 | CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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151 | ) | |
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152 | IS | |
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153 | BEGIN | |
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154 | SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0'); | |
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155 | SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0'); | |
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156 | RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR); | |
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157 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr); | |
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158 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr); | |
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159 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr); | |
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160 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr); | |
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161 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr); | |
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162 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr); | |
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163 | UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8"); | |
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164 | END; | |
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165 | ||
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166 | PROCEDURE SET_SM_IRQ_onNewMatrix( | |
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167 | SIGNAL TX : OUT STD_LOGIC; | |
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168 | SIGNAL RX : IN STD_LOGIC; | |
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169 | CONSTANT tx_period : IN TIME; | |
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170 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ; | |
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171 | CONSTANT PARAM_value : IN STD_LOGIC | |
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172 | ) | |
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173 | IS | |
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174 | VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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175 | BEGIN | |
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176 | UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read); | |
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177 | IF PARAM_value = '1' THEN | |
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178 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' ); | |
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179 | ELSE | |
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180 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' ); | |
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181 | END IF; | |
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182 | END; | |
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183 | ||
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184 | PROCEDURE SET_SM_IRQ_ERROR( | |
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185 | SIGNAL TX : OUT STD_LOGIC; | |
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186 | SIGNAL RX : IN STD_LOGIC; | |
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187 | CONSTANT tx_period : IN TIME; | |
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188 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ; | |
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189 | CONSTANT PARAM_value : IN STD_LOGIC | |
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190 | ) | |
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191 | IS | |
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192 | VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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193 | BEGIN | |
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194 | UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read); | |
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195 | IF PARAM_value = '1' THEN | |
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196 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) ); | |
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197 | ELSE | |
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198 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) ); | |
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199 | END IF; | |
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200 | END; | |
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201 | ||
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202 | PROCEDURE RESET_SM_STATUS( | |
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203 | SIGNAL TX : OUT STD_LOGIC; | |
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204 | SIGNAL RX : IN STD_LOGIC; | |
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205 | CONSTANT tx_period : IN TIME; | |
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206 | CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) | |
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207 | ) | |
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208 | IS | |
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209 | BEGIN | |
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210 | UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF"); | |
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211 | END; | |
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212 | ||
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213 | END lpp_lfr_sim_pkg; |
@@ -171,7 +171,24 BEGIN | |||
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171 | 171 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); |
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172 | 172 | -- |
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173 | 173 | message_simu <= "3 - LFR CONFIG "; |
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174 | UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); | |
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174 | --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); | |
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175 | LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, | |
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176 | X"40000000", | |
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177 | X"40001000", | |
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178 | X"40002000", | |
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179 | X"40003000", | |
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180 | X"40004000", | |
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181 | X"40005000"); | |
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182 | message_simu <= "4 - GO GO GO !!"; | |
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183 | UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); | |
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184 | ||
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185 | READ_STATUS: LOOP | |
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186 | WAIT FOR 2 ms; | |
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187 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); | |
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188 | data_read <= data_read_v; | |
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189 | data_message <= "READ_NEW_STATUS"; | |
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190 | UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); | |
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191 | END LOOP READ_STATUS; | |
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175 | 192 | |
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176 | 193 | WAIT; |
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177 | 194 | END PROCESS; |
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