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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 COMPONENT lpp_lfr_ms_tb
118 GENERIC (
119 Mem_use : INTEGER);
120 PORT (
121 clk : IN STD_LOGIC;
122 rstn : IN STD_LOGIC;
123 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
124 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
126 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
127 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
128 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
130 MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
131 MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
132 MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
133 MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
134 MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
135 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
136 observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
137 observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
138 END COMPONENT;
139
140 COMPONENT lpp_lfr_apbreg_tb
141 GENERIC (
142 pindex : INTEGER;
143 paddr : INTEGER;
144 pmask : INTEGER);
145 PORT (
146 HCLK : IN STD_ULOGIC;
147 HRESETn : IN STD_ULOGIC;
148 apbi : IN apb_slv_in_type;
149 apbo : OUT apb_slv_out_type;
150 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
151 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
152 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
153 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
154 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
155 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
156 MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
157 MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
158 MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
159 MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
160 MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
161 MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
162 END COMPONENT;
163
164
165
166 SIGNAL clk_50_s : STD_LOGIC := '0';
167 SIGNAL clk_25 : STD_LOGIC := '0';
168 SIGNAL clk_24 : STD_LOGIC := '0';
169 -----------------------------------------------------------------------------
170 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
172 --
173 SIGNAL errorn : STD_LOGIC;
174 -- UART AHB ---------------------------------------------------------------
175 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
176 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
177
178 -- UART APB ---------------------------------------------------------------
179 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
180 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
181 --
182 SIGNAL I00_s : STD_LOGIC;
183
184 -- CONSTANTS
185 CONSTANT CFG_PADTECH : INTEGER := inferred;
186 --
187 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
188 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
189 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
190
191 SIGNAL apbi_ext : apb_slv_in_type;
192 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
193 SIGNAL ahbi_s_ext : ahb_slv_in_type;
194 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
195 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
196 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
197
198 -- Spacewire signals
199 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
200 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL spw_rxtxclk : STD_ULOGIC;
203 SIGNAL spw_rxclkn : STD_ULOGIC;
204 SIGNAL spw_clk : STD_LOGIC;
205 SIGNAL swni : grspw_in_type;
206 SIGNAL swno : grspw_out_type;
207 -- SIGNAL clkmn : STD_ULOGIC;
208 -- SIGNAL txclk : STD_ULOGIC;
209
210 --GPIO
211 SIGNAL gpioi : gpio_in_type;
212 SIGNAL gpioo : gpio_out_type;
213
214 -- AD Converter ADS7886
215 SIGNAL sample : Samples14v(7 DOWNTO 0);
216 SIGNAL sample_s : Samples(7 DOWNTO 0);
217 SIGNAL sample_val : STD_LOGIC;
218 SIGNAL ADC_nCS_sig : STD_LOGIC;
219 SIGNAL ADC_CLK_sig : STD_LOGIC;
220 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
221
222 SIGNAL bias_fail_sw_sig : STD_LOGIC;
223
224 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
226 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
227 -----------------------------------------------------------------------------
228
229
230 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
232 --
233 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
234 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
235 --
236 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
238
239
240 ---------------------------------------------------------------------------
241 --
242 ---------------------------------------------------------------------------
243 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
244 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
245 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
246 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
247 SIGNAL MEM_IN_SM_Full_pad : STD_LOGIC_VECTOR(4 DOWNTO 0);
248 SIGNAL MEM_IN_SM_Empty_pad : STD_LOGIC_VECTOR(4 DOWNTO 0);
249
250
251
252 BEGIN -- beh
253
254 -----------------------------------------------------------------------------
255 -- CLK
256 -----------------------------------------------------------------------------
257
258 PROCESS(clk_50)
259 BEGIN
260 IF clk_50'EVENT AND clk_50 = '1' THEN
261 clk_50_s <= NOT clk_50_s;
262 END IF;
263 END PROCESS;
264
265 PROCESS(clk_50_s)
266 BEGIN
267 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
268 clk_25 <= NOT clk_25;
269 END IF;
270 END PROCESS;
271
272 PROCESS(clk_49)
273 BEGIN
274 IF clk_49'EVENT AND clk_49 = '1' THEN
275 clk_24 <= NOT clk_24;
276 END IF;
277 END PROCESS;
278
279 -----------------------------------------------------------------------------
280
281 PROCESS (clk_25, reset)
282 BEGIN -- PROCESS
283 IF reset = '0' THEN -- asynchronous reset (active low)
284 LED0 <= '0';
285 LED1 <= '0';
286 LED2 <= '0';
287 --IO1 <= '0';
288 --IO2 <= '1';
289 --IO3 <= '0';
290 --IO4 <= '0';
291 --IO5 <= '0';
292 --IO6 <= '0';
293 --IO7 <= '0';
294 --IO8 <= '0';
295 --IO9 <= '0';
296 --IO10 <= '0';
297 --IO11 <= '0';
298 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
299 LED0 <= '0';
300 LED1 <= '1';
301 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
302 --IO1 <= '1';
303 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
304 --IO3 <= ADC_SDO(0);
305 --IO4 <= ADC_SDO(1);
306 --IO5 <= ADC_SDO(2);
307 --IO6 <= ADC_SDO(3);
308 --IO7 <= ADC_SDO(4);
309 --IO8 <= ADC_SDO(5);
310 --IO9 <= ADC_SDO(6);
311 --IO10 <= ADC_SDO(7);
312 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
313 END IF;
314 END PROCESS;
315
316 PROCESS (clk_24, reset)
317 BEGIN -- PROCESS
318 IF reset = '0' THEN -- asynchronous reset (active low)
319 I00_s <= '0';
320 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
321 I00_s <= NOT I00_s;
322 END IF;
323 END PROCESS;
324 -- IO0 <= I00_s;
325
326 --UARTs
327 nCTS1 <= '1';
328 nCTS2 <= '1';
329 nDCD2 <= '1';
330
331 --EXT CONNECTOR
332
333 --SPACE WIRE
334
335 leon3_soc_1 : leon3_soc
336 GENERIC MAP (
337 fabtech => apa3e,
338 memtech => apa3e,
339 padtech => inferred,
340 clktech => inferred,
341 disas => 0,
342 dbguart => 0,
343 pclow => 2,
344 clk_freq => 25000,
345 NB_CPU => 1,
346 ENABLE_FPU => 1,
347 FPU_NETLIST => 0,
348 ENABLE_DSU => 1,
349 ENABLE_AHB_UART => 1,
350 ENABLE_APB_UART => 1,
351 ENABLE_IRQMP => 1,
352 ENABLE_GPT => 1,
353 NB_AHB_MASTER => NB_AHB_MASTER,
354 NB_AHB_SLAVE => NB_AHB_SLAVE,
355 NB_APB_SLAVE => NB_APB_SLAVE)
356 PORT MAP (
357 clk => clk_25,
358 reset => reset,
359 errorn => errorn,
360 ahbrxd => TXD1,
361 ahbtxd => RXD1,
362 urxd1 => TXD2,
363 utxd1 => RXD2,
364 address => SRAM_A,
365 data => SRAM_DQ,
366 nSRAM_BE0 => SRAM_nBE(0),
367 nSRAM_BE1 => SRAM_nBE(1),
368 nSRAM_BE2 => SRAM_nBE(2),
369 nSRAM_BE3 => SRAM_nBE(3),
370 nSRAM_WE => SRAM_nWE,
371 nSRAM_CE => SRAM_CE,
372 nSRAM_OE => SRAM_nOE,
373
374 apbi_ext => apbi_ext,
375 apbo_ext => apbo_ext,
376 ahbi_s_ext => ahbi_s_ext,
377 ahbo_s_ext => ahbo_s_ext,
378 ahbi_m_ext => ahbi_m_ext,
379 ahbo_m_ext => ahbo_m_ext);
380
381 -------------------------------------------------------------------------------
382 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
383 -------------------------------------------------------------------------------
384 apb_lfr_time_management_1 : apb_lfr_time_management
385 GENERIC MAP (
386 pindex => 6,
387 paddr => 6,
388 pmask => 16#fff#,
389 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
390 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
391 PORT MAP (
392 clk25MHz => clk_25,
393 clk24_576MHz => clk_24, -- 49.152MHz/2
394 resetn => reset,
395 grspw_tick => swno.tickout,
396 apbi => apbi_ext,
397 apbo => apbo_ext(6),
398 coarse_time => coarse_time,
399 fine_time => fine_time);
400
401 -----------------------------------------------------------------------
402 --- SpaceWire --------------------------------------------------------
403 -----------------------------------------------------------------------
404
405 SPW_EN <= '1';
406
407 spw_clk <= clk_50_s;
408 spw_rxtxclk <= spw_clk;
409 spw_rxclkn <= NOT spw_rxtxclk;
410
411 -- PADS for SPW1
412 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
413 PORT MAP (SPW_NOM_DIN, dtmp(0));
414 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_NOM_SIN, stmp(0));
416 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_DOUT, swno.d(0));
418 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SOUT, swno.s(0));
420 -- PADS FOR SPW2
421 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
422 PORT MAP (SPW_RED_SIN, dtmp(1));
423 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
424 PORT MAP (SPW_RED_DIN, stmp(1));
425 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_RED_DOUT, swno.d(1));
427 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
428 PORT MAP (SPW_RED_SOUT, swno.s(1));
429
430 -- GRSPW PHY
431 --spw1_input: if CFG_SPW_GRSPW = 1 generate
432 spw_inputloop : FOR j IN 0 TO 1 GENERATE
433 spw_phy0 : grspw_phy
434 GENERIC MAP(
435 tech => apa3e,
436 rxclkbuftype => 1,
437 scantest => 0)
438 PORT MAP(
439 rxrst => swno.rxrst,
440 di => dtmp(j),
441 si => stmp(j),
442 rxclko => spw_rxclk(j),
443 do => swni.d(j),
444 ndo => swni.nd(j*5+4 DOWNTO j*5),
445 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
446 END GENERATE spw_inputloop;
447
448 -- SPW core
449 sw0 : grspwm GENERIC MAP(
450 tech => apa3e,
451 hindex => 1,
452 pindex => 5,
453 paddr => 5,
454 pirq => 11,
455 sysfreq => 25000, -- CPU_FREQ
456 rmap => 1,
457 rmapcrc => 1,
458 fifosize1 => 16,
459 fifosize2 => 16,
460 rxclkbuftype => 1,
461 rxunaligned => 0,
462 rmapbufs => 4,
463 ft => 0,
464 netlist => 0,
465 ports => 2,
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
467 memtech => apa3e,
468 destkey => 2,
469 spwcore => 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
473 )
474 PORT MAP(reset, clk_25, spw_rxclk(0),
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
477 swni, swno);
478
479 swni.tickin <= '0';
480 swni.rmapen <= '1';
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
482 swni.tickinraw <= '0';
483 swni.timein <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
486
487 -------------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
490 --lpp_lfr_1 : lpp_lfr
491 -- GENERIC MAP (
492 -- Mem_use => use_RAM,
493 -- nb_data_by_buffer_size => 32,
494 -- nb_word_by_buffer_size => 30,
495 -- nb_snapshot_param_size => 32,
496 -- delta_vector_size => 32,
497 -- delta_vector_size_f0_2 => 7, -- log2(96)
498 -- pindex => 15,
499 -- paddr => 15,
500 -- pmask => 16#fff#,
501 -- pirq_ms => 6,
502 -- pirq_wfp => 14,
503 -- hindex => 2,
504 -- top_lfr_version => X"000117") -- aa.bb.cc version
505 -- PORT MAP (
506 -- clk => clk_25,
507 -- rstn => reset,
508 -- sample_B => sample_s(2 DOWNTO 0),
509 -- sample_E => sample_s(7 DOWNTO 3),
510 -- sample_val => sample_val,
511 -- apbi => apbi_ext,
512 -- apbo => apbo_ext(15),
513 -- ahbi => ahbi_m_ext,
514 -- ahbo => ahbo_m_ext(2),
515 -- coarse_time => coarse_time,
516 -- fine_time => fine_time,
517 -- data_shaping_BW => bias_fail_sw_sig,
518 -- observation_vector_0=> observation_vector_0,
519 -- observation_vector_1 => observation_vector_1,
520 -- observation_reg => observation_reg);
521
522 lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
523 GENERIC MAP (
524 pindex => 15,
525 paddr => 15,
526 pmask => 16#fff#)
527 PORT MAP (
528 HCLK => clk_25,
529 HRESETn => reset,
530 apbi => apbi_ext,
531 apbo => apbo_ext(15),
532
533 sample_f0_wen => sample_f0_wen,
534 sample_f1_wen => sample_f1_wen,
535 sample_f2_wen => sample_f2_wen,
536 sample_f0_wdata => sample_f0_wdata,
537 sample_f1_wdata => sample_f1_wdata,
538 sample_f2_wdata => sample_f2_wdata,
539 MEM_IN_SM_locked => MEM_IN_SM_locked,
540 MEM_IN_SM_ReUse => MEM_IN_SM_ReUse,
541 MEM_IN_SM_ren => MEM_IN_SM_ren,
542 MEM_IN_SM_rData => MEM_IN_SM_rData,
543 MEM_IN_SM_Full => MEM_IN_SM_Full_pad,
544 MEM_IN_SM_Empty => MEM_IN_SM_Empty_pad);
545
546 lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb
547 GENERIC MAP (
548 Mem_use =>use_RAM)
549 PORT MAP (
550 clk => clk_25,
551 rstn => reset,
552 sample_f0_wen => sample_f0_wen,
553 sample_f0_wdata => sample_f0_wdata,
554 sample_f1_wen => sample_f1_wen,
555 sample_f1_wdata => sample_f1_wdata,
556 sample_f2_wen => sample_f2_wen,
557 sample_f2_wdata => sample_f2_wdata,
558
559 MEM_IN_SM_locked => MEM_IN_SM_locked,
560 MEM_IN_SM_ReUse => MEM_IN_SM_ReUse,
561 MEM_IN_SM_ren => MEM_IN_SM_ren,
562 MEM_IN_SM_rData => MEM_IN_SM_rData,
563 MEM_IN_SM_Full_pad => MEM_IN_SM_Full_pad,
564 MEM_IN_SM_Empty_pad => MEM_IN_SM_Empty_pad,
565
566 error_input_fifo_write => OPEN,
567 observation_vector_0 => observation_vector_0,
568 observation_vector_1 => observation_vector_1);
569
570 -----------------------------------------------------------------------------
571
572
573
574
575
576 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
577 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
578 END GENERATE all_sample;
579
580
581
582 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
583 GENERIC MAP(
584 ChannelCount => 8,
585 SampleNbBits => 14,
586 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
587 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
588 PORT MAP (
589 -- CONV
590 cnv_clk => clk_24,
591 cnv_rstn => reset,
592 cnv => ADC_nCS_sig,
593 -- DATA
594 clk => clk_25,
595 rstn => reset,
596 sck => ADC_CLK_sig,
597 sdo => ADC_SDO_sig,
598 -- SAMPLE
599 sample => sample,
600 sample_val => sample_val);
601
602 --IO10 <= ADC_SDO_sig(5);
603 --IO9 <= ADC_SDO_sig(4);
604 --IO8 <= ADC_SDO_sig(3);
605
606 ADC_nCS <= ADC_nCS_sig;
607 ADC_CLK <= ADC_CLK_sig;
608 ADC_SDO_sig <= ADC_SDO;
609
610 ----------------------------------------------------------------------
611 --- GPIO -----------------------------------------------------------
612 ----------------------------------------------------------------------
613
614 grgpio0 : grgpio
615 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
616 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
617
618 --pio_pad_0 : iopad
619 -- GENERIC MAP (tech => CFG_PADTECH)
620 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
621 --pio_pad_1 : iopad
622 -- GENERIC MAP (tech => CFG_PADTECH)
623 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
624 --pio_pad_2 : iopad
625 -- GENERIC MAP (tech => CFG_PADTECH)
626 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
627 --pio_pad_3 : iopad
628 -- GENERIC MAP (tech => CFG_PADTECH)
629 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
630 --pio_pad_4 : iopad
631 -- GENERIC MAP (tech => CFG_PADTECH)
632 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
633 --pio_pad_5 : iopad
634 -- GENERIC MAP (tech => CFG_PADTECH)
635 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
636 --pio_pad_6 : iopad
637 -- GENERIC MAP (tech => CFG_PADTECH)
638 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
639 --pio_pad_7 : iopad
640 -- GENERIC MAP (tech => CFG_PADTECH)
641 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
642
643 PROCESS (clk_25, reset)
644 BEGIN -- PROCESS
645 IF reset = '0' THEN -- asynchronous reset (active low)
646 IO0 <= '0';
647 IO1 <= '0';
648 IO2 <= '0';
649 IO3 <= '0';
650 IO4 <= '0';
651 IO5 <= '0';
652 IO6 <= '0';
653 IO7 <= '0';
654 IO8 <= '0';
655 IO9 <= '0';
656 IO10 <= '0';
657 IO11 <= '0';
658 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
659 CASE gpioo.dout(2 DOWNTO 0) IS
660 WHEN "011" =>
661 IO0 <= observation_reg(0);
662 IO1 <= observation_reg(1);
663 IO2 <= observation_reg(2);
664 IO3 <= observation_reg(3);
665 IO4 <= observation_reg(4);
666 IO5 <= observation_reg(5);
667 IO6 <= observation_reg(6);
668 IO7 <= observation_reg(7);
669 IO8 <= observation_reg(8);
670 IO9 <= observation_reg(9);
671 IO10 <= observation_reg(10);
672 IO11 <= observation_reg(11);
673 WHEN "001" =>
674 IO0 <= observation_reg(0 + 12);
675 IO1 <= observation_reg(1 + 12);
676 IO2 <= observation_reg(2 + 12);
677 IO3 <= observation_reg(3 + 12);
678 IO4 <= observation_reg(4 + 12);
679 IO5 <= observation_reg(5 + 12);
680 IO6 <= observation_reg(6 + 12);
681 IO7 <= observation_reg(7 + 12);
682 IO8 <= observation_reg(8 + 12);
683 IO9 <= observation_reg(9 + 12);
684 IO10 <= observation_reg(10 + 12);
685 IO11 <= observation_reg(11 + 12);
686 WHEN "010" =>
687 IO0 <= observation_reg(0 + 12 + 12);
688 IO1 <= observation_reg(1 + 12 + 12);
689 IO2 <= observation_reg(2 + 12 + 12);
690 IO3 <= observation_reg(3 + 12 + 12);
691 IO4 <= observation_reg(4 + 12 + 12);
692 IO5 <= observation_reg(5 + 12 + 12);
693 IO6 <= observation_reg(6 + 12 + 12);
694 IO7 <= observation_reg(7 + 12 + 12);
695 IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2);
696 IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5);
697 IO10 <= ADC_SDO(6) OR ADC_SDO(7) ;
698 IO11 <= '0';
699 WHEN "000" =>
700 IO0 <= observation_vector_0(0);
701 IO1 <= observation_vector_0(1);
702 IO2 <= observation_vector_0(2);
703 IO3 <= observation_vector_0(3);
704 IO4 <= observation_vector_0(4);
705 IO5 <= observation_vector_0(5);
706 IO6 <= observation_vector_0(6);
707 IO7 <= observation_vector_0(7);
708 IO8 <= observation_vector_0(8);
709 IO9 <= observation_vector_0(9);
710 IO10 <= observation_vector_0(10);
711 IO11 <= observation_vector_0(11);
712 WHEN "100" =>
713 IO0 <= observation_vector_1(0);
714 IO1 <= observation_vector_1(1);
715 IO2 <= observation_vector_1(2);
716 IO3 <= observation_vector_1(3);
717 IO4 <= observation_vector_1(4);
718 IO5 <= observation_vector_1(5);
719 IO6 <= observation_vector_1(6);
720 IO7 <= observation_vector_1(7);
721 IO8 <= observation_vector_1(8);
722 IO9 <= observation_vector_1(9);
723 IO10 <= observation_vector_1(10);
724 IO11 <= observation_vector_1(11);
725 WHEN OTHERS => NULL;
726 END CASE;
727
728 END IF;
729 END PROCESS;
730
731 END beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_uart \
33 ./lpp_usb \
34 ./dsp/lpp_fft_rtax \
35 ./lpp_sim/CY7C1061DV33 \
36
37 FILESKIP =i2cmst.vhd \
38 APB_MULTI_DIODE.vhd \
39 APB_SIMPLE_DIODE.vhd \
40 Top_MatrixSpec.vhd \
41 APB_FFT.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 );
26 END;
27
28 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
29
30 BEGIN
31
32 -----------------------------------------------------------------------------
33
34 lppFIFOxN_f0_a : lppFIFOxN
35 GENERIC MAP (
36 tech => 0,
37 Mem_use => Mem_use,
38 Data_sz => 16,
39 Addr_sz => 8,
40 FifoCnt => 5)
41 PORT MAP (
42 clk => clk,
43 rstn => rstn,
44
45 ReUse => (OTHERS => '0'),
46
47 wen => sample_f0_A_wen,
48 wdata => sample_f0_wdata,
49
50 ren => sample_f0_A_ren,
51 rdata => sample_f0_A_rdata,
52
53 empty => sample_f0_A_empty,
54 full => sample_f0_A_full,
55 almost_full => OPEN);
56
57 -----------------------------------------------------------------------------
58
59 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
60 PORT MAP (
61 clk => clk,
62 rstn => rstn,
63 sample_valid => sample_valid, -- WRITE in
64 fft_read => fft_read, -- READ in
65 sample_data => sample_data, -- WRITE in
66 sample_load => sample_load, -- WRITE out
67 fft_pong => fft_pong, -- READ out
68 fft_data_im => fft_data_im, -- READ out
69 fft_data_re => fft_data_re, -- READ out
70 fft_data_valid => fft_data_valid, -- READ out
71 fft_ready => fft_ready); -- READ out
72
73 -----------------------------------------------------------------------------
74
75 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY lpp_lfr_apbreg_tb IS
39 GENERIC (
40 pindex : INTEGER := 4;
41 paddr : INTEGER := 4;
42 pmask : INTEGER := 16#fff#);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 ---------------------------------------------------------------------------
53 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
54 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
56
57 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 ---------------------------------------------------------------------------
61 MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
62 MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
63 MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
64 MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
65 MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
66 MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
67 ---------------------------------------------------------------------------
68 );
69
70 END lpp_lfr_apbreg_tb;
71
72 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
73
74 CONSTANT REVISION : INTEGER := 1;
75
76 CONSTANT pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1),
78 1 => apb_iobar(paddr, pmask));
79
80 TYPE reg_debug_fft IS RECORD
81 in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
82 in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
83 in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
84
85 in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 --
89 out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 END RECORD;
93 SIGNAL reg_ftt : reg_debug_fft;
94
95 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
96
97 BEGIN -- beh
98
99 ---------------------------------------------------------------------------
100 sample_f0_wen <= reg_ftt.in_wen_f0;
101 sample_f1_wen <= reg_ftt.in_wen_f1;
102 sample_f2_wen <= reg_ftt.in_wen_f2;
103
104 sample_f0_wdata <= reg_ftt.in_data_f0;
105 sample_f1_wdata <= reg_ftt.in_data_f1;
106 sample_f2_wdata <= reg_ftt.in_data_f2;
107 ---------------------------------------------------------------------------
108 MEM_IN_SM_ReUse <= reg_ftt.out_reuse;
109 MEM_IN_SM_locked <= reg_ftt.out_locked;
110 MEM_IN_SM_ren <= reg_ftt.out_ren;
111 ---------------------------------------------------------------------------
112
113 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
114 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
115 BEGIN
116 IF HRESETn = '0' THEN
117
118 reg_ftt.in_data_f0 <= (OTHERS => '0');
119 reg_ftt.in_data_f1 <= (OTHERS => '0');
120 reg_ftt.in_data_f2 <= (OTHERS => '0');
121
122 reg_ftt.in_wen_f0 <= (OTHERS => '1');
123 reg_ftt.in_wen_f1 <= (OTHERS => '1');
124 reg_ftt.in_wen_f2 <= (OTHERS => '1');
125
126
127 reg_ftt.out_reuse <= (OTHERS => '0');
128 reg_ftt.out_locked <= (OTHERS => '0');
129 reg_ftt.out_ren <= (OTHERS => '1');
130
131 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
132
133
134 reg_ftt.in_wen_f0 <= (OTHERS => '1');
135 reg_ftt.in_wen_f1 <= (OTHERS => '1');
136 reg_ftt.in_wen_f2 <= (OTHERS => '1');
137 reg_ftt.out_ren <= (OTHERS => '1');
138
139 paddr := "000000";
140 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
141 prdata <= (OTHERS => '0');
142 IF apbi.psel(pindex) = '1' THEN
143 -- APB DMA READ --
144 CASE paddr(7 DOWNTO 2) IS
145 --0
146 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0);
147 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32);
148 WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64);
149 WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0;
150
151 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0);
152 WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32);
153 WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64);
154 WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1;
155
156 WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0);
157 WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32);
158 WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64);
159 WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2;
160
161 WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0);
162 WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1);
163 WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2);
164 WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3);
165 WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4);
166
167 WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren;
168 prdata(9 DOWNTO 5) <= reg_ftt.out_reuse;
169 prdata(14 DOWNTO 10) <= reg_ftt.out_locked;
170 prdata(19 DOWNTO 15) <= MEM_IN_SM_Full;
171 prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty;
172 WHEN OTHERS => NULL;
173
174 END CASE;
175 IF (apbi.pwrite AND apbi.penable) = '1' THEN
176 -- APB DMA WRITE --
177 CASE paddr(7 DOWNTO 2) IS
178 WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata;
179 WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata;
180 WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
181 WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0);
182
183 WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata;
184 WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata;
185 WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
186 WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0);
187
188 WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata;
189 WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata;
190 WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
191 WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0);
192
193 WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0);
194 reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5);
195 reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10);
196
197 WHEN OTHERS => NULL;
198 END CASE;
199 END IF;
200 END IF;
201
202 END IF;
203 END PROCESS lpp_lfr_apbreg;
204
205 apbo.pindex <= pindex;
206 apbo.pconfig <= pconfig;
207 apbo.prdata <= prdata;
208
209 END beh;
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@@ -0,0 +1,209
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY lpp_lfr_apbreg_tb IS
39 GENERIC (
40 pindex : INTEGER := 4;
41 paddr : INTEGER := 4;
42 pmask : INTEGER := 16#fff#);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 ---------------------------------------------------------------------------
53 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
54 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
56
57 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 ---------------------------------------------------------------------------
61 MEM_IN_SM_locked : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
62 MEM_IN_SM_ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
63 MEM_IN_SM_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
64 MEM_IN_SM_rData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
65 MEM_IN_SM_Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
66 MEM_IN_SM_Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
67 ---------------------------------------------------------------------------
68 );
69
70 END lpp_lfr_apbreg_tb;
71
72 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
73
74 CONSTANT REVISION : INTEGER := 1;
75
76 CONSTANT pconfig : apb_config_type := (
77 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, 1),
78 1 => apb_iobar(paddr, pmask));
79
80 TYPE reg_debug_fft IS RECORD
81 in_data_f0 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
82 in_data_f1 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
83 in_data_f2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
84
85 in_wen_f0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 in_wen_f1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 in_wen_f2 : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 --
89 out_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 out_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 out_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 END RECORD;
93 SIGNAL reg_ftt : reg_debug_fft;
94
95 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
96
97 BEGIN -- beh
98
99 ---------------------------------------------------------------------------
100 sample_f0_wen <= reg_ftt.in_wen_f0;
101 sample_f1_wen <= reg_ftt.in_wen_f1;
102 sample_f2_wen <= reg_ftt.in_wen_f2;
103
104 sample_f0_wdata <= reg_ftt.in_data_f0;
105 sample_f1_wdata <= reg_ftt.in_data_f1;
106 sample_f2_wdata <= reg_ftt.in_data_f2;
107 ---------------------------------------------------------------------------
108 MEM_IN_SM_ReUse <= reg_ftt.out_reuse;
109 MEM_IN_SM_locked <= reg_ftt.out_locked;
110 MEM_IN_SM_ren <= reg_ftt.out_ren;
111 ---------------------------------------------------------------------------
112
113 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
114 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
115 BEGIN
116 IF HRESETn = '0' THEN
117
118 reg_ftt.in_data_f0 <= (OTHERS => '0');
119 reg_ftt.in_data_f1 <= (OTHERS => '0');
120 reg_ftt.in_data_f2 <= (OTHERS => '0');
121
122 reg_ftt.in_wen_f0 <= (OTHERS => '1');
123 reg_ftt.in_wen_f1 <= (OTHERS => '1');
124 reg_ftt.in_wen_f2 <= (OTHERS => '1');
125
126
127 reg_ftt.out_reuse <= (OTHERS => '0');
128 reg_ftt.out_locked <= (OTHERS => '0');
129 reg_ftt.out_ren <= (OTHERS => '1');
130
131 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
132
133
134 reg_ftt.in_wen_f0 <= (OTHERS => '1');
135 reg_ftt.in_wen_f1 <= (OTHERS => '1');
136 reg_ftt.in_wen_f2 <= (OTHERS => '1');
137 reg_ftt.out_ren <= (OTHERS => '1');
138
139 paddr := "000000";
140 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
141 prdata <= (OTHERS => '0');
142 IF apbi.psel(pindex) = '1' THEN
143 -- APB DMA READ --
144 CASE paddr(7 DOWNTO 2) IS
145 --0
146 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(31 DOWNTO 0);
147 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f0(63 DOWNTO 32);
148 WHEN "000010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f0(79 DOWNTO 64);
149 WHEN "000011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f0;
150
151 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(31 DOWNTO 0);
152 WHEN "000101" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f1(63 DOWNTO 32);
153 WHEN "000110" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f1(79 DOWNTO 64);
154 WHEN "000111" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f1;
155
156 WHEN "001000" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(31 DOWNTO 0);
157 WHEN "001001" => prdata(31 DOWNTO 0) <= reg_ftt.in_data_f2(63 DOWNTO 32);
158 WHEN "001010" => prdata(15 DOWNTO 0) <= reg_ftt.in_data_f2(79 DOWNTO 64);
159 WHEN "001011" => prdata(4 DOWNTO 0) <= reg_ftt.in_wen_f2;
160
161 WHEN "001100" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*1-1 DOWNTO 32*0);
162 WHEN "001101" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*2-1 DOWNTO 32*1);
163 WHEN "001110" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*3-1 DOWNTO 32*2);
164 WHEN "001111" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*4-1 DOWNTO 32*3);
165 WHEN "010000" => prdata(31 DOWNTO 0) <= MEM_IN_SM_rData(32*5-1 DOWNTO 32*4);
166
167 WHEN "010001" => prdata(4 DOWNTO 0) <= reg_ftt.out_ren;
168 prdata(9 DOWNTO 5) <= reg_ftt.out_reuse;
169 prdata(14 DOWNTO 10) <= reg_ftt.out_locked;
170 prdata(19 DOWNTO 15) <= MEM_IN_SM_Full;
171 prdata(24 DOWNTO 20) <= MEM_IN_SM_Empty;
172 WHEN OTHERS => NULL;
173
174 END CASE;
175 IF (apbi.pwrite AND apbi.penable) = '1' THEN
176 -- APB DMA WRITE --
177 CASE paddr(7 DOWNTO 2) IS
178 WHEN "000000" => reg_ftt.in_data_f0(31 DOWNTO 0) <= apbi.pwdata;
179 WHEN "000001" => reg_ftt.in_data_f0(63 DOWNTO 32) <= apbi.pwdata;
180 WHEN "000010" => reg_ftt.in_data_f0(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
181 WHEN "000011" => reg_ftt.in_wen_f0 <= apbi.pwdata(4 DOWNTO 0);
182
183 WHEN "000100" => reg_ftt.in_data_f1(31 DOWNTO 0) <= apbi.pwdata;
184 WHEN "000101" => reg_ftt.in_data_f1(63 DOWNTO 32) <= apbi.pwdata;
185 WHEN "000110" => reg_ftt.in_data_f1(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
186 WHEN "000111" => reg_ftt.in_wen_f1 <= apbi.pwdata(4 DOWNTO 0);
187
188 WHEN "001000" => reg_ftt.in_data_f2(31 DOWNTO 0) <= apbi.pwdata;
189 WHEN "001001" => reg_ftt.in_data_f2(63 DOWNTO 32) <= apbi.pwdata;
190 WHEN "001010" => reg_ftt.in_data_f2(79 DOWNTO 64) <= apbi.pwdata(15 DOWNTO 0);
191 WHEN "001011" => reg_ftt.in_wen_f2 <= apbi.pwdata(4 DOWNTO 0);
192
193 WHEN "010001" => reg_ftt.out_ren <= apbi.pwdata(4 DOWNTO 0);
194 reg_ftt.out_reuse <= apbi.pwdata(9 DOWNTO 5);
195 reg_ftt.out_locked <= apbi.pwdata(14 DOWNTO 10);
196
197 WHEN OTHERS => NULL;
198 END CASE;
199 END IF;
200 END IF;
201
202 END IF;
203 END PROCESS lpp_lfr_apbreg;
204
205 apbo.pindex <= pindex;
206 apbo.pconfig <= pconfig;
207 apbo.prdata <= prdata;
208
209 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms_tb IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 ---------------------------------------------------------------------------
26 --
27 ---------------------------------------------------------------------------
28 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 --
31 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 --
34 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36
37
38 ---------------------------------------------------------------------------
39 --
40 ---------------------------------------------------------------------------
41 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
42 MEM_IN_SM_ReUse : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 MEM_IN_SM_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 MEM_IN_SM_rData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
45 MEM_IN_SM_Full_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 MEM_IN_SM_Empty_pad : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47
48
49 ---------------------------------------------------------------------------
50 --
51 ---------------------------------------------------------------------------
52 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
53 --
54 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
55 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
56 );
57 END;
58
59 ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS
60
61 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
62 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
64 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66
67 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
68 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
70 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
71 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
72
73 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
74 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
77
78 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
79
80 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
84
85 SIGNAL error_wen_f0 : STD_LOGIC;
86 SIGNAL error_wen_f1 : STD_LOGIC;
87 SIGNAL error_wen_f2 : STD_LOGIC;
88
89 SIGNAL one_sample_f1_full : STD_LOGIC;
90 SIGNAL one_sample_f1_wen : STD_LOGIC;
91 SIGNAL one_sample_f2_full : STD_LOGIC;
92 SIGNAL one_sample_f2_wen : STD_LOGIC;
93
94 -----------------------------------------------------------------------------
95 -- FSM / SWITCH SELECT CHANNEL
96 -----------------------------------------------------------------------------
97 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
98 SIGNAL state_fsm_select_channel : fsm_select_channel;
99 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
100
101 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105
106 -----------------------------------------------------------------------------
107 -- FSM LOAD FFT
108 -----------------------------------------------------------------------------
109 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
110 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
111 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
112
113 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL sample_load : STD_LOGIC;
115 SIGNAL sample_valid : STD_LOGIC;
116 SIGNAL sample_valid_r : STD_LOGIC;
117 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
118
119
120 -----------------------------------------------------------------------------
121 -- FFT
122 -----------------------------------------------------------------------------
123 SIGNAL fft_read : STD_LOGIC;
124 SIGNAL fft_pong : STD_LOGIC;
125 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 SIGNAL fft_data_valid : STD_LOGIC;
128 SIGNAL fft_ready : STD_LOGIC;
129 -----------------------------------------------------------------------------
130 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
133 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
134 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
135 SIGNAL current_fifo_empty : STD_LOGIC;
136 SIGNAL current_fifo_locked : STD_LOGIC;
137 SIGNAL current_fifo_full : STD_LOGIC;
138 -- SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
139
140 -----------------------------------------------------------------------------
141 -- SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
142 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
144 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
145
146 -- SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
147 -- SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
148 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
149 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
150 -----------------------------------------------------------------------------
151 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
152 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
154
155 SIGNAL SM_correlation_start : STD_LOGIC;
156 SIGNAL SM_correlation_auto : STD_LOGIC;
157 SIGNAL SM_correlation_done : STD_LOGIC;
158 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
159 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
160 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
161 SIGNAL SM_correlation_begin : STD_LOGIC;
162
163 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
164 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
166
167 SIGNAL current_matrix_write : STD_LOGIC;
168 SIGNAL current_matrix_wait_empty : STD_LOGIC;
169 -----------------------------------------------------------------------------
170 SIGNAL fifo_0_ready : STD_LOGIC;
171 SIGNAL fifo_1_ready : STD_LOGIC;
172 SIGNAL fifo_ongoing : STD_LOGIC;
173
174 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
175 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
176 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
178 -----------------------------------------------------------------------------
179 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
181 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
182 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
183 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
184 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
185
186 -----------------------------------------------------------------------------
187 -- TIME REG & INFOs
188 -----------------------------------------------------------------------------
189 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
190
191 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
195
196 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
197 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
198 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
199 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
200
201 --SIGNAL time_update_f0_A : STD_LOGIC;
202 --SIGNAL time_update_f0_B : STD_LOGIC;
203 --SIGNAL time_update_f1 : STD_LOGIC;
204 --SIGNAL time_update_f2 : STD_LOGIC;
205 --
206 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
207 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
208 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
209
210 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
211 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
212 SIGNAL status_component_fifo_0_end : STD_LOGIC;
213 SIGNAL status_component_fifo_1_end : STD_LOGIC;
214 -----------------------------------------------------------------------------
215 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
216
217 SIGNAL fft_ready_reg : STD_LOGIC;
218 SIGNAL fft_ready_rising_down : STD_LOGIC;
219
220 SIGNAL sample_load_reg : STD_LOGIC;
221 SIGNAL sample_load_rising_down : STD_LOGIC;
222
223 -----------------------------------------------------------------------------
224 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
226 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
227 SIGNAL sample_f1_full_head_in : STD_LOGIC;
228 SIGNAL sample_f1_full_head_out : STD_LOGIC;
229 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
230
231 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
232
233 BEGIN
234
235
236 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
237
238
239 switch_f0_inst : spectral_matrix_switch_f0
240 PORT MAP (
241 clk => clk,
242 rstn => rstn,
243
244 sample_wen => sample_f0_wen,
245
246 fifo_A_empty => sample_f0_A_empty,
247 fifo_A_full => sample_f0_A_full,
248 fifo_A_wen => sample_f0_A_wen,
249
250 fifo_B_empty => sample_f0_B_empty,
251 fifo_B_full => sample_f0_B_full,
252 fifo_B_wen => sample_f0_B_wen,
253
254 error_wen => error_wen_f0); -- TODO
255
256 -----------------------------------------------------------------------------
257 -- FIFO IN
258 -----------------------------------------------------------------------------
259 lppFIFOxN_f0_a : lppFIFOxN
260 GENERIC MAP (
261 tech => 0,
262 Mem_use => Mem_use,
263 Data_sz => 16,
264 Addr_sz => 8,
265 FifoCnt => 5)
266 PORT MAP (
267 clk => clk,
268 rstn => rstn,
269
270 ReUse => (OTHERS => '0'),
271
272 wen => sample_f0_A_wen,
273 wdata => sample_f0_wdata,
274
275 ren => sample_f0_A_ren,
276 rdata => sample_f0_A_rdata,
277
278 empty => sample_f0_A_empty,
279 full => sample_f0_A_full,
280 almost_full => OPEN);
281
282 lppFIFOxN_f0_b : lppFIFOxN
283 GENERIC MAP (
284 tech => 0,
285 Mem_use => Mem_use,
286 Data_sz => 16,
287 Addr_sz => 8,
288 FifoCnt => 5)
289 PORT MAP (
290 clk => clk,
291 rstn => rstn,
292
293 ReUse => (OTHERS => '0'),
294
295 wen => sample_f0_B_wen,
296 wdata => sample_f0_wdata,
297 ren => sample_f0_B_ren,
298 rdata => sample_f0_B_rdata,
299 empty => sample_f0_B_empty,
300 full => sample_f0_B_full,
301 almost_full => OPEN);
302
303 -----------------------------------------------------------------------------
304 -- sample_f1_wen in
305 -- sample_f1_wdata in
306 -- sample_f1_full OUT
307
308 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
309 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
310 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
311
312 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
313 PORT MAP (
314 clk => clk,
315 rstn => rstn,
316 in_wen => sample_f1_wen_head_in,
317 in_data => sample_f1_wdata,
318 in_full => sample_f1_full_head_in,
319 in_empty => sample_f1_empty_head_in,
320 out_wen => sample_f1_wen_head_out,
321 out_data => sample_f1_wdata_head,
322 out_full => sample_f1_full_head_out);
323
324 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
325
326
327 lppFIFOxN_f1 : lppFIFOxN
328 GENERIC MAP (
329 tech => 0,
330 Mem_use => Mem_use,
331 Data_sz => 16,
332 Addr_sz => 8,
333 FifoCnt => 5)
334 PORT MAP (
335 clk => clk,
336 rstn => rstn,
337
338 ReUse => (OTHERS => '0'),
339
340 wen => sample_f1_wen_head,
341 wdata => sample_f1_wdata_head,
342 ren => sample_f1_ren,
343 rdata => sample_f1_rdata,
344 empty => sample_f1_empty,
345 full => sample_f1_full,
346 almost_full => sample_f1_almost_full);
347
348
349 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
350
351 PROCESS (clk, rstn)
352 BEGIN -- PROCESS
353 IF rstn = '0' THEN -- asynchronous reset (active low)
354 one_sample_f1_full <= '0';
355 error_wen_f1 <= '0';
356 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
357 IF sample_f1_full_head_out = '0' THEN
358 one_sample_f1_full <= '0';
359 ELSE
360 one_sample_f1_full <= '1';
361 END IF;
362 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
363 END IF;
364 END PROCESS;
365
366 -----------------------------------------------------------------------------
367
368
369 lppFIFOxN_f2 : lppFIFOxN
370 GENERIC MAP (
371 tech => 0,
372 Mem_use => Mem_use,
373 Data_sz => 16,
374 Addr_sz => 8,
375 FifoCnt => 5)
376 PORT MAP (
377 clk => clk,
378 rstn => rstn,
379
380 ReUse => (OTHERS => '0'),
381
382 wen => sample_f2_wen,
383 wdata => sample_f2_wdata,
384 ren => sample_f2_ren,
385 rdata => sample_f2_rdata,
386 empty => sample_f2_empty,
387 full => sample_f2_full,
388 almost_full => OPEN);
389
390
391 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
392
393 PROCESS (clk, rstn)
394 BEGIN -- PROCESS
395 IF rstn = '0' THEN -- asynchronous reset (active low)
396 one_sample_f2_full <= '0';
397 error_wen_f2 <= '0';
398 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
399 IF sample_f2_full = "00000" THEN
400 one_sample_f2_full <= '0';
401 ELSE
402 one_sample_f2_full <= '1';
403 END IF;
404 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
405 END IF;
406 END PROCESS;
407
408 -----------------------------------------------------------------------------
409 -- FSM SELECT CHANNEL
410 -----------------------------------------------------------------------------
411 PROCESS (clk, rstn)
412 BEGIN
413 IF rstn = '0' THEN
414 state_fsm_select_channel <= IDLE;
415 ELSIF clk'EVENT AND clk = '1' THEN
416 CASE state_fsm_select_channel IS
417 WHEN IDLE =>
418 IF sample_f1_full = "11111" THEN
419 state_fsm_select_channel <= SWITCH_F1;
420 ELSIF sample_f1_almost_full = "00000" THEN
421 IF sample_f0_A_full = "11111" THEN
422 state_fsm_select_channel <= SWITCH_F0_A;
423 ELSIF sample_f0_B_full = "11111" THEN
424 state_fsm_select_channel <= SWITCH_F0_B;
425 ELSIF sample_f2_full = "11111" THEN
426 state_fsm_select_channel <= SWITCH_F2;
427 END IF;
428 END IF;
429
430 WHEN SWITCH_F0_A =>
431 IF sample_f0_A_empty = "11111" THEN
432 state_fsm_select_channel <= IDLE;
433 END IF;
434 WHEN SWITCH_F0_B =>
435 IF sample_f0_B_empty = "11111" THEN
436 state_fsm_select_channel <= IDLE;
437 END IF;
438 WHEN SWITCH_F1 =>
439 IF sample_f1_empty = "11111" THEN
440 state_fsm_select_channel <= IDLE;
441 END IF;
442 WHEN SWITCH_F2 =>
443 IF sample_f2_empty = "11111" THEN
444 state_fsm_select_channel <= IDLE;
445 END IF;
446 WHEN OTHERS => NULL;
447 END CASE;
448
449 END IF;
450 END PROCESS;
451
452 PROCESS (clk, rstn)
453 BEGIN
454 IF rstn = '0' THEN
455 pre_state_fsm_select_channel <= IDLE;
456 ELSIF clk'EVENT AND clk = '1' THEN
457 pre_state_fsm_select_channel <= state_fsm_select_channel;
458 END IF;
459 END PROCESS;
460
461
462 -----------------------------------------------------------------------------
463 -- SWITCH SELECT CHANNEL
464 -----------------------------------------------------------------------------
465 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
466 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
467 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
468 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
469 (OTHERS => '1');
470
471 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
472 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
473 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
474 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
475 (OTHERS => '0');
476
477 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
478 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
479 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
480 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
481
482
483 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
484 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
485 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
486 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
487
488
489 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
490 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
491 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
492 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
493
494 -----------------------------------------------------------------------------
495 -- FSM LOAD FFT
496 -----------------------------------------------------------------------------
497
498 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
499 sample_ren_s WHEN sample_load = '1' ELSE
500 (OTHERS => '1');
501
502 PROCESS (clk, rstn)
503 BEGIN
504 IF rstn = '0' THEN
505 sample_ren_s <= (OTHERS => '1');
506 state_fsm_load_FFT <= IDLE;
507 status_MS_input <= (OTHERS => '0');
508 --next_state_fsm_load_FFT <= IDLE;
509 --sample_valid <= '0';
510 ELSIF clk'EVENT AND clk = '1' THEN
511 CASE state_fsm_load_FFT IS
512 WHEN IDLE =>
513 --sample_valid <= '0';
514 sample_ren_s <= (OTHERS => '1');
515 IF sample_full = "11111" AND sample_load = '1' THEN
516 state_fsm_load_FFT <= FIFO_1;
517 status_MS_input <= status_channel;
518 END IF;
519
520 WHEN FIFO_1 =>
521 sample_ren_s <= "1111" & NOT(sample_load);
522 IF sample_empty(0) = '1' THEN
523 sample_ren_s <= (OTHERS => '1');
524 state_fsm_load_FFT <= FIFO_2;
525 END IF;
526
527 WHEN FIFO_2 =>
528 sample_ren_s <= "111" & NOT(sample_load) & '1';
529 IF sample_empty(1) = '1' THEN
530 sample_ren_s <= (OTHERS => '1');
531 state_fsm_load_FFT <= FIFO_3;
532 END IF;
533
534 WHEN FIFO_3 =>
535 sample_ren_s <= "11" & NOT(sample_load) & "11";
536 IF sample_empty(2) = '1' THEN
537 sample_ren_s <= (OTHERS => '1');
538 state_fsm_load_FFT <= FIFO_4;
539 END IF;
540
541 WHEN FIFO_4 =>
542 sample_ren_s <= '1' & NOT(sample_load) & "111";
543 IF sample_empty(3) = '1' THEN
544 sample_ren_s <= (OTHERS => '1');
545 state_fsm_load_FFT <= FIFO_5;
546 END IF;
547
548 WHEN FIFO_5 =>
549 sample_ren_s <= NOT(sample_load) & "1111";
550 IF sample_empty(4) = '1' THEN
551 sample_ren_s <= (OTHERS => '1');
552 state_fsm_load_FFT <= IDLE;
553 END IF;
554 WHEN OTHERS => NULL;
555 END CASE;
556 END IF;
557 END PROCESS;
558
559 PROCESS (clk, rstn)
560 BEGIN
561 IF rstn = '0' THEN
562 sample_valid_r <= '0';
563 next_state_fsm_load_FFT <= IDLE;
564 ELSIF clk'EVENT AND clk = '1' THEN
565 next_state_fsm_load_FFT <= state_fsm_load_FFT;
566 IF sample_ren_s = "11111" THEN
567 sample_valid_r <= '0';
568 ELSE
569 sample_valid_r <= '1';
570 END IF;
571 END IF;
572 END PROCESS;
573
574 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
575
576 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
577 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
578 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
579 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
580 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
581
582 -----------------------------------------------------------------------------
583 -- FFT
584 -----------------------------------------------------------------------------
585 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
586 PORT MAP (
587 clk => clk,
588 rstn => rstn,
589 sample_valid => sample_valid,
590 fft_read => fft_read,
591 sample_data => sample_data,
592 sample_load => sample_load,
593 fft_pong => fft_pong,
594 fft_data_im => fft_data_im,
595 fft_data_re => fft_data_re,
596 fft_data_valid => fft_data_valid,
597 fft_ready => fft_ready);
598
599 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
600 fft_ongoing_counter & --9 8
601 sample_load_rising_down & --7
602 fft_ready_rising_down & --6
603 fft_ready & --5
604 fft_data_valid & --4
605 fft_pong & --3
606 sample_load & --2
607 fft_read & --1
608 sample_valid; --0
609
610 -----------------------------------------------------------------------------
611 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
612 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
613
614 PROCESS (clk, rstn)
615 BEGIN
616 IF rstn = '0' THEN
617 fft_ready_reg <= '0';
618 sample_load_reg <= '0';
619
620 fft_ongoing_counter <= '0';
621 ELSIF clk'event AND clk = '1' THEN
622 fft_ready_reg <= fft_ready;
623 sample_load_reg <= sample_load;
624
625 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
626 fft_ongoing_counter <= '0';
627
628 -- CASE fft_ongoing_counter IS
629 -- WHEN "01" => fft_ongoing_counter <= "00";
630 ---- WHEN "10" => fft_ongoing_counter <= "01";
631 -- WHEN OTHERS => NULL;
632 -- END CASE;
633 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
634 fft_ongoing_counter <= '1';
635 -- CASE fft_ongoing_counter IS
636 -- WHEN "00" => fft_ongoing_counter <= "01";
637 ---- WHEN "01" => fft_ongoing_counter <= "10";
638 -- WHEN OTHERS => NULL;
639 -- END CASE;
640 END IF;
641
642 END IF;
643 END PROCESS;
644
645 -----------------------------------------------------------------------------
646 PROCESS (clk, rstn)
647 BEGIN
648 IF rstn = '0' THEN
649 state_fsm_load_MS_memory <= IDLE;
650 current_fifo_load <= "00001";
651 ELSIF clk'EVENT AND clk = '1' THEN
652 CASE state_fsm_load_MS_memory IS
653 WHEN IDLE =>
654 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
655 state_fsm_load_MS_memory <= LOAD_FIFO;
656 END IF;
657 WHEN LOAD_FIFO =>
658 IF current_fifo_full = '1' THEN
659 state_fsm_load_MS_memory <= TRASH_FFT;
660 END IF;
661 WHEN TRASH_FFT =>
662 IF fft_ready = '0' THEN
663 state_fsm_load_MS_memory <= IDLE;
664 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
665 END IF;
666 WHEN OTHERS => NULL;
667 END CASE;
668
669 END IF;
670 END PROCESS;
671
672 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
673 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
674 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
675 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
676 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
677
678 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
679 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
680 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
681 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
682 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
683
684 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
685 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
686 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
687 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
688 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
689
690 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
691
692 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
693 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
694 AND state_fsm_load_MS_memory = LOAD_FIFO
695 AND current_fifo_load(I) = '1'
696 ELSE '1';
697 END GENERATE all_fifo;
698
699 PROCESS (clk, rstn)
700 BEGIN
701 IF rstn = '0' THEN
702 MEM_IN_SM_wen <= (OTHERS => '1');
703 ELSIF clk'EVENT AND clk = '1' THEN
704 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
705 END IF;
706 END PROCESS;
707
708 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
709 (fft_data_im & fft_data_re) &
710 (fft_data_im & fft_data_re) &
711 (fft_data_im & fft_data_re) &
712 (fft_data_im & fft_data_re);
713 -----------------------------------------------------------------------------
714
715
716 -----------------------------------------------------------------------------
717 Mem_In_SpectralMatrix : lppFIFOxN
718 GENERIC MAP (
719 tech => 0,
720 Mem_use => Mem_use,
721 Data_sz => 32, --16,
722 Addr_sz => 8, --8
723 FifoCnt => 5)
724 PORT MAP (
725 clk => clk,
726 rstn => rstn,
727
728 ReUse => MEM_IN_SM_ReUse,
729
730 wen => MEM_IN_SM_wen,
731 wdata => MEM_IN_SM_wData,
732
733 ren => MEM_IN_SM_ren,
734 rdata => MEM_IN_SM_rData,
735 full => MEM_IN_SM_Full,
736 empty => MEM_IN_SM_Empty,
737 almost_full => OPEN);
738
739 MEM_IN_SM_Full_pad <= MEM_IN_SM_Full;
740 MEM_IN_SM_Empty_pad <= MEM_IN_SM_Empty;
741
742 -------------------------------------------------------------------------------
743
744 --observation_vector_1(11 DOWNTO 0) <= '0' &
745 -- SM_correlation_done & --4
746 -- SM_correlation_auto & --3
747 -- SM_correlation_start &
748 -- SM_correlation_start & --7
749 -- status_MS_input(1 DOWNTO 0)& --6..5
750 -- MEM_IN_SM_locked(4 DOWNTO 0); --4..0
751
752 -------------------------------------------------------------------------------
753 --MS_control_1 : MS_control
754 -- PORT MAP (
755 -- clk => clk,
756 -- rstn => rstn,
757
758 -- current_status_ms => status_MS_input,
759
760 -- fifo_in_lock => MEM_IN_SM_locked,
761 -- fifo_in_data => MEM_IN_SM_rdata,
762 -- fifo_in_full => MEM_IN_SM_Full,
763 -- fifo_in_empty => MEM_IN_SM_Empty,
764 -- fifo_in_ren => MEM_IN_SM_ren,
765 -- fifo_in_reuse => MEM_IN_SM_ReUse,
766
767 -- fifo_out_data => SM_in_data,
768 -- fifo_out_ren => SM_in_ren,
769 -- fifo_out_empty => SM_in_empty,
770
771 -- current_status_component => status_component,
772
773 -- correlation_start => SM_correlation_start,
774 -- correlation_auto => SM_correlation_auto,
775 -- correlation_done => SM_correlation_done);
776
777
778 --MS_calculation_1 : MS_calculation
779 -- PORT MAP (
780 -- clk => clk,
781 -- rstn => rstn,
782
783 -- fifo_in_data => SM_in_data,
784 -- fifo_in_ren => SM_in_ren,
785 -- fifo_in_empty => SM_in_empty,
786
787 -- fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
788 -- fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
789 -- fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
790
791 -- correlation_start => SM_correlation_start,
792 -- correlation_auto => SM_correlation_auto,
793 -- correlation_begin => SM_correlation_begin,
794 -- correlation_done => SM_correlation_done);
795
796 -------------------------------------------------------------------------------
797 --PROCESS (clk, rstn)
798 --BEGIN -- PROCESS
799 -- IF rstn = '0' THEN -- asynchronous reset (active low)
800 -- current_matrix_write <= '0';
801 -- current_matrix_wait_empty <= '1';
802 -- status_component_fifo_0 <= (OTHERS => '0');
803 -- status_component_fifo_1 <= (OTHERS => '0');
804 -- status_component_fifo_0_end <= '0';
805 -- status_component_fifo_1_end <= '0';
806 -- SM_correlation_done_reg1 <= '0';
807 -- SM_correlation_done_reg2 <= '0';
808 -- SM_correlation_done_reg3 <= '0';
809
810 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
811 -- SM_correlation_done_reg1 <= SM_correlation_done;
812 -- SM_correlation_done_reg2 <= SM_correlation_done_reg1;
813 -- SM_correlation_done_reg3 <= SM_correlation_done_reg2;
814 -- status_component_fifo_0_end <= '0';
815 -- status_component_fifo_1_end <= '0';
816 -- IF SM_correlation_begin = '1' THEN
817 -- IF current_matrix_write = '0' THEN
818 -- status_component_fifo_0 <= status_component;
819 -- ELSE
820 -- status_component_fifo_1 <= status_component;
821 -- END IF;
822 -- END IF;
823
824 -- IF SM_correlation_done_reg3 = '1' THEN
825 -- IF current_matrix_write = '0' THEN
826 -- status_component_fifo_0_end <= '1';
827 -- ELSE
828 -- status_component_fifo_1_end <= '1';
829 -- END IF;
830 -- current_matrix_wait_empty <= '1';
831 -- current_matrix_write <= NOT current_matrix_write;
832 -- END IF;
833
834 -- IF current_matrix_wait_empty <= '1' THEN
835 -- IF current_matrix_write = '0' THEN
836 -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
837 -- ELSE
838 -- current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
839 -- END IF;
840 -- END IF;
841
842 -- END IF;
843 --END PROCESS;
844
845 --MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
846 -- '1' WHEN SM_correlation_done_reg1 = '1' ELSE
847 -- '1' WHEN SM_correlation_done_reg2 = '1' ELSE
848 -- '1' WHEN SM_correlation_done_reg3 = '1' ELSE
849 -- '1' WHEN current_matrix_wait_empty = '1' ELSE
850 -- MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
851 -- MEM_OUT_SM_Full(1);
852
853 --MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
854 --MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
855
856 --MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
857 -------------------------------------------------------------------------------
858
859 --Mem_Out_SpectralMatrix : lppFIFOxN
860 -- GENERIC MAP (
861 -- tech => 0,
862 -- Mem_use => Mem_use,
863 -- Data_sz => 32,
864 -- Addr_sz => 8,
865 -- FifoCnt => 2)
866 -- PORT MAP (
867 -- clk => clk,
868 -- rstn => rstn,
869
870 -- ReUse => (OTHERS => '0'),
871
872 -- wen => MEM_OUT_SM_Write,
873 -- wdata => MEM_OUT_SM_Data_in,
874
875 -- ren => MEM_OUT_SM_Read,
876 -- rdata => MEM_OUT_SM_Data_out,
877
878 -- full => MEM_OUT_SM_Full,
879 -- empty => MEM_OUT_SM_Empty,
880 -- almost_full => OPEN);
881
882 -- -----------------------------------------------------------------------------
883 ---- MEM_OUT_SM_Read <= "00";
884 -- PROCESS (clk, rstn)
885 -- BEGIN
886 -- IF rstn = '0' THEN
887 -- fifo_0_ready <= '0';
888 -- fifo_1_ready <= '0';
889 -- fifo_ongoing <= '0';
890 -- ELSIF clk'EVENT AND clk = '1' THEN
891 -- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
892 -- fifo_ongoing <= '1';
893 -- fifo_0_ready <= '0';
894 -- ELSIF status_component_fifo_0_end = '1' THEN
895 -- fifo_0_ready <= '1';
896 -- END IF;
897
898 -- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
899 -- fifo_ongoing <= '0';
900 -- fifo_1_ready <= '0';
901 -- ELSIF status_component_fifo_1_end = '1' THEN
902 -- fifo_1_ready <= '1';
903 -- END IF;
904
905 -- END IF;
906 -- END PROCESS;
907
908 -- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
909 -- '1' WHEN fifo_0_ready = '0' ELSE
910 -- FSM_DMA_fifo_ren;
911
912 -- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
913 -- '1' WHEN fifo_1_ready = '0' ELSE
914 -- FSM_DMA_fifo_ren;
915
916 -- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
917 -- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
918 -- '1';
919
920 -- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
921 -- status_component_fifo_1;
922
923 -- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
924 -- MEM_OUT_SM_Data_out(63 DOWNTO 32);
925
926 -- -----------------------------------------------------------------------------
927 -- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
928 -- PORT MAP (
929 -- HCLK => clk,
930 -- HRESETn => rstn,
931
932 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
933 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
934 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
935 -- fifo_data => FSM_DMA_fifo_data,
936 -- fifo_empty => FSM_DMA_fifo_empty,
937 -- fifo_ren => FSM_DMA_fifo_ren,
938
939 -- dma_addr => dma_addr,
940 -- dma_data => dma_data,
941 -- dma_valid => dma_valid,
942 -- dma_valid_burst => dma_valid_burst,
943 -- dma_ren => dma_ren,
944 -- dma_done => dma_done,
945
946 -- ready_matrix_f0 => ready_matrix_f0,
947 -- ready_matrix_f1 => ready_matrix_f1,
948 -- ready_matrix_f2 => ready_matrix_f2,
949
950 -- error_bad_component_error => error_bad_component_error,
951 -- error_buffer_full => error_buffer_full,
952
953 -- debug_reg => debug_reg,
954 -- status_ready_matrix_f0 => status_ready_matrix_f0,
955 -- status_ready_matrix_f1 => status_ready_matrix_f1,
956 -- status_ready_matrix_f2 => status_ready_matrix_f2,
957
958 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
959 -- config_active_interruption_onError => config_active_interruption_onError,
960
961 -- addr_matrix_f0 => addr_matrix_f0,
962 -- addr_matrix_f1 => addr_matrix_f1,
963 -- addr_matrix_f2 => addr_matrix_f2,
964
965 -- matrix_time_f0 => matrix_time_f0,
966 -- matrix_time_f1 => matrix_time_f1,
967 -- matrix_time_f2 => matrix_time_f2
968 -- );
969 -- -----------------------------------------------------------------------------
970
971
972
973
974
975 -- -----------------------------------------------------------------------------
976 -- -- TIME MANAGMENT
977 -- -----------------------------------------------------------------------------
978 -- all_time <= coarse_time & fine_time;
979 -- --
980 -- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
981 -- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
982 -- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
983 -- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
984
985 -- all_time_reg: FOR I IN 0 TO 3 GENERATE
986
987 -- PROCESS (clk, rstn)
988 -- BEGIN
989 -- IF rstn = '0' THEN
990 -- f_empty_reg(I) <= '1';
991 -- ELSIF clk'event AND clk = '1' THEN
992 -- f_empty_reg(I) <= f_empty(I);
993 -- END IF;
994 -- END PROCESS;
995
996 -- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
997
998 -- s_m_t_m_f0_A : spectral_matrix_time_managment
999 -- PORT MAP (
1000 -- clk => clk,
1001 -- rstn => rstn,
1002 -- time_in => all_time,
1003 -- update_1 => time_update_f(I),
1004 -- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1005 -- );
1006
1007 -- END GENERATE all_time_reg;
1008
1009 -- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1010 -- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1011 -- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1012 -- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1013
1014 -- -----------------------------------------------------------------------------
1015
1016 END Behavioral;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
48
49 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
51
52 ################## project specific targets ##########################
53
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1 vcom -quiet -93 -work work tb.vhd
2
3 vsim work.testbench
4
5 log -r *
6
7 do wave.do
8
9 run -all
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
6
7 LIBRARY lpp;
8 USE lpp.lpp_memory.ALL;
9 USE lpp.iir_filter.ALL;
10
11
12 ENTITY testbench IS
13 END;
14
15 ARCHITECTURE behav OF testbench IS
16
17 -----------------------------------------------------------------------------
18 -- Common signal
19 SIGNAL clk : STD_LOGIC := '0';
20 SIGNAL rstn : STD_LOGIC := '0';
21 SIGNAL run : STD_LOGIC := '0';
22
23 -----------------------------------------------------------------------------
24
25 SIGNAL full_almost : STD_LOGIC;
26 SIGNAL full : STD_LOGIC;
27 SIGNAL data_wen : STD_LOGIC;
28 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
29
30 SIGNAL empty : STD_LOGIC;
31 SIGNAL data_ren : STD_LOGIC;
32 SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
33 SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0);
34
35 SIGNAL empty_reg : STD_LOGIC;
36 SIGNAL full_reg : STD_LOGIC;
37
38 -----------------------------------------------------------------------------
39 TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL data_in : DATA_CHANNEL;
41
42 -----------------------------------------------------------------------------
43 CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE
44 CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0;
45 SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
46 --
47 SIGNAL rand_ren : STD_LOGIC;
48 SIGNAL rand_wen : STD_LOGIC;
49
50 SIGNAL pointer_read : INTEGER;
51 SIGNAL pointer_write : INTEGER := 0;
52
53 SIGNAL error_now : STD_LOGIC;
54 SIGNAL error_new : STD_LOGIC;
55
56 SIGNAL read_stop : STD_LOGIC;
57 BEGIN
58
59
60 all_J : FOR J IN 0 TO 127 GENERATE
61 data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32));
62 END GENERATE all_J;
63
64
65 -----------------------------------------------------------------------------
66 lpp_fifo_1 : lpp_fifo
67 GENERIC MAP (
68 tech => 0,
69 Mem_use => use_CEL,
70 DataSz => 32,
71 AddrSz => 8)
72 PORT MAP (
73 clk => clk,
74 rstn => rstn,
75 reUse => '0',
76 ren => data_ren,
77 rdata => data_out,
78 wen => data_wen,
79 wdata => wdata,
80 empty => empty,
81 full => full,
82 almost_full => full_almost);
83
84 -----------------------------------------------------------------------------
85
86
87
88 -----------------------------------------------------------------------------
89 -- READ
90 -----------------------------------------------------------------------------
91 PROCESS (clk, rstn)
92 BEGIN -- PROCESS
93 IF rstn = '0' THEN -- asynchronous reset (active low)
94 empty_reg <= '1';
95 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
96 empty_reg <= empty;
97 END IF;
98 END PROCESS;
99
100 PROCESS (clk, rstn)
101 BEGIN -- PROCESS
102 IF rstn = '0' THEN -- asynchronous reset (active low)
103 data_out_obs <= (OTHERS => '0');
104
105 pointer_read <= 0;
106 error_now <= '0';
107 error_new <= '0';
108
109 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
110 error_now <= '0';
111 IF empty_reg = '0' THEN
112 IF data_ren = '0' THEN
113 --IF data_ren_and_not_empty = '0' THEN
114 error_new <= '0';
115 data_out_obs <= data_out;
116
117 IF pointer_read < 127 THEN
118 pointer_read <= pointer_read + 1;
119 ELSE
120 pointer_read <= 0;
121 END IF;
122
123 IF data_out /= data_in(pointer_read) THEN
124 error_now <= '1';
125 error_new <= '1';
126 END IF;
127 END IF;
128
129 END IF;
130 END IF;
131 END PROCESS;
132 -----------------------------------------------------------------------------
133
134
135
136
137 -----------------------------------------------------------------------------
138 -- WRITE
139 -----------------------------------------------------------------------------
140 PROCESS (clk, rstn)
141 BEGIN -- PROCESS
142 IF rstn = '0' THEN -- asynchronous reset (active low)
143 full_reg <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 full_reg <= full;
146 END IF;
147 END PROCESS;
148
149 proc_verif : PROCESS (clk, rstn)
150 BEGIN -- PROCESS proc_verif
151 IF rstn = '0' THEN -- asynchronous reset (active low)
152 pointer_write <= 0;
153 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
154 IF data_wen = '0' THEN
155 IF full_reg = '0' THEN
156 IF pointer_write < 127 THEN
157 pointer_write <= pointer_write+1;
158 ELSE
159 pointer_write <= 0;
160 END IF;
161 END IF;
162 END IF;
163 END IF;
164 END PROCESS proc_verif;
165
166 wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X');
167 -----------------------------------------------------------------------------
168
169
170
171 -----------------------------------------------------------------------------
172 clk <= NOT clk AFTER 5 ns; -- 100 MHz
173 -----------------------------------------------------------------------------
174 WaveGen_Proc : PROCESS
175 BEGIN
176 -- insert signal assignments here
177 WAIT UNTIL clk = '1';
178 read_stop <= '0';
179 rstn <= '0';
180 run <= '0';
181 WAIT UNTIL clk = '1';
182 WAIT UNTIL clk = '1';
183 WAIT UNTIL clk = '1';
184 rstn <= '1';
185 WAIT UNTIL clk = '1';
186 WAIT UNTIL clk = '1';
187 WAIT UNTIL clk = '1';
188 WAIT UNTIL clk = '1';
189 WAIT UNTIL clk = '1';
190 run <= '1';
191 WAIT UNTIL clk = '1';
192 WAIT UNTIL clk = '1';
193 WAIT UNTIL clk = '1';
194 WAIT UNTIL clk = '1';
195 WAIT FOR 10 us;
196 read_stop <= '1';
197 WAIT FOR 10 us;
198 read_stop <= '0';
199 WAIT FOR 80 us;
200 REPORT "*** END simulation ***" SEVERITY failure;
201 WAIT;
202 END PROCESS WaveGen_Proc;
203 -----------------------------------------------------------------------------
204
205
206
207 -----------------------------------------------------------------------------
208 -- RANDOM GENERATOR
209 -----------------------------------------------------------------------------
210 PROCESS (clk, rstn)
211 VARIABLE seed1, seed2 : POSITIVE;
212 VARIABLE rand1 : REAL;
213 VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
214 BEGIN -- PROCESS
215 IF rstn = '0' THEN -- asynchronous reset (active low)
216 random_vector <= (OTHERS => '0');
217 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
218 UNIFORM(seed1, seed2, rand1);
219 RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
220 to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
221 RANDOM_VECTOR_VAR'LENGTH)
222 );
223 random_vector <= RANDOM_VECTOR_VAR;
224 END IF;
225 END PROCESS;
226 -----------------------------------------------------------------------------
227 rand_wen <= random_vector(1);
228 rand_ren <= random_vector(0);
229 -----------------------------------------------------------------------------
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 data_wen <= '1';
234 data_ren <= '1';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 data_wen <= rand_wen;
237 IF read_stop = '0' THEN
238 data_ren <= rand_ren;
239 ELSE
240 data_ren <= '1';
241 END IF;
242 END IF;
243 END PROCESS;
244 -----------------------------------------------------------------------------
245
246
247
248 END;
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1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group COMMON /testbench/clk
4 add wave -noupdate -expand -group COMMON /testbench/rstn
5 add wave -noupdate -expand -group COMMON /testbench/run
6 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost
7 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full
8 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen
9 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata
10 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty
11 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren
12 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out
13 add wave -noupdate -radix hexadecimal /testbench/data_out_obs
14 add wave -noupdate /testbench/pointer_read
15 add wave -noupdate /testbench/pointer_write
16 add wave -noupdate /testbench/error_now
17 add wave -noupdate /testbench/error_new
18 add wave -noupdate /testbench/read_stop
19 TreeUpdate [SetDefaultTree]
20 WaveRestoreCursors {{Cursor 1} {56085000 ps} 0}
21 configure wave -namecolwidth 510
22 configure wave -valuecolwidth 172
23 configure wave -justifyvalue left
24 configure wave -signalnamewidth 0
25 configure wave -snapdistance 10
26 configure wave -datasetprefix 0
27 configure wave -rowmargin 4
28 configure wave -childrowmargin 2
29 configure wave -gridoffset 0
30 configure wave -gridperiod 1
31 configure wave -griddelta 40
32 configure wave -timeline 0
33 configure wave -timelineunits ns
34 update
35 WaveRestoreZoom {0 ps} {105131250 ps}
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=TB
6
7 CMD_VLIB=vlib
8 CMD_VMAP=vmap
9 CMD_VCOM=@vcom -quiet -93 -work
10
11 ################## project specific targets ##########################
12
13 all:
14 @echo "make vsim"
15 @echo "make libs"
16 @echo "make clean"
17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18
19 run:
20 @vsim work.TB -do run.do
21
22 vsim: libs vcom run
23
24 libs:
25 @$(CMD_VLIB) modelsim
26 @$(CMD_VMAP) modelsim modelsim
27 @$(CMD_VLIB) modelsim/techmap
28 @$(CMD_VMAP) techmap modelsim/techmap
29 @$(CMD_VLIB) modelsim/grlib
30 @$(CMD_VMAP) grlib modelsim/grlib
31 @$(CMD_VLIB) modelsim/work
32 @$(CMD_VMAP) work modelsim/work
33 @echo "libs done"
34
35
36 clean:
37 @rm -Rf modelsim
38 @rm -Rf modelsim.ini
39 @rm -Rf *~
40 @rm -Rf transcript
41 @rm -Rf wlft*
42 @rm -Rf *.wlf
43 @rm -Rf vish_stacktrace.vstf
44 @rm -Rf libs.do
45
46 vcom: vcom_grlib vcom_techmap vcom_tb
47
48
49 vcom_tb:
50 $(CMD_VCOM) work $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
51 $(CMD_VCOM) work TB.vhd
52
53 vcom_grlib:
54 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
55 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
56 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
57 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
58
59 vcom_techmap:
60 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
61 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
62 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
63 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
64 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
65
66
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.MATH_REAL.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
28 --LIBRARY lpp;
29 --USE lpp.iir_filter.ALL;
30
31 LIBRARY techmap;
32 USE techmap.gencomp.ALL;
33
34 ENTITY TB IS
35
36
37 END TB;
38
39
40 ARCHITECTURE beh OF TB IS
41
42 COMPONENT RAM_CEL
43 GENERIC (
44 DataSz : integer range 1 to 32;
45 abits : integer range 2 to 12);
46 PORT (
47 WD : in std_logic_vector(DataSz-1 downto 0);
48 RD : out std_logic_vector(DataSz-1 downto 0);
49 WEN, REN : in std_logic;
50 WADDR : in std_logic_vector(abits-1 downto 0);
51 RADDR : in std_logic_vector(abits-1 downto 0);
52 RWCLK, RESET : in std_logic);
53 END COMPONENT;
54
55 CONSTANT DATA_SIZE : INTEGER := 8;
56 CONSTANT ADDR_BIT_NUMBER : INTEGER := 8;
57
58 -----------------------------------------------------------------------------
59 SIGNAL clk : STD_LOGIC := '0';
60 SIGNAL rstn : STD_LOGIC := '0';
61
62 -----------------------------------------------------------------------------
63 SIGNAL write_data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
64 SIGNAL write_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0);
65 SIGNAL write_enable : STD_LOGIC;
66 SIGNAL write_enable_n : STD_LOGIC;
67
68 SIGNAL read_data_ram : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
69 SIGNAL read_data_cel : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0);
70 SIGNAL read_addr : STD_LOGIC_VECTOR(ADDR_BIT_NUMBER-1 DOWNTO 0);
71 SIGNAL read_enable : STD_LOGIC;
72 SIGNAL read_enable_n : STD_LOGIC;
73 -----------------------------------------------------------------------------
74 CONSTANT RANDOM_VECTOR_SIZE : INTEGER := DATA_SIZE + ADDR_BIT_NUMBER + ADDR_BIT_NUMBER + 2;
75 CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : real := (2**RANDOM_VECTOR_SIZE)*1.0;
76 SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
77
78 -----------------------------------------------------------------------------
79 SIGNAL error_value : STD_LOGIC;
80 SIGNAL warning_value : STD_LOGIC;
81 SIGNAL warning_value_clocked : STD_LOGIC;
82
83 CONSTANT READ_DATA_ALL_X : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'X');
84 CONSTANT READ_DATA_ALL_U : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => 'U');
85 CONSTANT READ_DATA_ALL_0 : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0) := (OTHERS => '0');
86
87
88
89 BEGIN -- beh
90
91 clk <= NOT clk AFTER 10 ns;
92 rstn <= '1' AFTER 30 ns;
93 -----------------------------------------------------------------------------
94
95 CEL: RAM_CEL
96 GENERIC MAP (
97 DataSz => DATA_SIZE,
98 abits => ADDR_BIT_NUMBER)
99 PORT MAP (
100 WD => write_data,
101 RD => read_data_cel,
102 WEN => write_enable_n,
103 REN => read_enable_n,
104 WADDR => write_addr,
105 RADDR => read_addr,
106
107 RWCLK => clk,
108 RESET => rstn);
109
110 RAM : syncram_2p
111 GENERIC MAP(tech => 0, abits => ADDR_BIT_NUMBER, dbits => DATA_SIZE)
112 PORT MAP(rclk => clk, renable => read_enable, raddress => read_addr, dataout => read_data_ram,
113 wclk => clk, write => write_enable, waddress => write_addr, datain => write_data);
114
115 -----------------------------------------------------------------------------
116
117 PROCESS (clk, rstn)
118 VARIABLE seed1, seed2 : POSITIVE;
119 VARIABLE rand1 : REAL;
120 VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 random_vector <= (OTHERS => '0');
124 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
125 UNIFORM(seed1,seed2,rand1);
126 RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
127 to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
128 RANDOM_VECTOR_VAR'LENGTH)
129 );
130
131 random_vector <= RANDOM_VECTOR_VAR ;
132
133 END IF;
134 END PROCESS;
135
136 -----------------------------------------------------------------------------
137 write_data <= random_vector(DATA_SIZE-1 DOWNTO 0);
138 write_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE);
139 read_addr <= random_vector(DATA_SIZE+ADDR_BIT_NUMBER+ADDR_BIT_NUMBER-1 DOWNTO DATA_SIZE+ADDR_BIT_NUMBER);
140 read_enable <= random_vector(RANDOM_VECTOR_SIZE-2);
141 write_enable <= random_vector(RANDOM_VECTOR_SIZE-1);
142
143 read_enable_n <= NOT read_enable;
144 write_enable_n <= NOT write_enable;
145
146 -----------------------------------------------------------------------------
147 warning_value <= '0' WHEN read_data_ram = read_data_cel ELSE
148 '1';
149
150 PROCESS (clk, rstn)
151 BEGIN -- PROCESS
152 IF rstn = '0' THEN -- asynchronous reset (active low)
153 error_value <= '0';
154 warning_value_clocked <= '0';
155 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
156 IF read_data_ram = read_data_cel THEN
157 error_value <= '0';
158 warning_value_clocked <= '0';
159 ELSE
160 warning_value_clocked <= '1';
161 IF read_data_ram = READ_DATA_ALL_U AND read_data_cel = READ_DATA_ALL_0 THEN
162 error_value <= '0';
163 ELSE
164 error_value <= '1';
165 END IF;
166 END IF;
167 END IF;
168 END PROCESS;
169
170 END beh;
171
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@@ -0,0 +1,3
1 log -R *
2 do wave.do
3 run 10 ms No newline at end of file
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@@ -0,0 +1,34
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group COMMON /tb/clk
4 add wave -noupdate -expand -group COMMON /tb/rstn
5 add wave -noupdate -expand -group COMMON /tb/random_vector
6 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_data
7 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_addr
8 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_enable
9 add wave -noupdate -expand -group WRITE -radix hexadecimal /tb/write_enable_n
10 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_data_ram
11 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_data_cel
12 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_addr
13 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_enable
14 add wave -noupdate -expand -group READ -radix hexadecimal /tb/read_enable_n
15 add wave -noupdate -radix hexadecimal /tb/warning_value
16 add wave -noupdate -radix hexadecimal /tb/warning_value_clocked
17 add wave -noupdate -radix hexadecimal /tb/error_value
18 TreeUpdate [SetDefaultTree]
19 WaveRestoreCursors {{Cursor 1} {5926078 ps} 0} {{Cursor 2} {200000 ps} 0}
20 configure wave -namecolwidth 403
21 configure wave -valuecolwidth 198
22 configure wave -justifyvalue left
23 configure wave -signalnamewidth 0
24 configure wave -snapdistance 10
25 configure wave -datasetprefix 0
26 configure wave -rowmargin 4
27 configure wave -childrowmargin 2
28 configure wave -gridoffset 0
29 configure wave -gridperiod 1
30 configure wave -griddelta 40
31 configure wave -timeline 0
32 configure wave -timelineunits ps
33 update
34 WaveRestoreZoom {0 ps} {25526182 ps}
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@@ -1,50 +1,53
1 1 #GRLIB=../..
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=leon3mp
6 6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd
15 VHDLSYNFILES=
16 VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd
17 17 SIMTOP=testbench
18 18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 22 CLEAN=soft-clean
23 23
24 24 TECHLIBS = proasic3e
25 25
26 26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 27 tmtc openchip hynix ihp gleichmann micron usbhc
28 28
29 29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 31 ./amba_lcd_16x2_ctrlr \
32 32 ./general_purpose/lpp_AMR \
33 33 ./general_purpose/lpp_balise \
34 34 ./general_purpose/lpp_delay \
35 35 ./lpp_bootloader \
36 36 ./lpp_cna \
37 37 ./lpp_uart \
38 38 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
39 40
40 41 FILESKIP = i2cmst.vhd \
41 42 APB_MULTI_DIODE.vhd \
42 43 APB_MULTI_DIODE.vhd \
43 44 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
45 48
46 49 include $(GRLIB)/bin/Makefile
47 50 include $(GRLIB)/software/leon3/Makefile
48 51
49 52 ################## project specific targets ##########################
50 53
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@@ -1,28 +1,13
1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10
11 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
12 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
13 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd
14 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
15
16 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
17 2
18 3 vcom -quiet -93 -work lpp testbench_package.vhd
19 4
20 5 vcom -quiet -93 -work work tb_waveform.vhd
21 6
22 7 vsim work.testbench
23 8
24 9 log -r *
25 10
26 11 do wave_ms.do
27 12
28 13 run 2 ms
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@@ -1,532 +1,538
1 1 ------------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design test bench
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 ------------------------------------------------------------------------------
5 5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 7 --
8 8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 10 -- IN ADVANCE IN WRITING.
11 11 ------------------------------------------------------------------------------
12 12
13 13 LIBRARY ieee;
14 14 USE ieee.std_logic_1164.ALL;
15 15
16 16 --LIBRARY std;
17 17 --USE std.textio.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.AMBA_TestPackage.ALL;
23 23 LIBRARY gaisler;
24 24 USE gaisler.memctrl.ALL;
25 25 USE gaisler.leon3.ALL;
26 26 USE gaisler.uart.ALL;
27 27 USE gaisler.misc.ALL;
28 28 USE gaisler.libdcom.ALL;
29 29 USE gaisler.sim.ALL;
30 30 USE gaisler.jtagtst.ALL;
31 31 USE gaisler.misc.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 --LIBRARY micron;
37 37 --USE micron.components.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_waveform_pkg.ALL;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.testbench_package.ALL;
43 42 USE lpp.lpp_lfr_pkg.ALL;
44 43 USE lpp.iir_filter.ALL;
45 44 USE lpp.general_purpose.ALL;
46 45 USE lpp.CY7C1061DV33_pkg.ALL;
47 46
47 USE work.testbench_package.ALL;
48
48 49 ENTITY testbench IS
49 50 END;
50 51
51 52 ARCHITECTURE behav OF testbench IS
52 53 CONSTANT INDEX_LFR : INTEGER := 15;
53 54 CONSTANT ADDR_LFR : INTEGER := 15;
54 55 -- REG MS
55 56 CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00";
56 57 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
57 58 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
58 59 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
59 60
60 61 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
61 62 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
62 63 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
63 64 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C";
64 65
65 66 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
66 67 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
67 68 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
68 69 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
69 70
70 71 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
71 72 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
72 73 --X"00000F38";
73 74 CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3F";
74 75
75 76 -- REG WAVEFORM
76 77 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
77 78 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
78 79 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
79 80 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
80 81
81 82 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
82 83 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
83 84 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
84 85 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
85 86
86 87 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60";
87 88 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64";
88 89 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68";
89 90 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C";
90 91
91 92 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70";
92 93 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74";
93 94 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78";
94 95 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C";
95 96 -- RAM ADDRESS
96 97 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
97 98 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
98 99 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
99 100 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
100 101
101 102
102 103 -- Common signal
103 104 SIGNAL clk49_152MHz : STD_LOGIC := '0';
104 105 SIGNAL clk25MHz : STD_LOGIC := '0';
105 106 SIGNAL rstn : STD_LOGIC := '0';
106 107
107 108 -- ADC interface
108 109 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
109 110 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
110 111 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
111 112
112 113 -- AD Converter RHF1401
113 114 SIGNAL sample : Samples14v(7 DOWNTO 0);
115 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 116 SIGNAL sample_val : STD_LOGIC;
115 117
116 118 -- AHB/APB SIGNAL
117 119 SIGNAL apbi : apb_slv_in_type;
118 120 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
119 121 SIGNAL ahbsi : ahb_slv_in_type;
120 122 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
121 123 SIGNAL ahbmi : ahb_mst_in_type;
122 124 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
123 125
124 126 SIGNAL bias_fail_bw : STD_LOGIC;
125 127
126 128 -----------------------------------------------------------------------------
127 129 -- LPP_WAVEFORM
128 130 -----------------------------------------------------------------------------
129 131 CONSTANT data_size : INTEGER := 96;
130 132 CONSTANT nb_burst_available_size : INTEGER := 50;
131 133 CONSTANT nb_snapshot_param_size : INTEGER := 2;
132 134 CONSTANT delta_vector_size : INTEGER := 2;
133 135 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
134 136
135 137 SIGNAL reg_run : STD_LOGIC;
136 138 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
137 139 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
138 140 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
139 141 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
140 142 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
141 143 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
142 144 SIGNAL enable_f0 : STD_LOGIC;
143 145 SIGNAL enable_f1 : STD_LOGIC;
144 146 SIGNAL enable_f2 : STD_LOGIC;
145 147 SIGNAL enable_f3 : STD_LOGIC;
146 148 SIGNAL burst_f0 : STD_LOGIC;
147 149 SIGNAL burst_f1 : STD_LOGIC;
148 150 SIGNAL burst_f2 : STD_LOGIC;
149 151 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
150 152 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
151 153 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 154 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 155 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 156 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 157 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 158 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
157 159 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 160 SIGNAL data_f0_in_valid : STD_LOGIC;
159 161 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
160 162 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 163 SIGNAL data_f1_in_valid : STD_LOGIC;
162 164 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
163 165 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 166 SIGNAL data_f2_in_valid : STD_LOGIC;
165 167 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
166 168 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 169 SIGNAL data_f3_in_valid : STD_LOGIC;
168 170 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 171 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 172 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 173 SIGNAL data_f0_data_out_valid : STD_LOGIC;
172 174 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
173 175 SIGNAL data_f0_data_out_ack : STD_LOGIC;
174 176 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 177 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 178 SIGNAL data_f1_data_out_valid : STD_LOGIC;
177 179 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
178 180 SIGNAL data_f1_data_out_ack : STD_LOGIC;
179 181 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 182 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 183 SIGNAL data_f2_data_out_valid : STD_LOGIC;
182 184 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
183 185 SIGNAL data_f2_data_out_ack : STD_LOGIC;
184 186 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 187 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 188 SIGNAL data_f3_data_out_valid : STD_LOGIC;
187 189 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
188 190 SIGNAL data_f3_data_out_ack : STD_LOGIC;
189 191
190 192 --MEM CTRLR
191 193 SIGNAL memi : memory_in_type;
192 194 SIGNAL memo : memory_out_type;
193 195 SIGNAL wpo : wprot_out_type;
194 196 SIGNAL sdo : sdram_out_type;
195 197
196 198 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
197 199 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 200 SIGNAL nSRAM_BE0 : STD_LOGIC;
199 201 SIGNAL nSRAM_BE1 : STD_LOGIC;
200 202 SIGNAL nSRAM_BE2 : STD_LOGIC;
201 203 SIGNAL nSRAM_BE3 : STD_LOGIC;
202 204 SIGNAL nSRAM_WE : STD_LOGIC;
203 205 SIGNAL nSRAM_CE : STD_LOGIC;
204 206 SIGNAL nSRAM_OE : STD_LOGIC;
205 207
206 208 CONSTANT padtech : INTEGER := inferred;
207 209 SIGNAL not_ramsn_0 : STD_LOGIC;
208 210
209 211 -----------------------------------------------------------------------------
210 212 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 213 SIGNAL read_buffer : STD_LOGIC;
212 214 -----------------------------------------------------------------------------
213 215 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
214 216 SIGNAL state_read_buffer_on_going : STD_LOGIC;
215 217 CONSTANT hindex : INTEGER := 1;
216 218 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
217 219 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
218 220 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
219 221 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
220 222
221 223 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 224 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 225 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 226 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 227
226 228 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
227 229 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
228 230 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
229 231
230 232 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
231 233 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
232 234 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
233 235
234 236 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
235 237 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
236 238 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
237 239
238 240 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
239 241 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
240 242 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
241 243
242 244 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
243 245 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
244 246 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
245 247
246 248 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
247 249 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
248 250 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
249 251 -----------------------------------------------------------------------------
250 252
251 253 SIGNAL current_data : INTEGER;
252 254 SIGNAL LIMIT_DATA : INTEGER := 64;
253 255
254 256 SIGNAL read_buffer_temp : STD_LOGIC;
255 257 SIGNAL read_buffer_temp_2 : STD_LOGIC;
256 258
257 259
258 260 BEGIN
259 261
260 262 -----------------------------------------------------------------------------
261 263
262 264 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
263 265 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
264 266
265 267 -----------------------------------------------------------------------------
266 268
267 269 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
268 270 TestModule_RHF1401_1 : TestModule_RHF1401
269 271 GENERIC MAP (
270 272 freq => 24*(I+1),
271 273 amplitude => 8000/(I+1),
272 274 impulsion => 0)
273 275 PORT MAP (
274 276 ADC_smpclk => ADC_smpclk,
275 277 ADC_OEB_bar => ADC_OEB_bar_CH(I),
276 278 ADC_data => ADC_data);
277 279 END GENERATE MODULE_RHF1401;
278 280
279 281 -----------------------------------------------------------------------------
280 282
281 283 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
282 284 GENERIC MAP (
283 285 ChanelCount => 8,
284 286 ncycle_cnv_high => 79,
285 287 ncycle_cnv => 500)
286 288 PORT MAP (
287 289 cnv_clk => clk49_152MHz,
288 290 cnv_rstn => rstn,
289 291 cnv => ADC_smpclk,
290 292 clk => clk25MHz,
291 293 rstn => rstn,
292 294 ADC_data => ADC_data,
293 295 ADC_nOE => ADC_OEB_bar_CH,
294 296 sample => sample,
295 297 sample_val => sample_val);
296 298
297 299 -----------------------------------------------------------------------------
298 300
299 301 lpp_lfr_1 : lpp_lfr
300 302 GENERIC MAP (
301 303 Mem_use => use_CEL, -- use_RAM
302 304 nb_data_by_buffer_size => 32,
303 305 nb_word_by_buffer_size => 30,
304 306 nb_snapshot_param_size => 32,
305 307 delta_vector_size => 32,
306 308 delta_vector_size_f0_2 => 32,
307 309 pindex => INDEX_LFR,
308 310 paddr => ADDR_LFR,
309 311 pmask => 16#fff#,
310 312 pirq_ms => 6,
311 313 pirq_wfp => 14,
312 314 hindex => 0,
313 315 top_lfr_version => X"000001")
314 316 PORT MAP (
315 317 clk => clk25MHz,
316 318 rstn => rstn,
317 sample_B => sample(2 DOWNTO 0),
318 sample_E => sample(7 DOWNTO 3),
319 sample_B => sample_s(2 DOWNTO 0),
320 sample_E => sample_s(7 DOWNTO 3),
319 321 sample_val => sample_val,
320 322 apbi => apbi,
321 323 apbo => apbo(15),
322 324 ahbi => ahbmi,
323 325 ahbo => ahbmo(0),
324 326 coarse_time => coarse_time,
325 327 fine_time => fine_time,
326 328 data_shaping_BW => bias_fail_bw);
329
330 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
331 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
332 END GENERATE all_sample;
327 333
328 334 -----------------------------------------------------------------------------
329 335 --- AHB CONTROLLER -------------------------------------------------
330 336 ahb0 : ahbctrl -- AHB arbiter/multiplexer
331 337 GENERIC MAP (defmast => 0, split => 0,
332 338 rrobin => 1, ioaddr => 16#FFF#,
333 339 ioen => 0, nahbm => 2, nahbs => 1)
334 340 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
335 341
336 342
337 343
338 344 --- AHB RAM ----------------------------------------------------------
339 345 --ahbram0 : ahbram
340 346 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
341 347 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
342 348 --ahbram1 : ahbram
343 349 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
344 350 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
345 351 --ahbram2 : ahbram
346 352 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
347 353 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
348 354 --ahbram3 : ahbram
349 355 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
350 356 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
351 357
352 358 -----------------------------------------------------------------------------
353 359 ----------------------------------------------------------------------
354 360 --- Memory controllers ---------------------------------------------
355 361 ----------------------------------------------------------------------
356 362 memctrlr : mctrl GENERIC MAP (
357 363 hindex => 0,
358 364 pindex => 0,
359 365 paddr => 0,
360 366 srbanks => 1
361 367 )
362 368 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
363 369
364 370 memi.brdyn <= '1';
365 371 memi.bexcn <= '1';
366 372 memi.writen <= '1';
367 373 memi.wrn <= "1111";
368 374 memi.bwidth <= "10";
369 375
370 376 bdr : FOR i IN 0 TO 3 GENERATE
371 377 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
372 378 PORT MAP (
373 379 data(31-i*8 DOWNTO 24-i*8),
374 380 memo.data(31-i*8 DOWNTO 24-i*8),
375 381 memo.bdrive(i),
376 382 memi.data(31-i*8 DOWNTO 24-i*8));
377 383 END GENERATE;
378 384
379 385 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
380 386 PORT MAP (address, memo.address(21 DOWNTO 2));
381 387
382 388 not_ramsn_0 <= NOT(memo.ramsn(0));
383 389
384 390 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
385 391 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
386 392 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
387 393 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
388 394 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
389 395 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
390 396 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
391 397
392 398 async_1Mx16_0: CY7C1061DV33
393 399 GENERIC MAP (
394 400 ADDR_BITS => 20,
395 401 DATA_BITS => 16,
396 402 depth => 1048576,
397 403 MEM_ARRAY_DEBUG => 32,
398 404 TimingInfo => TRUE,
399 405 TimingChecks => '1')
400 406 PORT MAP (
401 407 CE1_b => '0',
402 408 CE2 => nSRAM_CE,
403 409 WE_b => nSRAM_WE,
404 410 OE_b => nSRAM_OE,
405 411 BHE_b => nSRAM_BE1,
406 412 BLE_b => nSRAM_BE0,
407 413 A => address,
408 414 DQ => data(15 DOWNTO 0));
409 415
410 416 async_1Mx16_1: CY7C1061DV33
411 417 GENERIC MAP (
412 418 ADDR_BITS => 20,
413 419 DATA_BITS => 16,
414 420 depth => 1048576,
415 421 MEM_ARRAY_DEBUG => 32,
416 422 TimingInfo => TRUE,
417 423 TimingChecks => '1')
418 424 PORT MAP (
419 425 CE1_b => '0',
420 426 CE2 => nSRAM_CE,
421 427 WE_b => nSRAM_WE,
422 428 OE_b => nSRAM_OE,
423 429 BHE_b => nSRAM_BE3,
424 430 BLE_b => nSRAM_BE2,
425 431 A => address,
426 432 DQ => data(31 DOWNTO 16));
427 433
428 434
429 435 -----------------------------------------------------------------------------
430 436
431 437 WaveGen_Proc : PROCESS
432 438 BEGIN
433 439
434 440 -- insert signal assignments here
435 441 WAIT UNTIL clk25MHz = '1';
436 442 rstn <= '0';
437 443 apbi.psel(15) <= '0';
438 444 apbi.pwrite <= '0';
439 445 apbi.penable <= '0';
440 446 apbi.paddr <= (OTHERS => '0');
441 447 apbi.pwdata <= (OTHERS => '0');
442 448 fine_time <= (OTHERS => '0');
443 449 coarse_time <= (OTHERS => '0');
444 450 WAIT UNTIL clk25MHz = '1';
445 451 -- ahbmi.HGRANT(2) <= '1';
446 452 -- ahbmi.HREADY <= '1';
447 453 -- ahbmi.HRESP <= HRESP_OKAY;
448 454
449 455 WAIT UNTIL clk25MHz = '1';
450 456 WAIT UNTIL clk25MHz = '1';
451 457 rstn <= '1';
452 458 WAIT UNTIL clk25MHz = '1';
453 459 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000");
454 460 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000");
455 461 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000");
456 462 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000");
457 463
458 464 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000");
459 465 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000");
460 466 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080");
461 467 WAIT UNTIL clk25MHz = '1';
462 468 ---------------------------------------------------------------------------
463 469 -- CONFIGURATION STEP
464 470 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
465 471 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
466 472 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
467 473 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
468 474
469 475 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020"
470 476 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019"
471 477 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
472 478 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019"
473 479 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
474 480
475 481 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
476 482 --
477 483 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
478 484 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
479 485 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
480 486
481 487
482 488 WAIT UNTIL clk25MHz = '1';
483 489 WAIT UNTIL clk25MHz = '1';
484 490
485 491
486 492 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
487 493 WAIT UNTIL clk25MHz = '1';
488 494 WAIT UNTIL clk25MHz = '1';
489 495 WAIT UNTIL clk25MHz = '1';
490 496 WAIT UNTIL clk25MHz = '1';
491 497 WAIT UNTIL clk25MHz = '1';
492 498 WAIT UNTIL clk25MHz = '1';
493 499 WAIT FOR 1 us;
494 500 coarse_time <= X"00000001";
495 501 ---------------------------------------------------------------------------
496 502 -- RUN STEP
497 503 WAIT FOR 200 ms;
498 504 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
499 505 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
500 506 WAIT FOR 10 us;
501 507 WAIT UNTIL clk25MHz = '1';
502 508 WAIT UNTIL clk25MHz = '1';
503 509 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
504 510 WAIT UNTIL clk25MHz = '1';
505 511 coarse_time <= X"00000010";
506 512 WAIT FOR 100 ms;
507 513 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
508 514 WAIT FOR 10 us;
509 515 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
510 516 WAIT FOR 200 ms;
511 517 REPORT "*** END simulation ***" SEVERITY failure;
512 518
513 519
514 520 WAIT;
515 521
516 522 END PROCESS WaveGen_Proc;
517 523 -----------------------------------------------------------------------------
518 524
519 525 -----------------------------------------------------------------------------
520 526 -- IRQ
521 527 -----------------------------------------------------------------------------
522 528 PROCESS (clk25MHz, rstn)
523 529 BEGIN -- PROCESS
524 530 IF rstn = '0' THEN -- asynchronous reset (active low)
525 531
526 532 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
527 533
528 534 END IF;
529 535 END PROCESS;
530 536 -----------------------------------------------------------------------------
531 537
532 538 END;
Show file before | Show file after | Hide comments
@@ -1,28 +1,28
1 1 ./amba_lcd_16x2_ctrlr
2 2 ./general_purpose
3 3 ./general_purpose/lpp_AMR
4 4 ./general_purpose/lpp_balise
5 5 ./general_purpose/lpp_delay
6 6 ./lpp_amba
7 7 ./dsp/iir_filter
8 8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft_rtax
10 ./lpp_memory
9 11 ./dsp/lpp_fft
10 ./dsp/lpp_fft_rtax
11 12 ./lfr_time_management
12 13 ./lpp_ad_Conv
13 14 ./lpp_bootloader
14 15 ./lpp_cna
15 16 ./lpp_spectral_matrix
16 17 ./lpp_demux
17 18 ./lpp_Header
18 19 ./lpp_matrix
19 ./lpp_memory
20 ./lpp_dma
21 20 ./lpp_uart
22 21 ./lpp_usb
23 22 ./lpp_waveform
23 ./lpp_dma
24 24 ./lpp_top_lfr
25 25 ./lpp_Header
26 26 ./lpp_leon3_soc
27 27 ./lpp_debug_lfr
28 28 ./lpp_sim/CY7C1061DV33
Show file before | Show file after | Hide comments
@@ -1,121 +1,122
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.iir_filter.ALL;
27 27 USE lpp.FILTERcfg.ALL;
28 28 USE lpp.general_purpose.ALL;
29 29 LIBRARY techmap;
30 30 USE techmap.gencomp.ALL;
31 31
32 32 ENTITY RAM_CTRLR_v2 IS
33 33 GENERIC(
34 34 tech : INTEGER := 0;
35 35 Input_SZ_1 : INTEGER := 16;
36 36 Mem_use : INTEGER := use_RAM
37 37 );
38 38 PORT(
39 39 rstn : IN STD_LOGIC;
40 40 clk : IN STD_LOGIC;
41 41 -- R/W Ctrl
42 42 ram_write : IN STD_LOGIC;
43 43 ram_read : IN STD_LOGIC;
44 44 -- ADDR Ctrl
45 45 raddr_rst : IN STD_LOGIC;
46 46 raddr_add1 : IN STD_LOGIC;
47 47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 48 -- Data
49 49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 51 );
52 52 END RAM_CTRLR_v2;
53 53
54 54
55 55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56 56
57 57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 59 SIGNAL WEN, REN : STD_LOGIC;
60 60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
63 63
64 64 BEGIN
65 65
66 66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
67 67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
68 68 -----------------------------------------------------------------------------
69 69 -- RAM
70 70 -----------------------------------------------------------------------------
71 71
72 72 memCEL : IF Mem_use = use_CEL GENERATE
73 73 WEN <= NOT ram_write;
74 74 REN <= NOT ram_read;
75 75 -- RAMblk : RAM_CEL_N
76 RAMblk : RAM_CEL_N
77 GENERIC MAP(Input_SZ_1)
76 -- GENERIC MAP(Input_SZ_1)
77 RAMblk : RAM_CEL
78 GENERIC MAP(Input_SZ_1, 8)
78 79 PORT MAP(
79 80 WD => WD,
80 81 RD => RD,
81 82 WEN => WEN,
82 83 REN => REN,
83 84 WADDR => WADDR,
84 85 RADDR => RADDR,
85 86 RWCLK => clk,
86 87 RESET => rstn
87 88 ) ;
88 89 END GENERATE;
89 90
90 91 memRAM : IF Mem_use = use_RAM GENERATE
91 92 SRAM : syncram_2p
92 93 GENERIC MAP(tech, 8, Input_SZ_1)
93 94 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
94 95 END GENERATE;
95 96
96 97 -----------------------------------------------------------------------------
97 98 -- RADDR
98 99 -----------------------------------------------------------------------------
99 100 PROCESS (clk, rstn)
100 101 BEGIN -- PROCESS
101 102 IF rstn = '0' THEN -- asynchronous reset (active low)
102 103 counter <= (OTHERS => '0');
103 104 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
104 105 IF raddr_rst = '1' THEN
105 106 counter <= (OTHERS => '0');
106 107 ELSIF raddr_add1 = '1' THEN
107 108 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
108 109 END IF;
109 110 END IF;
110 111 END PROCESS;
111 112 RADDR <= counter;
112 113
113 114 -----------------------------------------------------------------------------
114 115 -- WADDR
115 116 -----------------------------------------------------------------------------
116 117 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
117 118 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
118 119 STD_LOGIC_VECTOR(UNSIGNED(counter));
119 120
120 121
121 122 END ar_RAM_CTRLR_v2;
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@@ -1,16 +1,16
1 fft_components.vhd
1 2 lpp_fft.vhd
2 3 actar.vhd
3 4 actram.vhd
4 5 CoreFFT.vhd
5 fft_components.vhd
6 6 fftDp.vhd
7 7 fftSm.vhd
8 8 primitives.vhd
9 9 twiddle.vhd
10 10 APB_FFT.vhd
11 11 Driver_FFT.vhd
12 12 FFT.vhd
13 13 FFTamont.vhd
14 14 FFTaval.vhd
15 15 Flag_Extremum.vhd
16 16 Linker_FFT.vhd
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@@ -1,14 +1,14
1 lpp_matrix.vhd
1 2 ALU_Driver.vhd
2 3 APB_Matrix.vhd
3 4 ReUse_CTRLR.vhd
4 5 Dispatch.vhd
5 6 DriveInputs.vhd
6 7 GetResult.vhd
7 8 MatriceSpectrale.vhd
8 9 Matrix.vhd
9 10 SpectralMatrix.vhd
10 11 Starter.vhd
11 12 TopMatrix_PDR.vhd
12 13 TopSpecMatrix.vhd
13 14 Top_MatrixSpec.vhd
14 lpp_matrix.vhd
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@@ -1,218 +1,219
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.lpp_memory.ALL;
27 27 USE lpp.iir_filter.ALL;
28 28 USE lpp.lpp_waveform_pkg.ALL;
29 29
30 30 LIBRARY techmap;
31 31 USE techmap.gencomp.ALL;
32 32
33 33 ENTITY lpp_waveform_fifo_headreg IS
34 34 GENERIC(
35 35 tech : INTEGER := 0
36 36 );
37 37 PORT(
38 38 clk : IN STD_LOGIC;
39 39 rstn : IN STD_LOGIC;
40 40 ---------------------------------------------------------------------------
41 41 run : IN STD_LOGIC;
42 42 ---------------------------------------------------------------------------
43 43 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
44 44 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
47 47 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
48 48 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
49 49 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
50 50 ---------------------------------------------------------------------------
51 51 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 52 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 53 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
54 54 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 55 );
56 56 END ENTITY;
57 57
58 58
59 59 ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS
60 60 SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 61 SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 62 SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 63 SIGNAL one_ren_and_notEmpty : STD_LOGIC;
64 64 SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 65 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
66 66 SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 67 SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 68 SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 BEGIN
71 71
72 72 -----------------------------------------------------------------------------
73 73 -- DATA_REN_FIFO
74 74 -----------------------------------------------------------------------------
75 75 i_data_ren <= s_ren;
76
76 77 PROCESS (clk, rstn)
77 78 BEGIN
78 79 IF rstn = '0' THEN
79 80 s_ren_reg <= (OTHERS => '1');
80 81 ELSIF clk'EVENT AND clk = '1' THEN
81 82 IF run = '1' THEN
82 83 s_ren_reg <= s_ren;
83 84 ELSE
84 85 s_ren_reg <= (OTHERS => '1');
85 86 END IF;
86 87 END IF;
87 88 END PROCESS;
88 89
89 90 s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE
90 91 NOT ((NOT i_empty(0)) AND (NOT reg_full(0)));
91 s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
92 '1' WHEN s_ren(0) = '0' ELSE
92 s_ren(1) <= '1' WHEN s_ren(0) = '0' ELSE
93 o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
93 94 NOT ((NOT i_empty(1)) AND (NOT reg_full(1)));
94 s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
95 '1' WHEN s_ren(0) = '0' ELSE
95 s_ren(2) <= '1' WHEN s_ren(0) = '0' ELSE
96 96 '1' WHEN s_ren(1) = '0' ELSE
97 o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
97 98 NOT ((NOT i_empty(2)) AND (NOT reg_full(2)));
98 s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
99 '1' WHEN s_ren(0) = '0' ELSE
99 s_ren(3) <= '1' WHEN s_ren(0) = '0' ELSE
100 100 '1' WHEN s_ren(1) = '0' ELSE
101 101 '1' WHEN s_ren(2) = '0' ELSE
102 o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
102 103 NOT ((NOT i_empty(3)) AND (NOT reg_full(3)));
103 104 -----------------------------------------------------------------------------
104 105 all_ren : FOR I IN 3 DOWNTO 0 GENERATE
105 106 ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I));
106 107 END GENERATE all_ren;
107 108 one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1';
108 109
109 110 -----------------------------------------------------------------------------
110 111 -- DATA
111 112 -----------------------------------------------------------------------------
112 113 o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0;
113 114 o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1;
114 115 o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2;
115 116 o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3;
116 117
117 118 PROCESS (clk, rstn)
118 119 BEGIN
119 120 IF rstn = '0' THEN
120 121 s_rdata_0 <= (OTHERS => '0');
121 122 s_rdata_1 <= (OTHERS => '0');
122 123 s_rdata_2 <= (OTHERS => '0');
123 124 s_rdata_3 <= (OTHERS => '0');
124 125 ELSIF clk'EVENT AND clk = '1' THEN
125 126 IF run = '1' THEN
126 127 IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
127 128 IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
128 129 IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
129 130 IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
130 131 ELSE
131 s_rdata_0 <= (OTHERS => '0');
132 s_rdata_1 <= (OTHERS => '0');
133 s_rdata_2 <= (OTHERS => '0');
134 s_rdata_3 <= (OTHERS => '0');
132 s_rdata_0 <= (OTHERS => '0');
133 s_rdata_1 <= (OTHERS => '0');
134 s_rdata_2 <= (OTHERS => '0');
135 s_rdata_3 <= (OTHERS => '0');
135 136 END IF;
136 137 END IF;
137 138 END PROCESS;
138 139
139 140 all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE
140 141 PROCESS (clk, rstn)
141 142 BEGIN
142 143 IF rstn = '0' THEN
143 144 reg_full(I) <= '0';
144 145 ELSIF clk'EVENT AND clk = '1' THEN
145 146 -- IF s_ren_reg(I) = '0' THEN
146 147 IF run = '1' THEN
147 148 IF s_ren(I) = '0' THEN
148 149 reg_full(I) <= '1';
149 150 ELSIF o_data_ren(I) = '0' THEN
150 151 reg_full(I) <= '0';
151 152 END IF;
152 153 ELSE
153 154 reg_full(I) <= '0';
154 155 END IF;
155 156 END IF;
156 157 END PROCESS;
157 158 END GENERATE all_reg_full;
158 159
159 160 -----------------------------------------------------------------------------
160 161 -- EMPTY
161 162 -----------------------------------------------------------------------------
162 163 o_empty <= NOT reg_full;
163 164
164 165 -----------------------------------------------------------------------------
165 166 -- EMPTY_ALMOST
166 167 -----------------------------------------------------------------------------
167 168 o_empty_almost <= s_empty_almost;
168 169
169 170 all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE
170 171 PROCESS (clk, rstn)
171 172 BEGIN -- PROCESS
172 173 IF rstn = '0' THEN -- asynchronous reset (active low)
173 174 s_empty_almost(I) <= '1';
174 175 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
175 176 IF run = '1' THEN
176 177 IF s_ren(I) = '0' THEN
177 178 s_empty_almost(I) <= i_empty_almost(I);
178 179 ELSIF o_data_ren(I) = '0' THEN
179 180 s_empty_almost(I) <= '1';
180 181 ELSE
181 182 IF i_empty_almost(I) = '0' THEN
182 183 s_empty_almost(I) <= '0';
183 184 END IF;
184 185 END IF;
185 186 ELSE
186 187 s_empty_almost(I) <= '1';
187 188 END IF;
188 189 END IF;
189 190 END PROCESS;
190 191 END GENERATE all_empty_almost;
191 192
192 193 END ARCHITECTURE;
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