##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)
martin -
r95:236e70a254cc martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,128
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity Starter is
27 port(
28 clk : in std_logic;
29 raz : in std_logic;
30 Full : in std_logic_vector(1 downto 0);
31 Empty : in std_logic_vector(1 downto 0);
32 Statu : in std_logic_vector(3 downto 0);
33 Write : in std_logic;
34 Start : out std_logic
35 );
36 end Starter;
37
38
39 architecture ar_Starter of Starter is
40
41 type etat is (eX,e0,e1,e2);
42 signal ect : etat;
43
44 signal Write_reg : std_logic;
45 signal Conjugate : std_logic;
46
47 begin
48 process(clk,raz)
49 begin
50
51 if(raz='0')then
52 Start <= '0';
53 Write_reg <= '0';
54 ect <= eX;
55
56 elsif(clk'event and clk='1')then
57 Write_reg <= Write;
58
59 case ect is
60 when eX =>
61 if(Conjugate='0')then
62 if(full="11")then
63 Start <= '1';
64 ect <= e0;
65 end if;
66 else
67 if(full(0)='1')then
68 Start <= '1';
69 ect <= e0;
70 end if;
71 end if;
72
73 when e0 =>
74 if(Conjugate='0')then
75 if(empty="11")then
76 ect <= e1;
77 end if;
78 else
79 if(empty(0)='1')then
80 ect <= e2;
81 end if;
82 end if;
83
84 when e1 =>
85 if(Write_reg='1' and Write='0')then
86 ect <= e2;
87 end if;
88
89 when e2 =>
90 if(Write_reg='1' and Write='0')then
91 Start <= '0';
92 ect <= eX;
93 end if;
94
95 end case;
96
97 end if;
98 end process;
99
100
101 With Statu select
102 Conjugate <= '1' when "0001",
103 '1' when "0011",
104 '1' when "0110",
105 '1' when "1010",
106 '1' when "1111",
107 '0' when others;
108
109 end ar_Starter;
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Show file before | Show file after | Hide comments
@@ -0,0 +1,62
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity Top_MatrixSpec is
28 generic(
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
31 port(
32 clk : in std_logic;
33 reset : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 Full : in std_logic_vector(1 downto 0);
38 Empty : in std_logic_vector(1 downto 0);
39 ReadFIFO : out std_logic_vector(1 downto 0);
40 FullFIFO : in std_logic;
41 WriteFIFO : out std_logic;
42 Result : out std_logic_vector(Result_SZ-1 downto 0)
43 );
44 end entity;
45
46
47 architecture ar_Top_MatrixSpec of Top_MatrixSpec is
48
49 signal Start : std_logic;
50 signal Write : std_logic;
51
52 begin
53 WriteFIFO <= Write;
54
55 ST0 : Starter
56 port map(clk,reset,Full,Empty,Statu,Write,Start);
57
58 Mspec : SpectralMatrix
59 generic map(Input_SZ,Result_SZ)
60 port map(clk,reset,Start,FIFO1,FIFO2,Statu,FullFIFO,ReadFIFO,Write,Result);
61
62 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,178 +1,174
1 1 #include <stdio.h>
2 2 #include "lpp_apb_functions.h"
3 3 #include "apb_fifo_Driver.h"
4 4 #include "apb_Matrix_Driver.h"
5 5 #include "apb_uart_Driver.h"
6 #include "apb_delay_Driver.h"
7 6 #include "apb_gpio_Driver.h"
8 7
9 // Matrix With 2 FIFO Input
8 ///////////// Matrix With 2 FIFO Input /////////////////////////////////////////////
10 9 int main()
11 10 {
12 11 int i=0,save;
13 12 char temp[256];
14 13 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
15 14 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
16 15 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
17 16 // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
18 17 // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
19 18 int Table[256];
20 19
21 20
22 21 FIFO_Device* fifoX = openFIFO(0);
23 DELAY_Device* delay0 = openDELAY(0);
24 22 UART_Device* uart0 = openUART(0);
25 23 FIFO_Device* fifoIn = openFIFO(1);
26 24 MATRIX_Device* mspec = openMatrix(0);
27 25 FIFO_Device* fifoOut = openFIFO(2);
28 26 GPIO_Device* gpio0 = openGPIO(0);
29 27
30 28 printf("\nDebut Main\n\n");
31 29
32 Setup(delay0,30000000);
33 30 gpio0->oen = 0x3;
34 31 gpio0->Dout = 0x0;
35 32
36 33 ///////////////////////////////////////////////////////////////////////////
37 34 mspec->Statu = 2;
38 35 FillFifo(fifoIn,0,TblB1);
39 36 FillFifo(fifoIn,1,TblB2);
40 37 gpio0->Dout = 0x1;
41 38
42 39 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
43 40 {
44 41 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
45 42 i++;
46 43 }
47 44 save = i;
48 45 gpio0->Dout = 0x2;
49 46
50 47 sprintf(temp,"\nReels\tImaginaires\n\r");
51 48 uartputs(uart0,temp);
52 49 for (i = 0 ; i < save ; i+=2)
53 50 {
54 51 sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
55 52 uartputs(uart0,temp);
56 53 }
57 54 i = 0;
58 55 gpio0->Dout = 0x0;
59 56
60 57 ///////////////////////////////////////////////////////////////////////////
61 58 mspec->Statu = 1;
62 59 FillFifo(fifoIn,0,TblB1);
63 60 gpio0->Dout = 0x1;
64 Delay_us(delay0,20);
65 61 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
66 62 {
67 63 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
68 64 i++;
69 65 }
70 66 save = i;
71 67 gpio0->Dout = 0x2;
72 68
73 69 sprintf(temp,"\nReels\n\r");
74 70 uartputs(uart0,temp);
75 71 for (i = 0 ; i < save ; i++)
76 72 {
77 73 sprintf(temp,"%d\n\r",Table[i]);
78 74 uartputs(uart0,temp);
79 75 }
80 76 i = 0;
81 77 gpio0->Dout = 0x0;
82 78
83 79 ///////////////////////////////////////////////////////////////////////////
84 80 mspec->Statu = 4;
85 81 FillFifo(fifoIn,0,TblB1);
86 82 FillFifo(fifoIn,1,TblB3);
87 83 gpio0->Dout = 0x1;
88 84
89 85 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
90 86 {
91 87 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
92 88 i++;
93 89 }
94 90 save = i;
95 91 gpio0->Dout = 0x2;
96 92
97 93 sprintf(temp,"\nReels\tImaginaires\n\r");
98 94 uartputs(uart0,temp);
99 95 for (i = 0 ; i < save ; i+=2)
100 96 {
101 97 sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
102 98 uartputs(uart0,temp);
103 99 }
104 100 i = 0;
105 101 gpio0->Dout = 0x0;
106 102
107 103 printf("\nFin Main\n\n");
108 104 return 0;
109 105 }
110 106
111 107
112 // Matrix With 5 FIFO Input
108 ///////////// Matrix With 5 FIFO Input /////////////////////////////////////////////
113 109 int main2()
114 110 {
115 111 int save1,save2;
116 112 char temp[256];
117 113 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
118 114 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
119 115 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
120 116 int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
121 117 int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
122 118
123 119 FIFO_Device* fifoX = openFIFO(0);
124 120 UART_Device* uart0 = openUART(0);
125 121 FIFO_Device* fifoIn = openFIFO(1);
126 122 FIFO_Device* fifoOut = openFIFO(2);
127 123
128 124 printf("\nDebut Main\n\n");
129 125
130 126 FillFifo(fifoIn,0,TblB1);
131 127 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
132 128
133 129 FillFifo(fifoIn,1,TblB2);
134 130 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
135 131
136 132 FillFifo(fifoIn,2,TblB3);
137 133 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
138 134
139 135 FillFifo(fifoIn,3,TblE1);
140 136 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
141 137
142 138 FillFifo(fifoIn,4,TblE2);
143 139
144 140 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
145 141
146 142 while(1){
147 143
148 144 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
149 145
150 146 save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
151 147 save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
152 148
153 149 sprintf(temp,"%d\t%d\n\r",save1,save2);
154 150 uartputs(uart0,temp);
155 151 }
156 152 printf("\nFin Main\n\n");
157 153 return 0;
158 154 }
159 155
160 156
161 157
162 158
163 159 /////////////////// Test R/W Fifo OKAI ///////////////////////////////////
164 160
165 161 /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11;
166 162 Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata];
167 163 printf("data: %x\n",Table[1]);
168 164
169 165 FillFifo(fifoX,0,TblX);
170 166 for (i = 1 ; i < 8 ; i++)
171 167 {
172 168 Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex;
173 169 }
174 170 printf("data: %x\n",Table[1]);
175 171 printf("data: %x\n",Table[2]);
176 172 printf("data: %x\n",Table[3]);
177 173 printf("data: %x\n",Table[4]);*/
178 174
Show file before | Show file after | Hide comments
@@ -1,118 +1,117
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_matrix.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34 34
35 35 entity APB_Matrix is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Input_SZ : integer := 16;
43 43 Result_SZ : integer := 32);
44 44 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
45 clk : in std_logic;
46 rst : in std_logic;
47 47 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
48 48 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
49 Full : in std_logic_vector(1 downto 0);
50 Empty : in std_logic_vector(1 downto 0);
49 51 ReadFIFO : out std_logic_vector(1 downto 0);
52 FullFIFO : in std_logic;
50 53 WriteFIFO : out std_logic;
51 54 Result : out std_logic_vector(Result_SZ-1 downto 0);
52 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
53 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 57 );
55 58 end APB_Matrix;
56 59
57 60
58 61 architecture ar_APB_Matrix of APB_Matrix is
59 62
60 63 constant REVISION : integer := 1;
61 64
62 65 constant pconfig : apb_config_type := (
63 66 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
64 67 1 => apb_iobar(paddr, pmask));
65 68
66 69 type MATRIX_ctrlr_Reg is record
67 MATRIX_Ctrl : std_logic_vector(4 downto 0);
70 MATRIX_Statu : std_logic_vector(3 downto 0);
68 71 end record;
69 72
70 73 signal Rec : MATRIX_ctrlr_Reg;
71 74 signal Rdata : std_logic_vector(31 downto 0);
72 signal Start : std_logic;
73 signal statu : std_logic_vector(3 downto 0);
74 75
75 76 begin
76 77
77 Mspec0 : SpectralMatrix
78 Mspec0 : Top_MatrixSpec
78 79 generic map (Input_SZ,Result_SZ)
79 port map(clk,rst,Start,FIFO1,FIFO2,Statu,ReadFIFO,WriteFIFO,Result);
80 port map(clk,rst,Rec.MATRIX_Statu,FIFO1,FIFO2,Full,Empty,ReadFIFO,FullFIFO,WriteFIFO,Result);
80 81
81 Statu <= Rec.MATRIX_Ctrl(3 downto 0);
82 Start <= Rec.MATRIX_Ctrl(4);
83 82
84 83 process(rst,clk)
85 84 begin
86 85 if(rst='0')then
87 Rec.MATRIX_Ctrl <= (others => '0');
86 Rec.MATRIX_Statu <= (others => '0');
88 87
89 88 elsif(clk'event and clk='1')then
90 89
91 90 --APB Write OP
92 91 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 92 case apbi.paddr(abits-1 downto 2) is
94 93 when "000000" =>
95 Rec.MATRIX_Ctrl <= apbi.pwdata(4 downto 0);
94 Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
96 95 when others =>
97 96 null;
98 97 end case;
99 98 end if;
100 99
101 100 --APB Read OP
102 101 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
103 102 case apbi.paddr(abits-1 downto 2) is
104 103 when "000000" =>
105 Rdata(31 downto 5) <= (others => '0');
106 Rdata(4 downto 0) <= Rec.MATRIX_Ctrl;
104 Rdata(31 downto 4) <= (others => '0');
105 Rdata(3 downto 0) <= Rec.MATRIX_Statu;
107 106 when others =>
108 107 Rdata <= (others => '0');
109 108 end case;
110 109 end if;
111 110
112 111 end if;
113 112 apbo.pconfig <= pconfig;
114 113 end process;
115 114
116 115 apbo.prdata <= Rdata when apbi.penable = '1';
117 116
118 117 end ar_APB_MATRIX; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,209 +1,241
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 31
32 32 package lpp_matrix is
33 33
34 34 component APB_Matrix is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 Input_SZ : integer := 16;
42 42 Result_SZ : integer := 32);
43 43 port (
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
44 clk : in std_logic;
45 rst : in std_logic;
46 46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
48 50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
49 52 WriteFIFO : out std_logic;
50 53 Result : out std_logic_vector(Result_SZ-1 downto 0);
51 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
52 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
53 56 );
54 57 end component;
55 58
59 component Top_MatrixSpec is
60 generic(
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
63 port(
64 clk : in std_logic;
65 reset : in std_logic;
66 Statu : in std_logic_vector(3 downto 0);
67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
69 Full : in std_logic_vector(1 downto 0);
70 Empty : in std_logic_vector(1 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
72 FullFIFO : in std_logic;
73 WriteFIFO : out std_logic;
74 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 );
76 end component;
56 77
57 78 component SpectralMatrix is
58 79 generic(
59 80 Input_SZ : integer := 16;
60 81 Result_SZ : integer := 32);
61 82 port(
62 83 clk : in std_logic;
63 84 reset : in std_logic;
64 85 Start : in std_logic;
65 86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
66 87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
67 88 Statu : in std_logic_vector(3 downto 0);
68 89 FullFIFO : in std_logic;
69 90 ReadFIFO : out std_logic_vector(1 downto 0);
70 91 WriteFIFO : out std_logic;
71 92 Result : out std_logic_vector(Result_SZ-1 downto 0)
72 93 );
73 94 end component;
74 95
75 96
76 97 component Matrix is
77 98 generic(
78 99 Input_SZ : integer := 16);
79 100 port(
80 101 clk : in std_logic;
81 102 raz : in std_logic;
82 103 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
83 104 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
84 105 Take : in std_logic;
85 106 Received : in std_logic;
86 107 Conjugate : in std_logic;
87 108 Valid : out std_logic;
88 109 Read : out std_logic;
89 110 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
90 111 );
91 112 end component;
92 113
93 114 component GetResult is
94 115 generic(
95 116 Result_SZ : integer := 32);
96 117 port(
97 118 clk : in std_logic;
98 119 raz : in std_logic;
99 120 Valid : in std_logic;
100 121 Conjugate : in std_logic;
101 122 Res : in std_logic_vector(Result_SZ-1 downto 0);
102 123 Full : in std_logic;
103 124 WriteFIFO : out std_logic;
104 125 Received : out std_logic;
105 126 Result : out std_logic_vector(Result_SZ-1 downto 0)
106 127 );
107 128 end component;
108 129
109 130
110 131 component TopMatrix_PDR is
111 132 generic(
112 133 Input_SZ : integer := 16;
113 134 Result_SZ : integer := 32);
114 135 port(
115 136 clk : in std_logic;
116 137 reset : in std_logic;
117 138 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
118 139 FULLin : in std_logic_vector(4 downto 0);
119 140 READin : in std_logic_vector(1 downto 0);
120 141 WRITEin : in std_logic;
121 142 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
122 143 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
123 144 Start : out std_logic;
124 145 Read : out std_logic_vector(4 downto 0);
125 146 Statu : out std_logic_vector(3 downto 0)
126 147 );
127 148 end component;
128 149
129 150
130 151 component DriveInputs is
131 152 port(
132 153 clk : in std_logic;
133 154 raz : in std_logic;
134 155 Read : in std_logic;
135 156 Conjugate : in std_logic;
136 157 Take : out std_logic;
137 158 ReadFIFO : out std_logic_vector(1 downto 0)
138 159 );
139 160 end component;
140 161
162 component Starter is
163 port(
164 clk : in std_logic;
165 raz : in std_logic;
166 Full : in std_logic_vector(1 downto 0);
167 Empty : in std_logic_vector(1 downto 0);
168 Statu : in std_logic_vector(3 downto 0);
169 Write : in std_logic;
170 Start : out std_logic
171 );
172 end component;
141 173
142 174 component ALU_Driver is
143 175 generic(
144 176 Input_SZ_1 : integer := 16;
145 177 Input_SZ_2 : integer := 16);
146 178 port(
147 179 clk : in std_logic;
148 180 reset : in std_logic;
149 181 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
150 182 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
151 183 Take : in std_logic;
152 184 Received : in std_logic;
153 185 Conjugate : in std_logic;
154 186 Valid : out std_logic;
155 187 Read : out std_logic;
156 188 CTRL : out std_logic_vector(4 downto 0);
157 189 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
158 190 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
159 191 );
160 192 end component;
161 193
162 194
163 195 component ALU_v2 is
164 196 generic(
165 197 Arith_en : integer := 1;
166 198 Logic_en : integer := 1;
167 199 Input_SZ_1 : integer := 16;
168 200 Input_SZ_2 : integer := 9);
169 201 port(
170 202 clk : in std_logic;
171 203 reset : in std_logic;
172 204 ctrl : in std_logic_vector(4 downto 0);
173 205 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
174 206 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
175 207 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
176 208 );
177 209 end component;
178 210
179 211
180 212 component MAC_v2 is
181 213 generic(
182 214 Input_SZ_A : integer := 8;
183 215 Input_SZ_B : integer := 8);
184 216 port(
185 217 clk : in std_logic;
186 218 reset : in std_logic;
187 219 clr_MAC : in std_logic;
188 220 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
189 221 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
190 222 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
191 223 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
192 224 );
193 225 end component;
194 226
195 227
196 228 component TwoComplementer is
197 229 generic(
198 230 Input_SZ : integer := 16);
199 231 port(
200 232 clk : in std_logic;
201 233 reset : in std_logic;
202 234 clr : in std_logic;
203 235 TwoComp : in std_logic;
204 236 OP : in std_logic_vector(Input_SZ-1 downto 0);
205 237 RES : out std_logic_vector(Input_SZ-1 downto 0)
206 238 );
207 239 end component;
208 240
209 241 end; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,285 +1,286
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 -- APB_FIFO.vhd
23 23 library ieee;
24 24 use ieee.std_logic_1164.all;
25 25 use IEEE.numeric_std.all;
26 26 library techmap;
27 27 use techmap.gencomp.all;
28 28 library grlib;
29 29 use grlib.amba.all;
30 30 use grlib.stdlib.all;
31 31 use grlib.devices.all;
32 32 library lpp;
33 33 use lpp.lpp_amba.all;
34 34 use lpp.apb_devices_list.all;
35 35 use lpp.lpp_memory.all;
36 36
37 37
38 38 entity APB_FIFO is
39 39 generic (
40 tech : integer := apa3;
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
49 R : integer := 1;
50 W : integer := 1
40 tech : integer := apa3;
41 pindex : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
45 abits : integer := 8;
46 FifoCnt : integer := 2;
47 Data_sz : integer := 16;
48 Addr_sz : integer := 9;
49 Enable_ReUse : std_logic := '0';
50 R : integer := 1;
51 W : integer := 1
51 52 );
52 53 port (
53 54 clk : in std_logic; --! Horloge du composant
54 55 rst : in std_logic; --! Reset general du composant
55 56 rclk : in std_logic;
56 57 wclk : in std_logic;
57 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
58 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
58 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
59 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
59 60 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
60 61 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
61 62 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
62 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
63 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
63 64 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
64 65 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
65 66 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
66 67 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
67 68 );
68 69 end entity;
69 70
70 71 architecture ar_APB_FIFO of APB_FIFO is
71 72
72 73 constant REVISION : integer := 1;
73 74
74 75 constant pconfig : apb_config_type := (
75 76 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
76 77 1 => apb_iobar(paddr, pmask));
77 78
78 79 type FIFO_ctrlr_Reg is record
79 80 FIFO_Ctrl : std_logic_vector(31 downto 0);
80 81 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
81 82 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
82 83 end record;
83 84
84 85 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
85 86 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
86 87 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
87 88
88 89 signal Rec : FIFO_ctrlr_Reg_Vec;
89 90 signal PRdata : std_logic_vector(31 downto 0);
90 91 signal FIFO_ID : std_logic_vector(31 downto 0);
91 92 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
92 93 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
93 94 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
94 95 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
95 96 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
96 97 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
97 98 signal sRclk : std_logic;
98 99 signal sWclk : std_logic;
99 100 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
100 101 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
101 102 signal sRDATA : fifodatabus;
102 103 signal sWDATA : fifodatabus;
103 104 signal sWADDR : fifoaddressbus;
104 105 signal sRADDR : fifoaddressbus;
105 106 signal ReUse : std_logic_vector(FifoCnt-1 downto 0); --27/01/12
106 107
107 108 type state_t is (idle,Read);
108 109 signal fiforeadfsmst : state_t;
109 110
110 111 begin
111 112
112 113 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
113 114 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
114 115 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
115 116
116 117
117 118 Write : if W /= 0 generate
118 119 FIFO_ID(4) <= '1';
119 120 sWen <= sWen_APB;
120 121 sWclk <= clk;
121 122 Wrapb: for i in 0 to FifoCnt-1 generate
122 123 sWDATA(i) <= Rec(i).FIFO_Wdata;
123 124 end generate;
124 125 end generate;
125 126
126 127 Writeext : if W = 0 generate
127 128 FIFO_ID(4) <= '0';
128 129 sWen <= WEN;
129 130 sWclk <= Wclk;
130 131 Wrext: for i in 0 to FifoCnt-1 generate
131 132 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
132 133 end generate;
133 134 end generate;
134 135
135 136 Read : if R /= 0 generate
136 137 FIFO_ID(5) <= '1';
137 138 sRen <= sRen_APB;
138 139 srclk <= clk;
139 140 Rdapb: for i in 0 to FifoCnt-1 generate
140 141 Rec(i).FIFO_Rdata <= sRDATA(i);
141 142 end generate;
142 143 end generate;
143 144
144 145 Readext : if R = 0 generate
145 146 FIFO_ID(5) <= '0';
146 147 sRen <= REN;
147 148 srclk <= rclk;
148 149 Drext: for i in 0 to FifoCnt-1 generate
149 150 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
150 151 end generate;
151 152 end generate;
152 153
153 154 ctrlregs: for i in 0 to FifoCnt-1 generate
154 155 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
155 156 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
156 157 Rec(i).FIFO_Ctrl(16) <= sFull(i);
157 158 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
158 159 ReUse(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
159 160 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
160 161 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
161 162 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
162 163 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty|
163 164 end generate; -- 31 17 16 15 1 0
164 165
165 166 Empty <= sEmpty;
166 167 Full <= sFull;
167 168
168 169
169 170 fifos: for i in 0 to FifoCnt-1 generate
170 171 FIFO0 : lpp_fifo
171 generic map (tech,Data_sz,Addr_sz)
172 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
172 173 port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
173 174 end generate;
174 175
175 176 process(rst,clk)
176 177 begin
177 178 if(rst='0')then
178 179 rstloop1: for i in 0 to FifoCnt-1 loop
179 180 Rec(i).FIFO_Wdata <= (others => '0');
180 181 Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
181 182 --Rec(i).FIFO_Ctrl(17) <= '0';
182 183 sWen_APB(i) <= '1';
183 184 end loop;
184 185 elsif(clk'event and clk='1')then
185 186 --APB Write OP
186 187 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
187 188 writelp: for i in 0 to FifoCnt-1 loop
188 189 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
189 190 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
190 191 --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
191 192 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
192 193 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
193 194 sWen_APB(i) <= '0';
194 195 end if;
195 196 end loop;
196 197 else
197 198 sWen_APB <= (others =>'1');
198 199 end if;
199 200 --APB Read OP
200 201 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
201 202 if(apbi.paddr(abits-1 downto 2)="000000") then
202 203 PRdata <= FIFO_ID;
203 204 else
204 205 readlp: for i in 0 to FifoCnt-1 loop
205 206 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
206 207 PRdata <= Rec(i).FIFO_Ctrl;
207 208 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
208 209 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
209 210 end if;
210 211 end loop;
211 212 end if;
212 213 end if;
213 214 end if;
214 215 apbo.pconfig <= pconfig;
215 216 end process;
216 217 apbo.prdata <= PRdata when apbi.penable = '1';
217 218
218 219
219 220
220 221 process(rst,clk)
221 222 begin
222 223 if(rst='0')then
223 224 fiforeadfsmst <= idle;
224 225 rstloop: for i in 0 to FifoCnt-1 loop
225 226 sRen_APB(i) <= '1';
226 227 autoloaded(i) <= '1';
227 228 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
228 229 end loop;
229 230 elsif clk'event and clk = '1' then
230 231 sEmpty_d <= sEmpty;
231 232 case fiforeadfsmst is
232 233 when idle =>
233 234 idlelp: for i in 0 to FifoCnt-1 loop
234 235 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
235 236 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
236 237 autoloaded(i) <= '0';
237 238 else
238 239 autoloaded(i) <= '1';
239 240 end if;
240 241 sRen_APB(i) <= '0';
241 242 fiforeadfsmst <= read;
242 243 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
243 244 else
244 245 sRen_APB(i) <= '1';
245 246 end if;
246 247 end loop;
247 248 when read =>
248 249 sRen_APB <= (others => '1');
249 250 fiforeadfsmst <= idle;
250 251 when others =>
251 252 fiforeadfsmst <= idle;
252 253 end case;
253 254 end if;
254 255 end process;
255 256
256 257
257 258 end ar_APB_FIFO;
258 259
259 260
260 261
261 262
262 263
263 264
264 265
265 266
266 267
267 268
268 269
269 270
270 271
271 272
272 273
273 274
274 275
275 276
276 277
277 278
278 279
279 280
280 281
281 282
282 283
283 284
284 285
285 286
Show file before | Show file after | Hide comments
@@ -1,163 +1,164
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library lpp;
26 26 use lpp.lpp_memory.all;
27 27 library techmap;
28 28 use techmap.gencomp.all;
29 29
30 30 entity lpp_fifo is
31 31 generic(
32 tech : integer := 0;
33 DataSz : integer range 1 to 32 := 8;
34 abits : integer range 2 to 12 := 8
32 tech : integer := 0;
33 Enable_ReUse : std_logic := '0';
34 DataSz : integer range 1 to 32 := 8;
35 abits : integer range 2 to 12 := 8
35 36 );
36 37 port(
37 38 rstn : in std_logic;
38 39 ReUse : in std_logic; --27/01/12
39 40 rclk : in std_logic;
40 41 ren : in std_logic;
41 42 rdata : out std_logic_vector(DataSz-1 downto 0);
42 43 empty : out std_logic;
43 44 raddr : out std_logic_vector(abits-1 downto 0);
44 45 wclk : in std_logic;
45 46 wen : in std_logic;
46 47 wdata : in std_logic_vector(DataSz-1 downto 0);
47 48 full : out std_logic;
48 49 waddr : out std_logic_vector(abits-1 downto 0)
49 50 );
50 51 end entity;
51 52
52 53
53 54 architecture ar_lpp_fifo of lpp_fifo is
54 55
55 56 signal sFull : std_logic:='0';
56 57 signal sEmpty : std_logic:='1';
57 58 signal sREN : std_logic:='0';
58 59 signal sWEN : std_logic:='0';
59 60
60 61 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
61 62 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
62 63 signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
63 64 signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
64 65
65 66 begin
66 67
67 68 SRAM : syncram_2p
68 69 generic map(tech,abits,DataSz)
69 70 port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
70 71
71 72 --RAM0: entity work.RAM_CEL
72 73 -- generic map(abits, DataSz)
73 74 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
74 75
75 76
76 77 --=============================
77 78 -- Read section
78 79 --=============================
79 80 sREN <= not REN and not sempty;
80 81
81 82 process (rclk,rstn)
82 83 begin
83 84 if(rstn='0')then
84 85 Raddr_vect <= (others =>'0');
85 86 Raddr_vect_d <= (others =>'1');
86 87 sempty <= '1';
87 88 elsif(rclk'event and rclk='1')then
88 if(ReUse = '1')then --27/01/12
89 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
89 90 sempty <= '0'; --27/01/12
90 91 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
91 92 sempty <= '1';
92 93 elsif(Raddr_vect/=Waddr_vect) then
93 94 sempty <= '0';
94 95 end if;
95 96 if(sREN='1' and sempty = '0') then
96 97 Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
97 98 Raddr_vect_d <= Raddr_vect;
98 99 end if;
99 100
100 101 end if;
101 102 end process;
102 103
103 104 --=============================
104 105 -- Write section
105 106 --=============================
106 107 sWEN <= not WEN and not sfull;
107 108
108 109 process (wclk,rstn)
109 110 begin
110 111 if(rstn='0')then
111 112 Waddr_vect <= (others =>'0');
112 113 Waddr_vect_d <= (others =>'1');
113 114 sfull <= '0';
114 115 elsif(wclk'event and wclk='1')then
115 if(ReUse = '1')then --27/01/12
116 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
116 117 sfull <= '1'; --27/01/12
117 118 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
118 119 sfull <= '1';
119 120 elsif(Raddr_vect/=Waddr_vect) then
120 121 sfull <= '0';
121 122 end if;
122 123 if(sWEN='1' and sfull='0') then
123 124 Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
124 125 Waddr_vect_d <= Waddr_vect;
125 126 end if;
126 127
127 128
128 129 end if;
129 130 end process;
130 131
131 132
132 133 full <= sFull;
133 134 empty <= sEmpty;
134 135 waddr <= Waddr_vect;
135 136 raddr <= Raddr_vect;
136 137
137 138 end architecture;
138 139
139 140
140 141
141 142
142 143
143 144
144 145
145 146
146 147
147 148
148 149
149 150
150 151
151 152
152 153
153 154
154 155
155 156
156 157
157 158
158 159
159 160
160 161
161 162
162 163
163 164
Show file before | Show file after | Hide comments
@@ -1,119 +1,121
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 library gaisler;
30 30 use gaisler.misc.all;
31 31 use gaisler.memctrl.all;
32 32 library techmap;
33 33 use techmap.gencomp.all;
34 34
35 35 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36 36
37 37 package lpp_memory is
38 38
39 39 component APB_FIFO is
40 40 generic (
41 41 tech : integer := apa3;
42 42 pindex : integer := 0;
43 43 paddr : integer := 0;
44 44 pmask : integer := 16#fff#;
45 45 pirq : integer := 0;
46 46 abits : integer := 8;
47 47 FifoCnt : integer := 2;
48 48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
50 51 R : integer := 1;
51 52 W : integer := 1
52 53 );
53 54 port (
54 55 clk : in std_logic; --! Horloge du composant
55 56 rst : in std_logic; --! Reset general du composant
56 57 rclk : in std_logic;
57 58 wclk : in std_logic;
58 59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
59 60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
60 61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
61 62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
62 63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
63 64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
64 65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
65 66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
66 67 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
67 68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
68 69 );
69 70 end component;
70 71
71 72
72 73 component lpp_fifo is
73 74 generic(
74 tech : integer := 0;
75 DataSz : integer range 1 to 32 := 8;
76 abits : integer range 2 to 12 := 8
75 tech : integer := 0;
76 Enable_ReUse : std_logic := '0';
77 DataSz : integer range 1 to 32 := 8;
78 abits : integer range 2 to 12 := 8
77 79 );
78 80 port(
79 81 rstn : in std_logic;
80 82 ReUse : in std_logic; --27/01/12
81 83 rclk : in std_logic;
82 84 ren : in std_logic;
83 85 rdata : out std_logic_vector(DataSz-1 downto 0);
84 86 empty : out std_logic;
85 87 raddr : out std_logic_vector(abits-1 downto 0);
86 88 wclk : in std_logic;
87 89 wen : in std_logic;
88 90 wdata : in std_logic_vector(DataSz-1 downto 0);
89 91 full : out std_logic;
90 92 waddr : out std_logic_vector(abits-1 downto 0)
91 93 );
92 94 end component;
93 95
94 96 component ssram_plugin is
95 97 generic (tech : integer := 0);
96 98 port
97 99 (
98 100 clk : in std_logic;
99 101 mem_ctrlr_o : in memory_out_type;
100 102 SSRAM_CLK : out std_logic;
101 103 nBWa : out std_logic;
102 104 nBWb : out std_logic;
103 105 nBWc : out std_logic;
104 106 nBWd : out std_logic;
105 107 nBWE : out std_logic;
106 108 nADSC : out std_logic;
107 109 nADSP : out std_logic;
108 110 nADV : out std_logic;
109 111 nGW : out std_logic;
110 112 nCE1 : out std_logic;
111 113 CE2 : out std_logic;
112 114 nCE3 : out std_logic;
113 115 nOE : out std_logic;
114 116 MODE : out std_logic;
115 117 ZZ : out std_logic
116 118 );
117 119 end component;
118 120
119 121 end;
General Comments 0
You need to be logged in to leave comments. Login now