@@ -0,0 +1,128 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | library IEEE; | |
|
23 | use IEEE.numeric_std.all; | |
|
24 | use IEEE.std_logic_1164.all; | |
|
25 | ||
|
26 | entity Starter is | |
|
27 | port( | |
|
28 | clk : in std_logic; | |
|
29 | raz : in std_logic; | |
|
30 | Full : in std_logic_vector(1 downto 0); | |
|
31 | Empty : in std_logic_vector(1 downto 0); | |
|
32 | Statu : in std_logic_vector(3 downto 0); | |
|
33 | Write : in std_logic; | |
|
34 | Start : out std_logic | |
|
35 | ); | |
|
36 | end Starter; | |
|
37 | ||
|
38 | ||
|
39 | architecture ar_Starter of Starter is | |
|
40 | ||
|
41 | type etat is (eX,e0,e1,e2); | |
|
42 | signal ect : etat; | |
|
43 | ||
|
44 | signal Write_reg : std_logic; | |
|
45 | signal Conjugate : std_logic; | |
|
46 | ||
|
47 | begin | |
|
48 | process(clk,raz) | |
|
49 | begin | |
|
50 | ||
|
51 | if(raz='0')then | |
|
52 | Start <= '0'; | |
|
53 | Write_reg <= '0'; | |
|
54 | ect <= eX; | |
|
55 | ||
|
56 | elsif(clk'event and clk='1')then | |
|
57 | Write_reg <= Write; | |
|
58 | ||
|
59 | case ect is | |
|
60 | when eX => | |
|
61 | if(Conjugate='0')then | |
|
62 | if(full="11")then | |
|
63 | Start <= '1'; | |
|
64 | ect <= e0; | |
|
65 | end if; | |
|
66 | else | |
|
67 | if(full(0)='1')then | |
|
68 | Start <= '1'; | |
|
69 | ect <= e0; | |
|
70 | end if; | |
|
71 | end if; | |
|
72 | ||
|
73 | when e0 => | |
|
74 | if(Conjugate='0')then | |
|
75 | if(empty="11")then | |
|
76 | ect <= e1; | |
|
77 | end if; | |
|
78 | else | |
|
79 | if(empty(0)='1')then | |
|
80 | ect <= e2; | |
|
81 | end if; | |
|
82 | end if; | |
|
83 | ||
|
84 | when e1 => | |
|
85 | if(Write_reg='1' and Write='0')then | |
|
86 | ect <= e2; | |
|
87 | end if; | |
|
88 | ||
|
89 | when e2 => | |
|
90 | if(Write_reg='1' and Write='0')then | |
|
91 | Start <= '0'; | |
|
92 | ect <= eX; | |
|
93 | end if; | |
|
94 | ||
|
95 | end case; | |
|
96 | ||
|
97 | end if; | |
|
98 | end process; | |
|
99 | ||
|
100 | ||
|
101 | With Statu select | |
|
102 | Conjugate <= '1' when "0001", | |
|
103 | '1' when "0011", | |
|
104 | '1' when "0110", | |
|
105 | '1' when "1010", | |
|
106 | '1' when "1111", | |
|
107 | '0' when others; | |
|
108 | ||
|
109 | end ar_Starter; | |
|
110 | ||
|
111 | ||
|
112 | ||
|
113 | ||
|
114 | ||
|
115 | ||
|
116 | ||
|
117 | ||
|
118 | ||
|
119 | ||
|
120 | ||
|
121 | ||
|
122 | ||
|
123 | ||
|
124 | ||
|
125 | ||
|
126 | ||
|
127 | ||
|
128 |
@@ -0,0 +1,62 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | library IEEE; | |
|
23 | use IEEE.numeric_std.all; | |
|
24 | use IEEE.std_logic_1164.all; | |
|
25 | use lpp.lpp_matrix.all; | |
|
26 | ||
|
27 | entity Top_MatrixSpec is | |
|
28 | generic( | |
|
29 | Input_SZ : integer := 16; | |
|
30 | Result_SZ : integer := 32); | |
|
31 | port( | |
|
32 | clk : in std_logic; | |
|
33 | reset : in std_logic; | |
|
34 | Statu : in std_logic_vector(3 downto 0); | |
|
35 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
|
36 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
|
37 | Full : in std_logic_vector(1 downto 0); | |
|
38 | Empty : in std_logic_vector(1 downto 0); | |
|
39 | ReadFIFO : out std_logic_vector(1 downto 0); | |
|
40 | FullFIFO : in std_logic; | |
|
41 | WriteFIFO : out std_logic; | |
|
42 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
|
43 | ); | |
|
44 | end entity; | |
|
45 | ||
|
46 | ||
|
47 | architecture ar_Top_MatrixSpec of Top_MatrixSpec is | |
|
48 | ||
|
49 | signal Start : std_logic; | |
|
50 | signal Write : std_logic; | |
|
51 | ||
|
52 | begin | |
|
53 | WriteFIFO <= Write; | |
|
54 | ||
|
55 | ST0 : Starter | |
|
56 | port map(clk,reset,Full,Empty,Statu,Write,Start); | |
|
57 | ||
|
58 | Mspec : SpectralMatrix | |
|
59 | generic map(Input_SZ,Result_SZ) | |
|
60 | port map(clk,reset,Start,FIFO1,FIFO2,Statu,FullFIFO,ReadFIFO,Write,Result); | |
|
61 | ||
|
62 | end architecture; No newline at end of file |
@@ -3,10 +3,9 | |||
|
3 | 3 | #include "apb_fifo_Driver.h" |
|
4 | 4 | #include "apb_Matrix_Driver.h" |
|
5 | 5 | #include "apb_uart_Driver.h" |
|
6 | #include "apb_delay_Driver.h" | |
|
7 | 6 | #include "apb_gpio_Driver.h" |
|
8 | 7 | |
|
9 | // Matrix With 2 FIFO Input | |
|
8 | ///////////// Matrix With 2 FIFO Input ///////////////////////////////////////////// | |
|
10 | 9 | int main() |
|
11 | 10 | { |
|
12 | 11 | int i=0,save; |
@@ -20,7 +19,6 int main() | |||
|
20 | 19 | |
|
21 | 20 | |
|
22 | 21 | FIFO_Device* fifoX = openFIFO(0); |
|
23 | DELAY_Device* delay0 = openDELAY(0); | |
|
24 | 22 | UART_Device* uart0 = openUART(0); |
|
25 | 23 | FIFO_Device* fifoIn = openFIFO(1); |
|
26 | 24 | MATRIX_Device* mspec = openMatrix(0); |
@@ -29,7 +27,6 int main() | |||
|
29 | 27 | |
|
30 | 28 | printf("\nDebut Main\n\n"); |
|
31 | 29 | |
|
32 | Setup(delay0,30000000); | |
|
33 | 30 | gpio0->oen = 0x3; |
|
34 | 31 | gpio0->Dout = 0x0; |
|
35 | 32 | |
@@ -61,7 +58,6 int main() | |||
|
61 | 58 | mspec->Statu = 1; |
|
62 | 59 | FillFifo(fifoIn,0,TblB1); |
|
63 | 60 | gpio0->Dout = 0x1; |
|
64 | Delay_us(delay0,20); | |
|
65 | 61 | while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS |
|
66 | 62 | { |
|
67 | 63 | Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata]; |
@@ -109,7 +105,7 int main() | |||
|
109 | 105 | } |
|
110 | 106 | |
|
111 | 107 | |
|
112 | // Matrix With 5 FIFO Input | |
|
108 | ///////////// Matrix With 5 FIFO Input ///////////////////////////////////////////// | |
|
113 | 109 | int main2() |
|
114 | 110 | { |
|
115 | 111 | int save1,save2; |
@@ -42,15 +42,18 entity APB_Matrix is | |||
|
42 | 42 | Input_SZ : integer := 16; |
|
43 | 43 | Result_SZ : integer := 32); |
|
44 | 44 | port ( |
|
45 |
clk : in |
|
|
46 | rst : in std_logic; --! Reset general du composant | |
|
45 | clk : in std_logic; | |
|
46 | rst : in std_logic; | |
|
47 | 47 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
48 | 48 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
49 | Full : in std_logic_vector(1 downto 0); | |
|
50 | Empty : in std_logic_vector(1 downto 0); | |
|
49 | 51 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
52 | FullFIFO : in std_logic; | |
|
50 | 53 | WriteFIFO : out std_logic; |
|
51 | 54 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
|
52 |
apbi |
|
|
53 |
apbo |
|
|
55 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
|
56 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
|
54 | 57 | ); |
|
55 | 58 | end APB_Matrix; |
|
56 | 59 | |
@@ -64,27 +67,23 constant pconfig : apb_config_type := ( | |||
|
64 | 67 | 1 => apb_iobar(paddr, pmask)); |
|
65 | 68 | |
|
66 | 69 | type MATRIX_ctrlr_Reg is record |
|
67 |
MATRIX_ |
|
|
70 | MATRIX_Statu : std_logic_vector(3 downto 0); | |
|
68 | 71 | end record; |
|
69 | 72 | |
|
70 | 73 | signal Rec : MATRIX_ctrlr_Reg; |
|
71 | 74 | signal Rdata : std_logic_vector(31 downto 0); |
|
72 | signal Start : std_logic; | |
|
73 | signal statu : std_logic_vector(3 downto 0); | |
|
74 | 75 | |
|
75 | 76 | begin |
|
76 | 77 | |
|
77 |
Mspec0 : |
|
|
78 | Mspec0 : Top_MatrixSpec | |
|
78 | 79 | generic map (Input_SZ,Result_SZ) |
|
79 |
port map(clk,rst,Sta |
|
|
80 | port map(clk,rst,Rec.MATRIX_Statu,FIFO1,FIFO2,Full,Empty,ReadFIFO,FullFIFO,WriteFIFO,Result); | |
|
80 | 81 | |
|
81 | Statu <= Rec.MATRIX_Ctrl(3 downto 0); | |
|
82 | Start <= Rec.MATRIX_Ctrl(4); | |
|
83 | 82 | |
|
84 | 83 | process(rst,clk) |
|
85 | 84 | begin |
|
86 | 85 | if(rst='0')then |
|
87 |
Rec.MATRIX_ |
|
|
86 | Rec.MATRIX_Statu <= (others => '0'); | |
|
88 | 87 | |
|
89 | 88 | elsif(clk'event and clk='1')then |
|
90 | 89 | |
@@ -92,7 +91,7 Start <= Rec.MATRIX_Ctrl(4); | |||
|
92 | 91 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
93 | 92 | case apbi.paddr(abits-1 downto 2) is |
|
94 | 93 | when "000000" => |
|
95 |
Rec.MATRIX_ |
|
|
94 | Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0); | |
|
96 | 95 |
|
|
97 | 96 | null; |
|
98 | 97 | end case; |
@@ -102,8 +101,8 Start <= Rec.MATRIX_Ctrl(4); | |||
|
102 | 101 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
103 | 102 | case apbi.paddr(abits-1 downto 2) is |
|
104 | 103 | when "000000" => |
|
105 |
Rdata(31 downto |
|
|
106 |
Rdata( |
|
|
104 | Rdata(31 downto 4) <= (others => '0'); | |
|
105 | Rdata(3 downto 0) <= Rec.MATRIX_Statu; | |
|
107 | 106 | when others => |
|
108 | 107 | Rdata <= (others => '0'); |
|
109 | 108 | end case; |
@@ -41,18 +41,39 component APB_Matrix is | |||
|
41 | 41 | Input_SZ : integer := 16; |
|
42 | 42 | Result_SZ : integer := 32); |
|
43 | 43 | port ( |
|
44 |
clk : in |
|
|
45 | rst : in std_logic; --! Reset general du composant | |
|
44 | clk : in std_logic; | |
|
45 | rst : in std_logic; | |
|
46 | 46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
47 | 47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
48 | Full : in std_logic_vector(1 downto 0); | |
|
49 | Empty : in std_logic_vector(1 downto 0); | |
|
48 | 50 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
51 | FullFIFO : in std_logic; | |
|
49 | 52 | WriteFIFO : out std_logic; |
|
50 | 53 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
|
51 |
apbi |
|
|
52 |
apbo |
|
|
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
|
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
|
53 | 56 | ); |
|
54 | 57 | end component; |
|
55 | 58 | |
|
59 | component Top_MatrixSpec is | |
|
60 | generic( | |
|
61 | Input_SZ : integer := 16; | |
|
62 | Result_SZ : integer := 32); | |
|
63 | port( | |
|
64 | clk : in std_logic; | |
|
65 | reset : in std_logic; | |
|
66 | Statu : in std_logic_vector(3 downto 0); | |
|
67 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
|
68 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
|
69 | Full : in std_logic_vector(1 downto 0); | |
|
70 | Empty : in std_logic_vector(1 downto 0); | |
|
71 | ReadFIFO : out std_logic_vector(1 downto 0); | |
|
72 | FullFIFO : in std_logic; | |
|
73 | WriteFIFO : out std_logic; | |
|
74 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
|
75 | ); | |
|
76 | end component; | |
|
56 | 77 | |
|
57 | 78 | component SpectralMatrix is |
|
58 | 79 | generic( |
@@ -138,6 +159,17 port( | |||
|
138 | 159 | ); |
|
139 | 160 | end component; |
|
140 | 161 | |
|
162 | component Starter is | |
|
163 | port( | |
|
164 | clk : in std_logic; | |
|
165 | raz : in std_logic; | |
|
166 | Full : in std_logic_vector(1 downto 0); | |
|
167 | Empty : in std_logic_vector(1 downto 0); | |
|
168 | Statu : in std_logic_vector(3 downto 0); | |
|
169 | Write : in std_logic; | |
|
170 | Start : out std_logic | |
|
171 | ); | |
|
172 | end component; | |
|
141 | 173 | |
|
142 | 174 | component ALU_Driver is |
|
143 | 175 | generic( |
@@ -37,29 +37,30 use lpp.lpp_memory.all; | |||
|
37 | 37 | |
|
38 | 38 | entity APB_FIFO is |
|
39 | 39 | generic ( |
|
40 | tech : integer := apa3; | |
|
41 | pindex : integer := 0; | |
|
42 | paddr : integer := 0; | |
|
43 | pmask : integer := 16#fff#; | |
|
44 | pirq : integer := 0; | |
|
45 | abits : integer := 8; | |
|
46 | FifoCnt : integer := 2; | |
|
47 | Data_sz : integer := 16; | |
|
48 | Addr_sz : integer := 9; | |
|
49 | R : integer := 1; | |
|
50 |
|
|
|
40 | tech : integer := apa3; | |
|
41 | pindex : integer := 0; | |
|
42 | paddr : integer := 0; | |
|
43 | pmask : integer := 16#fff#; | |
|
44 | pirq : integer := 0; | |
|
45 | abits : integer := 8; | |
|
46 | FifoCnt : integer := 2; | |
|
47 | Data_sz : integer := 16; | |
|
48 | Addr_sz : integer := 9; | |
|
49 | Enable_ReUse : std_logic := '0'; | |
|
50 | R : integer := 1; | |
|
51 | W : integer := 1 | |
|
51 | 52 | ); |
|
52 | 53 | port ( |
|
53 | 54 | clk : in std_logic; --! Horloge du composant |
|
54 | 55 | rst : in std_logic; --! Reset general du composant |
|
55 | 56 | rclk : in std_logic; |
|
56 | 57 | wclk : in std_logic; |
|
57 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |
|
58 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |
|
58 | REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire | |
|
59 | WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire | |
|
59 | 60 | Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide |
|
60 | 61 | Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine |
|
61 | 62 | RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e |
|
62 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |
|
63 | WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie | |
|
63 | 64 | WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture) |
|
64 | 65 | RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) |
|
65 | 66 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
@@ -168,7 +169,7 Full <= sFull; | |||
|
168 | 169 | |
|
169 | 170 | fifos: for i in 0 to FifoCnt-1 generate |
|
170 | 171 | FIFO0 : lpp_fifo |
|
171 | generic map (tech,Data_sz,Addr_sz) | |
|
172 | generic map (tech,Enable_ReUse,Data_sz,Addr_sz) | |
|
172 | 173 | port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i)); |
|
173 | 174 | end generate; |
|
174 | 175 |
@@ -29,9 +29,10 use techmap.gencomp.all; | |||
|
29 | 29 | |
|
30 | 30 | entity lpp_fifo is |
|
31 | 31 | generic( |
|
32 | tech : integer := 0; | |
|
33 | DataSz : integer range 1 to 32 := 8; | |
|
34 |
|
|
|
32 | tech : integer := 0; | |
|
33 | Enable_ReUse : std_logic := '0'; | |
|
34 | DataSz : integer range 1 to 32 := 8; | |
|
35 | abits : integer range 2 to 12 := 8 | |
|
35 | 36 | ); |
|
36 | 37 | port( |
|
37 | 38 | rstn : in std_logic; |
@@ -85,7 +86,7 begin | |||
|
85 | 86 | Raddr_vect_d <= (others =>'1'); |
|
86 | 87 | sempty <= '1'; |
|
87 | 88 | elsif(rclk'event and rclk='1')then |
|
88 | if(ReUse = '1')then --27/01/12 | |
|
89 | if(ReUse = '1' and Enable_ReUse='1')then --27/01/12 | |
|
89 | 90 | sempty <= '0'; --27/01/12 |
|
90 | 91 | elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then |
|
91 | 92 | sempty <= '1'; |
@@ -112,7 +113,7 begin | |||
|
112 | 113 | Waddr_vect_d <= (others =>'1'); |
|
113 | 114 | sfull <= '0'; |
|
114 | 115 | elsif(wclk'event and wclk='1')then |
|
115 | if(ReUse = '1')then --27/01/12 | |
|
116 | if(ReUse = '1' and Enable_ReUse='1')then --27/01/12 | |
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116 | 117 | sfull <= '1'; --27/01/12 |
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117 | 118 | elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then |
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118 | 119 | sfull <= '1'; |
@@ -46,7 +46,8 generic ( | |||
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46 | 46 | abits : integer := 8; |
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47 | 47 | FifoCnt : integer := 2; |
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48 | 48 | Data_sz : integer := 16; |
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49 | Addr_sz : integer := 9; | |
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49 | Addr_sz : integer := 9; | |
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50 | Enable_ReUse : std_logic := '0'; | |
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50 | 51 | R : integer := 1; |
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51 | 52 | W : integer := 1 |
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52 | 53 | ); |
@@ -71,9 +72,10 end component; | |||
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71 | 72 | |
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72 | 73 | component lpp_fifo is |
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73 | 74 | generic( |
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74 | tech : integer := 0; | |
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75 | DataSz : integer range 1 to 32 := 8; | |
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76 |
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75 | tech : integer := 0; | |
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76 | Enable_ReUse : std_logic := '0'; | |
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77 | DataSz : integer range 1 to 32 := 8; | |
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78 | abits : integer range 2 to 12 := 8 | |
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77 | 79 | ); |
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78 | 80 | port( |
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79 | 81 | rstn : in std_logic; |
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