HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r95:236e70a254cc

Update Matrix Spectral function with 2 fifo inputs (APB and C-driver)

martin -

r95:236e70a254cc martin

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r95:236e70a254cc

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lib/lpp/lpp_matrix/Starter.vhd created 644 +128 0

@@ -0,0 +1,128
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22	library IEEE;
	23	use IEEE.numeric_std.all;
	24	use IEEE.std_logic_1164.all;
	25
	26	entity Starter is
	27	port(
	28	clk : in std_logic;
	29	raz : in std_logic;
	30	Full : in std_logic_vector(1 downto 0);
	31	Empty : in std_logic_vector(1 downto 0);
	32	Statu : in std_logic_vector(3 downto 0);
	33	Write : in std_logic;
	34	Start : out std_logic
	35	);
	36	end Starter;
	37
	38
	39	architecture ar_Starter of Starter is
	40
	41	type etat is (eX,e0,e1,e2);
	42	signal ect : etat;
	43
	44	signal Write_reg : std_logic;
	45	signal Conjugate : std_logic;
	46
	47	begin
	48	process(clk,raz)
	49	begin
	50
	51	if(raz='0')then
	52	Start <= '0';
	53	Write_reg <= '0';
	54	ect <= eX;
	55
	56	elsif(clk'event and clk='1')then
	57	Write_reg <= Write;
	58
	59	case ect is
	60	when eX =>
	61	if(Conjugate='0')then
	62	if(full="11")then
	63	Start <= '1';
	64	ect <= e0;
	65	end if;
	66	else
	67	if(full(0)='1')then
	68	Start <= '1';
	69	ect <= e0;
	70	end if;
	71	end if;
	72
	73	when e0 =>
	74	if(Conjugate='0')then
	75	if(empty="11")then
	76	ect <= e1;
	77	end if;
	78	else
	79	if(empty(0)='1')then
	80	ect <= e2;
	81	end if;
	82	end if;
	83
	84	when e1 =>
	85	if(Write_reg='1' and Write='0')then
	86	ect <= e2;
	87	end if;
	88
	89	when e2 =>
	90	if(Write_reg='1' and Write='0')then
	91	Start <= '0';
	92	ect <= eX;
	93	end if;
	94
	95	end case;
	96
	97	end if;
	98	end process;
	99
	100
	101	With Statu select
	102	Conjugate <= '1' when "0001",
	103	'1' when "0011",
	104	'1' when "0110",
	105	'1' when "1010",
	106	'1' when "1111",
	107	'0' when others;
	108
	109	end ar_Starter;
	110
	111
	112
	113
	114
	115
	116
	117
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lib/lpp/lpp_matrix/Top_MatrixSpec.vhd created 644 +62 0

@@ -0,0 +1,62
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22	library IEEE;
	23	use IEEE.numeric_std.all;
	24	use IEEE.std_logic_1164.all;
	25	use lpp.lpp_matrix.all;
	26
	27	entity Top_MatrixSpec is
	28	generic(
	29	Input_SZ : integer := 16;
	30	Result_SZ : integer := 32);
	31	port(
	32	clk : in std_logic;
	33	reset : in std_logic;
	34	Statu : in std_logic_vector(3 downto 0);
	35	FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
	36	FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
	37	Full : in std_logic_vector(1 downto 0);
	38	Empty : in std_logic_vector(1 downto 0);
	39	ReadFIFO : out std_logic_vector(1 downto 0);
	40	FullFIFO : in std_logic;
	41	WriteFIFO : out std_logic;
	42	Result : out std_logic_vector(Result_SZ-1 downto 0)
	43	);
	44	end entity;
	45
	46
	47	architecture ar_Top_MatrixSpec of Top_MatrixSpec is
	48
	49	signal Start : std_logic;
	50	signal Write : std_logic;
	51
	52	begin
	53	WriteFIFO <= Write;
	54
	55	ST0 : Starter
	56	port map(clk,reset,Full,Empty,Statu,Write,Start);
	57
	58	Mspec : SpectralMatrix
	59	generic map(Input_SZ,Result_SZ)
	60	port map(clk,reset,Start,FIFO1,FIFO2,Statu,FullFIFO,ReadFIFO,Write,Result);
	61
	62	end architecture; No newline at end of file

LPP_drivers/exemples/BenchMatrix/main.c +2 -6

             #include <stdio.h>
             #include "lpp_apb_functions.h"
             #include "apb_fifo_Driver.h"
             #include "apb_Matrix_Driver.h"
             #include "apb_uart_Driver.h"
-            #include "apb_delay_Driver.h"
             #include "apb_gpio_Driver.h"
-            // Matrix With 2 FIFO Input
+            ///////////// Matrix With 2 FIFO Input /////////////////////////////////////////////
             int main()
             {
                 int i=0,save;
                 char temp[256];
                 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
                 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
                 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
              //   int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
              //   int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
                 int Table[256];
                 FIFO_Device* fifoX = openFIFO(0);
-                DELAY_Device* delay0 = openDELAY(0);
                 UART_Device* uart0 = openUART(0);
                 FIFO_Device* fifoIn = openFIFO(1);
                 MATRIX_Device* mspec = openMatrix(0);
                 FIFO_Device* fifoOut = openFIFO(2);
                 GPIO_Device* gpio0 = openGPIO(0);
                 printf("\nDebut Main\n\n");
-                Setup(delay0,30000000);
                 gpio0->oen = 0x3;
                 gpio0->Dout = 0x0;
             ///////////////////////////////////////////////////////////////////////////
                 mspec->Statu = 2;
                 FillFifo(fifoIn,0,TblB1);
                 FillFifo(fifoIn,1,TblB2);
                 gpio0->Dout = 0x1;
                 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE  empty a 0  ALORS
                 {
                     Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
                     i++;
                 }
                 save = i;
                 gpio0->Dout = 0x2;
                 sprintf(temp,"\nReels\tImaginaires\n\r");
                 uartputs(uart0,temp);
                 for (i = 0 ; i < save ; i+=2)
                 {
                     sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
                     uartputs(uart0,temp);
                 }
                 i = 0;
                 gpio0->Dout = 0x0;
             ///////////////////////////////////////////////////////////////////////////
                 mspec->Statu = 1;
                 FillFifo(fifoIn,0,TblB1);
                 gpio0->Dout = 0x1;
-                Delay_us(delay0,20);
                 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE  empty a 0  ALORS
                 {
                     Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
                     i++;
                 }
                 save = i;
                 gpio0->Dout = 0x2;
                 sprintf(temp,"\nReels\n\r");
                 uartputs(uart0,temp);
                 for (i = 0 ; i < save ; i++)
                 {
                     sprintf(temp,"%d\n\r",Table[i]);
                     uartputs(uart0,temp);
                 }
                 i = 0;
                 gpio0->Dout = 0x0;
             ///////////////////////////////////////////////////////////////////////////
                 mspec->Statu = 4;
                 FillFifo(fifoIn,0,TblB1);
                 FillFifo(fifoIn,1,TblB3);
                 gpio0->Dout = 0x1;
                 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE  empty a 0  ALORS
                 {
                     Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
                     i++;
                 }
                 save = i;
                 gpio0->Dout = 0x2;
                 sprintf(temp,"\nReels\tImaginaires\n\r");
                 uartputs(uart0,temp);
                 for (i = 0 ; i < save ; i+=2)
                 {
                     sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
                     uartputs(uart0,temp);
                 }
                 i = 0;
                 gpio0->Dout = 0x0;
                 printf("\nFin Main\n\n");
                 return 0;
             }
-            // Matrix With 5 FIFO Input
+            ///////////// Matrix With 5 FIFO Input /////////////////////////////////////////////
             int main2()
             {
                 int save1,save2;
                 char temp[256];
                 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
                 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
                 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
                 int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
                 int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
                 FIFO_Device* fifoX      = openFIFO(0);
                 UART_Device* uart0      = openUART(0);
                 FIFO_Device* fifoIn     = openFIFO(1);
                 FIFO_Device* fifoOut    = openFIFO(2);
                 printf("\nDebut Main\n\n");
                 FillFifo(fifoIn,0,TblB1);
                 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
                 FillFifo(fifoIn,1,TblB2);
                 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
                 FillFifo(fifoIn,2,TblB3);
                 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
                 FillFifo(fifoIn,3,TblE1);
                 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
                 FillFifo(fifoIn,4,TblE2);
                 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
             while(1){
                 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE  empty a 1  RIEN
                     save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
                     save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
                     sprintf(temp,"%d\t%d\n\r",save1,save2);
                     uartputs(uart0,temp);
             }
                 printf("\nFin Main\n\n");
                 return 0;
             }
             /////////////////// Test R/W Fifo OKAI ///////////////////////////////////
                 /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11;
                 Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata];
                 printf("data: %x\n",Table[1]);
                 FillFifo(fifoX,0,TblX);
                 for (i = 1 ; i < 8 ; i++)
                 {
                     Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex;
                 }
                 printf("data: %x\n",Table[1]);
                 printf("data: %x\n",Table[2]);
                 printf("data: %x\n",Table[3]);
                 printf("data: %x\n",Table[4]);*/

lib/lpp/lpp_matrix/APB_Matrix.vhd +14 -15

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.lpp_matrix.all;
             --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
             entity APB_Matrix is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Input_SZ : integer := 16;
                 Result_SZ : integer := 32);
               port (
-                clk       : in  std_logic;           --! Horloge du composant
+                clk       : in std_logic;
-                rst       : in  std_logic;           --! Reset general du composant
+                rst     : in std_logic;
                 FIFO1     : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2     : in std_logic_vector(Input_SZ-1 downto 0);
+                Full      : in std_logic_vector(1 downto 0);
+                Empty     : in std_logic_vector(1 downto 0);
                 ReadFIFO  : out std_logic_vector(1 downto 0);
+                FullFIFO  : in std_logic;
                 WriteFIFO : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0);
-                apbi      : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
+                apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-                apbo      : out apb_slv_out_type     --! Registre de gestion des sorties du bus
+                apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
             );
             end APB_Matrix;
             architecture ar_APB_Matrix of APB_Matrix is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type MATRIX_ctrlr_Reg is record
-                 MATRIX_Ctrl : std_logic_vector(4 downto 0);
+                 MATRIX_Statu : std_logic_vector(3 downto 0);
             end record;
             signal Rec : MATRIX_ctrlr_Reg;
             signal Rdata : std_logic_vector(31 downto 0);
-            signal Start : std_logic;
-            signal statu : std_logic_vector(3 downto 0);
             begin
-            Mspec0 : SpectralMatrix
+            Mspec0 : Top_MatrixSpec
                 generic map (Input_SZ,Result_SZ)
-                port map(clk,rst,Start,FIFO1,FIFO2,Statu,ReadFIFO,WriteFIFO,Result);
+                port map(clk,rst,Rec.MATRIX_Statu,FIFO1,FIFO2,Full,Empty,ReadFIFO,FullFIFO,WriteFIFO,Result);
-            Statu <= Rec.MATRIX_Ctrl(3 downto 0);
-            Start <= Rec.MATRIX_Ctrl(4);
                 process(rst,clk)
                 begin
                     if(rst='0')then
-                        Rec.MATRIX_Ctrl <= (others => '0');
+                        Rec.MATRIX_Statu <= (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                     Rec.MATRIX_Ctrl <= apbi.pwdata(4 downto 0);
+                                     Rec.MATRIX_Statu <= apbi.pwdata(3 downto 0);
                                 when others =>
                                     null;
                             end case;
                         end if;
                 --APB Read OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                     Rdata(31 downto 5) <= (others => '0');
+                                     Rdata(31 downto 4) <= (others => '0');
-                                     Rdata(4 downto 0) <= Rec.MATRIX_Ctrl;
+                                     Rdata(3 downto 0) <= Rec.MATRIX_Statu;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
             end ar_APB_MATRIX;

lib/lpp/lpp_matrix/lpp_matrix.vhd +36 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_matrix is
             component APB_Matrix is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Input_SZ : integer := 16;
                 Result_SZ : integer := 32);
               port (
-                clk       : in  std_logic;           --! Horloge du composant
+                clk       : in std_logic;
-                rst       : in  std_logic;           --! Reset general du composant
+                rst     : in std_logic;
                 FIFO1     : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2     : in std_logic_vector(Input_SZ-1 downto 0);
+                Full      : in std_logic_vector(1 downto 0);
+                Empty     : in std_logic_vector(1 downto 0);
                 ReadFIFO  : out std_logic_vector(1 downto 0);
+                FullFIFO  : in std_logic;
                 WriteFIFO : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0);
-                apbi      : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
+                apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
-                apbo      : out apb_slv_out_type     --! Registre de gestion des sorties du bus
+                apbo    : out apb_slv_out_type     --! Registre de gestion des sorties du bus
             );
             end component;
+            component Top_MatrixSpec is
+            generic(
+                Input_SZ  : integer := 16;
+                Result_SZ : integer := 32);
+            port(
+                clk       : in std_logic;
+                reset     : in std_logic;
+                Statu     : in std_logic_vector(3 downto 0);
+                FIFO1     : in std_logic_vector(Input_SZ-1 downto 0);
+                FIFO2     : in std_logic_vector(Input_SZ-1 downto 0);
+                Full      : in std_logic_vector(1 downto 0);
+                Empty     : in std_logic_vector(1 downto 0);
+                ReadFIFO  : out std_logic_vector(1 downto 0);
+                FullFIFO  : in std_logic;
+                WriteFIFO : out std_logic;
+                Result    : out std_logic_vector(Result_SZ-1 downto 0)
+            );
+            end component;
             component SpectralMatrix is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk        : in std_logic;
                 reset      : in std_logic;
                 Start      : in std_logic;
                 FIFO1      : in std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2      : in std_logic_vector(Input_SZ-1 downto 0);
                 Statu      : in std_logic_vector(3 downto 0);
                 FullFIFO   : in std_logic;
                 ReadFIFO   : out std_logic_vector(1 downto 0);
                 WriteFIFO  : out std_logic;
                 Result     : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component Matrix is
               generic(
                   Input_SZ : integer := 16);
               port(
                   clk        : in std_logic;
                   raz        : in std_logic;
                   IN1        : in std_logic_vector(Input_SZ-1 downto 0);
                   IN2        : in std_logic_vector(Input_SZ-1 downto 0);
                   Take       : in std_logic;
                   Received   : in std_logic;
                   Conjugate  : in std_logic;
                   Valid      : out std_logic;
                   Read       : out std_logic;
                   Result     : out std_logic_vector(2*Input_SZ-1 downto 0)
             );
             end component;
             component GetResult is
             generic(
                 Result_SZ : integer := 32);
             port(
                 clk       : in  std_logic;
                 raz       : in  std_logic;
                 Valid     : in  std_logic;
                 Conjugate : in  std_logic;
                 Res       : in std_logic_vector(Result_SZ-1 downto 0);
                 Full      : in std_logic;
                 WriteFIFO : out std_logic;
                 Received  : out std_logic;
                 Result    : out std_logic_vector(Result_SZ-1 downto 0)
             );
             end component;
             component TopMatrix_PDR is
             generic(
                 Input_SZ  : integer := 16;
                 Result_SZ : integer := 32);
             port(
                 clk         : in std_logic;
                 reset       : in std_logic;
                 Data        : in std_logic_vector((5*Input_SZ)-1 downto 0);
                 FULLin      : in std_logic_vector(4 downto 0);
                 READin      : in std_logic_vector(1 downto 0);
                 WRITEin     : in std_logic;
                 FIFO1       : out std_logic_vector(Input_SZ-1 downto 0);
                 FIFO2       : out std_logic_vector(Input_SZ-1 downto 0);
                 Start       : out std_logic;
                 Read        : out std_logic_vector(4 downto 0);
                 Statu       : out std_logic_vector(3 downto 0)
             );
             end component;
             component DriveInputs is
             port(
                 clk     : in  std_logic;
                 raz     : in  std_logic;
                 Read    : in  std_logic;
                 Conjugate : in std_logic;
                 Take    : out std_logic;
                 ReadFIFO : out std_logic_vector(1 downto 0)
             );
             end component;
+            component Starter is
+            port(
+                clk     : in  std_logic;
+                raz     : in  std_logic;
+                Full    : in  std_logic_vector(1 downto 0);
+                Empty   : in  std_logic_vector(1 downto 0);
+                Statu   : in std_logic_vector(3 downto 0);
+                Write   : in std_logic;
+                Start   : out std_logic
+            );
+            end component;
             component ALU_Driver is
               generic(
                   Input_SZ_1      :   integer := 16;
                   Input_SZ_2      :   integer := 16);
               port(
                   clk       :   in std_logic;
                   reset     :   in std_logic;
                   IN1       :   in std_logic_vector(Input_SZ_1-1 downto 0);
                   IN2       :   in std_logic_vector(Input_SZ_2-1 downto 0);
                   Take      :   in std_logic;
                   Received  :   in std_logic;
                   Conjugate :   in std_logic;
                   Valid     :   out std_logic;
                   Read      :   out std_logic;
                   CTRL      :   out std_logic_vector(4 downto 0);
                   OP1       :   out std_logic_vector(Input_SZ_1-1 downto 0);
                   OP2       :   out std_logic_vector(Input_SZ_2-1 downto 0)
             );
             end component;
             component ALU_v2 is
             generic(
                 Arith_en        :   integer := 1;
                 Logic_en        :   integer := 1;
                 Input_SZ_1      :   integer := 16;
                 Input_SZ_2      :   integer := 9);
             port(
                 clk     :   in  std_logic;
                 reset   :   in  std_logic;
                 ctrl    :   in  std_logic_vector(4 downto 0);
                 OP1     :   in  std_logic_vector(Input_SZ_1-1 downto 0);
                 OP2     :   in  std_logic_vector(Input_SZ_2-1 downto 0);
                 RES     :   out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
             );
             end component;
             component MAC_v2 is
             generic(
                 Input_SZ_A     :   integer := 8;
                 Input_SZ_B     :   integer := 8);
             port(
                 clk             :   in  std_logic;
                 reset           :   in  std_logic;
                 clr_MAC         :   in  std_logic;
                 MAC_MUL_ADD_2C  :   in  std_logic_vector(3 downto 0);
                 OP1             :   in  std_logic_vector(Input_SZ_A-1 downto 0);
                 OP2             :   in  std_logic_vector(Input_SZ_B-1 downto 0);
                 RES             :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
             );
             end component;
             component TwoComplementer is
             generic(
                 Input_SZ : integer := 16);
             port(
                 clk     : in  std_logic;
                 reset   : in  std_logic;
                 clr     : in  std_logic;
                 TwoComp : in  std_logic;
                 OP      : in  std_logic_vector(Input_SZ-1 downto 0);
                 RES     : out std_logic_vector(Input_SZ-1 downto 0)
             );
             end component;
             end;

lib/lpp/lpp_memory/APB_FIFO.vhd +16 -15

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             -- APB_FIFO.vhd
             library ieee;
             use ieee.std_logic_1164.all;
             use IEEE.numeric_std.all;
             library techmap;
             use techmap.gencomp.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.lpp_memory.all;
             entity APB_FIFO is
             generic (
-                tech         : integer := apa3;
+                tech           : integer := apa3;
-                pindex       : integer := 0;
+                pindex         : integer := 0;
-                paddr        : integer := 0;
+                paddr          : integer := 0;
-                pmask        : integer := 16#fff#;
+                pmask          : integer := 16#fff#;
-                pirq         : integer := 0;
+                pirq           : integer := 0;
-                abits        : integer := 8;
+                abits          : integer := 8;
-                FifoCnt      : integer := 2;
+                FifoCnt        : integer := 2;
-                Data_sz      : integer := 16;
+                Data_sz        : integer := 16;
-                Addr_sz      : integer := 9;
+                Addr_sz        : integer := 9;
-                R            : integer := 1;
+                Enable_ReUse   : std_logic := '0';
-                W            : integer := 1
+                R              : integer := 1;
+                W              : integer := 1
                 );
               port (
                 clk          : in  std_logic;                              --! Horloge du composant
                 rst          : in  std_logic;                              --! Reset general du composant
                 rclk         : in  std_logic;
                 wclk         : in  std_logic;
-                REN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en m�moire
+                REN          : in  std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en m�moire
-                WEN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'�criture en m�moire
+                WEN          : in  std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'�criture en m�moire
                 Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, M�moire vide
                 Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, M�moire pleine
                 RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de donn�es en entr�e
-                WDATA        : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de donn�es en sortie
+                WDATA        : in  std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de donn�es en sortie
                 WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (�criture)
                 RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
                 apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entr�es du bus
                 apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
                 );
             end entity;
             architecture ar_APB_FIFO of APB_FIFO is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type FIFO_ctrlr_Reg is record
                  FIFO_Ctrl  : std_logic_vector(31 downto 0);
                  FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
                  FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
             end record;
             type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
             type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
             type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
             signal Rec      : FIFO_ctrlr_Reg_Vec;
             signal PRdata    : std_logic_vector(31 downto 0);
             signal FIFO_ID  : std_logic_vector(31 downto 0);
             signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
             signal sFull     : std_logic_vector(FifoCnt-1 downto 0);
             signal sEmpty    : std_logic_vector(FifoCnt-1 downto 0);
             signal sEmpty_d  : std_logic_vector(FifoCnt-1 downto 0);
             signal sWen      : std_logic_vector(FifoCnt-1 downto 0);
             signal sRen      : std_logic_vector(FifoCnt-1 downto 0);
             signal sRclk     : std_logic;
             signal sWclk     : std_logic;
             signal sWen_APB  : std_logic_vector(FifoCnt-1 downto 0);
             signal sRen_APB  : std_logic_vector(FifoCnt-1 downto 0);
             signal sRDATA    : fifodatabus;
             signal sWDATA    : fifodatabus;
             signal sWADDR    : fifoaddressbus;
             signal sRADDR    : fifoaddressbus;
             signal ReUse     : std_logic_vector(FifoCnt-1 downto 0);   --27/01/12
             type state_t is (idle,Read);
             signal fiforeadfsmst : state_t;
             begin
             FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
             FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
             FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
             Write : if W /= 0 generate
                 FIFO_ID(4) <= '1';
                 sWen   <= sWen_APB;
                 sWclk  <=  clk;
                 Wrapb: for i in 0 to FifoCnt-1 generate
                     sWDATA(i) <= Rec(i).FIFO_Wdata;
                 end generate;
             end generate;
             Writeext : if W = 0 generate
                 FIFO_ID(4) <= '0';
                 sWen   <=  WEN;
                 sWclk  <=  Wclk;
                 Wrext: for i in 0 to FifoCnt-1 generate
                     sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
                 end generate;
             end generate;
             Read : if R /= 0 generate
              FIFO_ID(5) <= '1';
              sRen   <=  sRen_APB;
              srclk  <=  clk;
              Rdapb: for i in 0 to FifoCnt-1 generate
                     Rec(i).FIFO_Rdata  <= sRDATA(i);
              end generate;
             end generate;
             Readext : if R = 0 generate
                 FIFO_ID(5) <= '0';
                 sRen   <=  REN;
                 srclk  <=  rclk;
                 Drext: for i in 0 to FifoCnt-1 generate
                     RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i)  <= sRDATA(i);
                 end generate;
             end generate;
             ctrlregs: for i in 0 to FifoCnt-1 generate
                 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
                 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
                 Rec(i).FIFO_Ctrl(16) <= sFull(i);
                 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
                 ReUse(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
                 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
                 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
                 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
                 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);  ---|free|Waddrs|Full||free|Raddrs|empty|
             end generate;                                               -- 31         17  16 15          1     0
             Empty <= sEmpty;
             Full <= sFull;
             fifos: for i in 0 to FifoCnt-1 generate
                 FIFO0 : lpp_fifo
-                    generic map (tech,Data_sz,Addr_sz)
+                    generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
                     port map(rst,ReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
             end generate;
                 process(rst,clk)
                 begin
                     if(rst='0')then
                     rstloop1: for i in 0 to FifoCnt-1 loop
                         Rec(i).FIFO_Wdata <=  (others => '0');
                         Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
                         --Rec(i).FIFO_Ctrl(17) <= '0';
                         sWen_APB(i) <= '1';
                     end loop;
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                                writelp: for i in 0 to FifoCnt-1 loop
                                     if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
                                         Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
                                         --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
                                     elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
                                         Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
                                         sWen_APB(i) <= '0';
                                     end if;
                                end loop;
                         else
                             sWen_APB <= (others =>'1');
                         end if;
              --APB Read OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                            if(apbi.paddr(abits-1 downto 2)="000000") then
                                 PRdata   <= FIFO_ID;
                             else
                                readlp: for i in 0 to FifoCnt-1 loop
                                     if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
                                         PRdata   <= Rec(i).FIFO_Ctrl;
                                     elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
                                         PRdata(Data_sz-1 downto 0)  <= Rec(i).FIFO_rdata;
                                     end if;
                                end loop;
                             end if;
                         end if;
                 end if;
                 apbo.pconfig <= pconfig;
             end process;
             apbo.prdata     <=   PRdata when apbi.penable = '1';
             process(rst,clk)
                 begin
                     if(rst='0')then
                         fiforeadfsmst   <= idle;
                         rstloop: for i in 0 to FifoCnt-1 loop
                             sRen_APB(i) <= '1';
                             autoloaded(i)  <= '1';
                             Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
                         end loop;
                     elsif clk'event and clk = '1' then
                         sEmpty_d    <= sEmpty;
                         case fiforeadfsmst is
                             when idle =>
                                 idlelp: for i in 0 to FifoCnt-1 loop
                                     if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
                                         if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
                                              autoloaded(i)  <= '0';
                                         else
                                              autoloaded(i)  <= '1';
                                         end if;
                                         sRen_APB(i) <= '0';
                                         fiforeadfsmst   <= read;
                                         Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
                                     else
                                         sRen_APB(i) <= '1';
                                     end if;
                                 end loop;
                             when read =>
                                 sRen_APB        <= (others => '1');
                                 fiforeadfsmst   <= idle;
                             when others =>
                                 fiforeadfsmst <= idle;
                         end case;
                     end if;
             end process;
             end ar_APB_FIFO;

lib/lpp/lpp_memory/lpp_FIFO.vhd +6 -5

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             library lpp;
             use lpp.lpp_memory.all;
             library techmap;
             use techmap.gencomp.all;
             entity lpp_fifo is
             generic(
-                tech    :   integer := 0;
+                tech          :   integer := 0;
-                DataSz  :   integer range 1 to 32 := 8;
+                Enable_ReUse  :   std_logic := '0';
-                abits   :   integer range 2 to 12 := 8
+                DataSz        :   integer range 1 to 32 := 8;
+                abits         :   integer range 2 to 12 := 8
                 );
             port(
                 rstn    :   in std_logic;
                 ReUse   :   in std_logic;   --27/01/12
                 rclk    :   in std_logic;
                 ren     :   in std_logic;
                 rdata   :   out std_logic_vector(DataSz-1 downto 0);
                 empty   :   out std_logic;
                 raddr   :   out std_logic_vector(abits-1 downto 0);
                 wclk    :   in std_logic;
                 wen     :   in std_logic;
                 wdata   :   in std_logic_vector(DataSz-1 downto 0);
                 full    :   out std_logic;
                 waddr   :   out std_logic_vector(abits-1 downto 0)
             );
             end entity;
             architecture ar_lpp_fifo of lpp_fifo is
             signal sFull        : std_logic:='0';
             signal sEmpty       : std_logic:='1';
             signal sREN         : std_logic:='0';
             signal sWEN         : std_logic:='0';
             signal Waddr_vect   : std_logic_vector(abits-1 downto 0):=(others =>'0');
             signal Raddr_vect   : std_logic_vector(abits-1 downto 0):=(others =>'0');
             signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
             signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
             begin
             SRAM : syncram_2p
             generic map(tech,abits,DataSz)
             port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
             --RAM0: entity work.RAM_CEL
             --    generic map(abits, DataSz)
             --    port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
             --=============================
             --     Read section
             --=============================
             sREN    <= not REN and not sempty;
             process (rclk,rstn)
             begin
                 if(rstn='0')then
                     Raddr_vect   <=  (others =>'0');
                     Raddr_vect_d <=  (others =>'1');
                     sempty  <= '1';
                 elsif(rclk'event and rclk='1')then
-                    if(ReUse = '1')then   --27/01/12
+                    if(ReUse = '1' and Enable_ReUse='1')then   --27/01/12
                         sempty  <= '0';    --27/01/12
                     elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
                         sempty  <= '1';
                     elsif(Raddr_vect/=Waddr_vect) then
                         sempty  <= '0';
                     end if;
                     if(sREN='1' and sempty = '0') then
                         Raddr_vect  <= std_logic_vector(unsigned(Raddr_vect) + 1);
                         Raddr_vect_d  <=  Raddr_vect;
                     end if;
                 end if;
             end process;
             --=============================
             --     Write section
             --=============================
             sWEN    <= not WEN and not sfull;
             process (wclk,rstn)
             begin
                 if(rstn='0')then
                     Waddr_vect   <=  (others =>'0');
                     Waddr_vect_d <=  (others =>'1');
                     sfull        <=   '0';
                 elsif(wclk'event and wclk='1')then
-                    if(ReUse = '1')then   --27/01/12
+                    if(ReUse = '1' and Enable_ReUse='1')then   --27/01/12
                         sfull  <= '1';    --27/01/12
                     elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
                         sfull  <= '1';
                     elsif(Raddr_vect/=Waddr_vect) then
                         sfull  <= '0';
                     end if;
                     if(sWEN='1' and sfull='0') then
                         Waddr_vect   <= std_logic_vector(unsigned(Waddr_vect) +1);
                         Waddr_vect_d <= Waddr_vect;
                     end if;
                 end if;
             end process;
             full    <= sFull;
             empty   <= sEmpty;
             waddr   <= Waddr_vect;
             raddr   <= Raddr_vect;
             end architecture;

lib/lpp/lpp_memory/lpp_memory.vhd +6 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             library gaisler;
             use gaisler.misc.all;
             use gaisler.memctrl.all;
             library techmap;
             use techmap.gencomp.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_memory is
             component APB_FIFO is
             generic (
                 tech         : integer := apa3;
                 pindex       : integer := 0;
                 paddr        : integer := 0;
                 pmask        : integer := 16#fff#;
                 pirq         : integer := 0;
                 abits        : integer := 8;
                 FifoCnt      : integer := 2;
                 Data_sz      : integer := 16;
-                Addr_sz      : integer := 9;
+                Addr_sz        : integer := 9;
+                Enable_ReUse   : std_logic := '0';
                 R            : integer := 1;
                 W            : integer := 1
                 );
               port (
                 clk          : in  std_logic;                              --! Horloge du composant
                 rst          : in  std_logic;                              --! Reset general du composant
                 rclk         : in  std_logic;
                 wclk         : in  std_logic;
                 REN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction de lecture en m�moire
                 WEN          : in std_logic_vector(FifoCnt-1 downto 0);   --! Instruction d'�criture en m�moire
                 Empty        : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, M�moire vide
                 Full         : out std_logic_vector(FifoCnt-1 downto 0);    --! Flag, M�moire pleine
                 RDATA        : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);   --! Registre de donn�es en entr�e
                 WDATA        : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);    --! Registre de donn�es en sortie
                 WADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (�criture)
                 RADDR        : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0);    --! Registre d'addresse (lecture)
                 apbi         : in  apb_slv_in_type;                        --! Registre de gestion des entr�es du bus
                 apbo         : out apb_slv_out_type                        --! Registre de gestion des sorties du bus
                 );
             end component;
             component lpp_fifo is
             generic(
-                tech    :   integer := 0;
+                tech          :   integer := 0;
-                DataSz  :   integer range 1 to 32 := 8;
+                Enable_ReUse  :   std_logic := '0';
-                abits   :   integer range 2 to 12 := 8
+                DataSz        :   integer range 1 to 32 := 8;
+                abits         :   integer range 2 to 12 := 8
                 );
             port(
                 rstn    :   in std_logic;
                 ReUse   :   in std_logic;   --27/01/12
                 rclk    :   in std_logic;
                 ren     :   in std_logic;
                 rdata   :   out std_logic_vector(DataSz-1 downto 0);
                 empty   :   out std_logic;
                 raddr   :   out std_logic_vector(abits-1 downto 0);
                 wclk    :   in std_logic;
                 wen     :   in std_logic;
                 wdata   :   in std_logic_vector(DataSz-1 downto 0);
                 full    :   out std_logic;
                 waddr   :   out std_logic_vector(abits-1 downto 0)
             );
             end component;
             component ssram_plugin is
             generic (tech : integer := 0);
             port
             (
                 clk             : in  std_logic;
                 mem_ctrlr_o     : in  memory_out_type;
                 SSRAM_CLK       : out std_logic;
                 nBWa            : out std_logic;
                 nBWb            : out std_logic;
                 nBWc            : out std_logic;
                 nBWd            : out std_logic;
                 nBWE            : out std_logic;
                 nADSC           : out std_logic;
                 nADSP           : out std_logic;
                 nADV            : out std_logic;
                 nGW             : out std_logic;
                 nCE1            : out std_logic;
                 CE2             : out std_logic;
                 nCE3            : out std_logic;
                 nOE             : out std_logic;
                 MODE            : out std_logic;
                 ZZ              : out std_logic
             );
             end component;
             end;

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