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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY LFR_em IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk100MHz : IN STD_ULOGIC; |
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52 | 52 | clk49_152MHz : IN STD_ULOGIC; |
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53 | 53 | reset : IN STD_ULOGIC; |
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54 | 54 | |
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55 | 55 | -- TAG -------------------------------------------------------------------- |
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56 | 56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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57 | 57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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58 | 58 | -- UART APB --------------------------------------------------------------- |
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59 | 59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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60 | 60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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61 | 61 | -- RAM -------------------------------------------------------------------- |
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62 | 62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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63 | 63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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64 | 64 | nSRAM_BE0 : OUT STD_LOGIC; |
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65 | 65 | nSRAM_BE1 : OUT STD_LOGIC; |
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66 | 66 | nSRAM_BE2 : OUT STD_LOGIC; |
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67 | 67 | nSRAM_BE3 : OUT STD_LOGIC; |
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68 | 68 | nSRAM_WE : OUT STD_LOGIC; |
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69 | 69 | nSRAM_CE : OUT STD_LOGIC; |
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70 | 70 | nSRAM_OE : OUT STD_LOGIC; |
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71 | 71 | -- SPW -------------------------------------------------------------------- |
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72 | 72 | spw1_din : IN STD_LOGIC; |
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73 | 73 | spw1_sin : IN STD_LOGIC; |
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74 | 74 | spw1_dout : OUT STD_LOGIC; |
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75 | 75 | spw1_sout : OUT STD_LOGIC; |
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76 | 76 | spw2_din : IN STD_LOGIC; |
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77 | 77 | spw2_sin : IN STD_LOGIC; |
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78 | 78 | spw2_dout : OUT STD_LOGIC; |
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79 | 79 | spw2_sout : OUT STD_LOGIC; |
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80 | 80 | -- ADC -------------------------------------------------------------------- |
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81 | 81 | bias_fail_sw : OUT STD_LOGIC; |
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82 | 82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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83 | 83 | ADC_smpclk : OUT STD_LOGIC; |
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84 | 84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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85 | 85 | --------------------------------------------------------------------------- |
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86 | 86 | TAG8 : OUT STD_LOGIC; |
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87 | 87 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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88 | 88 | ); |
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89 | 89 | |
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90 | 90 | END LFR_em; |
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91 | 91 | |
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92 | 92 | |
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93 | 93 | ARCHITECTURE beh OF LFR_em IS |
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94 | 94 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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95 | 95 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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96 | 96 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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97 | 97 | ----------------------------------------------------------------------------- |
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98 | 98 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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99 | 99 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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100 | 100 | |
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101 | 101 | -- CONSTANTS |
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102 | 102 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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103 | 103 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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104 | 104 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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105 | 105 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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106 | 106 | |
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107 | 107 | SIGNAL apbi_ext : apb_slv_in_type; |
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108 | 108 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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109 | 109 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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110 | 110 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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111 | 111 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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112 | 112 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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113 | 113 | |
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114 | 114 | -- Spacewire signals |
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115 | 115 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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116 | 116 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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117 | 117 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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118 | 118 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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119 | 119 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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120 | 120 | SIGNAL spw_clk : STD_LOGIC; |
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121 | 121 | SIGNAL swni : grspw_in_type; |
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122 | 122 | SIGNAL swno : grspw_out_type; |
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123 | 123 | |
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124 | 124 | --GPIO |
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125 | 125 | SIGNAL gpioi : gpio_in_type; |
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126 | 126 | SIGNAL gpioo : gpio_out_type; |
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127 | 127 | |
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128 | 128 | -- AD Converter ADS7886 |
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129 | 129 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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130 | 130 | SIGNAL sample_val : STD_LOGIC; |
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131 | 131 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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132 | 132 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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133 | 133 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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134 | 134 | |
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135 | 135 | ----------------------------------------------------------------------------- |
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136 | 136 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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137 | 137 | |
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138 | 138 | ----------------------------------------------------------------------------- |
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139 | 139 | SIGNAL rstn : STD_LOGIC; |
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140 | 140 | BEGIN -- beh |
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141 | 141 | |
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142 | 142 | ----------------------------------------------------------------------------- |
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143 | 143 | -- CLK |
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144 | 144 | ----------------------------------------------------------------------------- |
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145 | 145 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); |
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146 | 146 | |
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147 | 147 | PROCESS(clk100MHz) |
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148 | 148 | BEGIN |
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149 | 149 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
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150 | 150 | clk_50_s <= NOT clk_50_s; |
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151 | 151 | END IF; |
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152 | 152 | END PROCESS; |
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153 | 153 | |
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154 | 154 | PROCESS(clk_50_s) |
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155 | 155 | BEGIN |
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156 | 156 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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157 | 157 | clk_25 <= NOT clk_25; |
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158 | 158 | END IF; |
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159 | 159 | END PROCESS; |
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160 | 160 | |
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161 | 161 | PROCESS(clk49_152MHz) |
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162 | 162 | BEGIN |
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163 | 163 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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164 | 164 | clk_24 <= NOT clk_24; |
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165 | 165 | END IF; |
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166 | 166 | END PROCESS; |
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167 | 167 | |
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168 | 168 | ----------------------------------------------------------------------------- |
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169 | 169 | |
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170 | 170 | PROCESS (clk_25, rstn) |
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171 | 171 | BEGIN -- PROCESS |
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172 | 172 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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173 | 173 | led(0) <= '0'; |
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174 | 174 | led(1) <= '0'; |
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175 | 175 | led(2) <= '0'; |
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176 | 176 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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177 | 177 | led(0) <= '0'; |
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178 | 178 | led(1) <= '1'; |
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179 | 179 | led(2) <= '1'; |
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180 | 180 | END IF; |
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181 | 181 | END PROCESS; |
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182 | 182 | |
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183 | 183 | -- |
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184 | 184 | leon3_soc_1 : leon3_soc |
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185 | 185 | GENERIC MAP ( |
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186 | 186 | fabtech => apa3e, |
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187 | 187 | memtech => apa3e, |
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188 | 188 | padtech => inferred, |
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189 | 189 | clktech => inferred, |
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190 | 190 | disas => 0, |
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191 | 191 | dbguart => 0, |
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192 | 192 | pclow => 2, |
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193 | 193 | clk_freq => 25000, |
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194 | 194 | NB_CPU => 1, |
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195 | 195 | ENABLE_FPU => 1, |
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196 | 196 | FPU_NETLIST => 0, |
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197 | 197 | ENABLE_DSU => 1, |
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198 | 198 | ENABLE_AHB_UART => 1, |
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199 | 199 | ENABLE_APB_UART => 1, |
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200 | 200 | ENABLE_IRQMP => 1, |
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201 | 201 | ENABLE_GPT => 1, |
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202 | 202 | NB_AHB_MASTER => NB_AHB_MASTER, |
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203 | 203 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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204 | 204 | NB_APB_SLAVE => NB_APB_SLAVE) |
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205 | 205 | PORT MAP ( |
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206 | 206 | clk => clk_25, |
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207 | 207 | reset => rstn, |
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208 | 208 | errorn => OPEN, |
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209 | 209 | |
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210 | 210 | ahbrxd => TAG1, |
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211 | 211 | ahbtxd => TAG3, |
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212 | 212 | urxd1 => TAG2, |
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213 | 213 | utxd1 => TAG4, |
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214 | 214 | |
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215 | 215 | address => address, |
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216 | 216 | data => data, |
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217 | 217 | nSRAM_BE0 => nSRAM_BE0, |
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218 | 218 | nSRAM_BE1 => nSRAM_BE1, |
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219 | 219 | nSRAM_BE2 => nSRAM_BE2, |
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220 | 220 | nSRAM_BE3 => nSRAM_BE3, |
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221 | 221 | nSRAM_WE => nSRAM_WE, |
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222 | 222 | nSRAM_CE => nSRAM_CE, |
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223 | 223 | nSRAM_OE => nSRAM_OE, |
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224 | 224 | |
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225 | 225 | apbi_ext => apbi_ext, |
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226 | 226 | apbo_ext => apbo_ext, |
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227 | 227 | ahbi_s_ext => ahbi_s_ext, |
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228 | 228 | ahbo_s_ext => ahbo_s_ext, |
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229 | 229 | ahbi_m_ext => ahbi_m_ext, |
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230 | 230 | ahbo_m_ext => ahbo_m_ext); |
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231 | 231 | |
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232 | 232 | |
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233 | 233 | ------------------------------------------------------------------------------- |
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234 | 234 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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235 | 235 | ------------------------------------------------------------------------------- |
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236 | 236 | apb_lfr_time_management_1 : apb_lfr_time_management |
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237 | 237 | GENERIC MAP ( |
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238 | 238 | pindex => 6, |
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239 | 239 | paddr => 6, |
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240 | 240 | pmask => 16#fff#, |
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241 | 241 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
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242 | 242 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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243 | 243 | PORT MAP ( |
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244 | 244 | clk25MHz => clk_25, |
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245 | 245 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
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246 | 246 | resetn => rstn, |
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247 | 247 | grspw_tick => swno.tickout, |
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248 | 248 | apbi => apbi_ext, |
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249 | 249 | apbo => apbo_ext(6), |
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250 | 250 | coarse_time => coarse_time, |
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251 | 251 | fine_time => fine_time); |
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252 | 252 | |
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253 | 253 | ----------------------------------------------------------------------- |
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254 | 254 | --- SpaceWire -------------------------------------------------------- |
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255 | 255 | ----------------------------------------------------------------------- |
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256 | 256 | |
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257 | 257 | -- SPW_EN <= '1'; |
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258 | 258 | |
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259 | 259 | spw_clk <= clk_50_s; |
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260 | 260 | spw_rxtxclk <= spw_clk; |
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261 | 261 | spw_rxclkn <= NOT spw_rxtxclk; |
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262 | 262 | |
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263 | 263 | -- PADS for SPW1 |
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264 | 264 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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265 | 265 | PORT MAP (spw1_din, dtmp(0)); |
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266 | 266 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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267 | 267 | PORT MAP (spw1_sin, stmp(0)); |
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268 | 268 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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269 | 269 | PORT MAP (spw1_dout, swno.d(0)); |
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270 | 270 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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271 | 271 | PORT MAP (spw1_sout, swno.s(0)); |
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272 | 272 | -- PADS FOR SPW2 |
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273 | 273 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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274 | 274 | PORT MAP (spw2_sin, dtmp(1)); |
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275 | 275 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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276 | 276 | PORT MAP (spw2_din, stmp(1)); |
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277 | 277 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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278 | 278 | PORT MAP (spw2_dout, swno.d(1)); |
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279 | 279 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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280 | 280 | PORT MAP (spw2_sout, swno.s(1)); |
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281 | 281 | |
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282 | 282 | -- GRSPW PHY |
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283 | 283 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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284 | 284 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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285 | 285 | spw_phy0 : grspw_phy |
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286 | 286 | GENERIC MAP( |
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287 | 287 | tech => apa3e, |
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288 | 288 | rxclkbuftype => 1, |
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289 | 289 | scantest => 0) |
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290 | 290 | PORT MAP( |
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291 | 291 | rxrst => swno.rxrst, |
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292 | 292 | di => dtmp(j), |
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293 | 293 | si => stmp(j), |
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294 | 294 | rxclko => spw_rxclk(j), |
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295 | 295 | do => swni.d(j), |
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296 | 296 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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297 | 297 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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298 | 298 | END GENERATE spw_inputloop; |
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299 | 299 | |
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300 | 300 | -- SPW core |
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301 | 301 | sw0 : grspwm GENERIC MAP( |
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302 | 302 | tech => apa3e, |
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303 | 303 | hindex => 1, |
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304 | 304 | pindex => 5, |
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305 | 305 | paddr => 5, |
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306 | 306 | pirq => 11, |
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307 | 307 | sysfreq => 25000, -- CPU_FREQ |
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308 | 308 | rmap => 1, |
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309 | 309 | rmapcrc => 1, |
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310 | 310 | fifosize1 => 16, |
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311 | 311 | fifosize2 => 16, |
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312 | 312 | rxclkbuftype => 1, |
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313 | 313 | rxunaligned => 0, |
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314 | 314 | rmapbufs => 4, |
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315 | 315 | ft => 0, |
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316 | 316 | netlist => 0, |
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317 | 317 | ports => 2, |
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318 | 318 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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319 | 319 | memtech => apa3e, |
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320 | 320 | destkey => 2, |
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321 | 321 | spwcore => 1 |
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322 | 322 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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323 | 323 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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324 | 324 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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325 | 325 | ) |
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326 | 326 | PORT MAP(rstn, clk_25, spw_rxclk(0), |
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327 | 327 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
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328 | 328 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
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329 | 329 | swni, swno); |
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330 | 330 | |
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331 | 331 | swni.tickin <= '0'; |
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332 | 332 | swni.rmapen <= '1'; |
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333 | 333 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
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334 | 334 | swni.tickinraw <= '0'; |
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335 | 335 | swni.timein <= (OTHERS => '0'); |
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336 | 336 | swni.dcrstval <= (OTHERS => '0'); |
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337 | 337 | swni.timerrstval <= (OTHERS => '0'); |
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338 | 338 | |
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339 | 339 | ------------------------------------------------------------------------------- |
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340 | 340 | -- LFR ------------------------------------------------------------------------ |
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341 | 341 | ------------------------------------------------------------------------------- |
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342 | 342 | lpp_lfr_1 : lpp_lfr_WFP_nMS |
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343 | 343 | GENERIC MAP ( |
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344 | 344 | Mem_use => use_RAM, |
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345 | 345 | nb_data_by_buffer_size => 32, |
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346 | 346 | nb_word_by_buffer_size => 30, |
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347 | 347 | nb_snapshot_param_size => 32, |
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348 | 348 | delta_vector_size => 32, |
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349 | 349 | delta_vector_size_f0_2 => 7, -- log2(96) |
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350 | 350 | pindex => 15, |
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351 | 351 | paddr => 15, |
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352 | 352 | pmask => 16#fff#, |
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353 | 353 | pirq_ms => 6, |
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354 | 354 | pirq_wfp => 14, |
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355 | 355 | hindex => 2, |
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356 |
top_lfr_version => X"00010 |
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356 | top_lfr_version => X"00010A") -- aa.bb.cc version | |
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357 | 357 | -- AA : BOARD NUMBER |
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358 | 358 | -- 0 => MINI_LFR |
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359 | 359 | -- 1 => EM |
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360 | 360 | PORT MAP ( |
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361 | 361 | clk => clk_25, |
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362 | 362 | rstn => rstn, |
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363 | 363 | sample_B => sample(2 DOWNTO 0), |
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364 | 364 | sample_E => sample(7 DOWNTO 3), |
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365 | 365 | sample_val => sample_val, |
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366 | 366 | apbi => apbi_ext, |
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367 | 367 | apbo => apbo_ext(15), |
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368 | 368 | ahbi => ahbi_m_ext, |
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369 | 369 | ahbo => ahbo_m_ext(2), |
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370 | 370 | coarse_time => coarse_time, |
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371 | 371 | fine_time => fine_time, |
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372 | 372 | data_shaping_BW => bias_fail_sw, |
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373 | 373 | observation_reg => observation_reg); |
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374 | 374 | |
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375 | 375 | ----------------------------------------------------------------------------- |
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376 | 376 | -- |
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377 | 377 | ----------------------------------------------------------------------------- |
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378 | 378 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
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379 | 379 | GENERIC MAP ( |
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380 | 380 | ChanelCount => 8, |
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381 | 381 | ncycle_cnv_high => 40, -- TODO : 79 |
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382 | 382 | ncycle_cnv => 250) -- TODO : 500 |
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383 | 383 | PORT MAP ( |
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384 | 384 | cnv_clk => clk_24, -- TODO : 49.152 |
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385 | 385 | cnv_rstn => rstn, -- ok |
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386 | 386 | cnv => ADC_smpclk, -- ok |
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387 | 387 | clk => clk_25, -- ok |
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388 | 388 | rstn => rstn, -- ok |
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389 | 389 | ADC_data => ADC_data, -- ok |
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390 | 390 | ADC_nOE => ADC_OEB_bar_CH, -- ok |
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391 | 391 | sample => sample, -- ok |
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392 | 392 | sample_val => sample_val); -- ok |
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393 | 393 | |
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394 | 394 | TAG8 <= ADC_smpclk; |
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395 | 395 | |
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396 | 396 | END beh; |
@@ -1,580 +1,580 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
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51 | 51 | clk_50 : IN STD_LOGIC; |
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52 | 52 | clk_49 : IN STD_LOGIC; |
|
53 | 53 | reset : IN STD_LOGIC; |
|
54 | 54 | --BPs |
|
55 | 55 | BP0 : IN STD_LOGIC; |
|
56 | 56 | BP1 : IN STD_LOGIC; |
|
57 | 57 | --LEDs |
|
58 | 58 | LED0 : OUT STD_LOGIC; |
|
59 | 59 | LED1 : OUT STD_LOGIC; |
|
60 | 60 | LED2 : OUT STD_LOGIC; |
|
61 | 61 | --UARTs |
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62 | 62 | TXD1 : IN STD_LOGIC; |
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63 | 63 | RXD1 : OUT STD_LOGIC; |
|
64 | 64 | nCTS1 : OUT STD_LOGIC; |
|
65 | 65 | nRTS1 : IN STD_LOGIC; |
|
66 | 66 | |
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67 | 67 | TXD2 : IN STD_LOGIC; |
|
68 | 68 | RXD2 : OUT STD_LOGIC; |
|
69 | 69 | nCTS2 : OUT STD_LOGIC; |
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70 | 70 | nDTR2 : IN STD_LOGIC; |
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71 | 71 | nRTS2 : IN STD_LOGIC; |
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72 | 72 | nDCD2 : OUT STD_LOGIC; |
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73 | 73 | |
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74 | 74 | --EXT CONNECTOR |
|
75 | 75 | IO0 : INOUT STD_LOGIC; |
|
76 | 76 | IO1 : INOUT STD_LOGIC; |
|
77 | 77 | IO2 : INOUT STD_LOGIC; |
|
78 | 78 | IO3 : INOUT STD_LOGIC; |
|
79 | 79 | IO4 : INOUT STD_LOGIC; |
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80 | 80 | IO5 : INOUT STD_LOGIC; |
|
81 | 81 | IO6 : INOUT STD_LOGIC; |
|
82 | 82 | IO7 : INOUT STD_LOGIC; |
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83 | 83 | IO8 : INOUT STD_LOGIC; |
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84 | 84 | IO9 : INOUT STD_LOGIC; |
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85 | 85 | IO10 : INOUT STD_LOGIC; |
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86 | 86 | IO11 : INOUT STD_LOGIC; |
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87 | 87 | |
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88 | 88 | --SPACE WIRE |
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89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
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92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
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96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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98 | 98 | -- MINI LFR ADC INPUTS |
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99 | 99 | ADC_nCS : OUT STD_LOGIC; |
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100 | 100 | ADC_CLK : OUT STD_LOGIC; |
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101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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102 | 102 | |
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103 | 103 | -- SRAM |
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104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
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105 | 105 | SRAM_CE : OUT STD_LOGIC; |
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106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
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107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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110 | 110 | ); |
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111 | 111 | |
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112 | 112 | END MINI_LFR_top; |
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113 | 113 | |
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114 | 114 | |
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115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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119 | 119 | ----------------------------------------------------------------------------- |
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120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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122 | 122 | -- |
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123 | 123 | SIGNAL errorn : STD_LOGIC; |
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124 | 124 | -- UART AHB --------------------------------------------------------------- |
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125 | 125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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126 | 126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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127 | 127 | |
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128 | 128 | -- UART APB --------------------------------------------------------------- |
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129 | 129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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130 | 130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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131 | 131 | -- |
|
132 | 132 | SIGNAL I00_s : STD_LOGIC; |
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133 | 133 | |
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134 | 134 | -- CONSTANTS |
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135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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136 | 136 | -- |
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137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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140 | 140 | |
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141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
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142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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147 | 147 | |
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148 | 148 | -- Spacewire signals |
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149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
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155 | 155 | SIGNAL swni : grspw_in_type; |
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156 | 156 | SIGNAL swno : grspw_out_type; |
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157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
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158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
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159 | 159 | |
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160 | 160 | --GPIO |
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161 | 161 | SIGNAL gpioi : gpio_in_type; |
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162 | 162 | SIGNAL gpioo : gpio_out_type; |
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163 | 163 | |
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164 | 164 | -- AD Converter ADS7886 |
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165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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166 | 166 | SIGNAL sample_val : STD_LOGIC; |
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167 | 167 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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168 | 168 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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169 | 169 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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170 | 170 | |
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171 | 171 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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172 | 172 | |
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173 | 173 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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174 | 174 | ----------------------------------------------------------------------------- |
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175 | 175 | |
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176 | 176 | BEGIN -- beh |
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177 | 177 | |
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178 | 178 | ----------------------------------------------------------------------------- |
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179 | 179 | -- CLK |
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180 | 180 | ----------------------------------------------------------------------------- |
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181 | 181 | |
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182 | 182 | PROCESS(clk_50) |
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183 | 183 | BEGIN |
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184 | 184 | IF clk_50'EVENT AND clk_50 = '1' THEN |
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185 | 185 | clk_50_s <= NOT clk_50_s; |
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186 | 186 | END IF; |
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187 | 187 | END PROCESS; |
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188 | 188 | |
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189 | 189 | PROCESS(clk_50_s) |
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190 | 190 | BEGIN |
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191 | 191 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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192 | 192 | clk_25 <= NOT clk_25; |
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193 | 193 | END IF; |
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194 | 194 | END PROCESS; |
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195 | 195 | |
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196 | 196 | PROCESS(clk_49) |
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197 | 197 | BEGIN |
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198 | 198 | IF clk_49'EVENT AND clk_49 = '1' THEN |
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199 | 199 | clk_24 <= NOT clk_24; |
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200 | 200 | END IF; |
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201 | 201 | END PROCESS; |
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202 | 202 | |
|
203 | 203 | ----------------------------------------------------------------------------- |
|
204 | 204 | |
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205 | 205 | PROCESS (clk_25, reset) |
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206 | 206 | BEGIN -- PROCESS |
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207 | 207 | IF reset = '0' THEN -- asynchronous reset (active low) |
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208 | 208 | LED0 <= '0'; |
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209 | 209 | LED1 <= '0'; |
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210 | 210 | LED2 <= '0'; |
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211 | 211 | --IO1 <= '0'; |
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212 | 212 | --IO2 <= '1'; |
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213 | 213 | --IO3 <= '0'; |
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214 | 214 | --IO4 <= '0'; |
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215 | 215 | --IO5 <= '0'; |
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216 | 216 | --IO6 <= '0'; |
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217 | 217 | --IO7 <= '0'; |
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218 | 218 | --IO8 <= '0'; |
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219 | 219 | --IO9 <= '0'; |
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220 | 220 | --IO10 <= '0'; |
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221 | 221 | --IO11 <= '0'; |
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222 | 222 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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223 | 223 | LED0 <= '0'; |
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224 | 224 | LED1 <= '1'; |
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225 | 225 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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226 | 226 | --IO1 <= '1'; |
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227 | 227 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
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228 | 228 | --IO3 <= ADC_SDO(0); |
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229 | 229 | --IO4 <= ADC_SDO(1); |
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230 | 230 | --IO5 <= ADC_SDO(2); |
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231 | 231 | --IO6 <= ADC_SDO(3); |
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232 | 232 | --IO7 <= ADC_SDO(4); |
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233 | 233 | --IO8 <= ADC_SDO(5); |
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234 | 234 | --IO9 <= ADC_SDO(6); |
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235 | 235 | --IO10 <= ADC_SDO(7); |
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236 | 236 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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237 | 237 | END IF; |
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238 | 238 | END PROCESS; |
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239 | 239 | |
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240 | 240 | PROCESS (clk_24, reset) |
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241 | 241 | BEGIN -- PROCESS |
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242 | 242 | IF reset = '0' THEN -- asynchronous reset (active low) |
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243 | 243 | I00_s <= '0'; |
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244 | 244 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
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245 | 245 | I00_s <= NOT I00_s ; |
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246 | 246 | END IF; |
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247 | 247 | END PROCESS; |
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248 | 248 | -- IO0 <= I00_s; |
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249 | 249 | |
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250 | 250 | --UARTs |
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251 | 251 | nCTS1 <= '1'; |
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252 | 252 | nCTS2 <= '1'; |
|
253 | 253 | nDCD2 <= '1'; |
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254 | 254 | |
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255 | 255 | --EXT CONNECTOR |
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256 | 256 | |
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257 | 257 | --SPACE WIRE |
|
258 | 258 | |
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259 | 259 | leon3_soc_1 : leon3_soc |
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260 | 260 | GENERIC MAP ( |
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261 | 261 | fabtech => apa3e, |
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262 | 262 | memtech => apa3e, |
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263 | 263 | padtech => inferred, |
|
264 | 264 | clktech => inferred, |
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265 | 265 | disas => 0, |
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266 | 266 | dbguart => 0, |
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267 | 267 | pclow => 2, |
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268 | 268 | clk_freq => 25000, |
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269 | 269 | NB_CPU => 1, |
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270 | 270 | ENABLE_FPU => 1, |
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271 | 271 | FPU_NETLIST => 0, |
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272 | 272 | ENABLE_DSU => 1, |
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273 | 273 | ENABLE_AHB_UART => 1, |
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274 | 274 | ENABLE_APB_UART => 1, |
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275 | 275 | ENABLE_IRQMP => 1, |
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276 | 276 | ENABLE_GPT => 1, |
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277 | 277 | NB_AHB_MASTER => NB_AHB_MASTER, |
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278 | 278 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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279 | 279 | NB_APB_SLAVE => NB_APB_SLAVE) |
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280 | 280 | PORT MAP ( |
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281 | 281 | clk => clk_25, |
|
282 | 282 | reset => reset, |
|
283 | 283 | errorn => errorn, |
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284 | 284 | ahbrxd => TXD1, |
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285 | 285 | ahbtxd => RXD1, |
|
286 | 286 | urxd1 => TXD2, |
|
287 | 287 | utxd1 => RXD2, |
|
288 | 288 | address => SRAM_A, |
|
289 | 289 | data => SRAM_DQ, |
|
290 | 290 | nSRAM_BE0 => SRAM_nBE(0), |
|
291 | 291 | nSRAM_BE1 => SRAM_nBE(1), |
|
292 | 292 | nSRAM_BE2 => SRAM_nBE(2), |
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293 | 293 | nSRAM_BE3 => SRAM_nBE(3), |
|
294 | 294 | nSRAM_WE => SRAM_nWE, |
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295 | 295 | nSRAM_CE => SRAM_CE, |
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296 | 296 | nSRAM_OE => SRAM_nOE, |
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297 | 297 | |
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298 | 298 | apbi_ext => apbi_ext, |
|
299 | 299 | apbo_ext => apbo_ext, |
|
300 | 300 | ahbi_s_ext => ahbi_s_ext, |
|
301 | 301 | ahbo_s_ext => ahbo_s_ext, |
|
302 | 302 | ahbi_m_ext => ahbi_m_ext, |
|
303 | 303 | ahbo_m_ext => ahbo_m_ext); |
|
304 | 304 | |
|
305 | 305 | ------------------------------------------------------------------------------- |
|
306 | 306 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
307 | 307 | ------------------------------------------------------------------------------- |
|
308 | 308 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
309 | 309 | GENERIC MAP ( |
|
310 | 310 | pindex => 6, |
|
311 | 311 | paddr => 6, |
|
312 | 312 | pmask => 16#fff#, |
|
313 | 313 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
314 | 314 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
315 | 315 | PORT MAP ( |
|
316 | 316 | clk25MHz => clk_25, |
|
317 | 317 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
318 | 318 | resetn => reset, |
|
319 | 319 | grspw_tick => swno.tickout, |
|
320 | 320 | apbi => apbi_ext, |
|
321 | 321 | apbo => apbo_ext(6), |
|
322 | 322 | coarse_time => coarse_time, |
|
323 | 323 | fine_time => fine_time); |
|
324 | 324 | |
|
325 | 325 | ----------------------------------------------------------------------- |
|
326 | 326 | --- SpaceWire -------------------------------------------------------- |
|
327 | 327 | ----------------------------------------------------------------------- |
|
328 | 328 | |
|
329 | 329 | SPW_EN <= '1'; |
|
330 | 330 | |
|
331 | 331 | spw_clk <= clk_50_s; |
|
332 | 332 | spw_rxtxclk <= spw_clk; |
|
333 | 333 | spw_rxclkn <= NOT spw_rxtxclk; |
|
334 | 334 | |
|
335 | 335 | -- PADS for SPW1 |
|
336 | 336 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
337 | 337 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
338 | 338 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
339 | 339 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
340 | 340 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
341 | 341 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
342 | 342 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
343 | 343 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
344 | 344 | -- PADS FOR SPW2 |
|
345 | 345 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
346 | 346 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
347 | 347 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
348 | 348 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
349 | 349 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
350 | 350 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
351 | 351 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
352 | 352 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
353 | 353 | |
|
354 | 354 | -- GRSPW PHY |
|
355 | 355 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
356 | 356 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
357 | 357 | spw_phy0 : grspw_phy |
|
358 | 358 | GENERIC MAP( |
|
359 | 359 | tech => apa3e, |
|
360 | 360 | rxclkbuftype => 1, |
|
361 | 361 | scantest => 0) |
|
362 | 362 | PORT MAP( |
|
363 | 363 | rxrst => swno.rxrst, |
|
364 | 364 | di => dtmp(j), |
|
365 | 365 | si => stmp(j), |
|
366 | 366 | rxclko => spw_rxclk(j), |
|
367 | 367 | do => swni.d(j), |
|
368 | 368 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
369 | 369 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
370 | 370 | END GENERATE spw_inputloop; |
|
371 | 371 | |
|
372 | 372 | -- SPW core |
|
373 | 373 | sw0 : grspwm GENERIC MAP( |
|
374 | 374 | tech => apa3e, |
|
375 | 375 | hindex => 1, |
|
376 | 376 | pindex => 5, |
|
377 | 377 | paddr => 5, |
|
378 | 378 | pirq => 11, |
|
379 | 379 | sysfreq => 25000, -- CPU_FREQ |
|
380 | 380 | rmap => 1, |
|
381 | 381 | rmapcrc => 1, |
|
382 | 382 | fifosize1 => 16, |
|
383 | 383 | fifosize2 => 16, |
|
384 | 384 | rxclkbuftype => 1, |
|
385 | 385 | rxunaligned => 0, |
|
386 | 386 | rmapbufs => 4, |
|
387 | 387 | ft => 0, |
|
388 | 388 | netlist => 0, |
|
389 | 389 | ports => 2, |
|
390 | 390 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
391 | 391 | memtech => apa3e, |
|
392 | 392 | destkey => 2, |
|
393 | 393 | spwcore => 1 |
|
394 | 394 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
395 | 395 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
396 | 396 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
397 | 397 | ) |
|
398 | 398 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
399 | 399 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
400 | 400 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
401 | 401 | swni, swno); |
|
402 | 402 | |
|
403 | 403 | swni.tickin <= '0'; |
|
404 | 404 | swni.rmapen <= '1'; |
|
405 | 405 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
406 | 406 | swni.tickinraw <= '0'; |
|
407 | 407 | swni.timein <= (OTHERS => '0'); |
|
408 | 408 | swni.dcrstval <= (OTHERS => '0'); |
|
409 | 409 | swni.timerrstval <= (OTHERS => '0'); |
|
410 | 410 | |
|
411 | 411 | ------------------------------------------------------------------------------- |
|
412 | 412 | -- LFR ------------------------------------------------------------------------ |
|
413 | 413 | ------------------------------------------------------------------------------- |
|
414 | 414 | lpp_lfr_1 : lpp_lfr |
|
415 | 415 | GENERIC MAP ( |
|
416 | 416 | Mem_use => use_RAM, |
|
417 | 417 | nb_data_by_buffer_size => 32, |
|
418 | 418 | nb_word_by_buffer_size => 30, |
|
419 | 419 | nb_snapshot_param_size => 32, |
|
420 | 420 | delta_vector_size => 32, |
|
421 | 421 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
422 | 422 | pindex => 15, |
|
423 | 423 | paddr => 15, |
|
424 | 424 | pmask => 16#fff#, |
|
425 | 425 | pirq_ms => 6, |
|
426 | 426 | pirq_wfp => 14, |
|
427 | 427 | hindex => 2, |
|
428 |
top_lfr_version => X"00010 |
|
|
428 | top_lfr_version => X"00010A") -- aa.bb.cc version | |
|
429 | 429 | PORT MAP ( |
|
430 | 430 | clk => clk_25, |
|
431 | 431 | rstn => reset, |
|
432 | 432 | sample_B => sample(2 DOWNTO 0), |
|
433 | 433 | sample_E => sample(7 DOWNTO 3), |
|
434 | 434 | sample_val => sample_val, |
|
435 | 435 | apbi => apbi_ext, |
|
436 | 436 | apbo => apbo_ext(15), |
|
437 | 437 | ahbi => ahbi_m_ext, |
|
438 | 438 | ahbo => ahbo_m_ext(2), |
|
439 | 439 | coarse_time => coarse_time, |
|
440 | 440 | fine_time => fine_time, |
|
441 | 441 | data_shaping_BW => bias_fail_sw_sig, |
|
442 | 442 | observation_reg => observation_reg); |
|
443 | 443 | |
|
444 | 444 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
445 | 445 | GENERIC MAP( |
|
446 | 446 | ChannelCount => 8, |
|
447 | 447 | SampleNbBits => 14, |
|
448 | 448 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
449 | 449 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
450 | 450 | PORT MAP ( |
|
451 | 451 | -- CONV |
|
452 | 452 | cnv_clk => clk_24, |
|
453 | 453 | cnv_rstn => reset, |
|
454 | 454 | cnv => ADC_nCS_sig, |
|
455 | 455 | -- DATA |
|
456 | 456 | clk => clk_25, |
|
457 | 457 | rstn => reset, |
|
458 | 458 | sck => ADC_CLK_sig, |
|
459 | 459 | sdo => ADC_SDO_sig, |
|
460 | 460 | -- SAMPLE |
|
461 | 461 | sample => sample, |
|
462 | 462 | sample_val => sample_val); |
|
463 | 463 | |
|
464 | 464 | --IO10 <= ADC_SDO_sig(5); |
|
465 | 465 | --IO9 <= ADC_SDO_sig(4); |
|
466 | 466 | --IO8 <= ADC_SDO_sig(3); |
|
467 | 467 | |
|
468 | 468 | ADC_nCS <= ADC_nCS_sig; |
|
469 | 469 | ADC_CLK <= ADC_CLK_sig; |
|
470 | 470 | ADC_SDO_sig <= ADC_SDO; |
|
471 | 471 | |
|
472 | 472 | ---------------------------------------------------------------------- |
|
473 | 473 | --- GPIO ----------------------------------------------------------- |
|
474 | 474 | ---------------------------------------------------------------------- |
|
475 | 475 | |
|
476 | 476 | grgpio0 : grgpio |
|
477 | 477 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
478 | 478 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
479 | 479 | |
|
480 | 480 | --pio_pad_0 : iopad |
|
481 | 481 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
482 | 482 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
483 | 483 | --pio_pad_1 : iopad |
|
484 | 484 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
485 | 485 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
486 | 486 | --pio_pad_2 : iopad |
|
487 | 487 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
488 | 488 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
489 | 489 | --pio_pad_3 : iopad |
|
490 | 490 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
491 | 491 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
492 | 492 | --pio_pad_4 : iopad |
|
493 | 493 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
494 | 494 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
495 | 495 | --pio_pad_5 : iopad |
|
496 | 496 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
497 | 497 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
498 | 498 | --pio_pad_6 : iopad |
|
499 | 499 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
500 | 500 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
501 | 501 | --pio_pad_7 : iopad |
|
502 | 502 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
503 | 503 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
504 | 504 | |
|
505 | 505 | PROCESS (clk_25, reset) |
|
506 | 506 | BEGIN -- PROCESS |
|
507 | 507 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
508 | 508 | IO0 <= '0'; |
|
509 | 509 | IO1 <= '0'; |
|
510 | 510 | IO2 <= '0'; |
|
511 | 511 | IO3 <= '0'; |
|
512 | 512 | IO4 <= '0'; |
|
513 | 513 | IO5 <= '0'; |
|
514 | 514 | IO6 <= '0'; |
|
515 | 515 | IO7 <= '0'; |
|
516 | 516 | IO8 <= '0'; |
|
517 | 517 | IO9 <= '0'; |
|
518 | 518 | IO10 <= '0'; |
|
519 | 519 | IO11 <= '0'; |
|
520 | 520 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
521 | 521 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
522 | 522 | WHEN "00" => |
|
523 | 523 | IO0 <= observation_reg(0 ); |
|
524 | 524 | IO1 <= observation_reg(1 ); |
|
525 | 525 | IO2 <= observation_reg(2 ); |
|
526 | 526 | IO3 <= observation_reg(3 ); |
|
527 | 527 | IO4 <= observation_reg(4 ); |
|
528 | 528 | IO5 <= observation_reg(5 ); |
|
529 | 529 | IO6 <= observation_reg(6 ); |
|
530 | 530 | IO7 <= observation_reg(7 ); |
|
531 | 531 | IO8 <= observation_reg(8 ); |
|
532 | 532 | IO9 <= observation_reg(9 ); |
|
533 | 533 | IO10 <= observation_reg(10); |
|
534 | 534 | IO11 <= observation_reg(11); |
|
535 | 535 | WHEN "01" => |
|
536 | 536 | IO0 <= observation_reg(0 + 12); |
|
537 | 537 | IO1 <= observation_reg(1 + 12); |
|
538 | 538 | IO2 <= observation_reg(2 + 12); |
|
539 | 539 | IO3 <= observation_reg(3 + 12); |
|
540 | 540 | IO4 <= observation_reg(4 + 12); |
|
541 | 541 | IO5 <= observation_reg(5 + 12); |
|
542 | 542 | IO6 <= observation_reg(6 + 12); |
|
543 | 543 | IO7 <= observation_reg(7 + 12); |
|
544 | 544 | IO8 <= observation_reg(8 + 12); |
|
545 | 545 | IO9 <= observation_reg(9 + 12); |
|
546 | 546 | IO10 <= observation_reg(10 + 12); |
|
547 | 547 | IO11 <= observation_reg(11 + 12); |
|
548 | 548 | WHEN "10" => |
|
549 | 549 | IO0 <= observation_reg(0 + 12 + 12); |
|
550 | 550 | IO1 <= observation_reg(1 + 12 + 12); |
|
551 | 551 | IO2 <= observation_reg(2 + 12 + 12); |
|
552 | 552 | IO3 <= observation_reg(3 + 12 + 12); |
|
553 | 553 | IO4 <= observation_reg(4 + 12 + 12); |
|
554 | 554 | IO5 <= observation_reg(5 + 12 + 12); |
|
555 | 555 | IO6 <= observation_reg(6 + 12 + 12); |
|
556 | 556 | IO7 <= observation_reg(7 + 12 + 12); |
|
557 | 557 | IO8 <= '0'; |
|
558 | 558 | IO9 <= '0'; |
|
559 | 559 | IO10 <= '0'; |
|
560 | 560 | IO11 <= '0'; |
|
561 | 561 | WHEN "11" => |
|
562 | 562 | IO0 <= '0'; |
|
563 | 563 | IO1 <= '0'; |
|
564 | 564 | IO2 <= '0'; |
|
565 | 565 | IO3 <= '0'; |
|
566 | 566 | IO4 <= '0'; |
|
567 | 567 | IO5 <= '0'; |
|
568 | 568 | IO6 <= '0'; |
|
569 | 569 | IO7 <= '0'; |
|
570 | 570 | IO8 <= '0'; |
|
571 | 571 | IO9 <= '0'; |
|
572 | 572 | IO10 <= '0'; |
|
573 | 573 | IO11 <= '0'; |
|
574 | 574 | WHEN OTHERS => NULL; |
|
575 | 575 | END CASE; |
|
576 | 576 | |
|
577 | 577 | END IF; |
|
578 | 578 | END PROCESS; |
|
579 | 579 | |
|
580 | END beh; No newline at end of file | |
|
580 | END beh; |
@@ -1,121 +1,122 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | library IEEE; | |
|
23 |
|
|
|
24 |
|
|
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.std_logic_1164.ALL; | |
|
24 | USE IEEE.numeric_std.ALL; | |
|
25 | 25 | |
|
26 |
|
|
|
27 | generic( | |
|
28 |
Data_sz |
|
|
29 |
NbData : |
|
|
26 | ENTITY Driver_FFT IS | |
|
27 | GENERIC( | |
|
28 | Data_sz : INTEGER RANGE 1 TO 32 := 16; | |
|
29 | NbData : INTEGER RANGE 1 TO 512 := 256 | |
|
30 | 30 | ); |
|
31 | port( | |
|
32 | clk : in std_logic; | |
|
33 | rstn : in std_logic; | |
|
34 | Load : in std_logic; | |
|
35 | Empty : in std_logic_vector(4 downto 0); | |
|
36 | DATA : in std_logic_vector((5*Data_sz)-1 downto 0); | |
|
37 | Valid : out std_logic; | |
|
38 | Read : out std_logic_vector(4 downto 0); | |
|
39 | Data_re : out std_logic_vector(Data_sz-1 downto 0); | |
|
40 | Data_im : out std_logic_vector(Data_sz-1 downto 0) | |
|
41 | ); | |
|
42 | end entity; | |
|
31 | PORT( | |
|
32 | clk : IN STD_LOGIC; | |
|
33 | rstn : IN STD_LOGIC; | |
|
34 | Load : IN STD_LOGIC; -- (CoreFFT) FFT_Load | |
|
35 | -- Load | |
|
36 | Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- FifoIN_Empty | |
|
37 | DATA : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); -- FifoIN_Data | |
|
38 | Valid : OUT STD_LOGIC; --(CoreFFT) Drive_write | |
|
39 | Read : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Read | |
|
40 | Data_re : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --(CoreFFT) Drive_DataRE | |
|
41 | Data_im : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0) --(CoreFFT) Drive_DataIM | |
|
42 | ); | |
|
43 | END ENTITY; | |
|
43 | 44 | |
|
44 | 45 | |
|
45 | architecture ar_Driver of Driver_FFT is | |
|
46 | ARCHITECTURE ar_Driver OF Driver_FFT IS | |
|
46 | 47 | |
|
47 |
|
|
|
48 |
|
|
|
48 | TYPE etat IS (eX, e0, e1, e2); | |
|
49 | SIGNAL ect : etat; | |
|
49 | 50 | |
|
50 | signal DataCount : integer range 0 to 255 := 0; | |
|
51 | signal FifoCpt : integer range 0 to 4 := 0; | |
|
51 | SIGNAL DataCount : INTEGER RANGE 0 TO 255 := 0; | |
|
52 | SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0; | |
|
52 | 53 | |
|
53 | signal sLoad : std_logic; | |
|
54 | SIGNAL sLoad : STD_LOGIC; | |
|
54 | 55 | |
|
55 | begin | |
|
56 | BEGIN | |
|
56 | 57 | |
|
57 | process(clk,rstn) | |
|
58 | begin | |
|
59 |
|
|
|
60 |
|
|
|
61 |
|
|
|
62 |
|
|
|
63 |
|
|
|
64 |
|
|
|
65 |
|
|
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
|
69 | elsif(clk'event and clk='1')then | |
|
70 |
|
|
|
58 | PROCESS(clk, rstn) | |
|
59 | BEGIN | |
|
60 | IF(rstn = '0')then | |
|
61 | ect <= e0; | |
|
62 | Read <= (OTHERS => '1'); | |
|
63 | Valid <= '0'; | |
|
64 | Data_re <= (OTHERS => '0'); | |
|
65 | Data_im <= (OTHERS => '0'); | |
|
66 | DataCount <= 0; | |
|
67 | FifoCpt <= 0; | |
|
68 | sLoad <= '0'; | |
|
69 | ||
|
70 | ELSIF(clk'EVENT AND clk = '1')then | |
|
71 | sLoad <= Load; | |
|
71 | 72 | |
|
72 |
|
|
|
73 |
|
|
|
74 |
|
|
|
75 | else | |
|
76 |
|
|
|
77 | end if; | |
|
78 | end if; | |
|
79 | ||
|
80 | case ect is | |
|
73 | IF(sLoad = '1' and Load = '0')THEN | |
|
74 | IF(FifoCpt = 4)THEN | |
|
75 | FifoCpt <= 0; | |
|
76 | ELSE | |
|
77 | FifoCpt <= FifoCpt + 1; | |
|
78 | END IF; | |
|
79 | END IF; | |
|
80 | ||
|
81 | CASE ect IS | |
|
81 | 82 | |
|
82 |
|
|
|
83 |
|
|
|
84 |
|
|
|
85 |
|
|
|
86 | end if; | |
|
83 | WHEN e0 => | |
|
84 | IF(Load = '1' and Empty(FifoCpt) = '0')THEN | |
|
85 | Read(FifoCpt) <= '0'; | |
|
86 | ect <= e1; | |
|
87 | END IF; | |
|
87 | 88 | |
|
88 |
|
|
|
89 |
|
|
|
90 |
|
|
|
91 |
|
|
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
|
96 |
|
|
|
97 |
|
|
|
98 |
|
|
|
99 |
|
|
|
100 | else | |
|
101 |
|
|
|
102 |
|
|
|
103 |
|
|
|
104 |
|
|
|
105 | else | |
|
106 |
|
|
|
107 | end if; | |
|
108 | end if; | |
|
89 | WHEN e1 => | |
|
90 | Valid <= '0'; | |
|
91 | Read(FifoCpt) <= '1'; | |
|
92 | ect <= e2; | |
|
93 | ||
|
94 | WHEN e2 => | |
|
95 | Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)); | |
|
96 | Data_im <= (OTHERS => '0'); | |
|
97 | Valid <= '1'; | |
|
98 | IF(DataCount = NbData-1)THEN | |
|
99 | DataCount <= 0; | |
|
100 | ect <= eX; | |
|
101 | ELSE | |
|
102 | DataCount <= DataCount + 1; | |
|
103 | IF(Load = '1' and Empty(FifoCpt) = '0')THEN | |
|
104 | Read(FifoCpt) <= '0'; | |
|
105 | ect <= e1; | |
|
106 | ELSE | |
|
107 | ect <= eX; | |
|
108 | END IF; | |
|
109 | END IF; | |
|
109 | 110 | |
|
110 |
|
|
|
111 |
|
|
|
112 |
|
|
|
111 | WHEN eX => | |
|
112 | Valid <= '0'; | |
|
113 | ect <= e0; | |
|
113 | 114 | |
|
114 | when others => | |
|
115 | null; | |
|
115 | WHEN OTHERS => | |
|
116 | NULL; | |
|
116 | 117 | |
|
117 | end case; | |
|
118 | end if; | |
|
119 | end process; | |
|
118 | END CASE; | |
|
119 | END IF; | |
|
120 | END PROCESS; | |
|
120 | 121 | |
|
121 | end architecture; No newline at end of file | |
|
122 | END ARCHITECTURE; |
@@ -1,100 +1,105 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library IEEE; |
|
23 | 23 | use IEEE.std_logic_1164.all; |
|
24 | 24 | use IEEE.numeric_std.all; |
|
25 | 25 | library lpp; |
|
26 | 26 | use lpp.lpp_fft.all; |
|
27 | 27 | use lpp.fft_components.all; |
|
28 | 28 | |
|
29 | 29 | -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau" |
|
30 | 30 | |
|
31 | 31 | entity FFT is |
|
32 | 32 | generic( |
|
33 | 33 | Data_sz : integer := 16; |
|
34 | 34 | NbData : integer := 256); |
|
35 | 35 | port( |
|
36 | 36 | clkm : in std_logic; |
|
37 | 37 | rstn : in std_logic; |
|
38 | 38 | FifoIN_Empty : in std_logic_vector(4 downto 0); |
|
39 | 39 | FifoIN_Data : in std_logic_vector(79 downto 0); |
|
40 | 40 | FifoOUT_Full : in std_logic_vector(4 downto 0); |
|
41 | 41 | Load : out std_logic; |
|
42 | 42 | Read : out std_logic_vector(4 downto 0); |
|
43 | 43 | Write : out std_logic_vector(4 downto 0); |
|
44 | 44 | ReUse : out std_logic_vector(4 downto 0); |
|
45 | 45 | Data : out std_logic_vector(79 downto 0) |
|
46 | 46 | ); |
|
47 | 47 | end entity; |
|
48 | 48 | |
|
49 | 49 | |
|
50 | 50 | architecture ar_FFT of FFT is |
|
51 | 51 | |
|
52 | 52 | signal Drive_Write : std_logic; |
|
53 | 53 | signal Drive_DataRE : std_logic_vector(15 downto 0); |
|
54 | 54 | signal Drive_DataIM : std_logic_vector(15 downto 0); |
|
55 | 55 | |
|
56 | 56 | signal Start : std_logic; |
|
57 | 57 | signal FFT_Load : std_logic; |
|
58 | 58 | signal FFT_Ready : std_logic; |
|
59 | 59 | signal FFT_Valid : std_logic; |
|
60 | 60 | signal FFT_DataRE : std_logic_vector(15 downto 0); |
|
61 | 61 | signal FFT_DataIM : std_logic_vector(15 downto 0); |
|
62 | 62 | |
|
63 | 63 | signal Link_Read : std_logic; |
|
64 | 64 | |
|
65 | 65 | begin |
|
66 | 66 | |
|
67 | 67 | Start <= '0'; |
|
68 | 68 | Load <= FFT_Load; |
|
69 | 69 | |
|
70 | 70 | DRIVE : Driver_FFT |
|
71 | 71 | generic map(Data_sz,NbData) |
|
72 | 72 | port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM); |
|
73 | 73 | |
|
74 | 74 | FFT0 : CoreFFT |
|
75 | 75 | generic map( |
|
76 | 76 | LOGPTS => gLOGPTS, |
|
77 | 77 | LOGLOGPTS => gLOGLOGPTS, |
|
78 | 78 | WSIZE => gWSIZE, |
|
79 | 79 | TWIDTH => gTWIDTH, |
|
80 | 80 | DWIDTH => gDWIDTH, |
|
81 | 81 | TDWIDTH => gTDWIDTH, |
|
82 | 82 | RND_MODE => gRND_MODE, |
|
83 | 83 | SCALE_MODE => gSCALE_MODE, |
|
84 | 84 | PTS => gPTS, |
|
85 | 85 | HALFPTS => gHALFPTS, |
|
86 | 86 | inBuf_RWDLY => gInBuf_RWDLY) |
|
87 | 87 | port map(clkm,start,rstn, |
|
88 |
Drive_Write, |
|
|
89 | Drive_DataIM,Drive_DataRE, | |
|
90 | FFT_Load,open, | |
|
91 | FFT_DataIM,FFT_DataRE, | |
|
92 |
FFT_ |
|
|
88 | Drive_Write, -- ifiD_valid | |
|
89 | Link_Read, -- ifiRead_y | |
|
90 | Drive_DataIM, -- ifiD_im | |
|
91 | Drive_DataRE, -- ifiD_re | |
|
92 | FFT_Load, -- ifoLoad | |
|
93 | open, -- ifoPong | |
|
94 | FFT_DataIM, -- ifoY_im | |
|
95 | FFT_DataRE, -- ifoY_re | |
|
96 | FFT_Valid, -- ifiY_valid | |
|
97 | FFT_Ready); -- ifiY_rdy | |
|
93 | 98 | |
|
94 | 99 | |
|
95 | 100 | LINK : Linker_FFT |
|
96 | 101 | generic map(Data_sz,NbData) |
|
97 | 102 | port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data); |
|
98 | 103 | |
|
99 | 104 | |
|
100 | 105 | end architecture; |
@@ -1,112 +1,113 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | library IEEE; | |
|
23 |
|
|
|
24 |
|
|
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.std_logic_1164.ALL; | |
|
24 | USE IEEE.numeric_std.ALL; | |
|
25 | 25 | |
|
26 |
|
|
|
27 | generic( | |
|
28 |
Data_sz |
|
|
29 |
NbData : |
|
|
26 | ENTITY Linker_FFT IS | |
|
27 | GENERIC( | |
|
28 | Data_sz : INTEGER RANGE 1 TO 32 := 16; | |
|
29 | NbData : INTEGER RANGE 1 TO 512 := 256 | |
|
30 | 30 | ); |
|
31 | port( | |
|
32 | clk : in std_logic; | |
|
33 | rstn : in std_logic; | |
|
34 | Ready : in std_logic; | |
|
35 | Valid : in std_logic; | |
|
36 | Full : in std_logic_vector(4 downto 0); | |
|
37 | Data_re : in std_logic_vector(Data_sz-1 downto 0); | |
|
38 | Data_im : in std_logic_vector(Data_sz-1 downto 0); | |
|
39 | Read : out std_logic; | |
|
40 | Write : out std_logic_vector(4 downto 0); | |
|
41 | ReUse : out std_logic_vector(4 downto 0); | |
|
42 | DATA : out std_logic_vector((5*Data_sz)-1 downto 0) | |
|
43 | ); | |
|
44 | end entity; | |
|
31 | PORT( | |
|
32 | clk : IN STD_LOGIC; | |
|
33 | rstn : IN STD_LOGIC; | |
|
34 | Ready : IN STD_LOGIC; -- | |
|
35 | Valid : IN STD_LOGIC; -- | |
|
36 | Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- | |
|
37 | Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -- | |
|
38 | Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); -- | |
|
39 | ||
|
40 | Read : OUT STD_LOGIC; -- Link_Read | |
|
41 | Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- | |
|
42 | ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
43 | DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0) | |
|
44 | ); | |
|
45 | END ENTITY; | |
|
45 | 46 | |
|
46 | 47 | |
|
47 | architecture ar_Linker of Linker_FFT is | |
|
48 | ARCHITECTURE ar_Linker OF Linker_FFT IS | |
|
48 | 49 | |
|
49 |
|
|
|
50 |
|
|
|
50 | TYPE etat IS (eX, e0, e1, e2); | |
|
51 | SIGNAL ect : etat; | |
|
51 | 52 | |
|
52 | signal DataTmp : std_logic_vector(Data_sz-1 downto 0); | |
|
53 | SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); | |
|
53 | 54 | |
|
54 | signal sRead : std_logic; | |
|
55 | signal sReady : std_logic; | |
|
55 | SIGNAL sRead : STD_LOGIC; | |
|
56 | SIGNAL sReady : STD_LOGIC; | |
|
56 | 57 | |
|
57 | signal FifoCpt : integer range 0 to 4 := 0; | |
|
58 | SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0; | |
|
58 | 59 | |
|
59 | begin | |
|
60 | BEGIN | |
|
60 | 61 | |
|
61 | process(clk,rstn) | |
|
62 | begin | |
|
63 |
|
|
|
64 |
|
|
|
65 |
|
|
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
|
69 |
|
|
|
70 |
|
|
|
71 | elsif(clk'event and clk='1')then | |
|
72 |
|
|
|
62 | PROCESS(clk, rstn) | |
|
63 | BEGIN | |
|
64 | IF(rstn = '0')then | |
|
65 | ect <= e0; | |
|
66 | sRead <= '0'; | |
|
67 | sReady <= '0'; | |
|
68 | Write <= (OTHERS => '1'); | |
|
69 | Reuse <= (OTHERS => '0'); | |
|
70 | FifoCpt <= 0; | |
|
71 | ||
|
72 | ELSIF(clk'EVENT AND clk = '1')then | |
|
73 | sReady <= Ready; | |
|
73 | 74 | |
|
74 |
|
|
|
75 |
|
|
|
76 |
|
|
|
77 | else | |
|
78 |
|
|
|
79 | end if; | |
|
80 |
|
|
|
81 |
|
|
|
82 | else | |
|
83 |
|
|
|
84 | end if; | |
|
75 | IF(sReady = '1' and Ready = '0')THEN | |
|
76 | IF(FifoCpt = 4)THEN | |
|
77 | FifoCpt <= 0; | |
|
78 | ELSE | |
|
79 | FifoCpt <= FifoCpt + 1; | |
|
80 | END IF; | |
|
81 | ELSIF(Ready = '1')then | |
|
82 | sRead <= NOT sRead; | |
|
83 | ELSE | |
|
84 | sRead <= '0'; | |
|
85 | END IF; | |
|
85 | 86 | |
|
86 | case ect is | |
|
87 | CASE ect IS | |
|
87 | 88 | |
|
88 |
|
|
|
89 |
|
|
|
90 |
|
|
|
91 | DataTmp <= Data_im; | |
|
92 |
|
|
|
93 | Write(FifoCpt) <= '0'; | |
|
94 | ect <= e1; | |
|
95 |
|
|
|
96 |
|
|
|
97 | end if; | |
|
89 | WHEN e0 => | |
|
90 | Write(FifoCpt) <= '1'; | |
|
91 | IF(Valid = '1' and Full(FifoCpt) = '0')THEN | |
|
92 | DataTmp <= Data_im; | |
|
93 | DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re; | |
|
94 | Write(FifoCpt) <= '0'; | |
|
95 | ect <= e1; | |
|
96 | ELSIF(Full(FifoCpt) = '1')then | |
|
97 | ReUse(FifoCpt) <= '1'; | |
|
98 | END IF; | |
|
98 | 99 | |
|
99 |
|
|
|
100 |
|
|
|
101 | ect <= e0; | |
|
102 | ||
|
103 | when others => | |
|
104 | null; | |
|
100 | WHEN e1 => | |
|
101 | DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp; | |
|
102 | ect <= e0; | |
|
103 | ||
|
104 | WHEN OTHERS => | |
|
105 | NULL; | |
|
105 | 106 | |
|
106 | end case; | |
|
107 | end if; | |
|
108 | end process; | |
|
107 | END CASE; | |
|
108 | END IF; | |
|
109 | END PROCESS; | |
|
109 | 110 | |
|
110 | Read <= sRead; | |
|
111 | Read <= sRead; | |
|
111 | 112 | |
|
112 | end architecture; No newline at end of file | |
|
113 | END ARCHITECTURE; |
@@ -1,170 +1,173 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 |
-- |
|
|
20 |
-- |
|
|
19 | -- Author : Martin Morlot | |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | -- Update : Jean-christophe Pellion | |
|
23 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | 24 | ------------------------------------------------------------------------------ |
|
22 | library IEEE; | |
|
23 |
|
|
|
24 |
|
|
|
25 | LIBRARY IEEE; | |
|
26 | USE IEEE.std_logic_1164.ALL; | |
|
27 | USE IEEE.numeric_std.ALL; | |
|
25 | 28 | |
|
26 | entity DEMUX is | |
|
27 | generic( | |
|
28 |
Data_sz |
|
|
29 | port( | |
|
30 | clk : in std_logic; | |
|
31 | rstn : in std_logic; | |
|
29 | ENTITY DEMUX IS | |
|
30 | GENERIC( | |
|
31 | Data_sz : INTEGER RANGE 1 TO 32 := 16); | |
|
32 | PORT( | |
|
33 | clk : IN STD_LOGIC; | |
|
34 | rstn : IN STD_LOGIC; | |
|
32 | 35 | |
|
33 | Read : in std_logic_vector(4 downto 0); | |
|
34 | Load : in std_logic; | |
|
36 | Read : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
37 | Load : IN STD_LOGIC; | |
|
35 | 38 | |
|
36 | EmptyF0 : in std_logic_vector(4 downto 0); | |
|
37 | EmptyF1 : in std_logic_vector(4 downto 0); | |
|
38 | EmptyF2 : in std_logic_vector(4 downto 0); | |
|
39 | EmptyF0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
40 | EmptyF1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
41 | EmptyF2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
39 | 42 | |
|
40 | DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
|
41 | DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
|
42 | DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0); | |
|
43 | DataF0 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); | |
|
44 | DataF1 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); | |
|
45 | DataF2 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); | |
|
43 | 46 | |
|
44 | WorkFreq : out std_logic_vector(1 downto 0); | |
|
45 | Read_DEMUX : out std_logic_vector(14 downto 0); | |
|
46 | Empty : out std_logic_vector(4 downto 0); | |
|
47 | Data : out std_logic_vector((5*Data_sz)-1 downto 0) | |
|
48 | ); | |
|
49 | end entity; | |
|
47 | WorkFreq : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
48 | Read_DEMUX : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); | |
|
49 | Empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
50 | Data : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0) | |
|
51 | ); | |
|
52 | END ENTITY; | |
|
50 | 53 | |
|
51 | 54 | |
|
52 | architecture ar_DEMUX of DEMUX is | |
|
55 | ARCHITECTURE ar_DEMUX OF DEMUX IS | |
|
53 | 56 | |
|
54 |
|
|
|
55 |
|
|
|
57 | TYPE etat IS (eX, e0, e1, e2, e3); | |
|
58 | SIGNAL ect : etat; | |
|
56 | 59 | |
|
57 | 60 | |
|
58 | signal load_reg : std_logic; | |
|
59 | constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1'); | |
|
61 | SIGNAL load_reg : STD_LOGIC; | |
|
62 | CONSTANT Dummy_Read : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); | |
|
60 | 63 | |
|
61 | signal Countf0 : integer; | |
|
62 | signal Countf1 : integer; | |
|
63 | signal i : integer; | |
|
64 | SIGNAL Countf0 : INTEGER; | |
|
65 | SIGNAL Countf1 : INTEGER; | |
|
66 | SIGNAL i : INTEGER; | |
|
64 | 67 | |
|
65 | begin | |
|
66 | process(clk,rstn) | |
|
67 | begin | |
|
68 |
|
|
|
69 |
|
|
|
70 |
|
|
|
71 |
|
|
|
72 |
|
|
|
73 |
|
|
|
68 | BEGIN | |
|
69 | PROCESS(clk, rstn) | |
|
70 | BEGIN | |
|
71 | IF(rstn = '0')then | |
|
72 | ect <= e0; | |
|
73 | load_reg <= '0'; | |
|
74 | Countf0 <= 0; | |
|
75 | Countf1 <= 0; | |
|
76 | i <= 0; | |
|
74 | 77 | |
|
75 | elsif(clk'event and clk='1')then | |
|
76 |
|
|
|
78 | ELSIF(clk'EVENT AND clk = '1')then | |
|
79 | load_reg <= Load; | |
|
77 | 80 | |
|
78 | case ect is | |
|
81 | CASE ect IS | |
|
79 | 82 | |
|
80 |
|
|
|
81 |
|
|
|
82 |
|
|
|
83 |
|
|
|
84 |
|
|
|
85 | else | |
|
86 |
|
|
|
87 |
|
|
|
88 | end if; | |
|
89 | end if; | |
|
83 | WHEN e0 => | |
|
84 | IF(load_reg = '1' AND Load = '0')THEN | |
|
85 | IF(Countf0 = 24)THEN | |
|
86 | Countf0 <= 0; | |
|
87 | ect <= e1; | |
|
88 | ELSE | |
|
89 | Countf0 <= Countf0 + 1; | |
|
90 | ect <= e0; | |
|
91 | END IF; | |
|
92 | END IF; | |
|
90 | 93 | |
|
91 |
|
|
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
|
96 | else | |
|
97 |
|
|
|
98 | if(i=4)then | |
|
99 |
|
|
|
100 |
|
|
|
101 | else | |
|
102 |
|
|
|
103 |
|
|
|
104 | end if; | |
|
105 | end if; | |
|
106 | end if; | |
|
94 | WHEN e1 => | |
|
95 | IF(load_reg = '1' AND Load = '0')THEN | |
|
96 | IF(Countf1 = 74)THEN | |
|
97 | Countf1 <= 0; | |
|
98 | ect <= e2; | |
|
99 | ELSE | |
|
100 | Countf1 <= Countf1 + 1; | |
|
101 | IF(i = 4)THEN | |
|
102 | i <= 0; | |
|
103 | ect <= e0; | |
|
104 | ELSE | |
|
105 | i <= i+1; | |
|
106 | ect <= e1; | |
|
107 | END IF; | |
|
108 | END IF; | |
|
109 | END IF; | |
|
107 | 110 | |
|
108 |
|
|
|
109 |
|
|
|
110 | if(i=4)then | |
|
111 |
|
|
|
112 |
|
|
|
113 | else | |
|
114 |
|
|
|
115 |
|
|
|
116 | end if; | |
|
117 | end if; | |
|
118 |
|
|
|
119 | when others => | |
|
120 | null; | |
|
111 | WHEN e2 => | |
|
112 | IF(load_reg = '1' AND Load = '0')THEN | |
|
113 | IF(i = 4)THEN | |
|
114 | i <= 0; | |
|
115 | ect <= e0; | |
|
116 | ELSE | |
|
117 | i <= i+1; | |
|
118 | ect <= e2; | |
|
119 | END IF; | |
|
120 | END IF; | |
|
121 | ||
|
122 | WHEN OTHERS => | |
|
123 | NULL; | |
|
121 | 124 | |
|
122 | end case; | |
|
123 | end if; | |
|
124 | end process; | |
|
125 | END CASE; | |
|
126 | END IF; | |
|
127 | END PROCESS; | |
|
125 | 128 | |
|
126 | with ect select | |
|
127 |
Empty |
|
|
128 | EmptyF1 when e1, | |
|
129 | EmptyF2 when e2, | |
|
130 | (others => '1') when others; | |
|
129 | WITH ect SELECT | |
|
130 | Empty <= EmptyF0 WHEN e0, | |
|
131 | EmptyF1 WHEN e1, | |
|
132 | EmptyF2 WHEN e2, | |
|
133 | (OTHERS => '1') WHEN OTHERS; | |
|
131 | 134 | |
|
132 | with ect select | |
|
133 |
Data |
|
|
134 | DataF1 when e1, | |
|
135 | DataF2 when e2, | |
|
136 | (others => '0') when others; | |
|
135 | WITH ect SELECT | |
|
136 | Data <= DataF0 WHEN e0, | |
|
137 | DataF1 WHEN e1, | |
|
138 | DataF2 WHEN e2, | |
|
139 | (OTHERS => '0') WHEN OTHERS; | |
|
137 | 140 | |
|
138 | with ect select | |
|
139 |
Read_DEMUX |
|
|
140 |
|
|
|
141 |
|
|
|
142 | (others => '1') when others; | |
|
141 | WITH ect SELECT | |
|
142 | Read_DEMUX <= Dummy_Read & Dummy_Read & Read WHEN e0, | |
|
143 | Dummy_Read & Read & Dummy_Read WHEN e1, | |
|
144 | Read & Dummy_Read & Dummy_Read WHEN e2, | |
|
145 | (OTHERS => '1') WHEN OTHERS; | |
|
143 | 146 | |
|
144 | with ect select | |
|
145 |
WorkFreq |
|
|
146 | "10" when e1, | |
|
147 | "11" when e2, | |
|
148 | "00" when others; | |
|
147 | WITH ect SELECT | |
|
148 | WorkFreq <= "01" WHEN e0, | |
|
149 | "10" WHEN e1, | |
|
150 | "11" WHEN e2, | |
|
151 | "00" WHEN OTHERS; | |
|
149 | 152 | |
|
150 | end architecture; | |
|
153 | END ARCHITECTURE; | |
|
151 | 154 | |
|
152 | 155 | |
|
153 | 156 | |
|
154 | 157 | |
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@@ -1,85 +1,85 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library IEEE; |
|
23 | 23 | use IEEE.std_logic_1164.all; |
|
24 | 24 | use IEEE.numeric_std.all; |
|
25 | 25 | library lpp; |
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26 | 26 | use lpp.lpp_matrix.all; |
|
27 | 27 | |
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28 | 28 | entity MatriceSpectrale is |
|
29 | 29 | generic( |
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30 | 30 | Input_SZ : integer := 16; |
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31 | 31 | Result_SZ : integer := 32); |
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32 | 32 | port( |
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33 | 33 | clkm : in std_logic; |
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34 | 34 | rstn : in std_logic; |
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35 | 35 | |
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
|
37 | SetReUse : in std_logic_vector(4 downto 0); | |
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); -- | |
|
37 | SetReUse : in std_logic_vector(4 downto 0); -- | |
|
38 | 38 | Valid : in std_logic; |
|
39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
|
39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); -- | |
|
40 | 40 | ACK : in std_logic; |
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41 | 41 | SM_Write : out std_logic; |
|
42 | 42 | FlagError : out std_logic; |
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43 | 43 | Statu : out std_logic_vector(3 downto 0); |
|
44 | 44 | Write : out std_logic_vector(1 downto 0); |
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45 | Read : out std_logic_vector(4 downto 0); | |
|
46 | ReUse : out std_logic_vector(4 downto 0); | |
|
45 | Read : out std_logic_vector(4 downto 0); -- | |
|
46 | ReUse : out std_logic_vector(4 downto 0); -- | |
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47 | 47 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) |
|
48 | 48 | ); |
|
49 | 49 | end entity; |
|
50 | 50 | |
|
51 | 51 | |
|
52 | 52 | architecture ar_MatriceSpectrale of MatriceSpectrale is |
|
53 | 53 | |
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54 | 54 | signal Matrix_Write : std_logic; |
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55 | 55 | signal Matrix_Read : std_logic_vector(1 downto 0); |
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56 | 56 | signal Matrix_Result : std_logic_vector(31 downto 0); |
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57 | 57 | |
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58 | 58 | signal TopSM_Start : std_logic; |
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59 | 59 | signal TopSM_Statu : std_logic_vector(3 downto 0); |
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60 | 60 | signal TopSM_Data1 : std_logic_vector(15 downto 0); |
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61 | 61 | signal TopSM_Data2 : std_logic_vector(15 downto 0); |
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62 | 62 | |
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63 | 63 | begin |
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64 | 64 | |
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65 | 65 | CTRL0 : ReUse_CTRLR |
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66 | 66 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); |
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67 | 67 | |
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68 | 68 | |
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69 | 69 | TopSM : TopSpecMatrix |
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70 | 70 | generic map (Input_SZ) |
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71 | 71 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); |
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72 | 72 | |
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73 | 73 | SM : SpectralMatrix |
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74 | 74 | generic map (Input_SZ,Result_SZ) |
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75 | 75 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); |
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76 | 76 | |
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77 | 77 | DISP : Dispatch |
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78 | 78 | generic map(Result_SZ) |
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79 | 79 | port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError); |
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80 | 80 | |
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81 | 81 | Statu <= TopSM_Statu; |
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82 | 82 | SM_Write <= Matrix_Write; |
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83 | 83 | |
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84 | 84 | end architecture; |
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85 | 85 |
@@ -1,394 +1,394 | |||
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1 | 1 | LIBRARY ieee; |
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2 | 2 | USE ieee.std_logic_1164.ALL; |
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3 | 3 | |
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4 | 4 | LIBRARY lpp; |
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5 | 5 | USE lpp.lpp_amba.ALL; |
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6 | 6 | USE lpp.lpp_memory.ALL; |
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7 | 7 | --USE lpp.lpp_uart.ALL; |
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8 | 8 | USE lpp.lpp_matrix.ALL; |
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9 | 9 | --USE lpp.lpp_delay.ALL; |
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10 | 10 | USE lpp.lpp_fft.ALL; |
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11 | 11 | USE lpp.fft_components.ALL; |
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12 | 12 | USE lpp.lpp_ad_conv.ALL; |
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13 | 13 | USE lpp.iir_filter.ALL; |
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14 | 14 | USE lpp.general_purpose.ALL; |
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15 | 15 | USE lpp.Filtercfg.ALL; |
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16 | 16 | USE lpp.lpp_demux.ALL; |
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17 | 17 | USE lpp.lpp_top_lfr_pkg.ALL; |
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18 | 18 | USE lpp.lpp_dma_pkg.ALL; |
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19 | 19 | USE lpp.lpp_Header.ALL; |
|
20 | 20 | USE lpp.lpp_lfr_pkg.ALL; |
|
21 | 21 | |
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22 | 22 | LIBRARY grlib; |
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23 | 23 | USE grlib.amba.ALL; |
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24 | 24 | USE grlib.stdlib.ALL; |
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25 | 25 | USE grlib.devices.ALL; |
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26 | 26 | USE GRLIB.DMA2AHB_Package.ALL; |
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27 | 27 | |
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28 | 28 | |
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29 | 29 | ENTITY lpp_lfr_ms IS |
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30 | 30 | GENERIC ( |
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31 | 31 | Mem_use : INTEGER := use_RAM |
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32 | 32 | ); |
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33 | 33 | PORT ( |
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34 | 34 | clk : IN STD_LOGIC; |
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35 | 35 | rstn : IN STD_LOGIC; |
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36 | 36 | |
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37 | 37 | --------------------------------------------------------------------------- |
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38 | 38 | -- DATA INPUT |
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39 | 39 | --------------------------------------------------------------------------- |
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40 | 40 | -- TIME |
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41 | 41 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
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42 | 42 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
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43 | 43 | -- |
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44 | 44 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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45 | 45 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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46 | 46 | -- |
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47 | 47 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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48 | 48 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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49 | 49 | -- |
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50 | 50 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
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51 | 51 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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52 | 52 | |
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53 | 53 | --------------------------------------------------------------------------- |
|
54 | 54 | -- DMA |
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55 | 55 | --------------------------------------------------------------------------- |
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56 | 56 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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57 | 57 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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58 | 58 | dma_valid : OUT STD_LOGIC; |
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59 | 59 | dma_valid_burst : OUT STD_LOGIC; |
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60 | 60 | dma_ren : IN STD_LOGIC; |
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61 | 61 | dma_done : IN STD_LOGIC; |
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62 | 62 | |
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63 | 63 | -- Reg out |
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64 | 64 | ready_matrix_f0_0 : OUT STD_LOGIC; |
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65 | 65 | ready_matrix_f0_1 : OUT STD_LOGIC; |
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66 | 66 | ready_matrix_f1 : OUT STD_LOGIC; |
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67 | 67 | ready_matrix_f2 : OUT STD_LOGIC; |
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68 | 68 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
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69 | 69 | error_bad_component_error : OUT STD_LOGIC; |
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70 | 70 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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71 | 71 | |
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72 | 72 | -- Reg In |
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73 | 73 | status_ready_matrix_f0_0 :IN STD_LOGIC; |
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74 | 74 | status_ready_matrix_f0_1 :IN STD_LOGIC; |
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75 | 75 | status_ready_matrix_f1 :IN STD_LOGIC; |
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76 | 76 | status_ready_matrix_f2 :IN STD_LOGIC; |
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77 | 77 | status_error_anticipating_empty_fifo :IN STD_LOGIC; |
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78 | 78 | status_error_bad_component_error :IN STD_LOGIC; |
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79 | 79 | |
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80 | 80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
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81 | 81 | config_active_interruption_onError : IN STD_LOGIC; |
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82 | 82 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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83 | 83 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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84 | 84 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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85 | 85 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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86 | 86 | |
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87 | 87 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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88 | 88 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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89 | 89 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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90 | 90 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
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91 | 91 | |
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92 | 92 | ); |
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93 | 93 | END; |
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94 | 94 | |
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95 | 95 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
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96 | 96 | ----------------------------------------------------------------------------- |
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97 | 97 | SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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98 | 98 | SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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99 | 99 | SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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100 | 100 | SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
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101 | 101 | SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
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102 | 102 | SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
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103 | 103 | |
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104 | 104 | ----------------------------------------------------------------------------- |
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105 | 105 | SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); |
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106 | 106 | SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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107 | 107 | SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
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108 | 108 | SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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109 | 109 | |
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110 | 110 | ----------------------------------------------------------------------------- |
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111 | 111 | SIGNAL FFT_Load : STD_LOGIC; |
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112 | 112 | SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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113 | 113 | SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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114 | 114 | SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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115 | 115 | SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
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116 | 116 | |
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117 | 117 | ----------------------------------------------------------------------------- |
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118 | 118 | SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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119 | 119 | SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); |
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120 | 120 | |
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121 | 121 | ----------------------------------------------------------------------------- |
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122 | 122 | SIGNAL SM_FlagError : STD_LOGIC; |
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123 | 123 | -- SIGNAL SM_Pong : STD_LOGIC; |
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124 | 124 | SIGNAL SM_Wen : STD_LOGIC; |
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125 | 125 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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126 | 126 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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127 | 127 | SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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128 | 128 | SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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129 | 129 | SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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130 | 130 | |
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131 | 131 | ----------------------------------------------------------------------------- |
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132 | 132 | SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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133 | 133 | SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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134 | 134 | SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); |
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135 | 135 | |
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136 | 136 | ----------------------------------------------------------------------------- |
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137 | 137 | SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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138 | 138 | SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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139 | 139 | SIGNAL Head_Empty : STD_LOGIC; |
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140 | 140 | SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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141 | 141 | SIGNAL Head_Valid : STD_LOGIC; |
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142 | 142 | SIGNAL Head_Val : STD_LOGIC; |
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143 | 143 | |
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144 | 144 | ----------------------------------------------------------------------------- |
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145 | 145 | SIGNAL DMA_Read : STD_LOGIC; |
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146 | 146 | SIGNAL DMA_ack : STD_LOGIC; |
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147 | 147 | |
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148 | 148 | ----------------------------------------------------------------------------- |
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149 | 149 | SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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150 | 150 | |
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151 | 151 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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152 | 152 | SIGNAL dma_valid_s : STD_LOGIC; |
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153 | 153 | SIGNAL dma_valid_burst_s : STD_LOGIC; |
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154 | 154 | |
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155 | 155 | BEGIN |
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156 | 156 | |
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157 | 157 | ----------------------------------------------------------------------------- |
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158 | 158 | Memf0: lppFIFOxN |
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159 | 159 | GENERIC MAP ( |
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160 | 160 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
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161 | 161 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') |
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162 | 162 | PORT MAP ( |
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163 | 163 | rstn => rstn, wclk => clk, rclk => clk, |
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164 | 164 | ReUse => (OTHERS => '0'), |
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165 | 165 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), |
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166 | 166 | wdata => sample_f0_wdata, rdata => FifoF0_Data, |
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167 | 167 | full => OPEN, empty => FifoF0_Empty); |
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168 | 168 | |
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169 | 169 | Memf1: lppFIFOxN |
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170 | 170 | GENERIC MAP ( |
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171 | 171 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
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172 | 172 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
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173 | 173 | PORT MAP ( |
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174 | 174 | rstn => rstn, wclk => clk, rclk => clk, |
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175 | 175 | ReUse => (OTHERS => '0'), |
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176 | 176 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), |
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177 | 177 | wdata => sample_f1_wdata, rdata => FifoF1_Data, |
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178 | 178 | full => OPEN, empty => FifoF1_Empty); |
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179 | 179 | |
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180 | 180 | |
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181 | 181 | Memf2: lppFIFOxN |
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182 | 182 | GENERIC MAP ( |
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183 | 183 | tech => 0, Mem_use => Mem_use, Data_sz => 16, |
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184 | 184 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
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185 | 185 | PORT MAP ( |
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186 | 186 | rstn => rstn, wclk => clk, rclk => clk, |
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187 | 187 | ReUse => (OTHERS => '0'), |
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188 | 188 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), |
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189 | 189 | wdata => sample_f3_wdata, rdata => FifoF3_Data, |
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190 | 190 | full => OPEN, empty => FifoF3_Empty); |
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191 | 191 | ----------------------------------------------------------------------------- |
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192 | 192 | |
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193 | 193 | |
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194 | 194 | ----------------------------------------------------------------------------- |
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195 | 195 | DMUX0 : DEMUX |
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196 | 196 | GENERIC MAP ( |
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197 | 197 | Data_sz => 16) |
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198 | 198 | PORT MAP ( |
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199 | 199 | clk => clk, |
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200 | 200 | rstn => rstn, |
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201 | 201 | Read => FFT_Read, |
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202 | 202 | Load => FFT_Load, |
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203 | 203 | EmptyF0 => FifoF0_Empty, |
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204 | 204 | EmptyF1 => FifoF1_Empty, |
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205 | 205 | EmptyF2 => FifoF3_Empty, |
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206 | 206 | DataF0 => FifoF0_Data, |
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207 | 207 | DataF1 => FifoF1_Data, |
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208 | 208 | DataF2 => FifoF3_Data, |
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209 | 209 | WorkFreq => DMUX_WorkFreq, |
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210 | 210 | Read_DEMUX => DMUX_Read, |
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211 | 211 | Empty => DMUX_Empty, |
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212 | 212 | Data => DMUX_Data); |
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213 | 213 | ----------------------------------------------------------------------------- |
|
214 | 214 | |
|
215 | 215 | |
|
216 | 216 | ----------------------------------------------------------------------------- |
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217 | 217 | FFT0: FFT |
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218 | 218 | GENERIC MAP ( |
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219 | 219 | Data_sz => 16, |
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220 | 220 | NbData => 256) |
|
221 | 221 | PORT MAP ( |
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222 | 222 | clkm => clk, |
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223 | 223 | rstn => rstn, |
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224 | 224 | FifoIN_Empty => DMUX_Empty, |
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225 | 225 | FifoIN_Data => DMUX_Data, |
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226 | 226 | FifoOUT_Full => FifoINT_Full, |
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227 | 227 | Load => FFT_Load, |
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228 | 228 | Read => FFT_Read, |
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229 | 229 | Write => FFT_Write, |
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230 | 230 | ReUse => FFT_ReUse, |
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231 | 231 | Data => FFT_Data); |
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232 | 232 | ----------------------------------------------------------------------------- |
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233 | 233 | |
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234 | 234 | |
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235 | 235 | ----------------------------------------------------------------------------- |
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236 | 236 | MemInt : lppFIFOxN |
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237 | 237 | GENERIC MAP ( |
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238 | 238 | tech => 0, |
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239 | 239 | Mem_use => Mem_use, |
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240 | 240 | Data_sz => 16, |
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241 | 241 | Addr_sz => 8, |
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242 | 242 | FifoCnt => 5, |
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243 | 243 | Enable_ReUse => '1') |
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244 | 244 | PORT MAP ( |
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245 | 245 | rstn => rstn, |
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246 | 246 | wclk => clk, |
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247 | 247 | rclk => clk, |
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248 | 248 | ReUse => SM_ReUse, |
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249 | 249 | wen => FFT_Write, |
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250 | 250 | ren => SM_Read, |
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251 | 251 | wdata => FFT_Data, |
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252 | 252 | rdata => FifoINT_Data, |
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253 | 253 | full => FifoINT_Full, |
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254 | 254 | empty => OPEN); |
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255 | 255 | ----------------------------------------------------------------------------- |
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256 | 256 | |
|
257 | 257 | ----------------------------------------------------------------------------- |
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258 | 258 | SM0 : MatriceSpectrale |
|
259 | 259 | GENERIC MAP ( |
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260 | 260 | Input_SZ => 16, |
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261 | 261 | Result_SZ => 32) |
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262 | 262 | PORT MAP ( |
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263 | 263 | clkm => clk, |
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264 | 264 | rstn => rstn, |
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265 | FifoIN_Full => FifoINT_Full, | |
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266 | SetReUse => FFT_ReUse, | |
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267 | Valid => Head_Valid, | |
|
268 | Data_IN => FifoINT_Data, | |
|
269 | ACK => DMA_ack, | |
|
270 | SM_Write => SM_Wen, | |
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271 | FlagError => SM_FlagError, | |
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265 | FifoIN_Full => FifoINT_Full, -- | |
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266 | SetReUse => FFT_ReUse, -- | |
|
267 | Valid => Head_Valid, -- HeaderBuilder | |
|
268 | Data_IN => FifoINT_Data, -- | |
|
269 | ACK => DMA_ack, -- HeaderBuilder | |
|
270 | SM_Write => SM_Wen, -- HeaderBuilder | |
|
271 | FlagError => SM_FlagError, -- UNUSED | |
|
272 | 272 | -- Pong => SM_Pong, |
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273 | Statu => SM_Param, | |
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274 | Write => SM_Write, | |
|
275 | Read => SM_Read, | |
|
276 | ReUse => SM_ReUse, | |
|
277 | Data_OUT => SM_Data); | |
|
273 | Statu => SM_Param, -- HeaderBuilder | |
|
274 | Write => SM_Write, -- FIFO MemOut | |
|
275 | Read => SM_Read, -- | |
|
276 | ReUse => SM_ReUse, -- | |
|
277 | Data_OUT => SM_Data); -- FIFO MemOut | |
|
278 | 278 | ----------------------------------------------------------------------------- |
|
279 | 279 | |
|
280 | 280 | ----------------------------------------------------------------------------- |
|
281 | 281 | MemOut : lppFIFOxN |
|
282 | 282 | GENERIC MAP ( |
|
283 | 283 | tech => 0, |
|
284 | 284 | Mem_use => Mem_use, |
|
285 | 285 | Data_sz => 32, |
|
286 | 286 | Addr_sz => 8, |
|
287 | 287 | FifoCnt => 2, |
|
288 | 288 | Enable_ReUse => '0') |
|
289 | 289 | PORT MAP ( |
|
290 | 290 | rstn => rstn, |
|
291 | 291 | wclk => clk, |
|
292 | 292 | rclk => clk, |
|
293 | 293 | ReUse => (OTHERS => '0'), |
|
294 | 294 | wen => SM_Write, |
|
295 | 295 | ren => Head_Read, |
|
296 | 296 | wdata => SM_Data, |
|
297 | 297 | rdata => FifoOUT_Data, |
|
298 | 298 | full => FifoOUT_Full, |
|
299 | 299 | empty => FifoOUT_Empty); |
|
300 | 300 | ----------------------------------------------------------------------------- |
|
301 | 301 | |
|
302 | 302 | ----------------------------------------------------------------------------- |
|
303 | 303 | Head0 : HeaderBuilder |
|
304 | 304 | GENERIC MAP ( |
|
305 | 305 | Data_sz => 32) |
|
306 | 306 | PORT MAP ( |
|
307 | 307 | clkm => clk, |
|
308 | 308 | rstn => rstn, |
|
309 | 309 | -- pong => SM_Pong, |
|
310 | 310 | Statu => SM_Param, |
|
311 | 311 | Matrix_Type => DMUX_WorkFreq, |
|
312 | 312 | Matrix_Write => SM_Wen, |
|
313 | 313 | Valid => Head_Valid, |
|
314 | 314 | |
|
315 | 315 | dataIN => FifoOUT_Data, |
|
316 | 316 | emptyIN => FifoOUT_Empty, |
|
317 | 317 | RenOUT => Head_Read, |
|
318 | 318 | |
|
319 | 319 | dataOUT => Head_Data, |
|
320 | 320 | emptyOUT => Head_Empty, |
|
321 | 321 | RenIN => DMA_Read, |
|
322 | 322 | |
|
323 | 323 | header => Head_Header, |
|
324 | 324 | header_val => Head_Val, |
|
325 | 325 | header_ack => DMA_ack ); |
|
326 | 326 | ----------------------------------------------------------------------------- |
|
327 | 327 | data_time(31 DOWNTO 0) <= coarse_time; |
|
328 | 328 | data_time(47 DOWNTO 32) <= fine_time; |
|
329 | 329 | |
|
330 | 330 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
331 | 331 | PORT MAP ( |
|
332 | 332 | HCLK => clk, |
|
333 | 333 | HRESETn => rstn, |
|
334 | 334 | |
|
335 | 335 | data_time => data_time, |
|
336 | 336 | |
|
337 | 337 | fifo_data => Head_Data, |
|
338 | 338 | fifo_empty => Head_Empty, |
|
339 | 339 | fifo_ren => DMA_Read, |
|
340 | 340 | |
|
341 | 341 | header => Head_Header, |
|
342 | 342 | header_val => Head_Val, |
|
343 | 343 | header_ack => DMA_ack, |
|
344 | 344 | |
|
345 | 345 | dma_addr => dma_addr, |
|
346 | 346 | dma_data => dma_data, |
|
347 | 347 | dma_valid => dma_valid_s, |
|
348 | 348 | dma_valid_burst => dma_valid_burst_s, |
|
349 | 349 | dma_ren => dma_ren, |
|
350 | 350 | dma_done => dma_done, |
|
351 | 351 | |
|
352 | 352 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
353 | 353 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
354 | 354 | ready_matrix_f1 => ready_matrix_f1, |
|
355 | 355 | ready_matrix_f2 => ready_matrix_f2, |
|
356 | 356 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
357 | 357 | error_bad_component_error => error_bad_component_error, |
|
358 | 358 | debug_reg => debug_reg_s, |
|
359 | 359 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
360 | 360 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
361 | 361 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
362 | 362 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
363 | 363 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
364 | 364 | status_error_bad_component_error => status_error_bad_component_error, |
|
365 | 365 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
366 | 366 | config_active_interruption_onError => config_active_interruption_onError, |
|
367 | 367 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
368 | 368 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
369 | 369 | addr_matrix_f1 => addr_matrix_f1, |
|
370 | 370 | addr_matrix_f2 => addr_matrix_f2, |
|
371 | 371 | |
|
372 | 372 | matrix_time_f0_0 => matrix_time_f0_0, |
|
373 | 373 | matrix_time_f0_1 => matrix_time_f0_1, |
|
374 | 374 | matrix_time_f1 => matrix_time_f1, |
|
375 | 375 | matrix_time_f2 => matrix_time_f2 |
|
376 | 376 | ); |
|
377 | 377 | |
|
378 | 378 | dma_valid <= dma_valid_s; |
|
379 | 379 | dma_valid_burst <= dma_valid_burst_s; |
|
380 | 380 | |
|
381 | 381 | debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0); |
|
382 | 382 | debug_reg(10) <= Head_Empty; |
|
383 | 383 | debug_reg(11) <= DMA_Read; |
|
384 | 384 | debug_reg(12) <= Head_Val; |
|
385 | 385 | debug_reg(13) <= DMA_ack; |
|
386 | 386 | debug_reg(14) <= dma_ren; |
|
387 | 387 | debug_reg(15) <= dma_done; |
|
388 | 388 | debug_reg(16) <= dma_valid_s; |
|
389 | 389 | debug_reg(17) <= dma_valid_burst_s; |
|
390 | 390 | debug_reg(31 DOWNTO 18) <= (OTHERS => '0'); |
|
391 | 391 | |
|
392 | 392 | |
|
393 | 393 | |
|
394 | 394 | END Behavioral; |
@@ -1,431 +1,431 | |||
|
1 | 1 | |
|
2 | 2 | ------------------------------------------------------------------------------ |
|
3 | 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
4 | 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
5 | 5 | -- |
|
6 | 6 | -- This program is free software; you can redistribute it and/or modify |
|
7 | 7 | -- it under the terms of the GNU General Public License as published by |
|
8 | 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
9 | 9 | -- (at your option) any later version. |
|
10 | 10 | -- |
|
11 | 11 | -- This program is distributed in the hope that it will be useful, |
|
12 | 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 | 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
14 | 14 | -- GNU General Public License for more details. |
|
15 | 15 | -- |
|
16 | 16 | -- You should have received a copy of the GNU General Public License |
|
17 | 17 | -- along with this program; if not, write to the Free Software |
|
18 | 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 | 19 | ------------------------------------------------------------------------------- |
|
20 | 20 | -- Author : Jean-christophe Pellion |
|
21 | 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
22 | 22 | -- jean-christophe.pellion@easii-ic.com |
|
23 | 23 | ------------------------------------------------------------------------------- |
|
24 | 24 | -- 1.0 - initial version |
|
25 | 25 | ------------------------------------------------------------------------------- |
|
26 | 26 | LIBRARY ieee; |
|
27 | 27 | USE ieee.std_logic_1164.ALL; |
|
28 | 28 | USE ieee.numeric_std.ALL; |
|
29 | 29 | LIBRARY grlib; |
|
30 | 30 | USE grlib.amba.ALL; |
|
31 | 31 | USE grlib.stdlib.ALL; |
|
32 | 32 | USE grlib.devices.ALL; |
|
33 | 33 | USE GRLIB.DMA2AHB_Package.ALL; |
|
34 | 34 | LIBRARY lpp; |
|
35 | 35 | USE lpp.lpp_amba.ALL; |
|
36 | 36 | USE lpp.apb_devices_list.ALL; |
|
37 | 37 | USE lpp.lpp_memory.ALL; |
|
38 | 38 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | 39 | LIBRARY techmap; |
|
40 | 40 | USE techmap.gencomp.ALL; |
|
41 | 41 | |
|
42 | 42 | |
|
43 | 43 | ENTITY lpp_lfr_ms_fsmdma IS |
|
44 | 44 | PORT ( |
|
45 | 45 | -- AMBA AHB system signals |
|
46 | 46 | HCLK : IN STD_ULOGIC; |
|
47 | 47 | HRESETn : IN STD_ULOGIC; |
|
48 | 48 | |
|
49 | 49 | --TIME |
|
50 | 50 | data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- fifo interface |
|
53 | 53 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
54 | 54 | fifo_empty : IN STD_LOGIC; |
|
55 | 55 | fifo_ren : OUT STD_LOGIC; |
|
56 | 56 | |
|
57 | 57 | -- header |
|
58 | 58 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | 59 | header_val : IN STD_LOGIC; |
|
60 | 60 | header_ack : OUT STD_LOGIC; |
|
61 | 61 | |
|
62 | 62 | -- DMA |
|
63 | 63 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | 64 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
65 | 65 | dma_valid : OUT STD_LOGIC; |
|
66 | 66 | dma_valid_burst : OUT STD_LOGIC; |
|
67 | 67 | dma_ren : IN STD_LOGIC; |
|
68 | 68 | dma_done : IN STD_LOGIC; |
|
69 | 69 | |
|
70 | 70 | -- Reg out |
|
71 | 71 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
72 | 72 | ready_matrix_f0_1 : OUT STD_LOGIC; |
|
73 | 73 | ready_matrix_f1 : OUT STD_LOGIC; |
|
74 | 74 | ready_matrix_f2 : OUT STD_LOGIC; |
|
75 | 75 | error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
76 | 76 | error_bad_component_error : OUT STD_LOGIC; |
|
77 | 77 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | 78 | |
|
79 | 79 | -- Reg In |
|
80 | 80 | status_ready_matrix_f0_0 : IN STD_LOGIC; |
|
81 | 81 | status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
82 | 82 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
83 | 83 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
84 | 84 | status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
85 | 85 | status_error_bad_component_error : IN STD_LOGIC; |
|
86 | 86 | |
|
87 | 87 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
88 | 88 | config_active_interruption_onError : IN STD_LOGIC; |
|
89 | 89 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 90 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 91 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | 92 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
93 | 93 | |
|
94 |
matrix_time_f0_0 |
|
|
95 |
matrix_time_f0_1 |
|
|
96 |
matrix_time_f1 |
|
|
97 |
matrix_time_f2 |
|
|
94 | matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
95 | matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
96 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
97 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
|
98 | 98 | |
|
99 | 99 | ); |
|
100 | 100 | END; |
|
101 | 101 | |
|
102 | 102 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
103 | 103 | ----------------------------------------------------------------------------- |
|
104 | 104 | -- SIGNAL DMAIn : DMA_In_Type; |
|
105 | 105 | -- SIGNAL header_dmai : DMA_In_Type; |
|
106 | 106 | -- SIGNAL component_dmai : DMA_In_Type; |
|
107 | 107 | -- SIGNAL DMAOut : DMA_OUt_Type; |
|
108 | 108 | ----------------------------------------------------------------------------- |
|
109 | 109 | |
|
110 | 110 | ----------------------------------------------------------------------------- |
|
111 | 111 | ----------------------------------------------------------------------------- |
|
112 | 112 | TYPE state_DMAWriteBurst IS (IDLE, |
|
113 | 113 | CHECK_COMPONENT_TYPE, |
|
114 | 114 | WRITE_COARSE_TIME, |
|
115 | 115 | WRITE_FINE_TIME, |
|
116 | 116 | TRASH_FIFO, |
|
117 | 117 | SEND_DATA, |
|
118 | 118 | WAIT_DATA_ACK |
|
119 | 119 | ); |
|
120 | 120 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; |
|
121 | 121 | |
|
122 | 122 | -- SIGNAL nbSend : INTEGER; |
|
123 | 123 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
124 | 124 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
125 | 125 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
126 | 126 | SIGNAL header_check_ok : STD_LOGIC; |
|
127 | 127 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | 128 | SIGNAL send_matrix : STD_LOGIC; |
|
129 | 129 | -- SIGNAL request : STD_LOGIC; |
|
130 | 130 | -- SIGNAL remaining_data_request : INTEGER; |
|
131 | 131 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
132 | 132 | ----------------------------------------------------------------------------- |
|
133 | 133 | ----------------------------------------------------------------------------- |
|
134 | 134 | SIGNAL header_select : STD_LOGIC; |
|
135 | 135 | |
|
136 | 136 | SIGNAL header_send : STD_LOGIC; |
|
137 | 137 | SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
138 | 138 | SIGNAL header_send_ok : STD_LOGIC; |
|
139 | 139 | SIGNAL header_send_ko : STD_LOGIC; |
|
140 | 140 | |
|
141 | 141 | SIGNAL component_send : STD_LOGIC; |
|
142 | 142 | SIGNAL component_send_ok : STD_LOGIC; |
|
143 | 143 | SIGNAL component_send_ko : STD_LOGIC; |
|
144 | 144 | ----------------------------------------------------------------------------- |
|
145 | 145 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
146 | 146 | SIGNAL component_fifo_ren : STD_LOGIC; |
|
147 | 147 | |
|
148 | 148 | ----------------------------------------------------------------------------- |
|
149 | 149 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
150 | 150 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
151 | 151 | |
|
152 | 152 | ----------------------------------------------------------------------------- |
|
153 | 153 | SIGNAL log_empty_fifo : STD_LOGIC; |
|
154 | 154 | ----------------------------------------------------------------------------- |
|
155 | 155 | SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
156 | 156 | SIGNAL header_reg_val : STD_LOGIC; |
|
157 | 157 | SIGNAL header_reg_ack : STD_LOGIC; |
|
158 | 158 | SIGNAL header_error : STD_LOGIC; |
|
159 | 159 | |
|
160 | 160 | BEGIN |
|
161 | 161 | |
|
162 | 162 | debug_reg <= debug_reg_s; |
|
163 | 163 | |
|
164 | 164 | |
|
165 | 165 | send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE |
|
166 | 166 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE |
|
167 | 167 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE |
|
168 | 168 | '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE |
|
169 | 169 | '0'; |
|
170 | 170 | |
|
171 | 171 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
172 |
'1' WHEN component_type = "0000" |
|
|
172 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE | |
|
173 | 173 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
174 | 174 | '0'; |
|
175 | 175 | |
|
176 | 176 | address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE |
|
177 | 177 | addr_matrix_f0_1 WHEN matrix_type = "01" ELSE |
|
178 | 178 | addr_matrix_f1 WHEN matrix_type = "10" ELSE |
|
179 | 179 | addr_matrix_f2 WHEN matrix_type = "11" ELSE |
|
180 | 180 | (OTHERS => '0'); |
|
181 | 181 | |
|
182 | 182 | ----------------------------------------------------------------------------- |
|
183 | 183 | -- DMA control |
|
184 | 184 | ----------------------------------------------------------------------------- |
|
185 | 185 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
186 | 186 | BEGIN -- PROCESS DMAWriteBurst_p |
|
187 | 187 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
188 | 188 | matrix_type <= (OTHERS => '0'); |
|
189 | 189 | component_type <= (OTHERS => '0'); |
|
190 | 190 | state <= IDLE; |
|
191 | 191 | -- header_ack <= '0'; |
|
192 | 192 | ready_matrix_f0_0 <= '0'; |
|
193 | 193 | ready_matrix_f0_1 <= '0'; |
|
194 | 194 | ready_matrix_f1 <= '0'; |
|
195 | 195 | ready_matrix_f2 <= '0'; |
|
196 | 196 | error_anticipating_empty_fifo <= '0'; |
|
197 | 197 | error_bad_component_error <= '0'; |
|
198 | 198 | component_type_pre <= "0000"; |
|
199 | 199 | fifo_ren_trash <= '1'; |
|
200 | 200 | component_send <= '0'; |
|
201 | 201 | address <= (OTHERS => '0'); |
|
202 | 202 | header_select <= '0'; |
|
203 | 203 | header_send <= '0'; |
|
204 | 204 | header_data <= (OTHERS => '0'); |
|
205 | 205 | fine_time_reg <= (OTHERS => '0'); |
|
206 | 206 | |
|
207 |
debug_reg_s( |
|
|
207 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); | |
|
208 | 208 | debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); |
|
209 | 209 | |
|
210 | 210 | log_empty_fifo <= '0'; |
|
211 | 211 | |
|
212 | 212 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
213 | 213 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); |
|
214 | 214 | header_reg_ack <= '0'; |
|
215 | ||
|
215 | ||
|
216 | 216 | CASE state IS |
|
217 | 217 | WHEN IDLE => |
|
218 | 218 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
219 | ||
|
220 | matrix_type <= header(1 DOWNTO 0); | |
|
219 | ||
|
220 | --matrix_type <= header(1 DOWNTO 0); | |
|
221 | 221 | --component_type <= header(5 DOWNTO 2); |
|
222 | 222 | |
|
223 | 223 | ready_matrix_f0_0 <= '0'; |
|
224 | 224 | ready_matrix_f0_1 <= '0'; |
|
225 | 225 | ready_matrix_f1 <= '0'; |
|
226 | 226 | ready_matrix_f2 <= '0'; |
|
227 | 227 | error_bad_component_error <= '0'; |
|
228 | header_select <= '1'; | |
|
229 | ||
|
228 | --header_select <= '1'; | |
|
229 | ||
|
230 | 230 | IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
|
231 | header_reg_ack <= '1'; | |
|
231 | header_reg_ack <= '1'; | |
|
232 | 232 | debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0); |
|
233 | 233 | debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2); |
|
234 | ||
|
234 | ||
|
235 | 235 | matrix_type <= header_reg(1 DOWNTO 0); |
|
236 | 236 | component_type <= header_reg(5 DOWNTO 2); |
|
237 | 237 | component_type_pre <= component_type; |
|
238 | 238 | state <= CHECK_COMPONENT_TYPE; |
|
239 | 239 | END IF; |
|
240 | 240 | log_empty_fifo <= '0'; |
|
241 | 241 | |
|
242 | 242 | WHEN CHECK_COMPONENT_TYPE => |
|
243 | 243 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
244 | 244 | --header_ack <= '0'; |
|
245 | ||
|
245 | ||
|
246 | 246 | IF header_check_ok = '1' THEN |
|
247 | 247 | header_send <= '0'; |
|
248 | 248 | -- |
|
249 | 249 | IF component_type = "0000" THEN |
|
250 |
address |
|
|
250 | address <= address_matrix; | |
|
251 | 251 | CASE matrix_type IS |
|
252 | WHEN "00" => matrix_time_f0_0 <= data_time; | |
|
253 | WHEN "01" => matrix_time_f0_1 <= data_time; | |
|
254 | WHEN "10" => matrix_time_f1 <= data_time; | |
|
255 |
WHEN "11" => matrix_time_f2 <= data_time |
|
|
252 | WHEN "00" => matrix_time_f0_0 <= data_time; | |
|
253 | WHEN "01" => matrix_time_f0_1 <= data_time; | |
|
254 | WHEN "10" => matrix_time_f1 <= data_time; | |
|
255 | WHEN "11" => matrix_time_f2 <= data_time; | |
|
256 | 256 | WHEN OTHERS => NULL; |
|
257 | 257 | END CASE; |
|
258 | ||
|
259 | header_data <= data_time(31 DOWNTO 0); | |
|
260 | fine_time_reg <= data_time(47 DOWNTO 32); | |
|
258 | ||
|
259 | header_data <= data_time(31 DOWNTO 0); | |
|
260 | fine_time_reg <= data_time(47 DOWNTO 32); | |
|
261 | 261 | --state <= WRITE_COARSE_TIME; |
|
262 | 262 | --header_send <= '1'; |
|
263 | 263 | state <= SEND_DATA; |
|
264 | 264 | header_send <= '0'; |
|
265 | 265 | component_send <= '1'; |
|
266 | 266 | header_select <= '0'; |
|
267 | 267 | ELSE |
|
268 | 268 | state <= SEND_DATA; |
|
269 | 269 | END IF; |
|
270 | 270 | -- |
|
271 | 271 | ELSE |
|
272 | 272 | error_bad_component_error <= '1'; |
|
273 | 273 | component_type_pre <= "0000"; |
|
274 | 274 | state <= TRASH_FIFO; |
|
275 | 275 | END IF; |
|
276 | 276 | |
|
277 | --WHEN WRITE_COARSE_TIME => | |
|
278 | -- debug_reg_s(2 DOWNTO 0) <= "010"; | |
|
279 | ||
|
280 | -- header_ack <= '0'; | |
|
277 | --WHEN WRITE_COARSE_TIME => | |
|
278 | -- debug_reg_s(2 DOWNTO 0) <= "010"; | |
|
279 | ||
|
280 | -- header_ack <= '0'; | |
|
281 | 281 | |
|
282 | -- IF dma_ren = '0' THEN | |
|
283 | -- header_send <= '0'; | |
|
284 | -- ELSE | |
|
285 | -- header_send <= header_send; | |
|
286 | -- END IF; | |
|
282 | -- IF dma_ren = '0' THEN | |
|
283 | -- header_send <= '0'; | |
|
284 | -- ELSE | |
|
285 | -- header_send <= header_send; | |
|
286 | -- END IF; | |
|
287 | 287 | |
|
288 | 288 | |
|
289 | -- IF header_send_ko = '1' THEN | |
|
290 | -- header_send <= '0'; | |
|
291 | -- state <= TRASH_FIFO; | |
|
292 | -- error_anticipating_empty_fifo <= '1'; | |
|
293 | -- -- TODO : error sending header | |
|
294 | -- ELSIF header_send_ok = '1' THEN | |
|
295 | -- header_send <= '1'; | |
|
296 | -- header_select <= '1'; | |
|
297 | -- header_data(15 DOWNTO 0) <= fine_time_reg; | |
|
298 | -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); | |
|
299 | -- state <= WRITE_FINE_TIME; | |
|
300 | -- address <= address + 4; | |
|
301 | -- END IF; | |
|
302 | ||
|
303 | ||
|
304 | --WHEN WRITE_FINE_TIME => | |
|
305 | -- debug_reg_s(2 DOWNTO 0) <= "011"; | |
|
306 | ||
|
307 | -- header_ack <= '0'; | |
|
289 | -- IF header_send_ko = '1' THEN | |
|
290 | -- header_send <= '0'; | |
|
291 | -- state <= TRASH_FIFO; | |
|
292 | -- error_anticipating_empty_fifo <= '1'; | |
|
293 | -- -- TODO : error sending header | |
|
294 | -- ELSIF header_send_ok = '1' THEN | |
|
295 | -- header_send <= '1'; | |
|
296 | -- header_select <= '1'; | |
|
297 | -- header_data(15 DOWNTO 0) <= fine_time_reg; | |
|
298 | -- header_data(31 DOWNTO 16) <= (OTHERS => '0'); | |
|
299 | -- state <= WRITE_FINE_TIME; | |
|
300 | -- address <= address + 4; | |
|
301 | -- END IF; | |
|
302 | ||
|
303 | ||
|
304 | --WHEN WRITE_FINE_TIME => | |
|
305 | -- debug_reg_s(2 DOWNTO 0) <= "011"; | |
|
308 | 306 | |
|
309 | -- IF dma_ren = '0' THEN | |
|
310 | -- header_send <= '0'; | |
|
311 | -- ELSE | |
|
312 |
-- header_send <= |
|
|
313 |
|
|
|
307 | -- header_ack <= '0'; | |
|
308 | ||
|
309 | -- IF dma_ren = '0' THEN | |
|
310 | -- header_send <= '0'; | |
|
311 | -- ELSE | |
|
312 | -- header_send <= header_send; | |
|
313 | -- END IF; | |
|
314 | 314 | |
|
315 | -- IF header_send_ko = '1' THEN | |
|
316 | -- header_send <= '0'; | |
|
317 | -- state <= TRASH_FIFO; | |
|
318 | -- error_anticipating_empty_fifo <= '1'; | |
|
319 | -- -- TODO : error sending header | |
|
320 | -- ELSIF header_send_ok = '1' THEN | |
|
321 | -- header_send <= '0'; | |
|
322 | -- header_select <= '0'; | |
|
323 | -- state <= SEND_DATA; | |
|
324 | -- address <= address + 4; | |
|
325 | -- END IF; | |
|
315 | -- IF header_send_ko = '1' THEN | |
|
316 | -- header_send <= '0'; | |
|
317 | -- state <= TRASH_FIFO; | |
|
318 | -- error_anticipating_empty_fifo <= '1'; | |
|
319 | -- -- TODO : error sending header | |
|
320 | -- ELSIF header_send_ok = '1' THEN | |
|
321 | -- header_send <= '0'; | |
|
322 | -- header_select <= '0'; | |
|
323 | -- state <= SEND_DATA; | |
|
324 | -- address <= address + 4; | |
|
325 | -- END IF; | |
|
326 | 326 | |
|
327 | 327 | WHEN TRASH_FIFO => |
|
328 | 328 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
329 | ||
|
329 | ||
|
330 | 330 | -- header_ack <= '0'; |
|
331 | 331 | error_bad_component_error <= '0'; |
|
332 | 332 | error_anticipating_empty_fifo <= '0'; |
|
333 | 333 | IF fifo_empty = '1' THEN |
|
334 | 334 | state <= IDLE; |
|
335 | 335 | fifo_ren_trash <= '1'; |
|
336 | 336 | ELSE |
|
337 | 337 | fifo_ren_trash <= '0'; |
|
338 | 338 | END IF; |
|
339 | 339 | |
|
340 | 340 | WHEN SEND_DATA => |
|
341 | 341 | -- header_ack <= '0'; |
|
342 | 342 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
343 | ||
|
343 | ||
|
344 | 344 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
345 | 345 | state <= IDLE; |
|
346 | 346 | IF component_type = "1110" THEN --"1110" -- JC |
|
347 | 347 | CASE matrix_type IS |
|
348 | 348 | WHEN "00" => ready_matrix_f0_0 <= '1'; |
|
349 | 349 | WHEN "01" => ready_matrix_f0_1 <= '1'; |
|
350 | 350 | WHEN "10" => ready_matrix_f1 <= '1'; |
|
351 | 351 | WHEN "11" => ready_matrix_f2 <= '1'; |
|
352 | 352 | WHEN OTHERS => NULL; |
|
353 | 353 | END CASE; |
|
354 | 354 | |
|
355 | 355 | END IF; |
|
356 | 356 | ELSE |
|
357 | 357 | component_send <= '1'; |
|
358 | 358 | address <= address; |
|
359 | 359 | state <= WAIT_DATA_ACK; |
|
360 | 360 | END IF; |
|
361 | 361 | |
|
362 | 362 | WHEN WAIT_DATA_ACK => |
|
363 | 363 | log_empty_fifo <= fifo_empty OR log_empty_fifo; |
|
364 | ||
|
364 | ||
|
365 | 365 | debug_reg_s(2 DOWNTO 0) <= "110"; |
|
366 | ||
|
366 | ||
|
367 | 367 | component_send <= '0'; |
|
368 | 368 | IF component_send_ok = '1' THEN |
|
369 | 369 | address <= address + 64; |
|
370 | 370 | state <= SEND_DATA; |
|
371 | 371 | ELSIF component_send_ko = '1' THEN |
|
372 | 372 | error_anticipating_empty_fifo <= '0'; |
|
373 | state <= TRASH_FIFO; | |
|
373 | state <= TRASH_FIFO; | |
|
374 | 374 | END IF; |
|
375 | ||
|
376 | ||
|
377 | --WHEN CHECK_LENGTH => | |
|
378 | -- component_send <= '0'; | |
|
379 | -- debug_reg_s(2 DOWNTO 0) <= "111"; | |
|
380 | -- state <= IDLE; | |
|
375 | ||
|
376 | ||
|
377 | --WHEN CHECK_LENGTH => | |
|
378 | -- component_send <= '0'; | |
|
379 | -- debug_reg_s(2 DOWNTO 0) <= "111"; | |
|
380 | -- state <= IDLE; | |
|
381 | 381 | |
|
382 | 382 | WHEN OTHERS => NULL; |
|
383 | 383 | END CASE; |
|
384 | 384 | |
|
385 | 385 | END IF; |
|
386 | 386 | END PROCESS DMAWriteFSM_p; |
|
387 | ||
|
387 | ||
|
388 | 388 | dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send; |
|
389 | 389 | dma_valid <= header_send WHEN header_select = '1' ELSE '0'; |
|
390 | 390 | dma_data <= header_data WHEN header_select = '1' ELSE fifo_data; |
|
391 | 391 | dma_addr <= address; |
|
392 | 392 | fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren; |
|
393 | 393 | |
|
394 | 394 | component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done; |
|
395 | 395 | component_send_ko <= '0'; |
|
396 | 396 | |
|
397 | 397 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; |
|
398 | 398 | header_send_ko <= '0'; |
|
399 | 399 | |
|
400 | 400 | |
|
401 | 401 | ----------------------------------------------------------------------------- |
|
402 | 402 | -- FSM HEADER ACK |
|
403 | 403 | ----------------------------------------------------------------------------- |
|
404 | 404 | PROCESS (HCLK, HRESETn) |
|
405 | 405 | BEGIN -- PROCESS |
|
406 |
IF HRESETn = '0' THEN |
|
|
406 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
|
407 | 407 | header_ack <= '0'; |
|
408 | 408 | header_reg <= (OTHERS => '0'); |
|
409 | 409 | header_reg_val <= '0'; |
|
410 |
ELSIF HCLK' |
|
|
410 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
|
411 | 411 | header_ack <= '0'; |
|
412 | ||
|
412 | ||
|
413 | 413 | IF header_val = '1' THEN |
|
414 | 414 | header_ack <= '1'; |
|
415 | 415 | header_reg <= header; |
|
416 | 416 | END IF; |
|
417 | 417 | |
|
418 | 418 | IF header_val = '1' THEN |
|
419 | 419 | header_reg_val <= '1'; |
|
420 | 420 | ELSIF header_reg_ack = '1' THEN |
|
421 | 421 | header_reg_val <= '0'; |
|
422 | 422 | END IF; |
|
423 | 423 | |
|
424 | 424 | header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack); |
|
425 | 425 | |
|
426 | 426 | END IF; |
|
427 | 427 | END PROCESS; |
|
428 | 428 | |
|
429 | 429 | debug_reg_s(3) <= header_error; |
|
430 | 430 | |
|
431 | END Behavioral; No newline at end of file | |
|
431 | END Behavioral; |
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