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(MINI-LFR) WFP_MS_0-1-10
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r345:21fc600461fa (MINI-LFR) WFP_MS-0-1-10 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_val : STD_LOGIC;
130 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL ADC_nCS_sig : STD_LOGIC;
131 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_CLK_sig : STD_LOGIC;
132 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
133 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134
134
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 SIGNAL rstn : STD_LOGIC;
139 SIGNAL rstn : STD_LOGIC;
140 BEGIN -- beh
140 BEGIN -- beh
141
141
142 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
143 -- CLK
143 -- CLK
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
145 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146
146
147 PROCESS(clk100MHz)
147 PROCESS(clk100MHz)
148 BEGIN
148 BEGIN
149 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
149 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 clk_50_s <= NOT clk_50_s;
150 clk_50_s <= NOT clk_50_s;
151 END IF;
151 END IF;
152 END PROCESS;
152 END PROCESS;
153
153
154 PROCESS(clk_50_s)
154 PROCESS(clk_50_s)
155 BEGIN
155 BEGIN
156 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
156 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 clk_25 <= NOT clk_25;
157 clk_25 <= NOT clk_25;
158 END IF;
158 END IF;
159 END PROCESS;
159 END PROCESS;
160
160
161 PROCESS(clk49_152MHz)
161 PROCESS(clk49_152MHz)
162 BEGIN
162 BEGIN
163 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
163 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 clk_24 <= NOT clk_24;
164 clk_24 <= NOT clk_24;
165 END IF;
165 END IF;
166 END PROCESS;
166 END PROCESS;
167
167
168 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
169
169
170 PROCESS (clk_25, rstn)
170 PROCESS (clk_25, rstn)
171 BEGIN -- PROCESS
171 BEGIN -- PROCESS
172 IF rstn = '0' THEN -- asynchronous reset (active low)
172 IF rstn = '0' THEN -- asynchronous reset (active low)
173 led(0) <= '0';
173 led(0) <= '0';
174 led(1) <= '0';
174 led(1) <= '0';
175 led(2) <= '0';
175 led(2) <= '0';
176 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
176 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 led(0) <= '0';
177 led(0) <= '0';
178 led(1) <= '1';
178 led(1) <= '1';
179 led(2) <= '1';
179 led(2) <= '1';
180 END IF;
180 END IF;
181 END PROCESS;
181 END PROCESS;
182
182
183 --
183 --
184 leon3_soc_1 : leon3_soc
184 leon3_soc_1 : leon3_soc
185 GENERIC MAP (
185 GENERIC MAP (
186 fabtech => apa3e,
186 fabtech => apa3e,
187 memtech => apa3e,
187 memtech => apa3e,
188 padtech => inferred,
188 padtech => inferred,
189 clktech => inferred,
189 clktech => inferred,
190 disas => 0,
190 disas => 0,
191 dbguart => 0,
191 dbguart => 0,
192 pclow => 2,
192 pclow => 2,
193 clk_freq => 25000,
193 clk_freq => 25000,
194 NB_CPU => 1,
194 NB_CPU => 1,
195 ENABLE_FPU => 1,
195 ENABLE_FPU => 1,
196 FPU_NETLIST => 0,
196 FPU_NETLIST => 0,
197 ENABLE_DSU => 1,
197 ENABLE_DSU => 1,
198 ENABLE_AHB_UART => 1,
198 ENABLE_AHB_UART => 1,
199 ENABLE_APB_UART => 1,
199 ENABLE_APB_UART => 1,
200 ENABLE_IRQMP => 1,
200 ENABLE_IRQMP => 1,
201 ENABLE_GPT => 1,
201 ENABLE_GPT => 1,
202 NB_AHB_MASTER => NB_AHB_MASTER,
202 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_APB_SLAVE => NB_APB_SLAVE)
204 NB_APB_SLAVE => NB_APB_SLAVE)
205 PORT MAP (
205 PORT MAP (
206 clk => clk_25,
206 clk => clk_25,
207 reset => rstn,
207 reset => rstn,
208 errorn => OPEN,
208 errorn => OPEN,
209
209
210 ahbrxd => TAG1,
210 ahbrxd => TAG1,
211 ahbtxd => TAG3,
211 ahbtxd => TAG3,
212 urxd1 => TAG2,
212 urxd1 => TAG2,
213 utxd1 => TAG4,
213 utxd1 => TAG4,
214
214
215 address => address,
215 address => address,
216 data => data,
216 data => data,
217 nSRAM_BE0 => nSRAM_BE0,
217 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE1 => nSRAM_BE1,
218 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE2 => nSRAM_BE2,
219 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE3 => nSRAM_BE3,
220 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_WE => nSRAM_WE,
221 nSRAM_WE => nSRAM_WE,
222 nSRAM_CE => nSRAM_CE,
222 nSRAM_CE => nSRAM_CE,
223 nSRAM_OE => nSRAM_OE,
223 nSRAM_OE => nSRAM_OE,
224
224
225 apbi_ext => apbi_ext,
225 apbi_ext => apbi_ext,
226 apbo_ext => apbo_ext,
226 apbo_ext => apbo_ext,
227 ahbi_s_ext => ahbi_s_ext,
227 ahbi_s_ext => ahbi_s_ext,
228 ahbo_s_ext => ahbo_s_ext,
228 ahbo_s_ext => ahbo_s_ext,
229 ahbi_m_ext => ahbi_m_ext,
229 ahbi_m_ext => ahbi_m_ext,
230 ahbo_m_ext => ahbo_m_ext);
230 ahbo_m_ext => ahbo_m_ext);
231
231
232
232
233 -------------------------------------------------------------------------------
233 -------------------------------------------------------------------------------
234 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
234 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -------------------------------------------------------------------------------
235 -------------------------------------------------------------------------------
236 apb_lfr_time_management_1 : apb_lfr_time_management
236 apb_lfr_time_management_1 : apb_lfr_time_management
237 GENERIC MAP (
237 GENERIC MAP (
238 pindex => 6,
238 pindex => 6,
239 paddr => 6,
239 paddr => 6,
240 pmask => 16#fff#,
240 pmask => 16#fff#,
241 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
241 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
242 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 PORT MAP (
243 PORT MAP (
244 clk25MHz => clk_25,
244 clk25MHz => clk_25,
245 clk24_576MHz => clk_24, -- 49.152MHz/2
245 clk24_576MHz => clk_24, -- 49.152MHz/2
246 resetn => rstn,
246 resetn => rstn,
247 grspw_tick => swno.tickout,
247 grspw_tick => swno.tickout,
248 apbi => apbi_ext,
248 apbi => apbi_ext,
249 apbo => apbo_ext(6),
249 apbo => apbo_ext(6),
250 coarse_time => coarse_time,
250 coarse_time => coarse_time,
251 fine_time => fine_time);
251 fine_time => fine_time);
252
252
253 -----------------------------------------------------------------------
253 -----------------------------------------------------------------------
254 --- SpaceWire --------------------------------------------------------
254 --- SpaceWire --------------------------------------------------------
255 -----------------------------------------------------------------------
255 -----------------------------------------------------------------------
256
256
257 -- SPW_EN <= '1';
257 -- SPW_EN <= '1';
258
258
259 spw_clk <= clk_50_s;
259 spw_clk <= clk_50_s;
260 spw_rxtxclk <= spw_clk;
260 spw_rxtxclk <= spw_clk;
261 spw_rxclkn <= NOT spw_rxtxclk;
261 spw_rxclkn <= NOT spw_rxtxclk;
262
262
263 -- PADS for SPW1
263 -- PADS for SPW1
264 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
264 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 PORT MAP (spw1_din, dtmp(0));
265 PORT MAP (spw1_din, dtmp(0));
266 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
266 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 PORT MAP (spw1_sin, stmp(0));
267 PORT MAP (spw1_sin, stmp(0));
268 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
268 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 PORT MAP (spw1_dout, swno.d(0));
269 PORT MAP (spw1_dout, swno.d(0));
270 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
270 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 PORT MAP (spw1_sout, swno.s(0));
271 PORT MAP (spw1_sout, swno.s(0));
272 -- PADS FOR SPW2
272 -- PADS FOR SPW2
273 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
273 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 PORT MAP (spw2_sin, dtmp(1));
274 PORT MAP (spw2_sin, dtmp(1));
275 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
275 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 PORT MAP (spw2_din, stmp(1));
276 PORT MAP (spw2_din, stmp(1));
277 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
277 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 PORT MAP (spw2_dout, swno.d(1));
278 PORT MAP (spw2_dout, swno.d(1));
279 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
279 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 PORT MAP (spw2_sout, swno.s(1));
280 PORT MAP (spw2_sout, swno.s(1));
281
281
282 -- GRSPW PHY
282 -- GRSPW PHY
283 --spw1_input: if CFG_SPW_GRSPW = 1 generate
283 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 spw_inputloop : FOR j IN 0 TO 1 GENERATE
284 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_phy0 : grspw_phy
285 spw_phy0 : grspw_phy
286 GENERIC MAP(
286 GENERIC MAP(
287 tech => apa3e,
287 tech => apa3e,
288 rxclkbuftype => 1,
288 rxclkbuftype => 1,
289 scantest => 0)
289 scantest => 0)
290 PORT MAP(
290 PORT MAP(
291 rxrst => swno.rxrst,
291 rxrst => swno.rxrst,
292 di => dtmp(j),
292 di => dtmp(j),
293 si => stmp(j),
293 si => stmp(j),
294 rxclko => spw_rxclk(j),
294 rxclko => spw_rxclk(j),
295 do => swni.d(j),
295 do => swni.d(j),
296 ndo => swni.nd(j*5+4 DOWNTO j*5),
296 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
297 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 END GENERATE spw_inputloop;
298 END GENERATE spw_inputloop;
299
299
300 -- SPW core
300 -- SPW core
301 sw0 : grspwm GENERIC MAP(
301 sw0 : grspwm GENERIC MAP(
302 tech => apa3e,
302 tech => apa3e,
303 hindex => 1,
303 hindex => 1,
304 pindex => 5,
304 pindex => 5,
305 paddr => 5,
305 paddr => 5,
306 pirq => 11,
306 pirq => 11,
307 sysfreq => 25000, -- CPU_FREQ
307 sysfreq => 25000, -- CPU_FREQ
308 rmap => 1,
308 rmap => 1,
309 rmapcrc => 1,
309 rmapcrc => 1,
310 fifosize1 => 16,
310 fifosize1 => 16,
311 fifosize2 => 16,
311 fifosize2 => 16,
312 rxclkbuftype => 1,
312 rxclkbuftype => 1,
313 rxunaligned => 0,
313 rxunaligned => 0,
314 rmapbufs => 4,
314 rmapbufs => 4,
315 ft => 0,
315 ft => 0,
316 netlist => 0,
316 netlist => 0,
317 ports => 2,
317 ports => 2,
318 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
318 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 memtech => apa3e,
319 memtech => apa3e,
320 destkey => 2,
320 destkey => 2,
321 spwcore => 1
321 spwcore => 1
322 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
322 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
323 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
324 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 )
325 )
326 PORT MAP(rstn, clk_25, spw_rxclk(0),
326 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
327 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
328 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 swni, swno);
329 swni, swno);
330
330
331 swni.tickin <= '0';
331 swni.tickin <= '0';
332 swni.rmapen <= '1';
332 swni.rmapen <= '1';
333 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
333 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.tickinraw <= '0';
334 swni.tickinraw <= '0';
335 swni.timein <= (OTHERS => '0');
335 swni.timein <= (OTHERS => '0');
336 swni.dcrstval <= (OTHERS => '0');
336 swni.dcrstval <= (OTHERS => '0');
337 swni.timerrstval <= (OTHERS => '0');
337 swni.timerrstval <= (OTHERS => '0');
338
338
339 -------------------------------------------------------------------------------
339 -------------------------------------------------------------------------------
340 -- LFR ------------------------------------------------------------------------
340 -- LFR ------------------------------------------------------------------------
341 -------------------------------------------------------------------------------
341 -------------------------------------------------------------------------------
342 lpp_lfr_1 : lpp_lfr_WFP_nMS
342 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 GENERIC MAP (
343 GENERIC MAP (
344 Mem_use => use_RAM,
344 Mem_use => use_RAM,
345 nb_data_by_buffer_size => 32,
345 nb_data_by_buffer_size => 32,
346 nb_word_by_buffer_size => 30,
346 nb_word_by_buffer_size => 30,
347 nb_snapshot_param_size => 32,
347 nb_snapshot_param_size => 32,
348 delta_vector_size => 32,
348 delta_vector_size => 32,
349 delta_vector_size_f0_2 => 7, -- log2(96)
349 delta_vector_size_f0_2 => 7, -- log2(96)
350 pindex => 15,
350 pindex => 15,
351 paddr => 15,
351 paddr => 15,
352 pmask => 16#fff#,
352 pmask => 16#fff#,
353 pirq_ms => 6,
353 pirq_ms => 6,
354 pirq_wfp => 14,
354 pirq_wfp => 14,
355 hindex => 2,
355 hindex => 2,
356 top_lfr_version => X"000109") -- aa.bb.cc version
356 top_lfr_version => X"00010A") -- aa.bb.cc version
357 -- AA : BOARD NUMBER
357 -- AA : BOARD NUMBER
358 -- 0 => MINI_LFR
358 -- 0 => MINI_LFR
359 -- 1 => EM
359 -- 1 => EM
360 PORT MAP (
360 PORT MAP (
361 clk => clk_25,
361 clk => clk_25,
362 rstn => rstn,
362 rstn => rstn,
363 sample_B => sample(2 DOWNTO 0),
363 sample_B => sample(2 DOWNTO 0),
364 sample_E => sample(7 DOWNTO 3),
364 sample_E => sample(7 DOWNTO 3),
365 sample_val => sample_val,
365 sample_val => sample_val,
366 apbi => apbi_ext,
366 apbi => apbi_ext,
367 apbo => apbo_ext(15),
367 apbo => apbo_ext(15),
368 ahbi => ahbi_m_ext,
368 ahbi => ahbi_m_ext,
369 ahbo => ahbo_m_ext(2),
369 ahbo => ahbo_m_ext(2),
370 coarse_time => coarse_time,
370 coarse_time => coarse_time,
371 fine_time => fine_time,
371 fine_time => fine_time,
372 data_shaping_BW => bias_fail_sw,
372 data_shaping_BW => bias_fail_sw,
373 observation_reg => observation_reg);
373 observation_reg => observation_reg);
374
374
375 -----------------------------------------------------------------------------
375 -----------------------------------------------------------------------------
376 --
376 --
377 -----------------------------------------------------------------------------
377 -----------------------------------------------------------------------------
378 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
378 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
379 GENERIC MAP (
379 GENERIC MAP (
380 ChanelCount => 8,
380 ChanelCount => 8,
381 ncycle_cnv_high => 40, -- TODO : 79
381 ncycle_cnv_high => 40, -- TODO : 79
382 ncycle_cnv => 250) -- TODO : 500
382 ncycle_cnv => 250) -- TODO : 500
383 PORT MAP (
383 PORT MAP (
384 cnv_clk => clk_24, -- TODO : 49.152
384 cnv_clk => clk_24, -- TODO : 49.152
385 cnv_rstn => rstn, -- ok
385 cnv_rstn => rstn, -- ok
386 cnv => ADC_smpclk, -- ok
386 cnv => ADC_smpclk, -- ok
387 clk => clk_25, -- ok
387 clk => clk_25, -- ok
388 rstn => rstn, -- ok
388 rstn => rstn, -- ok
389 ADC_data => ADC_data, -- ok
389 ADC_data => ADC_data, -- ok
390 ADC_nOE => ADC_OEB_bar_CH, -- ok
390 ADC_nOE => ADC_OEB_bar_CH, -- ok
391 sample => sample, -- ok
391 sample => sample, -- ok
392 sample_val => sample_val); -- ok
392 sample_val => sample_val); -- ok
393
393
394 TAG8 <= ADC_smpclk;
394 TAG8 <= ADC_smpclk;
395
395
396 END beh;
396 END beh;
Show file before | Show file after | Hide comments
@@ -1,580 +1,580
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
175
175
176 BEGIN -- beh
176 BEGIN -- beh
177
177
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179 -- CLK
179 -- CLK
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181
181
182 PROCESS(clk_50)
182 PROCESS(clk_50)
183 BEGIN
183 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
186 END IF;
186 END IF;
187 END PROCESS;
187 END PROCESS;
188
188
189 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
190 BEGIN
190 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 PROCESS(clk_49)
196 PROCESS(clk_49)
197 BEGIN
197 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
200 END IF;
200 END IF;
201 END PROCESS;
201 END PROCESS;
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
208 LED0 <= '0';
209 LED1 <= '0';
209 LED1 <= '0';
210 LED2 <= '0';
210 LED2 <= '0';
211 --IO1 <= '0';
211 --IO1 <= '0';
212 --IO2 <= '1';
212 --IO2 <= '1';
213 --IO3 <= '0';
213 --IO3 <= '0';
214 --IO4 <= '0';
214 --IO4 <= '0';
215 --IO5 <= '0';
215 --IO5 <= '0';
216 --IO6 <= '0';
216 --IO6 <= '0';
217 --IO7 <= '0';
217 --IO7 <= '0';
218 --IO8 <= '0';
218 --IO8 <= '0';
219 --IO9 <= '0';
219 --IO9 <= '0';
220 --IO10 <= '0';
220 --IO10 <= '0';
221 --IO11 <= '0';
221 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
223 LED0 <= '0';
224 LED1 <= '1';
224 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
226 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
241 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
243 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s ;
245 I00_s <= NOT I00_s ;
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
249
249
250 --UARTs
250 --UARTs
251 nCTS1 <= '1';
251 nCTS1 <= '1';
252 nCTS2 <= '1';
252 nCTS2 <= '1';
253 nDCD2 <= '1';
253 nDCD2 <= '1';
254
254
255 --EXT CONNECTOR
255 --EXT CONNECTOR
256
256
257 --SPACE WIRE
257 --SPACE WIRE
258
258
259 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
260 GENERIC MAP (
261 fabtech => apa3e,
261 fabtech => apa3e,
262 memtech => apa3e,
262 memtech => apa3e,
263 padtech => inferred,
263 padtech => inferred,
264 clktech => inferred,
264 clktech => inferred,
265 disas => 0,
265 disas => 0,
266 dbguart => 0,
266 dbguart => 0,
267 pclow => 2,
267 pclow => 2,
268 clk_freq => 25000,
268 clk_freq => 25000,
269 NB_CPU => 1,
269 NB_CPU => 1,
270 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
280 PORT MAP (
281 clk => clk_25,
281 clk => clk_25,
282 reset => reset,
282 reset => reset,
283 errorn => errorn,
283 errorn => errorn,
284 ahbrxd => TXD1,
284 ahbrxd => TXD1,
285 ahbtxd => RXD1,
285 ahbtxd => RXD1,
286 urxd1 => TXD2,
286 urxd1 => TXD2,
287 utxd1 => RXD2,
287 utxd1 => RXD2,
288 address => SRAM_A,
288 address => SRAM_A,
289 data => SRAM_DQ,
289 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
297
297
298 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
304
304
305 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
309 GENERIC MAP (
310 pindex => 6,
310 pindex => 6,
311 paddr => 6,
311 paddr => 6,
312 pmask => 16#fff#,
312 pmask => 16#fff#,
313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
313 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
314 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 PORT MAP (
315 PORT MAP (
316 clk25MHz => clk_25,
316 clk25MHz => clk_25,
317 clk24_576MHz => clk_24, -- 49.152MHz/2
317 clk24_576MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
318 resetn => reset,
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
322 coarse_time => coarse_time,
323 fine_time => fine_time);
323 fine_time => fine_time);
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 SPW_EN <= '1';
329 SPW_EN <= '1';
330
330
331 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334
334
335 -- PADS for SPW1
335 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
344 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
353
354 -- GRSPW PHY
354 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
358 GENERIC MAP(
358 GENERIC MAP(
359 tech => apa3e,
359 tech => apa3e,
360 rxclkbuftype => 1,
360 rxclkbuftype => 1,
361 scantest => 0)
361 scantest => 0)
362 PORT MAP(
362 PORT MAP(
363 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
364 di => dtmp(j),
364 di => dtmp(j),
365 si => stmp(j),
365 si => stmp(j),
366 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
367 do => swni.d(j),
367 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
371
371
372 -- SPW core
372 -- SPW core
373 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
374 tech => apa3e,
375 hindex => 1,
375 hindex => 1,
376 pindex => 5,
376 pindex => 5,
377 paddr => 5,
377 paddr => 5,
378 pirq => 11,
378 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
380 rmap => 1,
381 rmapcrc => 1,
381 rmapcrc => 1,
382 fifosize1 => 16,
382 fifosize1 => 16,
383 fifosize2 => 16,
383 fifosize2 => 16,
384 rxclkbuftype => 1,
384 rxclkbuftype => 1,
385 rxunaligned => 0,
385 rxunaligned => 0,
386 rmapbufs => 4,
386 rmapbufs => 4,
387 ft => 0,
387 ft => 0,
388 netlist => 0,
388 netlist => 0,
389 ports => 2,
389 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
391 memtech => apa3e,
392 destkey => 2,
392 destkey => 2,
393 spwcore => 1
393 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
397 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
401 swni, swno);
402
402
403 swni.tickin <= '0';
403 swni.tickin <= '0';
404 swni.rmapen <= '1';
404 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410
410
411 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
415 GENERIC MAP (
416 Mem_use => use_RAM,
416 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"000109") -- aa.bb.cc version
428 top_lfr_version => X"00010A") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
434 sample_val => sample_val,
434 sample_val => sample_val,
435 apbi => apbi_ext,
435 apbi => apbi_ext,
436 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
439 coarse_time => coarse_time,
440 fine_time => fine_time,
440 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
442 observation_reg => observation_reg);
443
443
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
445 GENERIC MAP(
446 ChannelCount => 8,
446 ChannelCount => 8,
447 SampleNbBits => 14,
447 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
450 PORT MAP (
451 -- CONV
451 -- CONV
452 cnv_clk => clk_24,
452 cnv_clk => clk_24,
453 cnv_rstn => reset,
453 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
455 -- DATA
455 -- DATA
456 clk => clk_25,
456 clk => clk_25,
457 rstn => reset,
457 rstn => reset,
458 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
460 -- SAMPLE
460 -- SAMPLE
461 sample => sample,
461 sample => sample,
462 sample_val => sample_val);
462 sample_val => sample_val);
463
463
464 --IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
467
467
468 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
471
471
472 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
475
475
476 grgpio0 : grgpio
476 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
479
480 --pio_pad_0 : iopad
480 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
483 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
486 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
489 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
492 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
495 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
498 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
501 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
504
505 PROCESS (clk_25, reset)
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
508 IO0 <= '0';
509 IO1 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
557 IO8 <= '0';
558 IO9 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
561 WHEN "11" =>
562 IO0 <= '0';
562 IO0 <= '0';
563 IO1 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
574 WHEN OTHERS => NULL;
575 END CASE;
575 END CASE;
576
576
577 END IF;
577 END IF;
578 END PROCESS;
578 END PROCESS;
579
579
580 END beh; No newline at end of file
580 END beh;
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@@ -1,121 +1,122
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 LIBRARY IEEE;
23 use IEEE.std_logic_1164.all;
23 USE IEEE.std_logic_1164.ALL;
24 use IEEE.numeric_std.all;
24 USE IEEE.numeric_std.ALL;
25
25
26 entity Driver_FFT is
26 ENTITY Driver_FFT IS
27 generic(
27 GENERIC(
28 Data_sz : integer range 1 to 32 := 16;
28 Data_sz : INTEGER RANGE 1 TO 32 := 16;
29 NbData : integer range 1 to 512 := 256
29 NbData : INTEGER RANGE 1 TO 512 := 256
30 );
30 );
31 port(
31 PORT(
32 clk : in std_logic;
32 clk : IN STD_LOGIC;
33 rstn : in std_logic;
33 rstn : IN STD_LOGIC;
34 Load : in std_logic;
34 Load : IN STD_LOGIC; -- (CoreFFT) FFT_Load
35 Empty : in std_logic_vector(4 downto 0);
35 -- Load
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
36 Empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); -- FifoIN_Empty
37 Valid : out std_logic;
37 DATA : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0); -- FifoIN_Data
38 Read : out std_logic_vector(4 downto 0);
38 Valid : OUT STD_LOGIC; --(CoreFFT) Drive_write
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
39 Read : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); -- Read
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
40 Data_re : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --(CoreFFT) Drive_DataRE
41 );
41 Data_im : OUT STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0) --(CoreFFT) Drive_DataIM
42 end entity;
42 );
43 END ENTITY;
43
44
44
45
45 architecture ar_Driver of Driver_FFT is
46 ARCHITECTURE ar_Driver OF Driver_FFT IS
46
47
47 type etat is (eX,e0,e1,e2);
48 TYPE etat IS (eX, e0, e1, e2);
48 signal ect : etat;
49 SIGNAL ect : etat;
49
50
50 signal DataCount : integer range 0 to 255 := 0;
51 SIGNAL DataCount : INTEGER RANGE 0 TO 255 := 0;
51 signal FifoCpt : integer range 0 to 4 := 0;
52 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
52
53
53 signal sLoad : std_logic;
54 SIGNAL sLoad : STD_LOGIC;
54
55
55 begin
56 BEGIN
56
57
57 process(clk,rstn)
58 PROCESS(clk, rstn)
58 begin
59 BEGIN
59 if(rstn='0')then
60 IF(rstn = '0')then
60 ect <= e0;
61 ect <= e0;
61 Read <= (others => '1');
62 Read <= (OTHERS => '1');
62 Valid <= '0';
63 Valid <= '0';
63 Data_re <= (others => '0');
64 Data_re <= (OTHERS => '0');
64 Data_im <= (others => '0');
65 Data_im <= (OTHERS => '0');
65 DataCount <= 0;
66 DataCount <= 0;
66 FifoCpt <= 0;
67 FifoCpt <= 0;
67 sLoad <= '0';
68 sLoad <= '0';
68
69
69 elsif(clk'event and clk='1')then
70 ELSIF(clk'EVENT AND clk = '1')then
70 sLoad <= Load;
71 sLoad <= Load;
71
72
72 if(sLoad='1' and Load='0')then
73 IF(sLoad = '1' and Load = '0')THEN
73 if(FifoCpt=4)then
74 IF(FifoCpt = 4)THEN
74 FifoCpt <= 0;
75 FifoCpt <= 0;
75 else
76 ELSE
76 FifoCpt <= FifoCpt + 1;
77 FifoCpt <= FifoCpt + 1;
77 end if;
78 END IF;
78 end if;
79 END IF;
79
80
80 case ect is
81 CASE ect IS
81
82
82 when e0 =>
83 WHEN e0 =>
83 if(Load='1' and Empty(FifoCpt)='0')then
84 IF(Load = '1' and Empty(FifoCpt) = '0')THEN
84 Read(FifoCpt) <= '0';
85 Read(FifoCpt) <= '0';
85 ect <= e1;
86 ect <= e1;
86 end if;
87 END IF;
87
88
88 when e1 =>
89 WHEN e1 =>
89 Valid <= '0';
90 Valid <= '0';
90 Read(FifoCpt) <= '1';
91 Read(FifoCpt) <= '1';
91 ect <= e2;
92 ect <= e2;
92
93
93 when e2 =>
94 WHEN e2 =>
94 Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz));
95 Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz));
95 Data_im <= (others => '0');
96 Data_im <= (OTHERS => '0');
96 Valid <= '1';
97 Valid <= '1';
97 if(DataCount=NbData-1)then
98 IF(DataCount = NbData-1)THEN
98 DataCount <= 0;
99 DataCount <= 0;
99 ect <= eX;
100 ect <= eX;
100 else
101 ELSE
101 DataCount <= DataCount + 1;
102 DataCount <= DataCount + 1;
102 if(Load='1' and Empty(FifoCpt)='0')then
103 IF(Load = '1' and Empty(FifoCpt) = '0')THEN
103 Read(FifoCpt) <= '0';
104 Read(FifoCpt) <= '0';
104 ect <= e1;
105 ect <= e1;
105 else
106 ELSE
106 ect <= eX;
107 ect <= eX;
107 end if;
108 END IF;
108 end if;
109 END IF;
109
110
110 when eX =>
111 WHEN eX =>
111 Valid <= '0';
112 Valid <= '0';
112 ect <= e0;
113 ect <= e0;
113
114
114 when others =>
115 WHEN OTHERS =>
115 null;
116 NULL;
116
117
117 end case;
118 END CASE;
118 end if;
119 END IF;
119 end process;
120 END PROCESS;
120
121
121 end architecture; No newline at end of file
122 END ARCHITECTURE;
Show file before | Show file after | Hide comments
@@ -1,100 +1,105
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_fft.all;
26 use lpp.lpp_fft.all;
27 use lpp.fft_components.all;
27 use lpp.fft_components.all;
28
28
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
29 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "crοΏ½neau"
30
30
31 entity FFT is
31 entity FFT is
32 generic(
32 generic(
33 Data_sz : integer := 16;
33 Data_sz : integer := 16;
34 NbData : integer := 256);
34 NbData : integer := 256);
35 port(
35 port(
36 clkm : in std_logic;
36 clkm : in std_logic;
37 rstn : in std_logic;
37 rstn : in std_logic;
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
38 FifoIN_Empty : in std_logic_vector(4 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
39 FifoIN_Data : in std_logic_vector(79 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 FifoOUT_Full : in std_logic_vector(4 downto 0);
41 Load : out std_logic;
41 Load : out std_logic;
42 Read : out std_logic_vector(4 downto 0);
42 Read : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
43 Write : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
44 ReUse : out std_logic_vector(4 downto 0);
45 Data : out std_logic_vector(79 downto 0)
45 Data : out std_logic_vector(79 downto 0)
46 );
46 );
47 end entity;
47 end entity;
48
48
49
49
50 architecture ar_FFT of FFT is
50 architecture ar_FFT of FFT is
51
51
52 signal Drive_Write : std_logic;
52 signal Drive_Write : std_logic;
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
53 signal Drive_DataRE : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
54 signal Drive_DataIM : std_logic_vector(15 downto 0);
55
55
56 signal Start : std_logic;
56 signal Start : std_logic;
57 signal FFT_Load : std_logic;
57 signal FFT_Load : std_logic;
58 signal FFT_Ready : std_logic;
58 signal FFT_Ready : std_logic;
59 signal FFT_Valid : std_logic;
59 signal FFT_Valid : std_logic;
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
60 signal FFT_DataRE : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
61 signal FFT_DataIM : std_logic_vector(15 downto 0);
62
62
63 signal Link_Read : std_logic;
63 signal Link_Read : std_logic;
64
64
65 begin
65 begin
66
66
67 Start <= '0';
67 Start <= '0';
68 Load <= FFT_Load;
68 Load <= FFT_Load;
69
69
70 DRIVE : Driver_FFT
70 DRIVE : Driver_FFT
71 generic map(Data_sz,NbData)
71 generic map(Data_sz,NbData)
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
72 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
73
73
74 FFT0 : CoreFFT
74 FFT0 : CoreFFT
75 generic map(
75 generic map(
76 LOGPTS => gLOGPTS,
76 LOGPTS => gLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
77 LOGLOGPTS => gLOGLOGPTS,
78 WSIZE => gWSIZE,
78 WSIZE => gWSIZE,
79 TWIDTH => gTWIDTH,
79 TWIDTH => gTWIDTH,
80 DWIDTH => gDWIDTH,
80 DWIDTH => gDWIDTH,
81 TDWIDTH => gTDWIDTH,
81 TDWIDTH => gTDWIDTH,
82 RND_MODE => gRND_MODE,
82 RND_MODE => gRND_MODE,
83 SCALE_MODE => gSCALE_MODE,
83 SCALE_MODE => gSCALE_MODE,
84 PTS => gPTS,
84 PTS => gPTS,
85 HALFPTS => gHALFPTS,
85 HALFPTS => gHALFPTS,
86 inBuf_RWDLY => gInBuf_RWDLY)
86 inBuf_RWDLY => gInBuf_RWDLY)
87 port map(clkm,start,rstn,
87 port map(clkm,start,rstn,
88 Drive_Write,Link_Read,
88 Drive_Write, -- ifiD_valid
89 Drive_DataIM,Drive_DataRE,
89 Link_Read, -- ifiRead_y
90 FFT_Load,open,
90 Drive_DataIM, -- ifiD_im
91 FFT_DataIM,FFT_DataRE,
91 Drive_DataRE, -- ifiD_re
92 FFT_Valid,FFT_Ready);
92 FFT_Load, -- ifoLoad
93 open, -- ifoPong
94 FFT_DataIM, -- ifoY_im
95 FFT_DataRE, -- ifoY_re
96 FFT_Valid, -- ifiY_valid
97 FFT_Ready); -- ifiY_rdy
93
98
94
99
95 LINK : Linker_FFT
100 LINK : Linker_FFT
96 generic map(Data_sz,NbData)
101 generic map(Data_sz,NbData)
97 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
102 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
98
103
99
104
100 end architecture;
105 end architecture;
Show file before | Show file after | Hide comments
@@ -1,112 +1,113
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 LIBRARY IEEE;
23 use IEEE.std_logic_1164.all;
23 USE IEEE.std_logic_1164.ALL;
24 use IEEE.numeric_std.all;
24 USE IEEE.numeric_std.ALL;
25
25
26 entity Linker_FFT is
26 ENTITY Linker_FFT IS
27 generic(
27 GENERIC(
28 Data_sz : integer range 1 to 32 := 16;
28 Data_sz : INTEGER RANGE 1 TO 32 := 16;
29 NbData : integer range 1 to 512 := 256
29 NbData : INTEGER RANGE 1 TO 512 := 256
30 );
30 );
31 port(
31 PORT(
32 clk : in std_logic;
32 clk : IN STD_LOGIC;
33 rstn : in std_logic;
33 rstn : IN STD_LOGIC;
34 Ready : in std_logic;
34 Ready : IN STD_LOGIC; --
35 Valid : in std_logic;
35 Valid : IN STD_LOGIC; --
36 Full : in std_logic_vector(4 downto 0);
36 Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --
37 Data_re : in std_logic_vector(Data_sz-1 downto 0);
37 Data_re : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
38 Data_im : in std_logic_vector(Data_sz-1 downto 0);
38 Data_im : IN STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0); --
39 Read : out std_logic;
39
40 Write : out std_logic_vector(4 downto 0);
40 Read : OUT STD_LOGIC; -- Link_Read
41 ReUse : out std_logic_vector(4 downto 0);
41 Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --
42 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
42 ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 );
43 DATA : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
44 end entity;
44 );
45 END ENTITY;
45
46
46
47
47 architecture ar_Linker of Linker_FFT is
48 ARCHITECTURE ar_Linker OF Linker_FFT IS
48
49
49 type etat is (eX,e0,e1,e2);
50 TYPE etat IS (eX, e0, e1, e2);
50 signal ect : etat;
51 SIGNAL ect : etat;
51
52
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
53 SIGNAL DataTmp : STD_LOGIC_VECTOR(Data_sz-1 DOWNTO 0);
53
54
54 signal sRead : std_logic;
55 SIGNAL sRead : STD_LOGIC;
55 signal sReady : std_logic;
56 SIGNAL sReady : STD_LOGIC;
56
57
57 signal FifoCpt : integer range 0 to 4 := 0;
58 SIGNAL FifoCpt : INTEGER RANGE 0 TO 4 := 0;
58
59
59 begin
60 BEGIN
60
61
61 process(clk,rstn)
62 PROCESS(clk, rstn)
62 begin
63 BEGIN
63 if(rstn='0')then
64 IF(rstn = '0')then
64 ect <= e0;
65 ect <= e0;
65 sRead <= '0';
66 sRead <= '0';
66 sReady <= '0';
67 sReady <= '0';
67 Write <= (others => '1');
68 Write <= (OTHERS => '1');
68 Reuse <= (others => '0');
69 Reuse <= (OTHERS => '0');
69 FifoCpt <= 0;
70 FifoCpt <= 0;
70
71
71 elsif(clk'event and clk='1')then
72 ELSIF(clk'EVENT AND clk = '1')then
72 sReady <= Ready;
73 sReady <= Ready;
73
74
74 if(sReady='1' and Ready='0')then
75 IF(sReady = '1' and Ready = '0')THEN
75 if(FifoCpt=4)then
76 IF(FifoCpt = 4)THEN
76 FifoCpt <= 0;
77 FifoCpt <= 0;
77 else
78 ELSE
78 FifoCpt <= FifoCpt + 1;
79 FifoCpt <= FifoCpt + 1;
79 end if;
80 END IF;
80 elsif(Ready='1')then
81 ELSIF(Ready = '1')then
81 sRead <= not sRead;
82 sRead <= NOT sRead;
82 else
83 ELSE
83 sRead <= '0';
84 sRead <= '0';
84 end if;
85 END IF;
85
86
86 case ect is
87 CASE ect IS
87
88
88 when e0 =>
89 WHEN e0 =>
89 Write(FifoCpt) <= '1';
90 Write(FifoCpt) <= '1';
90 if(Valid='1' and Full(FifoCpt)='0')then
91 IF(Valid = '1' and Full(FifoCpt) = '0')THEN
91 DataTmp <= Data_im;
92 DataTmp <= Data_im;
92 DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re;
93 DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= Data_re;
93 Write(FifoCpt) <= '0';
94 Write(FifoCpt) <= '0';
94 ect <= e1;
95 ect <= e1;
95 elsif(Full(FifoCpt)='1')then
96 ELSIF(Full(FifoCpt) = '1')then
96 ReUse(FifoCpt) <= '1';
97 ReUse(FifoCpt) <= '1';
97 end if;
98 END IF;
98
99
99 when e1 =>
100 WHEN e1 =>
100 DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp;
101 DATA(((FifoCpt+1)*Data_sz)-1 DOWNTO (FifoCpt*Data_sz)) <= DataTmp;
101 ect <= e0;
102 ect <= e0;
102
103
103 when others =>
104 WHEN OTHERS =>
104 null;
105 NULL;
105
106
106 end case;
107 END CASE;
107 end if;
108 END IF;
108 end process;
109 END PROCESS;
109
110
110 Read <= sRead;
111 Read <= sRead;
111
112
112 end architecture; No newline at end of file
113 END ARCHITECTURE;
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@@ -1,170 +1,173
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 -- Update : Jean-christophe Pellion
23 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
24 ------------------------------------------------------------------------------
22 library IEEE;
25 LIBRARY IEEE;
23 use IEEE.std_logic_1164.all;
26 USE IEEE.std_logic_1164.ALL;
24 use IEEE.numeric_std.all;
27 USE IEEE.numeric_std.ALL;
25
28
26 entity DEMUX is
29 ENTITY DEMUX IS
27 generic(
30 GENERIC(
28 Data_sz : integer range 1 to 32 := 16);
31 Data_sz : INTEGER RANGE 1 TO 32 := 16);
29 port(
32 PORT(
30 clk : in std_logic;
33 clk : IN STD_LOGIC;
31 rstn : in std_logic;
34 rstn : IN STD_LOGIC;
32
35
33 Read : in std_logic_vector(4 downto 0);
36 Read : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 Load : in std_logic;
37 Load : IN STD_LOGIC;
35
38
36 EmptyF0 : in std_logic_vector(4 downto 0);
39 EmptyF0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 EmptyF1 : in std_logic_vector(4 downto 0);
40 EmptyF1 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 EmptyF2 : in std_logic_vector(4 downto 0);
41 EmptyF2 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39
42
40 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF0 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF1 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
45 DataF2 : IN STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0);
43
46
44 WorkFreq : out std_logic_vector(1 downto 0);
47 WorkFreq : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
45 Read_DEMUX : out std_logic_vector(14 downto 0);
48 Read_DEMUX : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
46 Empty : out std_logic_vector(4 downto 0);
49 Empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
50 Data : OUT STD_LOGIC_VECTOR((5*Data_sz)-1 DOWNTO 0)
48 );
51 );
49 end entity;
52 END ENTITY;
50
53
51
54
52 architecture ar_DEMUX of DEMUX is
55 ARCHITECTURE ar_DEMUX OF DEMUX IS
53
56
54 type etat is (eX,e0,e1,e2,e3);
57 TYPE etat IS (eX, e0, e1, e2, e3);
55 signal ect : etat;
58 SIGNAL ect : etat;
56
59
57
60
58 signal load_reg : std_logic;
61 SIGNAL load_reg : STD_LOGIC;
59 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
62 CONSTANT Dummy_Read : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
60
63
61 signal Countf0 : integer;
64 SIGNAL Countf0 : INTEGER;
62 signal Countf1 : integer;
65 SIGNAL Countf1 : INTEGER;
63 signal i : integer;
66 SIGNAL i : INTEGER;
64
67
65 begin
68 BEGIN
66 process(clk,rstn)
69 PROCESS(clk, rstn)
67 begin
70 BEGIN
68 if(rstn='0')then
71 IF(rstn = '0')then
69 ect <= e0;
72 ect <= e0;
70 load_reg <= '0';
73 load_reg <= '0';
71 Countf0 <= 0;
74 Countf0 <= 0;
72 Countf1 <= 0;
75 Countf1 <= 0;
73 i <= 0;
76 i <= 0;
74
77
75 elsif(clk'event and clk='1')then
78 ELSIF(clk'EVENT AND clk = '1')then
76 load_reg <= Load;
79 load_reg <= Load;
77
80
78 case ect is
81 CASE ect IS
79
82
80 when e0 =>
83 WHEN e0 =>
81 if(load_reg = '1' and Load = '0')then
84 IF(load_reg = '1' AND Load = '0')THEN
82 if(Countf0 = 24)then
85 IF(Countf0 = 24)THEN
83 Countf0 <= 0;
86 Countf0 <= 0;
84 ect <= e1;
87 ect <= e1;
85 else
88 ELSE
86 Countf0 <= Countf0 + 1;
89 Countf0 <= Countf0 + 1;
87 ect <= e0;
90 ect <= e0;
88 end if;
91 END IF;
89 end if;
92 END IF;
90
93
91 when e1 =>
94 WHEN e1 =>
92 if(load_reg = '1' and Load = '0')then
95 IF(load_reg = '1' AND Load = '0')THEN
93 if(Countf1 = 74)then
96 IF(Countf1 = 74)THEN
94 Countf1 <= 0;
97 Countf1 <= 0;
95 ect <= e2;
98 ect <= e2;
96 else
99 ELSE
97 Countf1 <= Countf1 + 1;
100 Countf1 <= Countf1 + 1;
98 if(i=4)then
101 IF(i = 4)THEN
99 i <= 0;
102 i <= 0;
100 ect <= e0;
103 ect <= e0;
101 else
104 ELSE
102 i <= i+1;
105 i <= i+1;
103 ect <= e1;
106 ect <= e1;
104 end if;
107 END IF;
105 end if;
108 END IF;
106 end if;
109 END IF;
107
110
108 when e2 =>
111 WHEN e2 =>
109 if(load_reg = '1' and Load = '0')then
112 IF(load_reg = '1' AND Load = '0')THEN
110 if(i=4)then
113 IF(i = 4)THEN
111 i <= 0;
114 i <= 0;
112 ect <= e0;
115 ect <= e0;
113 else
116 ELSE
114 i <= i+1;
117 i <= i+1;
115 ect <= e2;
118 ect <= e2;
116 end if;
119 END IF;
117 end if;
120 END IF;
118
121
119 when others =>
122 WHEN OTHERS =>
120 null;
123 NULL;
121
124
122 end case;
125 END CASE;
123 end if;
126 END IF;
124 end process;
127 END PROCESS;
125
128
126 with ect select
129 WITH ect SELECT
127 Empty <= EmptyF0 when e0,
130 Empty <= EmptyF0 WHEN e0,
128 EmptyF1 when e1,
131 EmptyF1 WHEN e1,
129 EmptyF2 when e2,
132 EmptyF2 WHEN e2,
130 (others => '1') when others;
133 (OTHERS => '1') WHEN OTHERS;
131
134
132 with ect select
135 WITH ect SELECT
133 Data <= DataF0 when e0,
136 Data <= DataF0 WHEN e0,
134 DataF1 when e1,
137 DataF1 WHEN e1,
135 DataF2 when e2,
138 DataF2 WHEN e2,
136 (others => '0') when others;
139 (OTHERS => '0') WHEN OTHERS;
137
140
138 with ect select
141 WITH ect SELECT
139 Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
142 Read_DEMUX <= Dummy_Read & Dummy_Read & Read WHEN e0,
140 Dummy_Read & Read & Dummy_Read when e1,
143 Dummy_Read & Read & Dummy_Read WHEN e1,
141 Read & Dummy_Read & Dummy_Read when e2,
144 Read & Dummy_Read & Dummy_Read WHEN e2,
142 (others => '1') when others;
145 (OTHERS => '1') WHEN OTHERS;
143
146
144 with ect select
147 WITH ect SELECT
145 WorkFreq <= "01" when e0,
148 WorkFreq <= "01" WHEN e0,
146 "10" when e1,
149 "10" WHEN e1,
147 "11" when e2,
150 "11" WHEN e2,
148 "00" when others;
151 "00" WHEN OTHERS;
149
152
150 end architecture;
153 END ARCHITECTURE;
151
154
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153
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@@ -1,85 +1,85
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_matrix.all;
26 use lpp.lpp_matrix.all;
27
27
28 entity MatriceSpectrale is
28 entity MatriceSpectrale is
29 generic(
29 generic(
30 Input_SZ : integer := 16;
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
31 Result_SZ : integer := 32);
32 port(
32 port(
33 clkm : in std_logic;
33 clkm : in std_logic;
34 rstn : in std_logic;
34 rstn : in std_logic;
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0); --
37 SetReUse : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0); --
38 Valid : in std_logic;
38 Valid : in std_logic;
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); --
40 ACK : in std_logic;
40 ACK : in std_logic;
41 SM_Write : out std_logic;
41 SM_Write : out std_logic;
42 FlagError : out std_logic;
42 FlagError : out std_logic;
43 Statu : out std_logic_vector(3 downto 0);
43 Statu : out std_logic_vector(3 downto 0);
44 Write : out std_logic_vector(1 downto 0);
44 Write : out std_logic_vector(1 downto 0);
45 Read : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0); --
46 ReUse : out std_logic_vector(4 downto 0);
46 ReUse : out std_logic_vector(4 downto 0); --
47 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
47 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
48 );
48 );
49 end entity;
49 end entity;
50
50
51
51
52 architecture ar_MatriceSpectrale of MatriceSpectrale is
52 architecture ar_MatriceSpectrale of MatriceSpectrale is
53
53
54 signal Matrix_Write : std_logic;
54 signal Matrix_Write : std_logic;
55 signal Matrix_Read : std_logic_vector(1 downto 0);
55 signal Matrix_Read : std_logic_vector(1 downto 0);
56 signal Matrix_Result : std_logic_vector(31 downto 0);
56 signal Matrix_Result : std_logic_vector(31 downto 0);
57
57
58 signal TopSM_Start : std_logic;
58 signal TopSM_Start : std_logic;
59 signal TopSM_Statu : std_logic_vector(3 downto 0);
59 signal TopSM_Statu : std_logic_vector(3 downto 0);
60 signal TopSM_Data1 : std_logic_vector(15 downto 0);
60 signal TopSM_Data1 : std_logic_vector(15 downto 0);
61 signal TopSM_Data2 : std_logic_vector(15 downto 0);
61 signal TopSM_Data2 : std_logic_vector(15 downto 0);
62
62
63 begin
63 begin
64
64
65 CTRL0 : ReUse_CTRLR
65 CTRL0 : ReUse_CTRLR
66 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
66 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
67
67
68
68
69 TopSM : TopSpecMatrix
69 TopSM : TopSpecMatrix
70 generic map (Input_SZ)
70 generic map (Input_SZ)
71 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
71 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
72
72
73 SM : SpectralMatrix
73 SM : SpectralMatrix
74 generic map (Input_SZ,Result_SZ)
74 generic map (Input_SZ,Result_SZ)
75 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
75 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
76
76
77 DISP : Dispatch
77 DISP : Dispatch
78 generic map(Result_SZ)
78 generic map(Result_SZ)
79 port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError);
79 port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError);
80
80
81 Statu <= TopSM_Statu;
81 Statu <= TopSM_Statu;
82 SM_Write <= Matrix_Write;
82 SM_Write <= Matrix_Write;
83
83
84 end architecture;
84 end architecture;
85
85
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@@ -1,394 +1,394
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 --USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 --USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
20 USE lpp.lpp_lfr_pkg.ALL;
21
21
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
26 USE GRLIB.DMA2AHB_Package.ALL;
27
27
28
28
29 ENTITY lpp_lfr_ms IS
29 ENTITY lpp_lfr_ms IS
30 GENERIC (
30 GENERIC (
31 Mem_use : INTEGER := use_RAM
31 Mem_use : INTEGER := use_RAM
32 );
32 );
33 PORT (
33 PORT (
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36
36
37 ---------------------------------------------------------------------------
37 ---------------------------------------------------------------------------
38 -- DATA INPUT
38 -- DATA INPUT
39 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
40 -- TIME
40 -- TIME
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
41 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
42 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
43 --
43 --
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
46 --
46 --
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 --
49 --
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
52
52
53 ---------------------------------------------------------------------------
53 ---------------------------------------------------------------------------
54 -- DMA
54 -- DMA
55 ---------------------------------------------------------------------------
55 ---------------------------------------------------------------------------
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
57 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_valid : OUT STD_LOGIC;
58 dma_valid : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
59 dma_valid_burst : OUT STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
60 dma_ren : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
61 dma_done : IN STD_LOGIC;
62
62
63 -- Reg out
63 -- Reg out
64 ready_matrix_f0_0 : OUT STD_LOGIC;
64 ready_matrix_f0_0 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
65 ready_matrix_f0_1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
66 ready_matrix_f1 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
67 ready_matrix_f2 : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
68 error_anticipating_empty_fifo : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
69 error_bad_component_error : OUT STD_LOGIC;
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71
71
72 -- Reg In
72 -- Reg In
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
73 status_ready_matrix_f0_0 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
74 status_ready_matrix_f0_1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
75 status_ready_matrix_f1 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
76 status_ready_matrix_f2 :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
77 status_error_anticipating_empty_fifo :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
78 status_error_bad_component_error :IN STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
90 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
91
91
92 );
92 );
93 END;
93 END;
94
94
95 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
95 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
100 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
101 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
101 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
102 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
102 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
103
103
104 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
105 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
106 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
108 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
108 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 SIGNAL FFT_Load : STD_LOGIC;
111 SIGNAL FFT_Load : STD_LOGIC;
112 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
115 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
119 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
120
120
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 SIGNAL SM_FlagError : STD_LOGIC;
122 SIGNAL SM_FlagError : STD_LOGIC;
123 -- SIGNAL SM_Pong : STD_LOGIC;
123 -- SIGNAL SM_Pong : STD_LOGIC;
124 SIGNAL SM_Wen : STD_LOGIC;
124 SIGNAL SM_Wen : STD_LOGIC;
125 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
129 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
130
130
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
134 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
138 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL Head_Empty : STD_LOGIC;
139 SIGNAL Head_Empty : STD_LOGIC;
140 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL Head_Valid : STD_LOGIC;
141 SIGNAL Head_Valid : STD_LOGIC;
142 SIGNAL Head_Val : STD_LOGIC;
142 SIGNAL Head_Val : STD_LOGIC;
143
143
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 SIGNAL DMA_Read : STD_LOGIC;
145 SIGNAL DMA_Read : STD_LOGIC;
146 SIGNAL DMA_ack : STD_LOGIC;
146 SIGNAL DMA_ack : STD_LOGIC;
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
149 SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
150
150
151 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL dma_valid_s : STD_LOGIC;
152 SIGNAL dma_valid_s : STD_LOGIC;
153 SIGNAL dma_valid_burst_s : STD_LOGIC;
153 SIGNAL dma_valid_burst_s : STD_LOGIC;
154
154
155 BEGIN
155 BEGIN
156
156
157 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
158 Memf0: lppFIFOxN
158 Memf0: lppFIFOxN
159 GENERIC MAP (
159 GENERIC MAP (
160 tech => 0, Mem_use => Mem_use, Data_sz => 16,
160 tech => 0, Mem_use => Mem_use, Data_sz => 16,
161 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
161 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
162 PORT MAP (
162 PORT MAP (
163 rstn => rstn, wclk => clk, rclk => clk,
163 rstn => rstn, wclk => clk, rclk => clk,
164 ReUse => (OTHERS => '0'),
164 ReUse => (OTHERS => '0'),
165 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
165 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
166 wdata => sample_f0_wdata, rdata => FifoF0_Data,
166 wdata => sample_f0_wdata, rdata => FifoF0_Data,
167 full => OPEN, empty => FifoF0_Empty);
167 full => OPEN, empty => FifoF0_Empty);
168
168
169 Memf1: lppFIFOxN
169 Memf1: lppFIFOxN
170 GENERIC MAP (
170 GENERIC MAP (
171 tech => 0, Mem_use => Mem_use, Data_sz => 16,
171 tech => 0, Mem_use => Mem_use, Data_sz => 16,
172 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
172 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
173 PORT MAP (
173 PORT MAP (
174 rstn => rstn, wclk => clk, rclk => clk,
174 rstn => rstn, wclk => clk, rclk => clk,
175 ReUse => (OTHERS => '0'),
175 ReUse => (OTHERS => '0'),
176 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
176 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
177 wdata => sample_f1_wdata, rdata => FifoF1_Data,
177 wdata => sample_f1_wdata, rdata => FifoF1_Data,
178 full => OPEN, empty => FifoF1_Empty);
178 full => OPEN, empty => FifoF1_Empty);
179
179
180
180
181 Memf2: lppFIFOxN
181 Memf2: lppFIFOxN
182 GENERIC MAP (
182 GENERIC MAP (
183 tech => 0, Mem_use => Mem_use, Data_sz => 16,
183 tech => 0, Mem_use => Mem_use, Data_sz => 16,
184 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
184 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
185 PORT MAP (
185 PORT MAP (
186 rstn => rstn, wclk => clk, rclk => clk,
186 rstn => rstn, wclk => clk, rclk => clk,
187 ReUse => (OTHERS => '0'),
187 ReUse => (OTHERS => '0'),
188 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
188 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
189 wdata => sample_f3_wdata, rdata => FifoF3_Data,
189 wdata => sample_f3_wdata, rdata => FifoF3_Data,
190 full => OPEN, empty => FifoF3_Empty);
190 full => OPEN, empty => FifoF3_Empty);
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192
192
193
193
194 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
195 DMUX0 : DEMUX
195 DMUX0 : DEMUX
196 GENERIC MAP (
196 GENERIC MAP (
197 Data_sz => 16)
197 Data_sz => 16)
198 PORT MAP (
198 PORT MAP (
199 clk => clk,
199 clk => clk,
200 rstn => rstn,
200 rstn => rstn,
201 Read => FFT_Read,
201 Read => FFT_Read,
202 Load => FFT_Load,
202 Load => FFT_Load,
203 EmptyF0 => FifoF0_Empty,
203 EmptyF0 => FifoF0_Empty,
204 EmptyF1 => FifoF1_Empty,
204 EmptyF1 => FifoF1_Empty,
205 EmptyF2 => FifoF3_Empty,
205 EmptyF2 => FifoF3_Empty,
206 DataF0 => FifoF0_Data,
206 DataF0 => FifoF0_Data,
207 DataF1 => FifoF1_Data,
207 DataF1 => FifoF1_Data,
208 DataF2 => FifoF3_Data,
208 DataF2 => FifoF3_Data,
209 WorkFreq => DMUX_WorkFreq,
209 WorkFreq => DMUX_WorkFreq,
210 Read_DEMUX => DMUX_Read,
210 Read_DEMUX => DMUX_Read,
211 Empty => DMUX_Empty,
211 Empty => DMUX_Empty,
212 Data => DMUX_Data);
212 Data => DMUX_Data);
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214
214
215
215
216 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
217 FFT0: FFT
217 FFT0: FFT
218 GENERIC MAP (
218 GENERIC MAP (
219 Data_sz => 16,
219 Data_sz => 16,
220 NbData => 256)
220 NbData => 256)
221 PORT MAP (
221 PORT MAP (
222 clkm => clk,
222 clkm => clk,
223 rstn => rstn,
223 rstn => rstn,
224 FifoIN_Empty => DMUX_Empty,
224 FifoIN_Empty => DMUX_Empty,
225 FifoIN_Data => DMUX_Data,
225 FifoIN_Data => DMUX_Data,
226 FifoOUT_Full => FifoINT_Full,
226 FifoOUT_Full => FifoINT_Full,
227 Load => FFT_Load,
227 Load => FFT_Load,
228 Read => FFT_Read,
228 Read => FFT_Read,
229 Write => FFT_Write,
229 Write => FFT_Write,
230 ReUse => FFT_ReUse,
230 ReUse => FFT_ReUse,
231 Data => FFT_Data);
231 Data => FFT_Data);
232 -----------------------------------------------------------------------------
232 -----------------------------------------------------------------------------
233
233
234
234
235 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
236 MemInt : lppFIFOxN
236 MemInt : lppFIFOxN
237 GENERIC MAP (
237 GENERIC MAP (
238 tech => 0,
238 tech => 0,
239 Mem_use => Mem_use,
239 Mem_use => Mem_use,
240 Data_sz => 16,
240 Data_sz => 16,
241 Addr_sz => 8,
241 Addr_sz => 8,
242 FifoCnt => 5,
242 FifoCnt => 5,
243 Enable_ReUse => '1')
243 Enable_ReUse => '1')
244 PORT MAP (
244 PORT MAP (
245 rstn => rstn,
245 rstn => rstn,
246 wclk => clk,
246 wclk => clk,
247 rclk => clk,
247 rclk => clk,
248 ReUse => SM_ReUse,
248 ReUse => SM_ReUse,
249 wen => FFT_Write,
249 wen => FFT_Write,
250 ren => SM_Read,
250 ren => SM_Read,
251 wdata => FFT_Data,
251 wdata => FFT_Data,
252 rdata => FifoINT_Data,
252 rdata => FifoINT_Data,
253 full => FifoINT_Full,
253 full => FifoINT_Full,
254 empty => OPEN);
254 empty => OPEN);
255 -----------------------------------------------------------------------------
255 -----------------------------------------------------------------------------
256
256
257 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
258 SM0 : MatriceSpectrale
258 SM0 : MatriceSpectrale
259 GENERIC MAP (
259 GENERIC MAP (
260 Input_SZ => 16,
260 Input_SZ => 16,
261 Result_SZ => 32)
261 Result_SZ => 32)
262 PORT MAP (
262 PORT MAP (
263 clkm => clk,
263 clkm => clk,
264 rstn => rstn,
264 rstn => rstn,
265 FifoIN_Full => FifoINT_Full,
265 FifoIN_Full => FifoINT_Full, --
266 SetReUse => FFT_ReUse,
266 SetReUse => FFT_ReUse, --
267 Valid => Head_Valid,
267 Valid => Head_Valid, -- HeaderBuilder
268 Data_IN => FifoINT_Data,
268 Data_IN => FifoINT_Data, --
269 ACK => DMA_ack,
269 ACK => DMA_ack, -- HeaderBuilder
270 SM_Write => SM_Wen,
270 SM_Write => SM_Wen, -- HeaderBuilder
271 FlagError => SM_FlagError,
271 FlagError => SM_FlagError, -- UNUSED
272 -- Pong => SM_Pong,
272 -- Pong => SM_Pong,
273 Statu => SM_Param,
273 Statu => SM_Param, -- HeaderBuilder
274 Write => SM_Write,
274 Write => SM_Write, -- FIFO MemOut
275 Read => SM_Read,
275 Read => SM_Read, --
276 ReUse => SM_ReUse,
276 ReUse => SM_ReUse, --
277 Data_OUT => SM_Data);
277 Data_OUT => SM_Data); -- FIFO MemOut
278 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 MemOut : lppFIFOxN
281 MemOut : lppFIFOxN
282 GENERIC MAP (
282 GENERIC MAP (
283 tech => 0,
283 tech => 0,
284 Mem_use => Mem_use,
284 Mem_use => Mem_use,
285 Data_sz => 32,
285 Data_sz => 32,
286 Addr_sz => 8,
286 Addr_sz => 8,
287 FifoCnt => 2,
287 FifoCnt => 2,
288 Enable_ReUse => '0')
288 Enable_ReUse => '0')
289 PORT MAP (
289 PORT MAP (
290 rstn => rstn,
290 rstn => rstn,
291 wclk => clk,
291 wclk => clk,
292 rclk => clk,
292 rclk => clk,
293 ReUse => (OTHERS => '0'),
293 ReUse => (OTHERS => '0'),
294 wen => SM_Write,
294 wen => SM_Write,
295 ren => Head_Read,
295 ren => Head_Read,
296 wdata => SM_Data,
296 wdata => SM_Data,
297 rdata => FifoOUT_Data,
297 rdata => FifoOUT_Data,
298 full => FifoOUT_Full,
298 full => FifoOUT_Full,
299 empty => FifoOUT_Empty);
299 empty => FifoOUT_Empty);
300 -----------------------------------------------------------------------------
300 -----------------------------------------------------------------------------
301
301
302 -----------------------------------------------------------------------------
302 -----------------------------------------------------------------------------
303 Head0 : HeaderBuilder
303 Head0 : HeaderBuilder
304 GENERIC MAP (
304 GENERIC MAP (
305 Data_sz => 32)
305 Data_sz => 32)
306 PORT MAP (
306 PORT MAP (
307 clkm => clk,
307 clkm => clk,
308 rstn => rstn,
308 rstn => rstn,
309 -- pong => SM_Pong,
309 -- pong => SM_Pong,
310 Statu => SM_Param,
310 Statu => SM_Param,
311 Matrix_Type => DMUX_WorkFreq,
311 Matrix_Type => DMUX_WorkFreq,
312 Matrix_Write => SM_Wen,
312 Matrix_Write => SM_Wen,
313 Valid => Head_Valid,
313 Valid => Head_Valid,
314
314
315 dataIN => FifoOUT_Data,
315 dataIN => FifoOUT_Data,
316 emptyIN => FifoOUT_Empty,
316 emptyIN => FifoOUT_Empty,
317 RenOUT => Head_Read,
317 RenOUT => Head_Read,
318
318
319 dataOUT => Head_Data,
319 dataOUT => Head_Data,
320 emptyOUT => Head_Empty,
320 emptyOUT => Head_Empty,
321 RenIN => DMA_Read,
321 RenIN => DMA_Read,
322
322
323 header => Head_Header,
323 header => Head_Header,
324 header_val => Head_Val,
324 header_val => Head_Val,
325 header_ack => DMA_ack );
325 header_ack => DMA_ack );
326 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
327 data_time(31 DOWNTO 0) <= coarse_time;
327 data_time(31 DOWNTO 0) <= coarse_time;
328 data_time(47 DOWNTO 32) <= fine_time;
328 data_time(47 DOWNTO 32) <= fine_time;
329
329
330 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
330 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
331 PORT MAP (
331 PORT MAP (
332 HCLK => clk,
332 HCLK => clk,
333 HRESETn => rstn,
333 HRESETn => rstn,
334
334
335 data_time => data_time,
335 data_time => data_time,
336
336
337 fifo_data => Head_Data,
337 fifo_data => Head_Data,
338 fifo_empty => Head_Empty,
338 fifo_empty => Head_Empty,
339 fifo_ren => DMA_Read,
339 fifo_ren => DMA_Read,
340
340
341 header => Head_Header,
341 header => Head_Header,
342 header_val => Head_Val,
342 header_val => Head_Val,
343 header_ack => DMA_ack,
343 header_ack => DMA_ack,
344
344
345 dma_addr => dma_addr,
345 dma_addr => dma_addr,
346 dma_data => dma_data,
346 dma_data => dma_data,
347 dma_valid => dma_valid_s,
347 dma_valid => dma_valid_s,
348 dma_valid_burst => dma_valid_burst_s,
348 dma_valid_burst => dma_valid_burst_s,
349 dma_ren => dma_ren,
349 dma_ren => dma_ren,
350 dma_done => dma_done,
350 dma_done => dma_done,
351
351
352 ready_matrix_f0_0 => ready_matrix_f0_0,
352 ready_matrix_f0_0 => ready_matrix_f0_0,
353 ready_matrix_f0_1 => ready_matrix_f0_1,
353 ready_matrix_f0_1 => ready_matrix_f0_1,
354 ready_matrix_f1 => ready_matrix_f1,
354 ready_matrix_f1 => ready_matrix_f1,
355 ready_matrix_f2 => ready_matrix_f2,
355 ready_matrix_f2 => ready_matrix_f2,
356 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
356 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
357 error_bad_component_error => error_bad_component_error,
357 error_bad_component_error => error_bad_component_error,
358 debug_reg => debug_reg_s,
358 debug_reg => debug_reg_s,
359 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
359 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
360 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
360 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
361 status_ready_matrix_f1 => status_ready_matrix_f1,
361 status_ready_matrix_f1 => status_ready_matrix_f1,
362 status_ready_matrix_f2 => status_ready_matrix_f2,
362 status_ready_matrix_f2 => status_ready_matrix_f2,
363 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
363 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
364 status_error_bad_component_error => status_error_bad_component_error,
364 status_error_bad_component_error => status_error_bad_component_error,
365 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
365 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
366 config_active_interruption_onError => config_active_interruption_onError,
366 config_active_interruption_onError => config_active_interruption_onError,
367 addr_matrix_f0_0 => addr_matrix_f0_0,
367 addr_matrix_f0_0 => addr_matrix_f0_0,
368 addr_matrix_f0_1 => addr_matrix_f0_1,
368 addr_matrix_f0_1 => addr_matrix_f0_1,
369 addr_matrix_f1 => addr_matrix_f1,
369 addr_matrix_f1 => addr_matrix_f1,
370 addr_matrix_f2 => addr_matrix_f2,
370 addr_matrix_f2 => addr_matrix_f2,
371
371
372 matrix_time_f0_0 => matrix_time_f0_0,
372 matrix_time_f0_0 => matrix_time_f0_0,
373 matrix_time_f0_1 => matrix_time_f0_1,
373 matrix_time_f0_1 => matrix_time_f0_1,
374 matrix_time_f1 => matrix_time_f1,
374 matrix_time_f1 => matrix_time_f1,
375 matrix_time_f2 => matrix_time_f2
375 matrix_time_f2 => matrix_time_f2
376 );
376 );
377
377
378 dma_valid <= dma_valid_s;
378 dma_valid <= dma_valid_s;
379 dma_valid_burst <= dma_valid_burst_s;
379 dma_valid_burst <= dma_valid_burst_s;
380
380
381 debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0);
381 debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0);
382 debug_reg(10) <= Head_Empty;
382 debug_reg(10) <= Head_Empty;
383 debug_reg(11) <= DMA_Read;
383 debug_reg(11) <= DMA_Read;
384 debug_reg(12) <= Head_Val;
384 debug_reg(12) <= Head_Val;
385 debug_reg(13) <= DMA_ack;
385 debug_reg(13) <= DMA_ack;
386 debug_reg(14) <= dma_ren;
386 debug_reg(14) <= dma_ren;
387 debug_reg(15) <= dma_done;
387 debug_reg(15) <= dma_done;
388 debug_reg(16) <= dma_valid_s;
388 debug_reg(16) <= dma_valid_s;
389 debug_reg(17) <= dma_valid_burst_s;
389 debug_reg(17) <= dma_valid_burst_s;
390 debug_reg(31 DOWNTO 18) <= (OTHERS => '0');
390 debug_reg(31 DOWNTO 18) <= (OTHERS => '0');
391
391
392
392
393
393
394 END Behavioral;
394 END Behavioral;
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@@ -1,431 +1,431
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26 LIBRARY ieee;
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
29 LIBRARY grlib;
30 USE grlib.amba.ALL;
30 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
32 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 LIBRARY lpp;
34 LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.lpp_dma_pkg.ALL;
39 LIBRARY techmap;
39 LIBRARY techmap;
40 USE techmap.gencomp.ALL;
40 USE techmap.gencomp.ALL;
41
41
42
42
43 ENTITY lpp_lfr_ms_fsmdma IS
43 ENTITY lpp_lfr_ms_fsmdma IS
44 PORT (
44 PORT (
45 -- AMBA AHB system signals
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
48
49 --TIME
49 --TIME
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
50 data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51
51
52 -- fifo interface
52 -- fifo interface
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 fifo_empty : IN STD_LOGIC;
54 fifo_empty : IN STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
55 fifo_ren : OUT STD_LOGIC;
56
56
57 -- header
57 -- header
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 header_val : IN STD_LOGIC;
59 header_val : IN STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
60 header_ack : OUT STD_LOGIC;
61
61
62 -- DMA
62 -- DMA
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 dma_valid : OUT STD_LOGIC;
65 dma_valid : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
66 dma_valid_burst : OUT STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
67 dma_ren : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
68 dma_done : IN STD_LOGIC;
69
69
70 -- Reg out
70 -- Reg out
71 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_0 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f0_1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f1 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
74 ready_matrix_f2 : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_anticipating_empty_fifo : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
76 error_bad_component_error : OUT STD_LOGIC;
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78
78
79 -- Reg In
79 -- Reg In
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
80 status_ready_matrix_f0_0 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
81 status_ready_matrix_f0_1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
82 status_ready_matrix_f1 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
83 status_ready_matrix_f2 : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
84 status_error_anticipating_empty_fifo : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
85 status_error_bad_component_error : IN STD_LOGIC;
86
86
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onNewMatrix : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
88 config_active_interruption_onError : IN STD_LOGIC;
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93
93
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
96 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
97 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
98
98
99 );
99 );
100 END;
100 END;
101
101
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
102 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -- SIGNAL DMAIn : DMA_In_Type;
104 -- SIGNAL DMAIn : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
105 -- SIGNAL header_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
106 -- SIGNAL component_dmai : DMA_In_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
107 -- SIGNAL DMAOut : DMA_OUt_Type;
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 TYPE state_DMAWriteBurst IS (IDLE,
112 TYPE state_DMAWriteBurst IS (IDLE,
113 CHECK_COMPONENT_TYPE,
113 CHECK_COMPONENT_TYPE,
114 WRITE_COARSE_TIME,
114 WRITE_COARSE_TIME,
115 WRITE_FINE_TIME,
115 WRITE_FINE_TIME,
116 TRASH_FIFO,
116 TRASH_FIFO,
117 SEND_DATA,
117 SEND_DATA,
118 WAIT_DATA_ACK
118 WAIT_DATA_ACK
119 );
119 );
120 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
120 SIGNAL state : state_DMAWriteBurst; -- := IDLE;
121
121
122 -- SIGNAL nbSend : INTEGER;
122 -- SIGNAL nbSend : INTEGER;
123 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
123 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
124 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
124 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL header_check_ok : STD_LOGIC;
126 SIGNAL header_check_ok : STD_LOGIC;
127 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL send_matrix : STD_LOGIC;
128 SIGNAL send_matrix : STD_LOGIC;
129 -- SIGNAL request : STD_LOGIC;
129 -- SIGNAL request : STD_LOGIC;
130 -- SIGNAL remaining_data_request : INTEGER;
130 -- SIGNAL remaining_data_request : INTEGER;
131 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
134 SIGNAL header_select : STD_LOGIC;
134 SIGNAL header_select : STD_LOGIC;
135
135
136 SIGNAL header_send : STD_LOGIC;
136 SIGNAL header_send : STD_LOGIC;
137 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL header_send_ok : STD_LOGIC;
138 SIGNAL header_send_ok : STD_LOGIC;
139 SIGNAL header_send_ko : STD_LOGIC;
139 SIGNAL header_send_ko : STD_LOGIC;
140
140
141 SIGNAL component_send : STD_LOGIC;
141 SIGNAL component_send : STD_LOGIC;
142 SIGNAL component_send_ok : STD_LOGIC;
142 SIGNAL component_send_ok : STD_LOGIC;
143 SIGNAL component_send_ko : STD_LOGIC;
143 SIGNAL component_send_ko : STD_LOGIC;
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145 SIGNAL fifo_ren_trash : STD_LOGIC;
145 SIGNAL fifo_ren_trash : STD_LOGIC;
146 SIGNAL component_fifo_ren : STD_LOGIC;
146 SIGNAL component_fifo_ren : STD_LOGIC;
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
151
151
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 SIGNAL log_empty_fifo : STD_LOGIC;
153 SIGNAL log_empty_fifo : STD_LOGIC;
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL header_reg_val : STD_LOGIC;
156 SIGNAL header_reg_val : STD_LOGIC;
157 SIGNAL header_reg_ack : STD_LOGIC;
157 SIGNAL header_reg_ack : STD_LOGIC;
158 SIGNAL header_error : STD_LOGIC;
158 SIGNAL header_error : STD_LOGIC;
159
159
160 BEGIN
160 BEGIN
161
161
162 debug_reg <= debug_reg_s;
162 debug_reg <= debug_reg_s;
163
163
164
164
165 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
165 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
166 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
166 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
167 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
167 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
168 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
168 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
169 '0';
169 '0';
170
170
171 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
171 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
172 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
172 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
173 '1' WHEN component_type = component_type_pre + "0001" ELSE
173 '1' WHEN component_type = component_type_pre + "0001" ELSE
174 '0';
174 '0';
175
175
176 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
176 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
177 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
177 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
178 addr_matrix_f1 WHEN matrix_type = "10" ELSE
178 addr_matrix_f1 WHEN matrix_type = "10" ELSE
179 addr_matrix_f2 WHEN matrix_type = "11" ELSE
179 addr_matrix_f2 WHEN matrix_type = "11" ELSE
180 (OTHERS => '0');
180 (OTHERS => '0');
181
181
182 -----------------------------------------------------------------------------
182 -----------------------------------------------------------------------------
183 -- DMA control
183 -- DMA control
184 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
185 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
186 BEGIN -- PROCESS DMAWriteBurst_p
186 BEGIN -- PROCESS DMAWriteBurst_p
187 IF HRESETn = '0' THEN -- asynchronous reset (active low)
187 IF HRESETn = '0' THEN -- asynchronous reset (active low)
188 matrix_type <= (OTHERS => '0');
188 matrix_type <= (OTHERS => '0');
189 component_type <= (OTHERS => '0');
189 component_type <= (OTHERS => '0');
190 state <= IDLE;
190 state <= IDLE;
191 -- header_ack <= '0';
191 -- header_ack <= '0';
192 ready_matrix_f0_0 <= '0';
192 ready_matrix_f0_0 <= '0';
193 ready_matrix_f0_1 <= '0';
193 ready_matrix_f0_1 <= '0';
194 ready_matrix_f1 <= '0';
194 ready_matrix_f1 <= '0';
195 ready_matrix_f2 <= '0';
195 ready_matrix_f2 <= '0';
196 error_anticipating_empty_fifo <= '0';
196 error_anticipating_empty_fifo <= '0';
197 error_bad_component_error <= '0';
197 error_bad_component_error <= '0';
198 component_type_pre <= "0000";
198 component_type_pre <= "0000";
199 fifo_ren_trash <= '1';
199 fifo_ren_trash <= '1';
200 component_send <= '0';
200 component_send <= '0';
201 address <= (OTHERS => '0');
201 address <= (OTHERS => '0');
202 header_select <= '0';
202 header_select <= '0';
203 header_send <= '0';
203 header_send <= '0';
204 header_data <= (OTHERS => '0');
204 header_data <= (OTHERS => '0');
205 fine_time_reg <= (OTHERS => '0');
205 fine_time_reg <= (OTHERS => '0');
206
206
207 debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0');
207 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
208 debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
208 debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
209
209
210 log_empty_fifo <= '0';
210 log_empty_fifo <= '0';
211
211
212 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
212 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
213 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
213 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
214 header_reg_ack <= '0';
214 header_reg_ack <= '0';
215
215
216 CASE state IS
216 CASE state IS
217 WHEN IDLE =>
217 WHEN IDLE =>
218 debug_reg_s(2 DOWNTO 0) <= "000";
218 debug_reg_s(2 DOWNTO 0) <= "000";
219
219
220 matrix_type <= header(1 DOWNTO 0);
220 --matrix_type <= header(1 DOWNTO 0);
221 --component_type <= header(5 DOWNTO 2);
221 --component_type <= header(5 DOWNTO 2);
222
222
223 ready_matrix_f0_0 <= '0';
223 ready_matrix_f0_0 <= '0';
224 ready_matrix_f0_1 <= '0';
224 ready_matrix_f0_1 <= '0';
225 ready_matrix_f1 <= '0';
225 ready_matrix_f1 <= '0';
226 ready_matrix_f2 <= '0';
226 ready_matrix_f2 <= '0';
227 error_bad_component_error <= '0';
227 error_bad_component_error <= '0';
228 header_select <= '1';
228 --header_select <= '1';
229
229
230 IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
230 IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
231 header_reg_ack <= '1';
231 header_reg_ack <= '1';
232 debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
232 debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
233 debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
233 debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
234
234
235 matrix_type <= header_reg(1 DOWNTO 0);
235 matrix_type <= header_reg(1 DOWNTO 0);
236 component_type <= header_reg(5 DOWNTO 2);
236 component_type <= header_reg(5 DOWNTO 2);
237 component_type_pre <= component_type;
237 component_type_pre <= component_type;
238 state <= CHECK_COMPONENT_TYPE;
238 state <= CHECK_COMPONENT_TYPE;
239 END IF;
239 END IF;
240 log_empty_fifo <= '0';
240 log_empty_fifo <= '0';
241
241
242 WHEN CHECK_COMPONENT_TYPE =>
242 WHEN CHECK_COMPONENT_TYPE =>
243 debug_reg_s(2 DOWNTO 0) <= "001";
243 debug_reg_s(2 DOWNTO 0) <= "001";
244 --header_ack <= '0';
244 --header_ack <= '0';
245
245
246 IF header_check_ok = '1' THEN
246 IF header_check_ok = '1' THEN
247 header_send <= '0';
247 header_send <= '0';
248 --
248 --
249 IF component_type = "0000" THEN
249 IF component_type = "0000" THEN
250 address <= address_matrix;
250 address <= address_matrix;
251 CASE matrix_type IS
251 CASE matrix_type IS
252 WHEN "00" => matrix_time_f0_0 <= data_time;
252 WHEN "00" => matrix_time_f0_0 <= data_time;
253 WHEN "01" => matrix_time_f0_1 <= data_time;
253 WHEN "01" => matrix_time_f0_1 <= data_time;
254 WHEN "10" => matrix_time_f1 <= data_time;
254 WHEN "10" => matrix_time_f1 <= data_time;
255 WHEN "11" => matrix_time_f2 <= data_time ;
255 WHEN "11" => matrix_time_f2 <= data_time;
256 WHEN OTHERS => NULL;
256 WHEN OTHERS => NULL;
257 END CASE;
257 END CASE;
258
258
259 header_data <= data_time(31 DOWNTO 0);
259 header_data <= data_time(31 DOWNTO 0);
260 fine_time_reg <= data_time(47 DOWNTO 32);
260 fine_time_reg <= data_time(47 DOWNTO 32);
261 --state <= WRITE_COARSE_TIME;
261 --state <= WRITE_COARSE_TIME;
262 --header_send <= '1';
262 --header_send <= '1';
263 state <= SEND_DATA;
263 state <= SEND_DATA;
264 header_send <= '0';
264 header_send <= '0';
265 component_send <= '1';
265 component_send <= '1';
266 header_select <= '0';
266 header_select <= '0';
267 ELSE
267 ELSE
268 state <= SEND_DATA;
268 state <= SEND_DATA;
269 END IF;
269 END IF;
270 --
270 --
271 ELSE
271 ELSE
272 error_bad_component_error <= '1';
272 error_bad_component_error <= '1';
273 component_type_pre <= "0000";
273 component_type_pre <= "0000";
274 state <= TRASH_FIFO;
274 state <= TRASH_FIFO;
275 END IF;
275 END IF;
276
276
277 --WHEN WRITE_COARSE_TIME =>
277 --WHEN WRITE_COARSE_TIME =>
278 -- debug_reg_s(2 DOWNTO 0) <= "010";
278 -- debug_reg_s(2 DOWNTO 0) <= "010";
279
279
280 -- header_ack <= '0';
280 -- header_ack <= '0';
281
281
282 -- IF dma_ren = '0' THEN
282 -- IF dma_ren = '0' THEN
283 -- header_send <= '0';
283 -- header_send <= '0';
284 -- ELSE
284 -- ELSE
285 -- header_send <= header_send;
285 -- header_send <= header_send;
286 -- END IF;
286 -- END IF;
287
287
288
288
289 -- IF header_send_ko = '1' THEN
289 -- IF header_send_ko = '1' THEN
290 -- header_send <= '0';
290 -- header_send <= '0';
291 -- state <= TRASH_FIFO;
291 -- state <= TRASH_FIFO;
292 -- error_anticipating_empty_fifo <= '1';
292 -- error_anticipating_empty_fifo <= '1';
293 -- -- TODO : error sending header
293 -- -- TODO : error sending header
294 -- ELSIF header_send_ok = '1' THEN
294 -- ELSIF header_send_ok = '1' THEN
295 -- header_send <= '1';
295 -- header_send <= '1';
296 -- header_select <= '1';
296 -- header_select <= '1';
297 -- header_data(15 DOWNTO 0) <= fine_time_reg;
297 -- header_data(15 DOWNTO 0) <= fine_time_reg;
298 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
298 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
299 -- state <= WRITE_FINE_TIME;
299 -- state <= WRITE_FINE_TIME;
300 -- address <= address + 4;
300 -- address <= address + 4;
301 -- END IF;
301 -- END IF;
302
302
303
303
304 --WHEN WRITE_FINE_TIME =>
304 --WHEN WRITE_FINE_TIME =>
305 -- debug_reg_s(2 DOWNTO 0) <= "011";
305 -- debug_reg_s(2 DOWNTO 0) <= "011";
306
307 -- header_ack <= '0';
308
306
309 -- IF dma_ren = '0' THEN
307 -- header_ack <= '0';
310 -- header_send <= '0';
308
311 -- ELSE
309 -- IF dma_ren = '0' THEN
312 -- header_send <= header_send;
310 -- header_send <= '0';
313 -- END IF;
311 -- ELSE
312 -- header_send <= header_send;
313 -- END IF;
314
314
315 -- IF header_send_ko = '1' THEN
315 -- IF header_send_ko = '1' THEN
316 -- header_send <= '0';
316 -- header_send <= '0';
317 -- state <= TRASH_FIFO;
317 -- state <= TRASH_FIFO;
318 -- error_anticipating_empty_fifo <= '1';
318 -- error_anticipating_empty_fifo <= '1';
319 -- -- TODO : error sending header
319 -- -- TODO : error sending header
320 -- ELSIF header_send_ok = '1' THEN
320 -- ELSIF header_send_ok = '1' THEN
321 -- header_send <= '0';
321 -- header_send <= '0';
322 -- header_select <= '0';
322 -- header_select <= '0';
323 -- state <= SEND_DATA;
323 -- state <= SEND_DATA;
324 -- address <= address + 4;
324 -- address <= address + 4;
325 -- END IF;
325 -- END IF;
326
326
327 WHEN TRASH_FIFO =>
327 WHEN TRASH_FIFO =>
328 debug_reg_s(2 DOWNTO 0) <= "100";
328 debug_reg_s(2 DOWNTO 0) <= "100";
329
329
330 -- header_ack <= '0';
330 -- header_ack <= '0';
331 error_bad_component_error <= '0';
331 error_bad_component_error <= '0';
332 error_anticipating_empty_fifo <= '0';
332 error_anticipating_empty_fifo <= '0';
333 IF fifo_empty = '1' THEN
333 IF fifo_empty = '1' THEN
334 state <= IDLE;
334 state <= IDLE;
335 fifo_ren_trash <= '1';
335 fifo_ren_trash <= '1';
336 ELSE
336 ELSE
337 fifo_ren_trash <= '0';
337 fifo_ren_trash <= '0';
338 END IF;
338 END IF;
339
339
340 WHEN SEND_DATA =>
340 WHEN SEND_DATA =>
341 -- header_ack <= '0';
341 -- header_ack <= '0';
342 debug_reg_s(2 DOWNTO 0) <= "101";
342 debug_reg_s(2 DOWNTO 0) <= "101";
343
343
344 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
344 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
345 state <= IDLE;
345 state <= IDLE;
346 IF component_type = "1110" THEN --"1110" -- JC
346 IF component_type = "1110" THEN --"1110" -- JC
347 CASE matrix_type IS
347 CASE matrix_type IS
348 WHEN "00" => ready_matrix_f0_0 <= '1';
348 WHEN "00" => ready_matrix_f0_0 <= '1';
349 WHEN "01" => ready_matrix_f0_1 <= '1';
349 WHEN "01" => ready_matrix_f0_1 <= '1';
350 WHEN "10" => ready_matrix_f1 <= '1';
350 WHEN "10" => ready_matrix_f1 <= '1';
351 WHEN "11" => ready_matrix_f2 <= '1';
351 WHEN "11" => ready_matrix_f2 <= '1';
352 WHEN OTHERS => NULL;
352 WHEN OTHERS => NULL;
353 END CASE;
353 END CASE;
354
354
355 END IF;
355 END IF;
356 ELSE
356 ELSE
357 component_send <= '1';
357 component_send <= '1';
358 address <= address;
358 address <= address;
359 state <= WAIT_DATA_ACK;
359 state <= WAIT_DATA_ACK;
360 END IF;
360 END IF;
361
361
362 WHEN WAIT_DATA_ACK =>
362 WHEN WAIT_DATA_ACK =>
363 log_empty_fifo <= fifo_empty OR log_empty_fifo;
363 log_empty_fifo <= fifo_empty OR log_empty_fifo;
364
364
365 debug_reg_s(2 DOWNTO 0) <= "110";
365 debug_reg_s(2 DOWNTO 0) <= "110";
366
366
367 component_send <= '0';
367 component_send <= '0';
368 IF component_send_ok = '1' THEN
368 IF component_send_ok = '1' THEN
369 address <= address + 64;
369 address <= address + 64;
370 state <= SEND_DATA;
370 state <= SEND_DATA;
371 ELSIF component_send_ko = '1' THEN
371 ELSIF component_send_ko = '1' THEN
372 error_anticipating_empty_fifo <= '0';
372 error_anticipating_empty_fifo <= '0';
373 state <= TRASH_FIFO;
373 state <= TRASH_FIFO;
374 END IF;
374 END IF;
375
375
376
376
377 --WHEN CHECK_LENGTH =>
377 --WHEN CHECK_LENGTH =>
378 -- component_send <= '0';
378 -- component_send <= '0';
379 -- debug_reg_s(2 DOWNTO 0) <= "111";
379 -- debug_reg_s(2 DOWNTO 0) <= "111";
380 -- state <= IDLE;
380 -- state <= IDLE;
381
381
382 WHEN OTHERS => NULL;
382 WHEN OTHERS => NULL;
383 END CASE;
383 END CASE;
384
384
385 END IF;
385 END IF;
386 END PROCESS DMAWriteFSM_p;
386 END PROCESS DMAWriteFSM_p;
387
387
388 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
388 dma_valid_burst <= '0' WHEN header_select = '1' ELSE component_send;
389 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
389 dma_valid <= header_send WHEN header_select = '1' ELSE '0';
390 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
390 dma_data <= header_data WHEN header_select = '1' ELSE fifo_data;
391 dma_addr <= address;
391 dma_addr <= address;
392 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
392 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
393
393
394 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
394 component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
395 component_send_ko <= '0';
395 component_send_ko <= '0';
396
396
397 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
397 header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
398 header_send_ko <= '0';
398 header_send_ko <= '0';
399
399
400
400
401 -----------------------------------------------------------------------------
401 -----------------------------------------------------------------------------
402 -- FSM HEADER ACK
402 -- FSM HEADER ACK
403 -----------------------------------------------------------------------------
403 -----------------------------------------------------------------------------
404 PROCESS (HCLK, HRESETn)
404 PROCESS (HCLK, HRESETn)
405 BEGIN -- PROCESS
405 BEGIN -- PROCESS
406 IF HRESETn = '0' THEN -- asynchronous reset (active low)
406 IF HRESETn = '0' THEN -- asynchronous reset (active low)
407 header_ack <= '0';
407 header_ack <= '0';
408 header_reg <= (OTHERS => '0');
408 header_reg <= (OTHERS => '0');
409 header_reg_val <= '0';
409 header_reg_val <= '0';
410 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
410 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
411 header_ack <= '0';
411 header_ack <= '0';
412
412
413 IF header_val = '1' THEN
413 IF header_val = '1' THEN
414 header_ack <= '1';
414 header_ack <= '1';
415 header_reg <= header;
415 header_reg <= header;
416 END IF;
416 END IF;
417
417
418 IF header_val = '1' THEN
418 IF header_val = '1' THEN
419 header_reg_val <= '1';
419 header_reg_val <= '1';
420 ELSIF header_reg_ack = '1' THEN
420 ELSIF header_reg_ack = '1' THEN
421 header_reg_val <= '0';
421 header_reg_val <= '0';
422 END IF;
422 END IF;
423
423
424 header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack);
424 header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack);
425
425
426 END IF;
426 END IF;
427 END PROCESS;
427 END PROCESS;
428
428
429 debug_reg_s(3) <= header_error;
429 debug_reg_s(3) <= header_error;
430
430
431 END Behavioral; No newline at end of file
431 END Behavioral;
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