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r322:2019ae31f08d (LFR-EM) LPP_LFR-em_WFP_1-0-0 JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY LFR_em IS
49
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
55 errorn : OUT STD_ULOGIC;
56 -- UART AHB ---------------------------------------------------------------
57 ahbrxd : IN STD_ULOGIC; -- DSU rx data
58 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
59 -- UART APB ---------------------------------------------------------------
60 urxd1 : IN STD_ULOGIC; -- UART1 rx data
61 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
62 -- RAM --------------------------------------------------------------------
63 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
64 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 nSRAM_BE0 : OUT STD_LOGIC;
66 nSRAM_BE1 : OUT STD_LOGIC;
67 nSRAM_BE2 : OUT STD_LOGIC;
68 nSRAM_BE3 : OUT STD_LOGIC;
69 nSRAM_WE : OUT STD_LOGIC;
70 nSRAM_CE : OUT STD_LOGIC;
71 nSRAM_OE : OUT STD_LOGIC;
72 -- SPW --------------------------------------------------------------------
73 spw1_din : IN STD_LOGIC;
74 spw1_sin : IN STD_LOGIC;
75 spw1_dout : OUT STD_LOGIC;
76 spw1_sout : OUT STD_LOGIC;
77 spw2_din : IN STD_LOGIC;
78 spw2_sin : IN STD_LOGIC;
79 spw2_dout : OUT STD_LOGIC;
80 spw2_sout : OUT STD_LOGIC;
81 -- ADC --------------------------------------------------------------------
82 bias_fail_sw : OUT STD_LOGIC;
83 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
84 ADC_smpclk : OUT STD_LOGIC;
85 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
86 ---------------------------------------------------------------------------
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
89
90 END LFR_em;
91
92
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 --
101 -- UART AHB ---------------------------------------------------------------
102 --SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
103 --SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
104
105 -- UART APB ---------------------------------------------------------------
106 --SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
107 --SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
108 --
109 -- CONSTANTS
110 CONSTANT CFG_PADTECH : INTEGER := inferred;
111 --
112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
115
116 SIGNAL apbi_ext : apb_slv_in_type;
117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
122
123 -- Spacewire signals
124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL spw_rxtxclk : STD_ULOGIC;
128 SIGNAL spw_rxclkn : STD_ULOGIC;
129 SIGNAL spw_clk : STD_LOGIC;
130 SIGNAL swni : grspw_in_type;
131 SIGNAL swno : grspw_out_type;
132 -- SIGNAL clkmn : STD_ULOGIC;
133 -- SIGNAL txclk : STD_ULOGIC;
134
135 --GPIO
136 SIGNAL gpioi : gpio_in_type;
137 SIGNAL gpioo : gpio_out_type;
138
139 -- AD Converter ADS7886
140 SIGNAL sample : Samples14v(7 DOWNTO 0);
141 SIGNAL sample_val : STD_LOGIC;
142 SIGNAL ADC_nCS_sig : STD_LOGIC;
143 SIGNAL ADC_CLK_sig : STD_LOGIC;
144 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
145
146 --SIGNAL bias_fail_sw_sig : STD_LOGIC;
147
148 -----------------------------------------------------------------------------
149 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
150
151 -----------------------------------------------------------------------------
152 SIGNAL rstn : STD_LOGIC;
153 BEGIN -- beh
154
155 -----------------------------------------------------------------------------
156 -- CLK
157 -----------------------------------------------------------------------------
158 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
159
160 PROCESS(clk100MHz)
161 BEGIN
162 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
163 clk_50_s <= NOT clk_50_s;
164 END IF;
165 END PROCESS;
166
167 PROCESS(clk_50_s)
168 BEGIN
169 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
170 clk_25 <= NOT clk_25;
171 END IF;
172 END PROCESS;
173
174 PROCESS(clk49_152MHz)
175 BEGIN
176 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
177 clk_24 <= NOT clk_24;
178 END IF;
179 END PROCESS;
180
181 -----------------------------------------------------------------------------
182
183 PROCESS (clk_25, rstn)
184 BEGIN -- PROCESS
185 IF rstn = '0' THEN -- asynchronous reset (active low)
186 led(0) <= '0';
187 led(1) <= '0';
188 led(2) <= '0';
189 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
190 led(0) <= '0';
191 led(1) <= '1';
192 led(2) <= '1';
193 END IF;
194 END PROCESS;
195
196 --
197 leon3_soc_1 : leon3_soc
198 GENERIC MAP (
199 fabtech => apa3e,
200 memtech => apa3e,
201 padtech => inferred,
202 clktech => inferred,
203 disas => 0,
204 dbguart => 0,
205 pclow => 2,
206 clk_freq => 25000,
207 NB_CPU => 1,
208 ENABLE_FPU => 1,
209 FPU_NETLIST => 0,
210 ENABLE_DSU => 1,
211 ENABLE_AHB_UART => 1,
212 ENABLE_APB_UART => 1,
213 ENABLE_IRQMP => 1,
214 ENABLE_GPT => 1,
215 NB_AHB_MASTER => NB_AHB_MASTER,
216 NB_AHB_SLAVE => NB_AHB_SLAVE,
217 NB_APB_SLAVE => NB_APB_SLAVE)
218 PORT MAP (
219 clk => clk_25,
220 reset => rstn,
221 errorn => errorn,
222 ahbrxd => ahbrxd,
223 ahbtxd => ahbtxd,
224 urxd1 => urxd1,
225 utxd1 => utxd1,
226 address => address,
227 data => data,
228 nSRAM_BE0 => nSRAM_BE0,
229 nSRAM_BE1 => nSRAM_BE1,
230 nSRAM_BE2 => nSRAM_BE2,
231 nSRAM_BE3 => nSRAM_BE3,
232 nSRAM_WE => nSRAM_WE,
233 nSRAM_CE => nSRAM_CE,
234 nSRAM_OE => nSRAM_OE,
235
236 apbi_ext => apbi_ext,
237 apbo_ext => apbo_ext,
238 ahbi_s_ext => ahbi_s_ext,
239 ahbo_s_ext => ahbo_s_ext,
240 ahbi_m_ext => ahbi_m_ext,
241 ahbo_m_ext => ahbo_m_ext);
242
243 -------------------------------------------------------------------------------
244 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
245 -------------------------------------------------------------------------------
246 apb_lfr_time_management_1 : apb_lfr_time_management
247 GENERIC MAP (
248 pindex => 6,
249 paddr => 6,
250 pmask => 16#fff#,
251 pirq => 12,
252 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
253 PORT MAP (
254 clk25MHz => clk_25,
255 clk49_152MHz => clk_24, -- 49.152MHz/2
256 resetn => rstn,
257 grspw_tick => swno.tickout,
258 apbi => apbi_ext,
259 apbo => apbo_ext(6),
260 coarse_time => coarse_time,
261 fine_time => fine_time);
262
263 -----------------------------------------------------------------------
264 --- SpaceWire --------------------------------------------------------
265 -----------------------------------------------------------------------
266
267 -- SPW_EN <= '1';
268
269 spw_clk <= clk_50_s;
270 spw_rxtxclk <= spw_clk;
271 spw_rxclkn <= NOT spw_rxtxclk;
272
273 -- PADS for SPW1
274 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
275 PORT MAP (spw1_din, dtmp(0));
276 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
277 PORT MAP (spw1_sin, stmp(0));
278 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
279 PORT MAP (spw1_dout, swno.d(0));
280 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
281 PORT MAP (spw1_sout, swno.s(0));
282 -- PADS FOR SPW2
283 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
284 PORT MAP (spw2_sin, dtmp(1));
285 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
286 PORT MAP (spw2_din, stmp(1));
287 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
288 PORT MAP (spw2_dout, swno.d(1));
289 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
290 PORT MAP (spw2_sout, swno.s(1));
291
292 -- GRSPW PHY
293 --spw1_input: if CFG_SPW_GRSPW = 1 generate
294 spw_inputloop : FOR j IN 0 TO 1 GENERATE
295 spw_phy0 : grspw_phy
296 GENERIC MAP(
297 tech => apa3e,
298 rxclkbuftype => 1,
299 scantest => 0)
300 PORT MAP(
301 rxrst => swno.rxrst,
302 di => dtmp(j),
303 si => stmp(j),
304 rxclko => spw_rxclk(j),
305 do => swni.d(j),
306 ndo => swni.nd(j*5+4 DOWNTO j*5),
307 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
308 END GENERATE spw_inputloop;
309
310 -- SPW core
311 sw0 : grspwm GENERIC MAP(
312 tech => apa3e,
313 hindex => 1,
314 pindex => 5,
315 paddr => 5,
316 pirq => 11,
317 sysfreq => 25000, -- CPU_FREQ
318 rmap => 1,
319 rmapcrc => 1,
320 fifosize1 => 16,
321 fifosize2 => 16,
322 rxclkbuftype => 1,
323 rxunaligned => 0,
324 rmapbufs => 4,
325 ft => 0,
326 netlist => 0,
327 ports => 2,
328 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
329 memtech => apa3e,
330 destkey => 2,
331 spwcore => 1
332 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
333 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
334 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
335 )
336 PORT MAP(rstn, clk_25, spw_rxclk(0),
337 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
338 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
339 swni, swno);
340
341 swni.tickin <= '0';
342 swni.rmapen <= '1';
343 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
344 swni.tickinraw <= '0';
345 swni.timein <= (OTHERS => '0');
346 swni.dcrstval <= (OTHERS => '0');
347 swni.timerrstval <= (OTHERS => '0');
348
349 -------------------------------------------------------------------------------
350 -- LFR ------------------------------------------------------------------------
351 -------------------------------------------------------------------------------
352 lpp_lfr_1 : lpp_lfr_WFP_nMS
353 GENERIC MAP (
354 Mem_use => use_RAM,
355 nb_data_by_buffer_size => 32,
356 nb_word_by_buffer_size => 30,
357 nb_snapshot_param_size => 32,
358 delta_vector_size => 32,
359 delta_vector_size_f0_2 => 7, -- log2(96)
360 pindex => 15,
361 paddr => 15,
362 pmask => 16#fff#,
363 pirq_ms => 6,
364 pirq_wfp => 14,
365 hindex => 2,
366 top_lfr_version => X"010000") -- aa.bb.cc version
367 -- AA : BOARD NUMBER
368 -- 0 => MINI_LFR
369 -- 1 => EM
370 PORT MAP (
371 clk => clk_25,
372 rstn => rstn,
373 sample_B => sample(2 DOWNTO 0),
374 sample_E => sample(7 DOWNTO 3),
375 sample_val => sample_val,
376 apbi => apbi_ext,
377 apbo => apbo_ext(15),
378 ahbi => ahbi_m_ext,
379 ahbo => ahbo_m_ext(2),
380 coarse_time => coarse_time,
381 fine_time => fine_time,
382 data_shaping_BW => bias_fail_sw,
383 observation_reg => observation_reg);
384
385 -----------------------------------------------------------------------------
386 --
387 -----------------------------------------------------------------------------
388 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
389 GENERIC MAP (
390 ChanelCount => 8,
391 ncycle_cnv_high => 40, -- TODO : 79
392 ncycle_cnv => 250) -- TODO : 500
393 PORT MAP (
394 cnv_clk => clk_24, -- TODO : 49.152
395 cnv_rstn => rstn, -- ok
396 cnv => ADC_smpclk, -- ok
397 clk => clk_25, -- ok
398 rstn => rstn, -- ok
399 ADC_data => ADC_data, -- ok
400 ADC_nOE => ADC_OEB_bar_CH, -- ok
401 sample => sample, -- ok
402 sample_val => sample_val); -- ok
403
404 END beh; No newline at end of file
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
25 ENTITY lpp_lfr_WFP_nMS IS
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
39
40 hindex : INTEGER := 2;
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
44 );
45 PORT (
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
52 -- APB
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
62 data_shaping_BW : OUT STD_LOGIC;
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
106 END lpp_lfr_WFP_nMS;
107
108 ARCHITECTURE beh OF lpp_lfr_WFP_nMS IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
117 -- SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 -- SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 -- SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
131 --SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 --SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 --SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
135 -- SM
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
209 -----------------------------------------------------------------------------
210 --
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
228 -----------------------------------------------------------------------------
229 -- DMA RR
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
240 -----------------------------------------------------------------------------
241 -- DMA_REG
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
250
251 -----------------------------------------------------------------------------
252 -- DMA
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
262 -----------------------------------------------------------------------------
263 -- DEBUG
264 -----------------------------------------------------------------------------
265 --
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279
280 -----------------------------------------------------------------------------
281 -- MS
282 -----------------------------------------------------------------------------
283
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL data_ms_valid : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
290
291 SIGNAL run_ms : STD_LOGIC;
292 --SIGNAL ms_softandhard_rstn : STD_LOGIC;
293
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298
299
300 BEGIN
301
302 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
303 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
304
305 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
306 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
307 END GENERATE all_channel;
308
309 -----------------------------------------------------------------------------
310 lpp_lfr_filter_1 : lpp_lfr_filter
311 GENERIC MAP (
312 Mem_use => Mem_use)
313 PORT MAP (
314 sample => sample_s,
315 sample_val => sample_val,
316 clk => clk,
317 rstn => rstn,
318 data_shaping_SP0 => data_shaping_SP0,
319 data_shaping_SP1 => data_shaping_SP1,
320 data_shaping_R0 => data_shaping_R0,
321 data_shaping_R1 => data_shaping_R1,
322 sample_f0_val => sample_f0_val,
323 sample_f1_val => sample_f1_val,
324 sample_f2_val => sample_f2_val,
325 sample_f3_val => sample_f3_val,
326 sample_f0_wdata => sample_f0_data,
327 sample_f1_wdata => sample_f1_data,
328 sample_f2_wdata => sample_f2_data,
329 sample_f3_wdata => sample_f3_data);
330
331 -----------------------------------------------------------------------------
332 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
333 GENERIC MAP (
334 nb_data_by_buffer_size => nb_data_by_buffer_size,
335 nb_word_by_buffer_size => nb_word_by_buffer_size,
336 nb_snapshot_param_size => nb_snapshot_param_size,
337 delta_vector_size => delta_vector_size,
338 delta_vector_size_f0_2 => delta_vector_size_f0_2,
339 pindex => pindex,
340 paddr => paddr,
341 pmask => pmask,
342 pirq_ms => pirq_ms,
343 pirq_wfp => pirq_wfp,
344 top_lfr_version => top_lfr_version)
345 PORT MAP (
346 HCLK => clk,
347 HRESETn => rstn,
348 apbi => apbi,
349 apbo => apbo,
350
351 run_ms => run_ms,
352
353 ready_matrix_f0_0 => ready_matrix_f0_0,
354 ready_matrix_f0_1 => ready_matrix_f0_1,
355 ready_matrix_f1 => ready_matrix_f1,
356 ready_matrix_f2 => ready_matrix_f2,
357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 error_bad_component_error => error_bad_component_error,
359 debug_reg => debug_reg,
360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 status_ready_matrix_f1 => status_ready_matrix_f1,
363 status_ready_matrix_f2 => status_ready_matrix_f2,
364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 status_error_bad_component_error => status_error_bad_component_error,
366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 config_active_interruption_onError => config_active_interruption_onError,
368
369 matrix_time_f0_0 => matrix_time_f0_0,
370 matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
373
374 addr_matrix_f0_0 => addr_matrix_f0_0,
375 addr_matrix_f0_1 => addr_matrix_f0_1,
376 addr_matrix_f1 => addr_matrix_f1,
377 addr_matrix_f2 => addr_matrix_f2,
378 status_full => status_full,
379 status_full_ack => status_full_ack,
380 status_full_err => status_full_err,
381 status_new_err => status_new_err,
382 data_shaping_BW => data_shaping_BW,
383 data_shaping_SP0 => data_shaping_SP0,
384 data_shaping_SP1 => data_shaping_SP1,
385 data_shaping_R0 => data_shaping_R0,
386 data_shaping_R1 => data_shaping_R1,
387 delta_snapshot => delta_snapshot,
388 delta_f0 => delta_f0,
389 delta_f0_2 => delta_f0_2,
390 delta_f1 => delta_f1,
391 delta_f2 => delta_f2,
392 nb_data_by_buffer => nb_data_by_buffer,
393 nb_word_by_buffer => nb_word_by_buffer,
394 nb_snapshot_param => nb_snapshot_param,
395 enable_f0 => enable_f0,
396 enable_f1 => enable_f1,
397 enable_f2 => enable_f2,
398 enable_f3 => enable_f3,
399 burst_f0 => burst_f0,
400 burst_f1 => burst_f1,
401 burst_f2 => burst_f2,
402 run => run,
403 addr_data_f0 => addr_data_f0,
404 addr_data_f1 => addr_data_f1,
405 addr_data_f2 => addr_data_f2,
406 addr_data_f3 => addr_data_f3,
407 start_date => start_date,
408 ---------------------------------------------------------------------------
409 debug_reg0 => debug_reg0,
410 debug_reg1 => debug_reg1,
411 debug_reg2 => debug_reg2,
412 debug_reg3 => debug_reg3,
413 debug_reg4 => debug_reg4,
414 debug_reg5 => debug_reg5,
415 debug_reg6 => debug_reg6,
416 debug_reg7 => debug_reg7);
417
418 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
419 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
420 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
421 -----------------------------------------------------------------------------
422 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
423 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
424 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
425 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
426
427
428 -----------------------------------------------------------------------------
429 lpp_waveform_1 : lpp_waveform
430 GENERIC MAP (
431 tech => inferred,
432 data_size => 6*16,
433 nb_data_by_buffer_size => nb_data_by_buffer_size,
434 nb_word_by_buffer_size => nb_word_by_buffer_size,
435 nb_snapshot_param_size => nb_snapshot_param_size,
436 delta_vector_size => delta_vector_size,
437 delta_vector_size_f0_2 => delta_vector_size_f0_2
438 )
439 PORT MAP (
440 clk => clk,
441 rstn => rstn,
442
443 reg_run => run,
444 reg_start_date => start_date,
445 reg_delta_snapshot => delta_snapshot,
446 reg_delta_f0 => delta_f0,
447 reg_delta_f0_2 => delta_f0_2,
448 reg_delta_f1 => delta_f1,
449 reg_delta_f2 => delta_f2,
450
451 enable_f0 => enable_f0,
452 enable_f1 => enable_f1,
453 enable_f2 => enable_f2,
454 enable_f3 => enable_f3,
455 burst_f0 => burst_f0,
456 burst_f1 => burst_f1,
457 burst_f2 => burst_f2,
458
459 nb_data_by_buffer => nb_data_by_buffer,
460 nb_word_by_buffer => nb_word_by_buffer,
461 nb_snapshot_param => nb_snapshot_param,
462 status_full => status_full,
463 status_full_ack => status_full_ack,
464 status_full_err => status_full_err,
465 status_new_err => status_new_err,
466
467 coarse_time => coarse_time,
468 fine_time => fine_time,
469
470 --f0
471 addr_data_f0 => addr_data_f0,
472 data_f0_in_valid => sample_f0_val,
473 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
474 --f1
475 addr_data_f1 => addr_data_f1,
476 data_f1_in_valid => sample_f1_val,
477 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
478 --f2
479 addr_data_f2 => addr_data_f2,
480 data_f2_in_valid => sample_f2_val,
481 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
482 --f3
483 addr_data_f3 => addr_data_f3,
484 data_f3_in_valid => sample_f3_val,
485 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
486 -- OUTPUT -- DMA interface
487 --f0
488 data_f0_addr_out => data_f0_addr_out_s,
489 data_f0_data_out => data_f0_data_out,
490 data_f0_data_out_valid => data_f0_data_out_valid_s,
491 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
492 data_f0_data_out_ren => data_f0_data_out_ren,
493 --f1
494 data_f1_addr_out => data_f1_addr_out_s,
495 data_f1_data_out => data_f1_data_out,
496 data_f1_data_out_valid => data_f1_data_out_valid_s,
497 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
498 data_f1_data_out_ren => data_f1_data_out_ren,
499 --f2
500 data_f2_addr_out => data_f2_addr_out_s,
501 data_f2_data_out => data_f2_data_out,
502 data_f2_data_out_valid => data_f2_data_out_valid_s,
503 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
504 data_f2_data_out_ren => data_f2_data_out_ren,
505 --f3
506 data_f3_addr_out => data_f3_addr_out_s,
507 data_f3_data_out => data_f3_data_out,
508 data_f3_data_out_valid => data_f3_data_out_valid_s,
509 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
510 data_f3_data_out_ren => data_f3_data_out_ren ,
511
512 -------------------------------------------------------------------------
513 observation_reg => OPEN
514
515 );
516
517
518 -----------------------------------------------------------------------------
519 -- TEMP
520 -----------------------------------------------------------------------------
521
522 PROCESS (clk, rstn)
523 BEGIN -- PROCESS
524 IF rstn = '0' THEN -- asynchronous reset (active low)
525 data_f0_data_out_valid <= '0';
526 data_f0_data_out_valid_burst <= '0';
527 data_f1_data_out_valid <= '0';
528 data_f1_data_out_valid_burst <= '0';
529 data_f2_data_out_valid <= '0';
530 data_f2_data_out_valid_burst <= '0';
531 data_f3_data_out_valid <= '0';
532 data_f3_data_out_valid_burst <= '0';
533 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
534 data_f0_data_out_valid <= data_f0_data_out_valid_s;
535 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
536 data_f1_data_out_valid <= data_f1_data_out_valid_s;
537 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
538 data_f2_data_out_valid <= data_f2_data_out_valid_s;
539 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
540 data_f3_data_out_valid <= data_f3_data_out_valid_s;
541 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
542 END IF;
543 END PROCESS;
544
545 data_f0_addr_out <= data_f0_addr_out_s;
546 data_f1_addr_out <= data_f1_addr_out_s;
547 data_f2_addr_out <= data_f2_addr_out_s;
548 data_f3_addr_out <= data_f3_addr_out_s;
549
550 -----------------------------------------------------------------------------
551 -- RoundRobin Selection For DMA
552 -----------------------------------------------------------------------------
553
554 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
555 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
556 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
557 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
558
559 RR_Arbiter_4_1 : RR_Arbiter_4
560 PORT MAP (
561 clk => clk,
562 rstn => rstn,
563 in_valid => dma_rr_valid,
564 out_grant => dma_rr_grant_s);
565
566 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
567 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
568 dma_rr_valid_ms(2) <= '0';
569 dma_rr_valid_ms(3) <= '0';
570
571 RR_Arbiter_4_2 : RR_Arbiter_4
572 PORT MAP (
573 clk => clk,
574 rstn => rstn,
575 in_valid => dma_rr_valid_ms,
576 out_grant => dma_rr_grant_ms);
577
578 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
579
580
581 -----------------------------------------------------------------------------
582 -- in : dma_rr_grant
583 -- send
584 -- out : dma_sel
585 -- dma_valid_burst
586 -- dma_sel_valid
587 -----------------------------------------------------------------------------
588 PROCESS (clk, rstn)
589 BEGIN -- PROCESS
590 IF rstn = '0' THEN -- asynchronous reset (active low)
591 dma_sel <= (OTHERS => '0');
592 dma_send <= '0';
593 dma_valid_burst <= '0';
594 data_ms_done <= '0';
595 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
596 IF run = '1' THEN
597 data_ms_done <= '0';
598 IF dma_sel = "00000" OR dma_done = '1' THEN
599 dma_sel <= dma_rr_grant;
600 IF dma_rr_grant(0) = '1' THEN
601 dma_send <= '1';
602 dma_valid_burst <= data_f0_data_out_valid_burst;
603 dma_sel_valid <= data_f0_data_out_valid;
604 ELSIF dma_rr_grant(1) = '1' THEN
605 dma_send <= '1';
606 dma_valid_burst <= data_f1_data_out_valid_burst;
607 dma_sel_valid <= data_f1_data_out_valid;
608 ELSIF dma_rr_grant(2) = '1' THEN
609 dma_send <= '1';
610 dma_valid_burst <= data_f2_data_out_valid_burst;
611 dma_sel_valid <= data_f2_data_out_valid;
612 ELSIF dma_rr_grant(3) = '1' THEN
613 dma_send <= '1';
614 dma_valid_burst <= data_f3_data_out_valid_burst;
615 dma_sel_valid <= data_f3_data_out_valid;
616 ELSIF dma_rr_grant(4) = '1' THEN
617 dma_send <= '1';
618 dma_valid_burst <= data_ms_valid_burst;
619 dma_sel_valid <= data_ms_valid;
620 END IF;
621
622 IF dma_sel(4) = '1' THEN
623 data_ms_done <= '1';
624 END IF;
625 ELSE
626 dma_sel <= dma_sel;
627 dma_send <= '0';
628 END IF;
629 ELSE
630 data_ms_done <= '0';
631 dma_sel <= (OTHERS => '0');
632 dma_send <= '0';
633 dma_valid_burst <= '0';
634 END IF;
635 END IF;
636 END PROCESS;
637
638
639 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
640 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
641 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
642 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
643 data_ms_addr;
644
645 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
646 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
647 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
648 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
649 data_ms_data;
650
651 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
652 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
653 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
654 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
655 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
656
657 dma_data_2 <= dma_data;
658
659 -----------------------------------------------------------------------------
660 -- DMA
661 -----------------------------------------------------------------------------
662 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
663 GENERIC MAP (
664 tech => inferred,
665 hindex => hindex)
666 PORT MAP (
667 HCLK => clk,
668 HRESETn => rstn,
669 run => run,
670 AHB_Master_In => ahbi,
671 AHB_Master_Out => ahbo,
672
673 send => dma_send,
674 valid_burst => dma_valid_burst,
675 done => dma_done,
676 ren => dma_ren,
677 address => dma_address,
678 data => dma_data_2);
679
680 -----------------------------------------------------------------------------
681 -- Matrix Spectral
682 -----------------------------------------------------------------------------
683 data_ms_addr <= (OTHERS => '0');
684 data_ms_data <= (OTHERS => '0');
685 data_ms_valid <= '0';
686 data_ms_valid_burst <= '0';
687
688 ready_matrix_f0_0 <= '0';
689 ready_matrix_f0_1 <= '0';
690 ready_matrix_f1 <= '0';
691 ready_matrix_f2 <= '0';
692 error_anticipating_empty_fifo <= '0';
693 error_bad_component_error <= '0';
694 observation_reg <= (OTHERS => '0');
695
696 matrix_time_f2 <= (OTHERS => '0');
697 matrix_time_f1 <= (OTHERS => '0');
698 matrix_time_f0_1 <= (OTHERS => '0');
699 matrix_time_f0_0 <= (OTHERS => '0');
700
701 END beh;
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@@ -2,7 +2,7
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
5 TOP=LFR_em
6 6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
@@ -12,7 +12,8 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 17 #VHDLSIMFILES=testbench.vhd
17 18 #SIMTOP=testbench
18 19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
@@ -37,8 +38,7 DIRSKIP = b1553 pcif leon2 leon2ft crypt
37 38 ./lpp_uart \
38 39 ./lpp_usb \
39 40
40 FILESKIP = lpp_lfr_ms.vhd \
41 i2cmst.vhd \
41 FILESKIP = i2cmst.vhd \
42 42 APB_MULTI_DIODE.vhd \
43 43 APB_MULTI_DIODE.vhd \
44 44 Top_MatrixSpec.vhd \
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@@ -48,25 +48,6 USE lpp.CY7C1061DV33_pkg.ALL;
48 48 ENTITY testbench IS
49 49 END;
50 50
51
52
53
54
55
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60
61
62
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64
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68
69
70 51 ARCHITECTURE behav OF testbench IS
71 52 CONSTANT INDEX_LFR : INTEGER := 15;
72 53 CONSTANT ADDR_LFR : INTEGER := 15;
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1 NO CONTENT: file renamed from lib/lpp/lpp_sim/CY7C1061DV33/vhdlsyn.txt to lib/lpp/lpp_sim/CY7C1061DV33/vhdlsim.txt
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@@ -173,10 +173,10 ARCHITECTURE beh OF lpp_lfr_apbreg IS
173 173 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 174 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175
176 fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
177 fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
178 fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
179 fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
176 -- fine_time_f0_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
177 -- fine_time_f0_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
178 -- fine_time_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
179 -- fine_time_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
180 180 END RECORD;
181 181 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
182 182
@@ -297,10 +297,10 BEGIN -- beh
297 297 reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
298 298 reg_sp.coarse_time_f1 <= (OTHERS => '0');
299 299 reg_sp.coarse_time_f2 <= (OTHERS => '0');
300 reg_sp.fine_time_f0_0 <= (OTHERS => '0');
301 reg_sp.fine_time_f0_1 <= (OTHERS => '0');
302 reg_sp.fine_time_f1 <= (OTHERS => '0');
303 reg_sp.fine_time_f2 <= (OTHERS => '0');
300 --reg_sp.fine_time_f0_0 <= (OTHERS => '0');
301 --reg_sp.fine_time_f0_1 <= (OTHERS => '0');
302 --reg_sp.fine_time_f1 <= (OTHERS => '0');
303 --reg_sp.fine_time_f2 <= (OTHERS => '0');
304 304
305 305 prdata <= (OTHERS => '0');
306 306
@@ -344,10 +344,10 BEGIN -- beh
344 344 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
345 345 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
346 346
347 reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
348 reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
349 reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
350 reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
347 --reg_sp.fine_time_f0_0 <= matrix_time_f0_0(15 DOWNTO 0);
348 --reg_sp.fine_time_f0_1 <= matrix_time_f0_1(15 DOWNTO 0);
349 --reg_sp.fine_time_f1 <= matrix_time_f1 (15 DOWNTO 0);
350 --reg_sp.fine_time_f2 <= matrix_time_f2 (15 DOWNTO 0);
351 351
352 352 status_full_ack <= (OTHERS => '0');
353 353
@@ -392,10 +392,10 BEGIN -- beh
392 392 WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
393 393 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
394 394 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
395 WHEN "001010" => prdata(15 downto 0) <= reg_sp.fine_time_f0_0;
396 WHEN "001011" => prdata(15 downto 0) <= reg_sp.fine_time_f0_1;
397 WHEN "001100" => prdata(15 downto 0) <= reg_sp.fine_time_f1;
398 WHEN "001101" => prdata(15 downto 0) <= reg_sp.fine_time_f2;
395 WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;
396 WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;
397 WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;
398 WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;
399 399
400 400 WHEN "001111" => prdata <= debug_reg;
401 401 ---------------------------------------------------------------------
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@@ -307,12 +307,15 BEGIN
307 307 Matrix_Type => DMUX_WorkFreq,
308 308 Matrix_Write => SM_Wen,
309 309 Valid => Head_Valid,
310
310 311 dataIN => FifoOUT_Data,
311 312 emptyIN => FifoOUT_Empty,
312 RenOUT => Head_Read,
313 RenOUT => Head_Read,
314
313 315 dataOUT => Head_Data,
314 316 emptyOUT => Head_Empty,
315 RenIN => DMA_Read,
317 RenIN => DMA_Read,
318
316 319 header => Head_Header,
317 320 header_val => Head_Val,
318 321 header_ack => DMA_ack );
@@ -368,47 +371,4 BEGIN
368 371 matrix_time_f2 => matrix_time_f2
369 372 );
370 373
371
372
373
374 -----------------------------------------------------------------------------
375 --lpp_dma_ip_1: lpp_dma_ip
376 -- GENERIC MAP (
377 -- tech => 0,
378 -- hindex => hindex)
379 -- PORT MAP (
380 -- HCLK => clk,
381 -- HRESETn => rstn,
382 -- AHB_Master_In => AHB_Master_In,
383 -- AHB_Master_Out => AHB_Master_Out,
384
385 -- fifo_data => Head_Data,
386 -- fifo_empty => Head_Empty,
387 -- fifo_ren => DMA_Read,
388
389 -- header => Head_Header,
390 -- header_val => Head_Val,
391 -- header_ack => DMA_ack,
392
393 -- ready_matrix_f0_0 => ready_matrix_f0_0,
394 -- ready_matrix_f0_1 => ready_matrix_f0_1,
395 -- ready_matrix_f1 => ready_matrix_f1,
396 -- ready_matrix_f2 => ready_matrix_f2,
397 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
398 -- error_bad_component_error => error_bad_component_error,
399 -- debug_reg => debug_reg,
400 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
401 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
402 -- status_ready_matrix_f1 => status_ready_matrix_f1,
403 -- status_ready_matrix_f2 => status_ready_matrix_f2,
404 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
405 -- status_error_bad_component_error => status_error_bad_component_error,
406 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
407 -- config_active_interruption_onError => config_active_interruption_onError,
408 -- addr_matrix_f0_0 => addr_matrix_f0_0,
409 -- addr_matrix_f0_1 => addr_matrix_f0_1,
410 -- addr_matrix_f1 => addr_matrix_f1,
411 -- addr_matrix_f2 => addr_matrix_f2);
412 -------------------------------------------------------------------------------
413
414 374 END Behavioral;
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@@ -260,55 +260,55 BEGIN
260 260 state <= TRASH_FIFO;
261 261 END IF;
262 262
263 WHEN WRITE_COARSE_TIME =>
264 debug_reg_s(2 DOWNTO 0) <= "010";
263 --WHEN WRITE_COARSE_TIME =>
264 -- debug_reg_s(2 DOWNTO 0) <= "010";
265 265
266 header_ack <= '0';
266 -- header_ack <= '0';
267 267
268 IF dma_ren = '0' THEN
269 header_send <= '0';
270 ELSE
271 header_send <= header_send;
272 END IF;
268 -- IF dma_ren = '0' THEN
269 -- header_send <= '0';
270 -- ELSE
271 -- header_send <= header_send;
272 -- END IF;
273 273
274 274
275 IF header_send_ko = '1' THEN
276 header_send <= '0';
277 state <= TRASH_FIFO;
278 error_anticipating_empty_fifo <= '1';
279 -- TODO : error sending header
280 ELSIF header_send_ok = '1' THEN
281 header_send <= '1';
282 header_select <= '1';
283 header_data(15 DOWNTO 0) <= fine_time_reg;
284 header_data(31 DOWNTO 16) <= (OTHERS => '0');
285 state <= WRITE_FINE_TIME;
286 address <= address + 4;
287 END IF;
275 -- IF header_send_ko = '1' THEN
276 -- header_send <= '0';
277 -- state <= TRASH_FIFO;
278 -- error_anticipating_empty_fifo <= '1';
279 -- -- TODO : error sending header
280 -- ELSIF header_send_ok = '1' THEN
281 -- header_send <= '1';
282 -- header_select <= '1';
283 -- header_data(15 DOWNTO 0) <= fine_time_reg;
284 -- header_data(31 DOWNTO 16) <= (OTHERS => '0');
285 -- state <= WRITE_FINE_TIME;
286 -- address <= address + 4;
287 -- END IF;
288 288
289 289
290 WHEN WRITE_FINE_TIME =>
291 debug_reg_s(2 DOWNTO 0) <= "011";
290 --WHEN WRITE_FINE_TIME =>
291 -- debug_reg_s(2 DOWNTO 0) <= "011";
292 292
293 header_ack <= '0';
293 -- header_ack <= '0';
294 294
295 IF dma_ren = '0' THEN
296 header_send <= '0';
297 ELSE
298 header_send <= header_send;
299 END IF;
295 -- IF dma_ren = '0' THEN
296 -- header_send <= '0';
297 -- ELSE
298 -- header_send <= header_send;
299 -- END IF;
300 300
301 IF header_send_ko = '1' THEN
302 header_send <= '0';
303 state <= TRASH_FIFO;
304 error_anticipating_empty_fifo <= '1';
305 -- TODO : error sending header
306 ELSIF header_send_ok = '1' THEN
307 header_send <= '0';
308 header_select <= '0';
309 state <= SEND_DATA;
310 address <= address + 4;
311 END IF;
301 -- IF header_send_ko = '1' THEN
302 -- header_send <= '0';
303 -- state <= TRASH_FIFO;
304 -- error_anticipating_empty_fifo <= '1';
305 -- -- TODO : error sending header
306 -- ELSIF header_send_ok = '1' THEN
307 -- header_send <= '0';
308 -- header_select <= '0';
309 -- state <= SEND_DATA;
310 -- address <= address + 4;
311 -- END IF;
312 312
313 313 WHEN TRASH_FIFO =>
314 314 debug_reg_s(2 DOWNTO 0) <= "100";
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@@ -165,6 +165,42 PACKAGE lpp_lfr_pkg IS
165 165 );
166 166 END COMPONENT;
167 167
168 -----------------------------------------------------------------------------
169 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
170 -----------------------------------------------------------------------------
171 COMPONENT lpp_lfr_WFP_nMS
172 GENERIC (
173 Mem_use : INTEGER;
174 nb_data_by_buffer_size : INTEGER;
175 nb_word_by_buffer_size : INTEGER;
176 nb_snapshot_param_size : INTEGER;
177 delta_vector_size : INTEGER;
178 delta_vector_size_f0_2 : INTEGER;
179 pindex : INTEGER;
180 paddr : INTEGER;
181 pmask : INTEGER;
182 pirq_ms : INTEGER;
183 pirq_wfp : INTEGER;
184 hindex : INTEGER;
185 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
186 PORT (
187 clk : IN STD_LOGIC;
188 rstn : IN STD_LOGIC;
189 sample_B : IN Samples14v(2 DOWNTO 0);
190 sample_E : IN Samples14v(4 DOWNTO 0);
191 sample_val : IN STD_LOGIC;
192 apbi : IN apb_slv_in_type;
193 apbo : OUT apb_slv_out_type;
194 ahbi : IN AHB_Mst_In_Type;
195 ahbo : OUT AHB_Mst_Out_Type;
196 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
198 data_shaping_BW : OUT STD_LOGIC;
199 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
200 END COMPONENT;
201 -----------------------------------------------------------------------------
202
203
168 204 COMPONENT lpp_lfr_apbreg
169 205 GENERIC (
170 206 nb_data_by_buffer_size : INTEGER;
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@@ -4,4 +4,5 lpp_lfr_filter.vhd
4 4 lpp_lfr_apbreg.vhd
5 5 lpp_lfr_ms_fsmdma.vhd
6 6 lpp_lfr_ms.vhd
7 lpp_lfr_WFP_nMS.vhd
7 8 lpp_lfr.vhd
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