@@ -331,6 +331,7 BEGIN -- beh | |||
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331 | 331 | -- time_out_2(J,I) <= time_out(J)(I); |
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332 | 332 | -- END GENERATE all_sample_of_time_out; |
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333 | 333 | --END GENERATE all_bit_of_time_out; |
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334 | ||
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334 | 335 |
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335 | 336 | time_out_debug(1) <= x"1B1B" & x"1B1B1B1B"; |
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336 | 337 | time_out_debug(2) <= x"2C2C" & x"2C2C2C2C"; |
@@ -383,40 +384,12 BEGIN -- beh | |||
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383 | 384 | data_f1_data_out <= rdata; |
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384 | 385 | data_f2_data_out <= rdata; |
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385 | 386 | data_f3_data_out <= rdata; |
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386 | ||
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387 | --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency | |
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388 | -- GENERIC MAP ( | |
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389 | -- tech => tech) | |
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390 | -- PORT MAP ( | |
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391 | -- clk => clk, | |
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392 | -- rstn => rstn, | |
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393 | -- run => run, | |
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394 | ||
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395 | -- empty_almost => empty_almost, | |
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396 | -- empty => empty, | |
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397 | -- data_ren => data_ren, | |
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398 | ||
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399 | -- rdata_0 => data_f0_data_out, | |
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400 | -- rdata_1 => data_f1_data_out, | |
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401 | -- rdata_2 => data_f2_data_out, | |
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402 | -- rdata_3 => data_f3_data_out, | |
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403 | ||
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404 | -- full_almost => full_almost, | |
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405 | -- full => full, | |
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406 | -- data_wen => data_wen, | |
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407 | -- wdata => wdata); | |
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408 | ||
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409 | ||
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410 | ||
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411 | 387 | |
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412 | 388 | data_ren <= data_f3_data_out_ren & |
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413 | 389 | data_f2_data_out_ren & |
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414 | 390 | data_f1_data_out_ren & |
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415 | 391 | data_f0_data_out_ren; |
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416 | 392 | |
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417 | ----------------------------------------------------------------------------- | |
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418 | -- TODO : set the alterance : time, data, data, ..... | |
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419 | ----------------------------------------------------------------------------- | |
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420 | 393 |
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421 | 394 | GENERIC MAP ( |
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422 | 395 | nb_data_by_buffer_size => nb_word_by_buffer_size) |
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