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LFR-EQM 2.1.83...
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r601:1b6a99d2ea09 (LFR-EQM) 2-1-83 simu_with_Leon3
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.sim.ALL;
32 32 USE gaisler.memctrl.ALL;
33 33 USE gaisler.leon3.ALL;
34 34 USE gaisler.uart.ALL;
35 35 USE gaisler.misc.ALL;
36 36 USE gaisler.spacewire.ALL;
37 37 LIBRARY esa;
38 38 USE esa.memoryctrl.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 44 USE lpp.iir_filter.ALL;
45 45 USE lpp.general_purpose.ALL;
46 46 USE lpp.lpp_lfr_management.ALL;
47 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 USE lpp.lpp_bootloader_pkg.ALL;
49 49
50 50 --library proasic3l;
51 51 --use proasic3l.all;
52 52
53 53 ENTITY LFR_EQM IS
54 54 GENERIC (
55 55 Mem_use : INTEGER := use_RAM;
56 56 USE_BOOTLOADER : INTEGER := 0;
57 57 USE_ADCDRIVER : INTEGER := 1;
58 58 tech : INTEGER := apa3e;
59 59 tech_leon : INTEGER := apa3e;
60 60 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 61 USE_DEBUG_VECTOR : INTEGER := 0
62 62 );
63 63
64 64 PORT (
65 65 clk50MHz : IN STD_ULOGIC;
66 66 clk49_152MHz : IN STD_ULOGIC;
67 67 reset : IN STD_ULOGIC;
68 68
69 69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 70
71 71 -- TAG --------------------------------------------------------------------
72 72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 74 -- UART APB ---------------------------------------------------------------
75 75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 77 -- RAM --------------------------------------------------------------------
78 78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 85 nSRAM_W : OUT STD_LOGIC; -- new
86 86 nSRAM_G : OUT STD_LOGIC; -- new
87 87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 88 -- SPW --------------------------------------------------------------------
89 89 spw1_en : OUT STD_LOGIC; -- new
90 90 spw1_din : IN STD_LOGIC;
91 91 spw1_sin : IN STD_LOGIC;
92 92 spw1_dout : OUT STD_LOGIC;
93 93 spw1_sout : OUT STD_LOGIC;
94 94 spw2_en : OUT STD_LOGIC; -- new
95 95 spw2_din : IN STD_LOGIC;
96 96 spw2_sin : IN STD_LOGIC;
97 97 spw2_dout : OUT STD_LOGIC;
98 98 spw2_sout : OUT STD_LOGIC;
99 99 -- ADC --------------------------------------------------------------------
100 100 bias_fail_sw : OUT STD_LOGIC;
101 101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102 ADC_smpclk : OUT STD_LOGIC;
103 103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 104 -- DAC --------------------------------------------------------------------
105 105 DAC_SDO : OUT STD_LOGIC;
106 106 DAC_SCK : OUT STD_LOGIC;
107 107 DAC_SYNC : OUT STD_LOGIC;
108 108 DAC_CAL_EN : OUT STD_LOGIC;
109 109 -- HK ---------------------------------------------------------------------
110 110 HK_smpclk : OUT STD_LOGIC;
111 111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 113 ---------------------------------------------------------------------------
114 114 -- TAG8 : OUT STD_LOGIC
115 115 );
116 116
117 117 END LFR_EQM;
118 118
119 119
120 120 ARCHITECTURE beh OF LFR_EQM IS
121 121
122 122 SIGNAL clk_25 : STD_LOGIC := '0';
123 123 SIGNAL clk_24 : STD_LOGIC := '0';
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 127
128 128 -- CONSTANTS
129 129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133 133
134 134 SIGNAL apbi_ext : apb_slv_in_type;
135 135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140 140
141 141 -- Spacewire signals
142 142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 147 SIGNAL spw_clk : STD_LOGIC;
148 148 SIGNAL swni : grspw_in_type;
149 149 SIGNAL swno : grspw_out_type;
150 150
151 151 --GPIO
152 152 SIGNAL gpioi : gpio_in_type;
153 153 SIGNAL gpioo : gpio_out_type;
154 154
155 155 -- AD Converter ADS7886
156 156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 158 SIGNAL sample_val : STD_LOGIC;
159 159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160 160
161 161 -----------------------------------------------------------------------------
162 162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 163
164 164 -----------------------------------------------------------------------------
165 165 SIGNAL rstn_25 : STD_LOGIC;
166 166 SIGNAL rstn_24 : STD_LOGIC;
167 167
168 168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 169 SIGNAL LFR_rstn : STD_LOGIC;
170 170
171 171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172 172
173 173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 174
175 175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 176 SIGNAL clk_25_int : STD_LOGIC := '0';
177 177
178 178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179 179
180 180 SIGNAL rstn_50 : STD_LOGIC;
181 181 SIGNAL clk_lock : STD_LOGIC;
182 182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184 184
185 185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 186 SIGNAL ahbrxd: STD_LOGIC;
187 187 SIGNAL ahbtxd: STD_LOGIC;
188 188 SIGNAL urxd1 : STD_LOGIC;
189 189 SIGNAL utxd1 : STD_LOGIC;
190 190 BEGIN -- beh
191 191
192 192 -----------------------------------------------------------------------------
193 193 -- CLK_LOCK
194 194 -----------------------------------------------------------------------------
195 195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196 196
197 197 PROCESS (clk50MHz_int, rstn_50)
198 198 BEGIN -- PROCESS
199 199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 200 clk_lock <= '0';
201 201 clk_busy_counter <= (OTHERS => '0');
202 202 nSRAM_BUSY_reg <= '0';
203 203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 206 IF clk_busy_counter = "1111" THEN
207 207 clk_lock <= '1';
208 208 ELSE
209 209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 210 END IF;
211 211 END IF;
212 212 END IF;
213 213 END PROCESS;
214 214
215 215 -----------------------------------------------------------------------------
216 216 -- CLK
217 217 -----------------------------------------------------------------------------
218 218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220 220
221 221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 222 clk50MHz_int <= clk50MHz;
223 223
224 224 PROCESS(clk50MHz_int)
225 225 BEGIN
226 226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 227 --clk_25_int <= NOT clk_25_int;
228 228 clk_25 <= NOT clk_25;
229 229 END IF;
230 230 END PROCESS;
231 231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232 232
233 233 PROCESS(clk49_152MHz)
234 234 BEGIN
235 235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 236 clk_24 <= NOT clk_24;
237 237 END IF;
238 238 END PROCESS;
239 239 -- clk_49 <= clk49_152MHz;
240 240
241 241 -----------------------------------------------------------------------------
242 242 --
243 243 leon3_soc_1 : leon3_soc
244 244 GENERIC MAP (
245 245 fabtech => tech_leon,
246 246 memtech => tech_leon,
247 247 padtech => inferred,
248 248 clktech => inferred,
249 249 disas => 0,
250 250 dbguart => 0,
251 251 pclow => 2,
252 252 clk_freq => 25000,
253 253 IS_RADHARD => 0,
254 254 NB_CPU => 1,
255 255 ENABLE_FPU => 1,
256 256 FPU_NETLIST => 0,
257 257 ENABLE_DSU => 1,
258 258 ENABLE_AHB_UART => 1,
259 259 ENABLE_APB_UART => 1,
260 260 ENABLE_IRQMP => 1,
261 261 ENABLE_GPT => 1,
262 262 NB_AHB_MASTER => NB_AHB_MASTER,
263 263 NB_AHB_SLAVE => NB_AHB_SLAVE,
264 264 NB_APB_SLAVE => NB_APB_SLAVE,
265 265 ADDRESS_SIZE => 19,
266 266 USES_IAP_MEMCTRLR => 1,
267 267 BYPASS_EDAC_MEMCTRLR => '0',
268 268 SRBANKSZ => 8)
269 269 PORT MAP (
270 270 clk => clk_25,
271 271 reset => rstn_25,
272 272 errorn => OPEN,
273 273
274 274 ahbrxd => ahbrxd, -- INPUT
275 275 ahbtxd => ahbtxd, -- OUTPUT
276 276 urxd1 => urxd1, -- INPUT
277 277 utxd1 => utxd1, -- OUTPUT
278 278
279 279 address => address,
280 280 data => data,
281 281 nSRAM_BE0 => OPEN,
282 282 nSRAM_BE1 => OPEN,
283 283 nSRAM_BE2 => OPEN,
284 284 nSRAM_BE3 => OPEN,
285 285 nSRAM_WE => nSRAM_W,
286 286 nSRAM_CE => nSRAM_CE,
287 287 nSRAM_OE => nSRAM_G,
288 288 nSRAM_READY => nSRAM_BUSY,
289 289 SRAM_MBE => nSRAM_MBE,
290 290
291 291 apbi_ext => apbi_ext,
292 292 apbo_ext => apbo_ext,
293 293 ahbi_s_ext => ahbi_s_ext,
294 294 ahbo_s_ext => ahbo_s_ext,
295 295 ahbi_m_ext => ahbi_m_ext,
296 296 ahbo_m_ext => ahbo_m_ext);
297 297
298 298
299 299 nSRAM_E1 <= nSRAM_CE(0);
300 300 nSRAM_E2 <= nSRAM_CE(1);
301 301
302 302 -------------------------------------------------------------------------------
303 303 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
304 304 -------------------------------------------------------------------------------
305 305 apb_lfr_management_1 : apb_lfr_management
306 306 GENERIC MAP (
307 307 tech => tech,
308 308 pindex => 6,
309 309 paddr => 6,
310 310 pmask => 16#fff#,
311 311 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
312 312 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
313 313 PORT MAP (
314 314 clk25MHz => clk_25,
315 315 resetn_25MHz => rstn_25, -- TODO
316 316 --clk24_576MHz => clk_24, -- 49.152MHz/2
317 317 --resetn_24_576MHz => rstn_24, -- TODO
318 318
319 319 grspw_tick => swno.tickout,
320 320 apbi => apbi_ext,
321 321 apbo => apbo_ext(6),
322 322
323 323 HK_sample => sample_s(8),
324 324 HK_val => sample_val,
325 325 HK_sel => HK_SEL,
326 326
327 327 DAC_SDO => DAC_SDO,
328 328 DAC_SCK => DAC_SCK,
329 329 DAC_SYNC => DAC_SYNC,
330 330 DAC_CAL_EN => DAC_CAL_EN,
331 331
332 332 coarse_time => coarse_time,
333 333 fine_time => fine_time,
334 334 LFR_soft_rstn => LFR_soft_rstn
335 335 );
336 336
337 337 -----------------------------------------------------------------------
338 338 --- SpaceWire --------------------------------------------------------
339 339 -----------------------------------------------------------------------
340 340
341 341 ------------------------------------------------------------------------------
342 342 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
343 343 ------------------------------------------------------------------------------
344 344 spw1_en <= '1';
345 345 spw2_en <= '1';
346 346 ------------------------------------------------------------------------------
347 347 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
348 348 ------------------------------------------------------------------------------
349 349
350 350 --spw_clk <= clk50MHz;
351 351 --spw_rxtxclk <= spw_clk;
352 352 --spw_rxclkn <= NOT spw_rxtxclk;
353 353
354 354 -- PADS for SPW1
355 355 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
356 356 PORT MAP (spw1_din, dtmp(0));
357 357 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
358 358 PORT MAP (spw1_sin, stmp(0));
359 359 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
360 360 PORT MAP (spw1_dout, swno.d(0));
361 361 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
362 362 PORT MAP (spw1_sout, swno.s(0));
363 363 -- PADS FOR SPW2
364 364 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
365 365 PORT MAP (spw2_din, dtmp(1));
366 366 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
367 367 PORT MAP (spw2_sin, stmp(1));
368 368 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
369 369 PORT MAP (spw2_dout, swno.d(1));
370 370 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
371 371 PORT MAP (spw2_sout, swno.s(1));
372 372
373 373 -- GRSPW PHY
374 374 --spw1_input: if CFG_SPW_GRSPW = 1 generate
375 375 spw_inputloop : FOR j IN 0 TO 1 GENERATE
376 376 spw_phy0 : grspw_phy
377 377 GENERIC MAP(
378 378 tech => tech_leon,
379 379 rxclkbuftype => 1,
380 380 scantest => 0)
381 381 PORT MAP(
382 382 rxrst => swno.rxrst,
383 383 di => dtmp(j),
384 384 si => stmp(j),
385 385 rxclko => spw_rxclk(j),
386 386 do => swni.d(j),
387 387 ndo => swni.nd(j*5+4 DOWNTO j*5),
388 388 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
389 389 END GENERATE spw_inputloop;
390 390
391 391 -- SPW core
392 392 sw0 : grspwm GENERIC MAP(
393 393 tech => tech_leon,
394 394 hindex => 1,
395 395 pindex => 5,
396 396 paddr => 5,
397 397 pirq => 11,
398 398 sysfreq => 25000, -- CPU_FREQ
399 399 rmap => 1,
400 400 rmapcrc => 1,
401 401 fifosize1 => 16,
402 402 fifosize2 => 16,
403 403 rxclkbuftype => 1,
404 404 rxunaligned => 0,
405 405 rmapbufs => 4,
406 406 ft => 0,
407 407 netlist => 0,
408 408 ports => 2,
409 409 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
410 410 memtech => tech_leon,
411 411 destkey => 2,
412 412 spwcore => 1
413 413 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
414 414 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
415 415 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
416 416 )
417 417 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
418 418 spw_rxclk(1),
419 419 clk50MHz_int,
420 420 clk50MHz_int,
421 421 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
422 422 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
423 423 swni, swno);
424 424
425 425 swni.tickin <= '0';
426 426 swni.rmapen <= '1';
427 427 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
428 428 swni.tickinraw <= '0';
429 429 swni.timein <= (OTHERS => '0');
430 430 swni.dcrstval <= (OTHERS => '0');
431 431 swni.timerrstval <= (OTHERS => '0');
432 432
433 433 -------------------------------------------------------------------------------
434 434 -- LFR ------------------------------------------------------------------------
435 435 -------------------------------------------------------------------------------
436 436 LFR_rstn <= LFR_soft_rstn AND rstn_25;
437 437
438 438 lpp_lfr_1 : lpp_lfr
439 439 GENERIC MAP (
440 440 Mem_use => Mem_use,
441 441 tech => tech,
442 442 nb_data_by_buffer_size => 32,
443 443 --nb_word_by_buffer_size => 30,
444 444 nb_snapshot_param_size => 32,
445 445 delta_vector_size => 32,
446 446 delta_vector_size_f0_2 => 7, -- log2(96)
447 447 pindex => 15,
448 448 paddr => 15,
449 449 pmask => 16#fff#,
450 450 pirq_ms => 6,
451 451 pirq_wfp => 14,
452 452 hindex => 2,
453 top_lfr_version => X"020152", -- aa.bb.cc version
453 top_lfr_version => X"020153", -- aa.bb.cc version
454 454 -- AA : BOARD NUMBER
455 455 -- 0 => MINI_LFR
456 456 -- 1 => EM
457 457 -- 2 => EQM (with A3PE3000)
458 458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
459 459 PORT MAP (
460 460 clk => clk_25,
461 461 rstn => LFR_rstn,
462 462 sample_B => sample_s(2 DOWNTO 0),
463 463 sample_E => sample_s(7 DOWNTO 3),
464 464 sample_val => sample_val,
465 465 apbi => apbi_ext,
466 466 apbo => apbo_ext(15),
467 467 ahbi => ahbi_m_ext,
468 468 ahbo => ahbo_m_ext(2),
469 469 coarse_time => coarse_time,
470 470 fine_time => fine_time,
471 471 data_shaping_BW => bias_fail_sw,
472 472 debug_vector => debug_vector,
473 473 debug_vector_ms => OPEN); --,
474 474 --observation_vector_0 => OPEN,
475 475 --observation_vector_1 => OPEN,
476 476 --observation_reg => observation_reg);
477 477
478 478
479 479 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
480 480 sample_s(I) <= sample(I) & '0' & '0';
481 481 END GENERATE all_sample;
482 482 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
483 483
484 484 -----------------------------------------------------------------------------
485 485 --
486 486 -----------------------------------------------------------------------------
487 487 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
488 488 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
489 489 GENERIC MAP (
490 490 ChanelCount => 9,
491 491 ncycle_cnv_high => 12,
492 492 ncycle_cnv => 25,
493 493 FILTER_ENABLED => 16#FF#)
494 494 PORT MAP (
495 495 cnv_clk => clk_24,
496 496 cnv_rstn => rstn_24,
497 497 cnv => ADC_smpclk_s,
498 498 clk => clk_25,
499 499 rstn => rstn_25,
500 500 ADC_data => ADC_data,
501 501 ADC_nOE => ADC_OEB_bar_CH_s,
502 502 sample => sample,
503 503 sample_val => sample_val);
504 504
505 505 END GENERATE USE_ADCDRIVER_true;
506 506
507 507 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
508 508 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
509 509 GENERIC MAP (
510 510 ChanelCount => 9,
511 511 ncycle_cnv_high => 25,
512 512 ncycle_cnv => 50,
513 513 FILTER_ENABLED => 16#FF#)
514 514 PORT MAP (
515 515 cnv_clk => clk_24,
516 516 cnv_rstn => rstn_24,
517 517 cnv => ADC_smpclk_s,
518 518 clk => clk_25,
519 519 rstn => rstn_25,
520 520 ADC_data => ADC_data,
521 521 ADC_nOE => OPEN,
522 522 sample => OPEN,
523 523 sample_val => sample_val);
524 524
525 525 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
526 526
527 527 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
528 528 ramp_generator_1: ramp_generator
529 529 GENERIC MAP (
530 530 DATA_SIZE => 14,
531 531 VALUE_UNSIGNED_INIT => 2**I,
532 532 VALUE_UNSIGNED_INCR => 0,
533 533 VALUE_UNSIGNED_MASK => 16#3FFF#)
534 534 PORT MAP (
535 535 clk => clk_25,
536 536 rstn => rstn_25,
537 537 new_data => sample_val,
538 538 output_data => sample(I) );
539 539 END GENERATE all_sample;
540 540
541 541
542 542 END GENERATE USE_ADCDRIVER_false;
543 543
544 544
545 545
546 546
547 547 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
548 548
549 549 ADC_smpclk <= ADC_smpclk_s;
550 550 HK_smpclk <= ADC_smpclk_s;
551 551
552 552
553 553 -----------------------------------------------------------------------------
554 554 -- HK
555 555 -----------------------------------------------------------------------------
556 556 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
557 557
558 558 -----------------------------------------------------------------------------
559 559 --
560 560 -----------------------------------------------------------------------------
561 561 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
562 562 lpp_bootloader_1: lpp_bootloader
563 563 GENERIC MAP (
564 564 pindex => 13,
565 565 paddr => 13,
566 566 pmask => 16#fff#,
567 567 hindex => 3,
568 568 haddr => 0,
569 569 hmask => 16#fff#)
570 570 PORT MAP (
571 571 HCLK => clk_25,
572 572 HRESETn => rstn_25,
573 573 apbi => apbi_ext,
574 574 apbo => apbo_ext(13),
575 575 ahbsi => ahbi_s_ext,
576 576 ahbso => ahbo_s_ext(3));
577 577 END GENERATE inst_bootloader;
578 578
579 579 -----------------------------------------------------------------------------
580 580 --
581 581 -----------------------------------------------------------------------------
582 582 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
583 583 PROCESS (clk_25, rstn_25)
584 584 BEGIN -- PROCESS
585 585 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
586 586 TAG <= (OTHERS => '0');
587 587 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
588 588 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
589 589 END IF;
590 590 END PROCESS;
591 591
592 592
593 593 END GENERATE USE_DEBUG_VECTOR_IF;
594 594
595 595 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
596 596 ahbrxd <= TAG(1);
597 597 TAG(3) <= ahbtxd;
598 598 urxd1 <= TAG(2);
599 599 TAG(4) <= utxd1;
600 600 TAG(8) <= nSRAM_BUSY;
601 601 END GENERATE USE_DEBUG_VECTOR_IF2;
602 602
603 603 END beh;
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@@ -1,301 +1,228
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 USE IEEE.numeric_std.ALL;
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.general_purpose.SYNC_FF;
8 8
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 25;
13 ncycle_cnv : INTEGER := 50;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
17 17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 18 cnv_rstn : IN STD_LOGIC;
19 19
20 20 cnv : OUT STD_LOGIC;
21 21
22 22 clk : IN STD_LOGIC; -- 25MHz
23 23 rstn : IN STD_LOGIC;
24 24 ADC_data : IN Samples14;
25 25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 27 sample_val : OUT STD_LOGIC
28 28 );
29 29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 33 SIGNAL cnv_cycle_counter : INTEGER;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
37 SIGNAL cnv_sync_reg : STD_LOGIC;
38 SIGNAL cnv_sync_falling : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
39 38
40 39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
41 40 SIGNAL enable_ADC : STD_LOGIC;
42 41
43 42
44 43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
45 44
46 45 SIGNAL channel_counter : INTEGER;
47 46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
48 47
49 48 SIGNAL ADC_data_selected : Samples14;
50 49 SIGNAL ADC_data_result : Samples15;
51 50
52 51 SIGNAL sample_counter : INTEGER;
53 52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54 53
55 54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
56
57 -----------------------------------------------------------------------------
58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 1;
59 CONSTANT DATA_CYCLE_VALID : INTEGER := 2;
60 55
61 -- GEN OutPut Enable
62 TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
63 SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
64 SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1 ;
66 SIGNAL ADC_data_valid : STD_LOGIC;
67 SIGNAL ADC_data_valid_s : STD_LOGIC;
68 SIGNAL ADC_data_reg : Samples14;
69 -----------------------------------------------------------------------------
70 CONSTANT SAMPLE_DIVISION : INTEGER := 10;
71 SIGNAL sample_val_s : STD_LOGIC;
72 SIGNAL sample_val_s2 : STD_LOGIC;
73 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
74 56 BEGIN
75 57
76 58
77 59 -----------------------------------------------------------------------------
78 60 -- CNV GEN
79 61 -----------------------------------------------------------------------------
80 62 PROCESS (cnv_clk, cnv_rstn)
81 63 BEGIN -- PROCESS
82 64 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
83 65 cnv_cycle_counter <= 0;
84 66 cnv_s <= '0';
85 67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
86 68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
87 69 cnv_cycle_counter <= cnv_cycle_counter + 1;
88 IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
70 IF cnv_cycle_counter < ncycle_cnv_high THEN
89 71 cnv_s <= '1';
90 72 ELSE
91 73 cnv_s <= '0';
92 74 END IF;
93 75 ELSE
94 76 cnv_s <= '1';
95 77 cnv_cycle_counter <= 0;
96 78 END IF;
97 79 END IF;
98 80 END PROCESS;
99 81
100 82 cnv <= cnv_s;
101 83
102 84 PROCESS (cnv_clk, cnv_rstn)
103 85 BEGIN -- PROCESS
104 86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
105 87 cnv_s_reg <= '0';
106 88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
107 89 cnv_s_reg <= cnv_s;
108 90 END IF;
109 91 END PROCESS;
110 92
111 93
112 94 -----------------------------------------------------------------------------
113 95 -- SYNC CNV
114 96 -----------------------------------------------------------------------------
115 97
116 98 SYNC_FF_cnv : SYNC_FF
117 99 GENERIC MAP (
118 100 NB_FF_OF_SYNC => 2)
119 101 PORT MAP (
120 102 clk => clk,
121 103 rstn => rstn,
122 104 A => cnv_s_reg,
123 105 A_sync => cnv_sync);
124 106
107
125 108 -----------------------------------------------------------------------------
126 --
109 -- DATA GEN Output Enable
110 -----------------------------------------------------------------------------
111 PROCESS (clk, rstn)
112 BEGIN -- PROCESS
113 IF rstn = '0' THEN -- asynchronous reset (active low)
114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
115 cnv_sync_pre <= '0';
116 enable_ADC <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 cnv_sync_pre <= cnv_sync;
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
120 enable_ADC <= '1';
121 ADC_nOE_reg(0) <= '0';
122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
123 ELSE
124 enable_ADC <= NOT enable_ADC;
125 IF enable_ADC = '0' THEN
126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
127 END IF;
128 END IF;
129
130 END IF;
131 END PROCESS;
132
133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
134
135 -----------------------------------------------------------------------------
136 -- ADC READ DATA
127 137 -----------------------------------------------------------------------------
128 138 PROCESS (clk, rstn)
129 139 BEGIN -- PROCESS
130 140 IF rstn = '0' THEN -- asynchronous reset (active low)
131 cnv_sync_reg <= '0';
141 channel_counter <= MAX_COUNTER;
142
143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
144 sample_reg(I) <= (OTHERS => '0');
145 END LOOP all_sample_reg_init;
146
147 sample_val <= '0';
148 sample_counter <= 0;
132 149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
133 cnv_sync_reg <= cnv_sync;
134 END IF;
135 END PROCESS;
136
137 cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0';
138
139 -----------------------------------------------------------------------------
140 -- GEN OutPut Enable
141 -----------------------------------------------------------------------------
142 PROCESS (clk, rstn)
143 BEGIN -- PROCESS
144 IF rstn = '0' THEN
145 -------------------------------------------------------------------------
146 ADC_nOE <= (OTHERS => '1');
147 ADC_current <= 0;
148 ADC_current_cycle_enabled <= 0;
149 state_GEN_OEn <= IDLE;
150 -------------------------------------------------------------------------
151 ADC_data_reg <= (OTHERS => '0');
152 all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
153 sample_reg(I) <= (OTHERS => '0');
154 sample(I) <= (OTHERS => '0');
155 END LOOP all_channel_sample_reg_init;
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
151 channel_counter <= 0;
152 ELSE
153 IF channel_counter < MAX_COUNTER THEN
154 channel_counter <= channel_counter + 1;
155 END IF;
156 END IF;
156 157 sample_val <= '0';
157 sample_val_s <= '0';
158 sample_val_counter <= 0;
159 -------------------------------------------------------------------------
160 ELSIF clk'event AND clk = '1' THEN
161 -------------------------------------------------------------------------
162 sample_val_s <= '0';
163 ADC_nOE <= (OTHERS => '1');
164 CASE state_GEN_OEn IS
165 WHEN IDLE =>
166 IF cnv_sync_falling = '1' THEN
167 --ADC_nOE(0) <= '1';
168 state_GEN_OEn <= GEN_OE;
169 ADC_current <= 0;
170 ADC_current_cycle_enabled <= 1;
158
159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
160 IF channel_counter = I*2 THEN
161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
163 ELSE
164 sample_reg(I) <= ADC_data;
171 165 END IF;
172
173 WHEN GEN_OE =>
174 ADC_nOE(ADC_current) <= '0';
175
176 ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
177
178 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
179 state_GEN_OEn <= WAIT_CYCLE;
180 END IF;
181
182 WHEN WAIT_CYCLE =>
183 ADC_current_cycle_enabled <= 1;
184 IF ADC_current = ChanelCount-1 THEN
185 state_GEN_OEn <= IDLE;
186 sample_val_s <= '1';
187 ELSE
188 ADC_current <= ADC_current + 1;
189 state_GEN_OEn <= GEN_OE;
190 END IF;
191 WHEN OTHERS => NULL;
192 END CASE;
193 -------------------------------------------------------------------------
194 ADC_data_reg <= ADC_data;
166 END IF;
167 END LOOP all_sample_reg;
195 168
196 all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
197 IF ADC_data_valid = '1' AND ADC_current = I THEN
198 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
169 IF channel_counter = (ChanelCount-1)*2 THEN
170
171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
172 sample_counter <= 0 ;
173 sample_val <= '1';
199 174 ELSE
200 sample_reg(I) <= sample_reg(I);
175 sample_counter <= sample_counter +1;
201 176 END IF;
202 END LOOP all_channel_sample_reg;
203 -------------------------------------------------------------------------
204 sample_val <= '0';
205 IF sample_val_s2 = '1' THEN
206 IF sample_val_counter = SAMPLE_DIVISION-1 THEN
207 sample_val_counter <= 0;
208 sample_val <= '1'; -- TODO
209 sample <= sample_reg;
210 ELSE
211 sample_val_counter <= sample_val_counter + 1;
212 sample_val <= '0';
213 END IF;
214 END IF;
215
177
178 END IF;
216 179 END IF;
217 180 END PROCESS;
218 181
182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
183 -- BEGIN -- PROCESS mux_adc
184 -- CASE channel_counter IS
185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
186 -- END CASE;
187 -- END PROCESS mux_adc;
219 188
220 189
221 REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE
222 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
223
224 PROCESS (clk, rstn)
225 BEGIN -- PROCESS
226 IF rstn = '0' THEN -- asynchronous reset (active low)
227 ADC_data_valid <= '0';
228 sample_val_s2 <= '0';
229 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
230 ADC_data_valid <= ADC_data_valid_s;
231 sample_val_s2 <= sample_val_s;
232 END IF;
233 END PROCESS;
234
235 END GENERATE REG_ADC_DATA_valid;
190 -----------------------------------------------------------------------------
191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
192 -----------------------------------------------------------------------------
236 193
237 noREG_ADC_DATA_valid: IF DATA_CYCLE_VALID < OE_NB_CYCLE_ENABLED GENERATE
238 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
239
240 ADC_data_valid <= ADC_data_valid_s;
241 sample_val_s2 <= sample_val_s;
242 END GENERATE noREG_ADC_DATA_valid;
243
244 REGm_ADC_DATA_valid: IF DATA_CYCLE_VALID > OE_NB_CYCLE_ENABLED GENERATE
245
246 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED + 1 ELSE '0';
247
248 REG_1: SYNC_FF
249 GENERIC MAP (
250 NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1)
251 PORT MAP (
252 clk => clk,
253 rstn => rstn,
254 A => ADC_data_valid_s,
255 A_sync => ADC_data_valid);
256
257 REG_2: SYNC_FF
258 GENERIC MAP (
259 NB_FF_OF_SYNC => DATA_CYCLE_VALID-OE_NB_CYCLE_ENABLED+1)
260 PORT MAP (
261 clk => clk,
262 rstn => rstn,
263 A => sample_val_s,
264 A_sync => sample_val_s2);
265 END GENERATE REGm_ADC_DATA_valid;
266
267
268
269 WITH ADC_current SELECT
270 ADC_data_selected <= sample_reg(0) WHEN 0,
271 sample_reg(1) WHEN 1,
272 sample_reg(2) WHEN 2,
273 sample_reg(3) WHEN 3,
274 sample_reg(4) WHEN 4,
275 sample_reg(5) WHEN 5,
276 sample_reg(6) WHEN 6,
277 sample_reg(7) WHEN 7,
194 WITH channel_counter SELECT
195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
196 sample_reg(1) WHEN 1*2,
197 sample_reg(2) WHEN 2*2,
198 sample_reg(3) WHEN 3*2,
199 sample_reg(4) WHEN 4*2,
200 sample_reg(5) WHEN 5*2,
201 sample_reg(6) WHEN 6*2,
202 sample_reg(7) WHEN 7*2,
278 203 sample_reg(8) WHEN OTHERS ;
279 204
280 ADC_data_result <= std_logic_vector((
281 signed( ADC_data_selected(13) & ADC_data_selected) +
282 signed( ADC_data_reg(13) & ADC_data_reg)
283 ));
205 -----------------------------------------------------------------------------
206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
207 -----------------------------------------------------------------------------
284 208
285 -- sample <= sample_reg;
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
210
211 sample <= sample_reg;
286 212
287 213 END ar_top_ad_conv_RHF1401;
288 214
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