@@ -1,95 +1,97 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 |
|
25 | |||
26 | entity Dispatch is |
|
26 | entity Dispatch is | |
27 | generic( |
|
27 | generic( | |
28 | Data_SZ : integer := 32); |
|
28 | Data_SZ : integer := 32); | |
29 | port( |
|
29 | port( | |
30 | clk : in std_logic; |
|
30 | clk : in std_logic; | |
31 | reset : in std_logic; |
|
31 | reset : in std_logic; | |
32 | Acq : in std_logic; |
|
32 | Acq : in std_logic; | |
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
33 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
34 | Write : in std_logic; |
|
34 | Write : in std_logic; | |
35 |
|
|
35 | Valid : in std_logic; | |
|
36 | -- Full : in std_logic_vector(1 downto 0); | |||
36 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
37 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
37 | FifoWrite : out std_logic_vector(1 downto 0); |
|
38 | FifoWrite : out std_logic_vector(1 downto 0); | |
38 | Pong : out std_logic; |
|
39 | Pong : out std_logic; | |
39 | Error : out std_logic |
|
40 | Error : out std_logic | |
40 | ); |
|
41 | ); | |
41 | end entity; |
|
42 | end entity; | |
42 |
|
43 | |||
43 |
|
44 | |||
44 | architecture ar_Dispatch of Dispatch is |
|
45 | architecture ar_Dispatch of Dispatch is | |
45 |
|
46 | |||
46 | type etat is (eX,e0,e1,e2); |
|
47 | type etat is (eX,e0,e1,e2); | |
47 | signal ect : etat; |
|
48 | signal ect : etat; | |
48 |
|
49 | |||
49 | signal Pong_int : std_logic; |
|
50 | signal Pong_int : std_logic; | |
50 | signal FifoCpt : integer range 0 to 1 := 0; |
|
51 | --signal FifoCpt : integer range 0 to 1 := 0; | |
51 |
|
52 | |||
52 | begin |
|
53 | begin | |
53 |
|
54 | |||
54 | process (clk,reset) |
|
55 | process (clk,reset) | |
55 | begin |
|
56 | begin | |
56 | if(reset='0')then |
|
57 | if(reset='0')then | |
57 | Pong_int <= '0'; |
|
58 | Pong_int <= '0'; | |
58 | Error <= '0'; |
|
59 | Error <= '0'; | |
59 | ect <= e0; |
|
60 | ect <= e0; | |
60 |
|
61 | |||
61 | elsif(clk' event and clk='1')then |
|
62 | elsif(clk' event and clk='1')then | |
62 |
|
63 | |||
63 | case ect is |
|
64 | case ect is | |
64 |
|
65 | |||
65 | when e0 => |
|
66 | when e0 => | |
66 | if(Full(FifoCpt) = '1')then |
|
67 | -- if(Full(FifoCpt) = '1')then | |
|
68 | if(Valid = '1')then | |||
67 | Pong_int <= not Pong_int; |
|
69 | Pong_int <= not Pong_int; | |
68 | ect <= e1; |
|
70 | ect <= e1; | |
69 | end if; |
|
71 | end if; | |
70 |
|
72 | |||
71 | when e1 => |
|
73 | when e1 => | |
72 | if(Acq = '0')then |
|
74 | if(Acq = '0')then | |
73 | Error <= '1'; |
|
75 | Error <= '1'; | |
74 | ect <= e1; |
|
76 | ect <= e1; | |
75 | else |
|
77 | else | |
76 | Error <= '0'; |
|
78 | Error <= '0'; | |
77 | ect <= e0; |
|
79 | ect <= e0; | |
78 | end if; |
|
80 | end if; | |
79 |
|
81 | |||
80 | when others => |
|
82 | when others => | |
81 | null; |
|
83 | null; | |
82 |
|
84 | |||
83 | end case; |
|
85 | end case; | |
84 |
|
86 | |||
85 | end if; |
|
87 | end if; | |
86 | end process; |
|
88 | end process; | |
87 |
|
89 | |||
88 | FifoData <= Data & Data; |
|
90 | FifoData <= Data & Data; | |
89 | Pong <= Pong_int; |
|
91 | Pong <= Pong_int; | |
90 |
|
92 | |||
91 | FifoCpt <= 0 when Pong_int='0' else 1; |
|
93 | --FifoCpt <= 0 when Pong_int='0' else 1; | |
92 |
|
94 | |||
93 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; |
|
95 | FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; | |
94 |
|
96 | |||
95 | end architecture; No newline at end of file |
|
97 | end architecture; |
@@ -1,84 +1,87 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | --library lpp; |
|
25 | --library lpp; | |
26 | --use lpp.lpp_matrix.all; |
|
26 | --use lpp.lpp_matrix.all; | |
27 |
|
27 | |||
28 | entity MatriceSpectrale is |
|
28 | entity MatriceSpectrale is | |
29 | generic( |
|
29 | generic( | |
30 | Input_SZ : integer := 16; |
|
30 | Input_SZ : integer := 16; | |
31 | Result_SZ : integer := 32); |
|
31 | Result_SZ : integer := 32); | |
32 | port( |
|
32 | port( | |
33 | clkm : in std_logic; |
|
33 | clkm : in std_logic; | |
34 | rstn : in std_logic; |
|
34 | rstn : in std_logic; | |
35 |
|
35 | |||
36 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
36 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
37 | SetReUse : in std_logic_vector(4 downto 0); |
|
37 | SetReUse : in std_logic_vector(4 downto 0); | |
38 | FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
38 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |
|
39 | Valid : in std_logic; | |||
39 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
40 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
40 | ACQ : in std_logic; |
|
41 | ACQ : in std_logic; | |
|
42 | SM_Write : out std_logic; | |||
41 | FlagError : out std_logic; |
|
43 | FlagError : out std_logic; | |
42 | Pong : out std_logic; |
|
44 | Pong : out std_logic; | |
43 | Statu : out std_logic_vector(3 downto 0); |
|
45 | Statu : out std_logic_vector(3 downto 0); | |
44 | Write : out std_logic_vector(1 downto 0); |
|
46 | Write : out std_logic_vector(1 downto 0); | |
45 | Read : out std_logic_vector(4 downto 0); |
|
47 | Read : out std_logic_vector(4 downto 0); | |
46 | ReUse : out std_logic_vector(4 downto 0); |
|
48 | ReUse : out std_logic_vector(4 downto 0); | |
47 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) |
|
49 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |
48 | ); |
|
50 | ); | |
49 | end entity; |
|
51 | end entity; | |
50 |
|
52 | |||
51 |
|
53 | |||
52 | architecture ar_MatriceSpectrale of MatriceSpectrale is |
|
54 | architecture ar_MatriceSpectrale of MatriceSpectrale is | |
53 |
|
55 | |||
54 | signal Matrix_Write : std_logic; |
|
56 | signal Matrix_Write : std_logic; | |
55 | signal Matrix_Read : std_logic_vector(1 downto 0); |
|
57 | signal Matrix_Read : std_logic_vector(1 downto 0); | |
56 | signal Matrix_Result : std_logic_vector(31 downto 0); |
|
58 | signal Matrix_Result : std_logic_vector(31 downto 0); | |
57 |
|
59 | |||
58 | signal TopSM_Start : std_logic; |
|
60 | signal TopSM_Start : std_logic; | |
59 | signal TopSM_Statu : std_logic_vector(3 downto 0); |
|
61 | signal TopSM_Statu : std_logic_vector(3 downto 0); | |
60 | signal TopSM_Data1 : std_logic_vector(15 downto 0); |
|
62 | signal TopSM_Data1 : std_logic_vector(15 downto 0); | |
61 | signal TopSM_Data2 : std_logic_vector(15 downto 0); |
|
63 | signal TopSM_Data2 : std_logic_vector(15 downto 0); | |
62 |
|
64 | |||
63 | begin |
|
65 | begin | |
64 |
|
66 | |||
65 | CTRL0 : entity work.ReUse_CTRLR |
|
67 | CTRL0 : entity work.ReUse_CTRLR | |
66 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); |
|
68 | port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); | |
67 |
|
69 | |||
68 |
|
70 | |||
69 | TopSM : entity work.TopSpecMatrix |
|
71 | TopSM : entity work.TopSpecMatrix | |
70 | generic map (Input_SZ) |
|
72 | generic map (Input_SZ) | |
71 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); |
|
73 | port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); | |
72 |
|
74 | |||
73 | SM : entity work.SpectralMatrix |
|
75 | SM : entity work.SpectralMatrix | |
74 | generic map (Input_SZ,Result_SZ) |
|
76 | generic map (Input_SZ,Result_SZ) | |
75 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); |
|
77 | port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); | |
76 |
|
78 | |||
77 | DISP : entity work.Dispatch |
|
79 | DISP : entity work.Dispatch | |
78 | generic map(Result_SZ) |
|
80 | generic map(Result_SZ) | |
79 |
port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write, |
|
81 | port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); | |
80 |
|
82 | |||
81 | Statu <= TopSM_Statu; |
|
83 | Statu <= TopSM_Statu; | |
|
84 | SM_Write <= Matrix_Write; | |||
82 |
|
85 | |||
83 | end architecture; |
|
86 | end architecture; | |
84 |
|
87 |
@@ -1,266 +1,269 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
31 |
|
31 | |||
32 | package lpp_matrix is |
|
32 | package lpp_matrix is | |
33 |
|
33 | |||
34 | component APB_Matrix is |
|
34 | component APB_Matrix is | |
35 | generic ( |
|
35 | generic ( | |
36 | pindex : integer := 0; |
|
36 | pindex : integer := 0; | |
37 | paddr : integer := 0; |
|
37 | paddr : integer := 0; | |
38 | pmask : integer := 16#fff#; |
|
38 | pmask : integer := 16#fff#; | |
39 | pirq : integer := 0; |
|
39 | pirq : integer := 0; | |
40 | abits : integer := 8; |
|
40 | abits : integer := 8; | |
41 | Input_SZ : integer := 16; |
|
41 | Input_SZ : integer := 16; | |
42 | Result_SZ : integer := 32); |
|
42 | Result_SZ : integer := 32); | |
43 | port ( |
|
43 | port ( | |
44 | clk : in std_logic; |
|
44 | clk : in std_logic; | |
45 | rst : in std_logic; |
|
45 | rst : in std_logic; | |
46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
46 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
47 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
48 | Full : in std_logic_vector(1 downto 0); |
|
48 | Full : in std_logic_vector(1 downto 0); | |
49 | Empty : in std_logic_vector(1 downto 0); |
|
49 | Empty : in std_logic_vector(1 downto 0); | |
50 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
50 | ReadFIFO : out std_logic_vector(1 downto 0); | |
51 | FullFIFO : in std_logic; |
|
51 | FullFIFO : in std_logic; | |
52 | WriteFIFO : out std_logic; |
|
52 | WriteFIFO : out std_logic; | |
53 | Result : out std_logic_vector(Result_SZ-1 downto 0); |
|
53 | Result : out std_logic_vector(Result_SZ-1 downto 0); | |
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
54 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
55 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
56 | ); |
|
56 | ); | |
57 | end component; |
|
57 | end component; | |
58 |
|
58 | |||
59 | component MatriceSpectrale is |
|
59 | component MatriceSpectrale is | |
60 | generic( |
|
60 | generic( | |
61 | Input_SZ : integer := 16; |
|
61 | Input_SZ : integer := 16; | |
62 | Result_SZ : integer := 32); |
|
62 | Result_SZ : integer := 32); | |
63 | port( |
|
63 | port( | |
64 | clkm : in std_logic; |
|
64 | clkm : in std_logic; | |
65 | rstn : in std_logic; |
|
65 | rstn : in std_logic; | |
66 |
|
66 | |||
67 | FifoIN_Full : in std_logic_vector(4 downto 0); |
|
67 | FifoIN_Full : in std_logic_vector(4 downto 0); | |
68 | SetReUse : in std_logic_vector(4 downto 0); |
|
68 | SetReUse : in std_logic_vector(4 downto 0); | |
69 | FifoOUT_Full : in std_logic_vector(1 downto 0); |
|
69 | -- FifoOUT_Full : in std_logic_vector(1 downto 0); | |
|
70 | Valid : in std_logic; | |||
70 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
71 | Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
71 | ACQ : in std_logic; |
|
72 | ACQ : in std_logic; | |
|
73 | SM_Write : out std_logic; | |||
72 | FlagError : out std_logic; |
|
74 | FlagError : out std_logic; | |
73 | Pong : out std_logic; |
|
75 | Pong : out std_logic; | |
74 | Statu : out std_logic_vector(3 downto 0); |
|
76 | Statu : out std_logic_vector(3 downto 0); | |
75 | Write : out std_logic_vector(1 downto 0); |
|
77 | Write : out std_logic_vector(1 downto 0); | |
76 | Read : out std_logic_vector(4 downto 0); |
|
78 | Read : out std_logic_vector(4 downto 0); | |
77 | ReUse : out std_logic_vector(4 downto 0); |
|
79 | ReUse : out std_logic_vector(4 downto 0); | |
78 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) |
|
80 | Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) | |
79 | ); |
|
81 | ); | |
80 | end component; |
|
82 | end component; | |
81 |
|
83 | |||
82 |
|
84 | |||
83 | component TopSpecMatrix is |
|
85 | component TopSpecMatrix is | |
84 | generic( |
|
86 | generic( | |
85 | Input_SZ : integer := 16); |
|
87 | Input_SZ : integer := 16); | |
86 | port( |
|
88 | port( | |
87 | clk : in std_logic; |
|
89 | clk : in std_logic; | |
88 | rstn : in std_logic; |
|
90 | rstn : in std_logic; | |
89 | Write : in std_logic; |
|
91 | Write : in std_logic; | |
90 | ReadIn : in std_logic_vector(1 downto 0); |
|
92 | ReadIn : in std_logic_vector(1 downto 0); | |
91 | Full : in std_logic_vector(4 downto 0); |
|
93 | Full : in std_logic_vector(4 downto 0); | |
92 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
94 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
93 | Start : out std_logic; |
|
95 | Start : out std_logic; | |
94 | ReadOut : out std_logic_vector(4 downto 0); |
|
96 | ReadOut : out std_logic_vector(4 downto 0); | |
95 | Statu : out std_logic_vector(3 downto 0); |
|
97 | Statu : out std_logic_vector(3 downto 0); | |
96 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
98 | DATA1 : out std_logic_vector(Input_SZ-1 downto 0); | |
97 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) |
|
99 | DATA2 : out std_logic_vector(Input_SZ-1 downto 0) | |
98 | ); |
|
100 | ); | |
99 | end component; |
|
101 | end component; | |
100 |
|
102 | |||
101 |
|
103 | |||
102 | component Top_MatrixSpec is |
|
104 | component Top_MatrixSpec is | |
103 | generic( |
|
105 | generic( | |
104 | Input_SZ : integer := 16; |
|
106 | Input_SZ : integer := 16; | |
105 | Result_SZ : integer := 32); |
|
107 | Result_SZ : integer := 32); | |
106 | port( |
|
108 | port( | |
107 | clk : in std_logic; |
|
109 | clk : in std_logic; | |
108 | reset : in std_logic; |
|
110 | reset : in std_logic; | |
109 | Statu : in std_logic_vector(3 downto 0); |
|
111 | Statu : in std_logic_vector(3 downto 0); | |
110 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
112 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
111 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
113 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
112 | Full : in std_logic_vector(1 downto 0); |
|
114 | Full : in std_logic_vector(1 downto 0); | |
113 | Empty : in std_logic_vector(1 downto 0); |
|
115 | Empty : in std_logic_vector(1 downto 0); | |
114 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
116 | ReadFIFO : out std_logic_vector(1 downto 0); | |
115 | FullFIFO : in std_logic; |
|
117 | FullFIFO : in std_logic; | |
116 | WriteFIFO : out std_logic; |
|
118 | WriteFIFO : out std_logic; | |
117 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
119 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
118 | ); |
|
120 | ); | |
119 | end component; |
|
121 | end component; | |
120 |
|
122 | |||
121 | component SpectralMatrix is |
|
123 | component SpectralMatrix is | |
122 | generic( |
|
124 | generic( | |
123 | Input_SZ : integer := 16; |
|
125 | Input_SZ : integer := 16; | |
124 | Result_SZ : integer := 32); |
|
126 | Result_SZ : integer := 32); | |
125 | port( |
|
127 | port( | |
126 | clk : in std_logic; |
|
128 | clk : in std_logic; | |
127 | reset : in std_logic; |
|
129 | reset : in std_logic; | |
128 | Start : in std_logic; |
|
130 | Start : in std_logic; | |
129 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
131 | FIFO1 : in std_logic_vector(Input_SZ-1 downto 0); | |
130 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
132 | FIFO2 : in std_logic_vector(Input_SZ-1 downto 0); | |
131 | Statu : in std_logic_vector(3 downto 0); |
|
133 | Statu : in std_logic_vector(3 downto 0); | |
132 | -- FullFIFO : in std_logic; |
|
134 | -- FullFIFO : in std_logic; | |
133 | ReadFIFO : out std_logic_vector(1 downto 0); |
|
135 | ReadFIFO : out std_logic_vector(1 downto 0); | |
134 | WriteFIFO : out std_logic; |
|
136 | WriteFIFO : out std_logic; | |
135 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
137 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
136 | ); |
|
138 | ); | |
137 | end component; |
|
139 | end component; | |
138 |
|
140 | |||
139 |
|
141 | |||
140 | component Matrix is |
|
142 | component Matrix is | |
141 | generic( |
|
143 | generic( | |
142 | Input_SZ : integer := 16); |
|
144 | Input_SZ : integer := 16); | |
143 | port( |
|
145 | port( | |
144 | clk : in std_logic; |
|
146 | clk : in std_logic; | |
145 | raz : in std_logic; |
|
147 | raz : in std_logic; | |
146 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
148 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
147 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
149 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
148 | Take : in std_logic; |
|
150 | Take : in std_logic; | |
149 | Received : in std_logic; |
|
151 | Received : in std_logic; | |
150 | Conjugate : in std_logic; |
|
152 | Conjugate : in std_logic; | |
151 | Valid : out std_logic; |
|
153 | Valid : out std_logic; | |
152 | Read : out std_logic; |
|
154 | Read : out std_logic; | |
153 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
|
155 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) | |
154 | ); |
|
156 | ); | |
155 | end component; |
|
157 | end component; | |
156 |
|
158 | |||
157 | component GetResult is |
|
159 | component GetResult is | |
158 | generic( |
|
160 | generic( | |
159 | Result_SZ : integer := 32); |
|
161 | Result_SZ : integer := 32); | |
160 | port( |
|
162 | port( | |
161 | clk : in std_logic; |
|
163 | clk : in std_logic; | |
162 | raz : in std_logic; |
|
164 | raz : in std_logic; | |
163 | Valid : in std_logic; |
|
165 | Valid : in std_logic; | |
164 | Conjugate : in std_logic; |
|
166 | Conjugate : in std_logic; | |
165 | Res : in std_logic_vector(Result_SZ-1 downto 0); |
|
167 | Res : in std_logic_vector(Result_SZ-1 downto 0); | |
166 | -- Full : in std_logic; |
|
168 | -- Full : in std_logic; | |
167 | WriteFIFO : out std_logic; |
|
169 | WriteFIFO : out std_logic; | |
168 | Received : out std_logic; |
|
170 | Received : out std_logic; | |
169 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
171 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
170 | ); |
|
172 | ); | |
171 | end component; |
|
173 | end component; | |
172 |
|
174 | |||
173 |
|
175 | |||
174 | component TopMatrix_PDR is |
|
176 | component TopMatrix_PDR is | |
175 | generic( |
|
177 | generic( | |
176 | Input_SZ : integer := 16; |
|
178 | Input_SZ : integer := 16; | |
177 | Result_SZ : integer := 32); |
|
179 | Result_SZ : integer := 32); | |
178 | port( |
|
180 | port( | |
179 | clk : in std_logic; |
|
181 | clk : in std_logic; | |
180 | reset : in std_logic; |
|
182 | reset : in std_logic; | |
181 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); |
|
183 | Data : in std_logic_vector((5*Input_SZ)-1 downto 0); | |
182 | FULLin : in std_logic_vector(4 downto 0); |
|
184 | FULLin : in std_logic_vector(4 downto 0); | |
183 | READin : in std_logic_vector(1 downto 0); |
|
185 | READin : in std_logic_vector(1 downto 0); | |
184 | WRITEin : in std_logic; |
|
186 | WRITEin : in std_logic; | |
185 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
187 | FIFO1 : out std_logic_vector(Input_SZ-1 downto 0); | |
186 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); |
|
188 | FIFO2 : out std_logic_vector(Input_SZ-1 downto 0); | |
187 | Start : out std_logic; |
|
189 | Start : out std_logic; | |
188 | Read : out std_logic_vector(4 downto 0); |
|
190 | Read : out std_logic_vector(4 downto 0); | |
189 | Statu : out std_logic_vector(3 downto 0) |
|
191 | Statu : out std_logic_vector(3 downto 0) | |
190 | ); |
|
192 | ); | |
191 | end component; |
|
193 | end component; | |
192 |
|
194 | |||
193 |
|
195 | |||
194 | component Dispatch is |
|
196 | component Dispatch is | |
195 | generic( |
|
197 | generic( | |
196 | Data_SZ : integer := 32); |
|
198 | Data_SZ : integer := 32); | |
197 | port( |
|
199 | port( | |
198 | clk : in std_logic; |
|
200 | clk : in std_logic; | |
199 | reset : in std_logic; |
|
201 | reset : in std_logic; | |
200 | Acq : in std_logic; |
|
202 | Acq : in std_logic; | |
201 | Data : in std_logic_vector(Data_SZ-1 downto 0); |
|
203 | Data : in std_logic_vector(Data_SZ-1 downto 0); | |
202 | Write : in std_logic; |
|
204 | Write : in std_logic; | |
203 |
|
|
205 | Valid : in std_logic; | |
|
206 | -- Full : in std_logic_vector(1 downto 0); | |||
204 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); |
|
207 | FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); | |
205 | FifoWrite : out std_logic_vector(1 downto 0); |
|
208 | FifoWrite : out std_logic_vector(1 downto 0); | |
206 | Pong : out std_logic; |
|
209 | Pong : out std_logic; | |
207 | Error : out std_logic |
|
210 | Error : out std_logic | |
208 | ); |
|
211 | ); | |
209 | end component; |
|
212 | end component; | |
210 |
|
213 | |||
211 |
|
214 | |||
212 | component DriveInputs is |
|
215 | component DriveInputs is | |
213 | port( |
|
216 | port( | |
214 | clk : in std_logic; |
|
217 | clk : in std_logic; | |
215 | raz : in std_logic; |
|
218 | raz : in std_logic; | |
216 | Read : in std_logic; |
|
219 | Read : in std_logic; | |
217 | Conjugate : in std_logic; |
|
220 | Conjugate : in std_logic; | |
218 | Take : out std_logic; |
|
221 | Take : out std_logic; | |
219 | ReadFIFO : out std_logic_vector(1 downto 0) |
|
222 | ReadFIFO : out std_logic_vector(1 downto 0) | |
220 | ); |
|
223 | ); | |
221 | end component; |
|
224 | end component; | |
222 |
|
225 | |||
223 | component Starter is |
|
226 | component Starter is | |
224 | port( |
|
227 | port( | |
225 | clk : in std_logic; |
|
228 | clk : in std_logic; | |
226 | raz : in std_logic; |
|
229 | raz : in std_logic; | |
227 | Full : in std_logic_vector(1 downto 0); |
|
230 | Full : in std_logic_vector(1 downto 0); | |
228 | Empty : in std_logic_vector(1 downto 0); |
|
231 | Empty : in std_logic_vector(1 downto 0); | |
229 | Statu : in std_logic_vector(3 downto 0); |
|
232 | Statu : in std_logic_vector(3 downto 0); | |
230 | Write : in std_logic; |
|
233 | Write : in std_logic; | |
231 | Start : out std_logic |
|
234 | Start : out std_logic | |
232 | ); |
|
235 | ); | |
233 | end component; |
|
236 | end component; | |
234 |
|
237 | |||
235 | component ALU_Driver is |
|
238 | component ALU_Driver is | |
236 | generic( |
|
239 | generic( | |
237 | Input_SZ_1 : integer := 16; |
|
240 | Input_SZ_1 : integer := 16; | |
238 | Input_SZ_2 : integer := 16); |
|
241 | Input_SZ_2 : integer := 16); | |
239 | port( |
|
242 | port( | |
240 | clk : in std_logic; |
|
243 | clk : in std_logic; | |
241 | reset : in std_logic; |
|
244 | reset : in std_logic; | |
242 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
245 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
243 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
246 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
244 | Take : in std_logic; |
|
247 | Take : in std_logic; | |
245 | Received : in std_logic; |
|
248 | Received : in std_logic; | |
246 | Conjugate : in std_logic; |
|
249 | Conjugate : in std_logic; | |
247 | Valid : out std_logic; |
|
250 | Valid : out std_logic; | |
248 | Read : out std_logic; |
|
251 | Read : out std_logic; | |
249 | CTRL : out std_logic_vector(2 downto 0); |
|
252 | CTRL : out std_logic_vector(2 downto 0); | |
250 | COMP : out std_logic_vector(1 downto 0); |
|
253 | COMP : out std_logic_vector(1 downto 0); | |
251 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); |
|
254 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); | |
252 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) |
|
255 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) | |
253 | ); |
|
256 | ); | |
254 | end component; |
|
257 | end component; | |
255 |
|
258 | |||
256 | component ReUse_CTRLR is |
|
259 | component ReUse_CTRLR is | |
257 | port( |
|
260 | port( | |
258 | clk : in std_logic; |
|
261 | clk : in std_logic; | |
259 | reset : in std_logic; |
|
262 | reset : in std_logic; | |
260 | SetReUse : in std_logic_vector(4 downto 0); |
|
263 | SetReUse : in std_logic_vector(4 downto 0); | |
261 | Statu : in std_logic_vector(3 downto 0); |
|
264 | Statu : in std_logic_vector(3 downto 0); | |
262 | ReUse : out std_logic_vector(4 downto 0) |
|
265 | ReUse : out std_logic_vector(4 downto 0) | |
263 | ); |
|
266 | ); | |
264 | end component; |
|
267 | end component; | |
265 |
|
268 | |||
266 | end; No newline at end of file |
|
269 | end; |
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