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Forward DATA_SHAPING_SATURATION generic from lpp_lfr to lpp_lfr_filter.
jeandet -
r666:165069c8bf8d default draft
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 tech : INTEGER := inferred;
28 tech : INTEGER := inferred;
29 nb_data_by_buffer_size : INTEGER := 32;
29 nb_data_by_buffer_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
30 nb_snapshot_param_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
31 delta_vector_size : INTEGER := 32;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 15;
34 pindex : INTEGER := 15;
35 paddr : INTEGER := 15;
35 paddr : INTEGER := 15;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 6;
37 pirq_ms : INTEGER := 6;
38 pirq_wfp : INTEGER := 14;
38 pirq_wfp : INTEGER := 14;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43
43
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
45 RTL_DESIGN_LIGHT : INTEGER := 0;
45 RTL_DESIGN_LIGHT : INTEGER := 0;
46 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15;
46 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15;
47 DATA_SHAPING_SATURATION : INTEGER := 0
47 DATA_SHAPING_SATURATION : INTEGER := 0
48 );
48 );
49 PORT (
49 PORT (
50 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
52 -- SAMPLE
52 -- SAMPLE
53 sample_B : IN Samples(2 DOWNTO 0);
53 sample_B : IN Samples(2 DOWNTO 0);
54 sample_E : IN Samples(4 DOWNTO 0);
54 sample_E : IN Samples(4 DOWNTO 0);
55 sample_val : IN STD_LOGIC;
55 sample_val : IN STD_LOGIC;
56 -- APB
56 -- APB
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59 -- AHB
59 -- AHB
60 ahbi : IN AHB_Mst_In_Type;
60 ahbi : IN AHB_Mst_In_Type;
61 ahbo : OUT AHB_Mst_Out_Type;
61 ahbo : OUT AHB_Mst_Out_Type;
62 -- TIME
62 -- TIME
63 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
63 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
64 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
64 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
65 --
65 --
66 data_shaping_BW : OUT STD_LOGIC;
66 data_shaping_BW : OUT STD_LOGIC;
67 --
67 --
68 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
68 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
69 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
69 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
70 );
70 );
71 END lpp_lfr;
71 END lpp_lfr;
72
72
73 ARCHITECTURE beh OF lpp_lfr IS
73 ARCHITECTURE beh OF lpp_lfr IS
74 SIGNAL sample_s : Samples(7 DOWNTO 0);
74 SIGNAL sample_s : Samples(7 DOWNTO 0);
75 --
75 --
76 SIGNAL data_shaping_SP0 : STD_LOGIC;
76 SIGNAL data_shaping_SP0 : STD_LOGIC;
77 SIGNAL data_shaping_SP1 : STD_LOGIC;
77 SIGNAL data_shaping_SP1 : STD_LOGIC;
78 SIGNAL data_shaping_R0 : STD_LOGIC;
78 SIGNAL data_shaping_R0 : STD_LOGIC;
79 SIGNAL data_shaping_R1 : STD_LOGIC;
79 SIGNAL data_shaping_R1 : STD_LOGIC;
80 SIGNAL data_shaping_R2 : STD_LOGIC;
80 SIGNAL data_shaping_R2 : STD_LOGIC;
81 --
81 --
82 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 --
85 --
86 SIGNAL sample_f0_val : STD_LOGIC;
86 SIGNAL sample_f0_val : STD_LOGIC;
87 SIGNAL sample_f1_val : STD_LOGIC;
87 SIGNAL sample_f1_val : STD_LOGIC;
88 SIGNAL sample_f2_val : STD_LOGIC;
88 SIGNAL sample_f2_val : STD_LOGIC;
89 SIGNAL sample_f3_val : STD_LOGIC;
89 SIGNAL sample_f3_val : STD_LOGIC;
90 --
90 --
91 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 --
95 --
96 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
96 SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
97 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
97 SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
98 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
98 SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
99 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
99 SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
100 --
100 --
101 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104
104
105 -- SM
105 -- SM
106 SIGNAL ready_matrix_f0 : STD_LOGIC;
106 SIGNAL ready_matrix_f0 : STD_LOGIC;
107 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
107 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
108 SIGNAL ready_matrix_f1 : STD_LOGIC;
108 SIGNAL ready_matrix_f1 : STD_LOGIC;
109 SIGNAL ready_matrix_f2 : STD_LOGIC;
109 SIGNAL ready_matrix_f2 : STD_LOGIC;
110 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
110 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
111 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
111 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
117 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
118 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
118 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
119 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
119 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
120
120
121 -- WFP
121 -- WFP
122 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
122 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
123 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
125 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
125 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
126 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
126 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
127 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
127 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
128
128
129 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
130 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
131 SIGNAL enable_f0 : STD_LOGIC;
131 SIGNAL enable_f0 : STD_LOGIC;
132 SIGNAL enable_f1 : STD_LOGIC;
132 SIGNAL enable_f1 : STD_LOGIC;
133 SIGNAL enable_f2 : STD_LOGIC;
133 SIGNAL enable_f2 : STD_LOGIC;
134 SIGNAL enable_f3 : STD_LOGIC;
134 SIGNAL enable_f3 : STD_LOGIC;
135 SIGNAL burst_f0 : STD_LOGIC;
135 SIGNAL burst_f0 : STD_LOGIC;
136 SIGNAL burst_f1 : STD_LOGIC;
136 SIGNAL burst_f1 : STD_LOGIC;
137 SIGNAL burst_f2 : STD_LOGIC;
137 SIGNAL burst_f2 : STD_LOGIC;
138
138
139 --SIGNAL run : STD_LOGIC;
139 --SIGNAL run : STD_LOGIC;
140 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
140 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
141
141
142 -----------------------------------------------------------------------------
142 -----------------------------------------------------------------------------
143 --
143 --
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145
145
146 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
146 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
147 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
147 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
148 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
148 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
149 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
150 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
151 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
152
152
153 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
153 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
154 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
154 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
155 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
155 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
156
156
157
157
158 SIGNAL error_buffer_full : STD_LOGIC;
158 SIGNAL error_buffer_full : STD_LOGIC;
159 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
159 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
160
160
161 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
162 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
163 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
164 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
164 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
165 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
165 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
166 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
166 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
167 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
169 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
170 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
170 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
171 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 SIGNAL dma_grant_error : STD_LOGIC;
173 SIGNAL dma_grant_error : STD_LOGIC;
174
174
175 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
177 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
181 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
181 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
182
182
183 BEGIN
183 BEGIN
184
184
185 -----------------------------------------------------------------------------
185 -----------------------------------------------------------------------------
186
186
187 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
187 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
188 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
188 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
189 sample_time <= coarse_time & fine_time;
189 sample_time <= coarse_time & fine_time;
190
190
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 lpp_lfr_filter_1 : lpp_lfr_filter
192 lpp_lfr_filter_1 : lpp_lfr_filter
193 GENERIC MAP (
193 GENERIC MAP (
194 tech => tech,
194 tech => tech,
195 Mem_use => Mem_use,
195 Mem_use => Mem_use,
196 RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
196 RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT,
197 DATA_SHAPING_SATURATION => DATA_SHAPING_SATURATION)
197 PORT MAP (
198 PORT MAP (
198 sample => sample_s,
199 sample => sample_s,
199 sample_val => sample_val,
200 sample_val => sample_val,
200 sample_time => sample_time,
201 sample_time => sample_time,
201 clk => clk,
202 clk => clk,
202 rstn => rstn,
203 rstn => rstn,
203 data_shaping_SP0 => data_shaping_SP0,
204 data_shaping_SP0 => data_shaping_SP0,
204 data_shaping_SP1 => data_shaping_SP1,
205 data_shaping_SP1 => data_shaping_SP1,
205 data_shaping_R0 => data_shaping_R0,
206 data_shaping_R0 => data_shaping_R0,
206 data_shaping_R1 => data_shaping_R1,
207 data_shaping_R1 => data_shaping_R1,
207 data_shaping_R2 => data_shaping_R2,
208 data_shaping_R2 => data_shaping_R2,
208 sample_f0_val => sample_f0_val,
209 sample_f0_val => sample_f0_val,
209 sample_f1_val => sample_f1_val,
210 sample_f1_val => sample_f1_val,
210 sample_f2_val => sample_f2_val,
211 sample_f2_val => sample_f2_val,
211 sample_f3_val => sample_f3_val,
212 sample_f3_val => sample_f3_val,
212 sample_f0_wdata => sample_f0_data,
213 sample_f0_wdata => sample_f0_data,
213 sample_f1_wdata => sample_f1_data,
214 sample_f1_wdata => sample_f1_data,
214 sample_f2_wdata => sample_f2_data,
215 sample_f2_wdata => sample_f2_data,
215 sample_f3_wdata => sample_f3_data,
216 sample_f3_wdata => sample_f3_data,
216 sample_f0_time => sample_f0_time,
217 sample_f0_time => sample_f0_time,
217 sample_f1_time => sample_f1_time,
218 sample_f1_time => sample_f1_time,
218 sample_f2_time => sample_f2_time,
219 sample_f2_time => sample_f2_time,
219 sample_f3_time => sample_f3_time
220 sample_f3_time => sample_f3_time
220 );
221 );
221
222
222 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
223 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
224 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
224 GENERIC MAP (
225 GENERIC MAP (
225 nb_data_by_buffer_size => nb_data_by_buffer_size,
226 nb_data_by_buffer_size => nb_data_by_buffer_size,
226 nb_snapshot_param_size => nb_snapshot_param_size,
227 nb_snapshot_param_size => nb_snapshot_param_size,
227 delta_vector_size => delta_vector_size,
228 delta_vector_size => delta_vector_size,
228 delta_vector_size_f0_2 => delta_vector_size_f0_2,
229 delta_vector_size_f0_2 => delta_vector_size_f0_2,
229 pindex => pindex,
230 pindex => pindex,
230 paddr => paddr,
231 paddr => paddr,
231 pmask => pmask,
232 pmask => pmask,
232 pirq_ms => pirq_ms,
233 pirq_ms => pirq_ms,
233 pirq_wfp => pirq_wfp,
234 pirq_wfp => pirq_wfp,
234 top_lfr_version => top_lfr_version)
235 top_lfr_version => top_lfr_version)
235 PORT MAP (
236 PORT MAP (
236 HCLK => clk,
237 HCLK => clk,
237 HRESETn => rstn,
238 HRESETn => rstn,
238 apbi => apbi,
239 apbi => apbi,
239 apbo => apbo,
240 apbo => apbo,
240
241
241 -- run_ms => OPEN,--run_ms,
242 -- run_ms => OPEN,--run_ms,
242
243
243 ready_matrix_f0 => ready_matrix_f0,
244 ready_matrix_f0 => ready_matrix_f0,
244 ready_matrix_f1 => ready_matrix_f1,
245 ready_matrix_f1 => ready_matrix_f1,
245 ready_matrix_f2 => ready_matrix_f2,
246 ready_matrix_f2 => ready_matrix_f2,
246 error_buffer_full => error_buffer_full,
247 error_buffer_full => error_buffer_full,
247 error_input_fifo_write => error_input_fifo_write,
248 error_input_fifo_write => error_input_fifo_write,
248 status_ready_matrix_f0 => status_ready_matrix_f0,
249 status_ready_matrix_f0 => status_ready_matrix_f0,
249 status_ready_matrix_f1 => status_ready_matrix_f1,
250 status_ready_matrix_f1 => status_ready_matrix_f1,
250 status_ready_matrix_f2 => status_ready_matrix_f2,
251 status_ready_matrix_f2 => status_ready_matrix_f2,
251
252
252 matrix_time_f0 => matrix_time_f0,
253 matrix_time_f0 => matrix_time_f0,
253 matrix_time_f1 => matrix_time_f1,
254 matrix_time_f1 => matrix_time_f1,
254 matrix_time_f2 => matrix_time_f2,
255 matrix_time_f2 => matrix_time_f2,
255
256
256 addr_matrix_f0 => addr_matrix_f0,
257 addr_matrix_f0 => addr_matrix_f0,
257 addr_matrix_f1 => addr_matrix_f1,
258 addr_matrix_f1 => addr_matrix_f1,
258 addr_matrix_f2 => addr_matrix_f2,
259 addr_matrix_f2 => addr_matrix_f2,
259
260
260 length_matrix_f0 => length_matrix_f0,
261 length_matrix_f0 => length_matrix_f0,
261 length_matrix_f1 => length_matrix_f1,
262 length_matrix_f1 => length_matrix_f1,
262 length_matrix_f2 => length_matrix_f2,
263 length_matrix_f2 => length_matrix_f2,
263 status_new_err => status_new_err,
264 status_new_err => status_new_err,
264 data_shaping_BW => data_shaping_BW,
265 data_shaping_BW => data_shaping_BW,
265 data_shaping_SP0 => data_shaping_SP0,
266 data_shaping_SP0 => data_shaping_SP0,
266 data_shaping_SP1 => data_shaping_SP1,
267 data_shaping_SP1 => data_shaping_SP1,
267 data_shaping_R0 => data_shaping_R0,
268 data_shaping_R0 => data_shaping_R0,
268 data_shaping_R1 => data_shaping_R1,
269 data_shaping_R1 => data_shaping_R1,
269 data_shaping_R2 => data_shaping_R2,
270 data_shaping_R2 => data_shaping_R2,
270 delta_snapshot => delta_snapshot,
271 delta_snapshot => delta_snapshot,
271 delta_f0 => delta_f0,
272 delta_f0 => delta_f0,
272 delta_f0_2 => delta_f0_2,
273 delta_f0_2 => delta_f0_2,
273 delta_f1 => delta_f1,
274 delta_f1 => delta_f1,
274 delta_f2 => delta_f2,
275 delta_f2 => delta_f2,
275 nb_data_by_buffer => nb_data_by_buffer,
276 nb_data_by_buffer => nb_data_by_buffer,
276 nb_snapshot_param => nb_snapshot_param,
277 nb_snapshot_param => nb_snapshot_param,
277 enable_f0 => enable_f0,
278 enable_f0 => enable_f0,
278 enable_f1 => enable_f1,
279 enable_f1 => enable_f1,
279 enable_f2 => enable_f2,
280 enable_f2 => enable_f2,
280 enable_f3 => enable_f3,
281 enable_f3 => enable_f3,
281 burst_f0 => burst_f0,
282 burst_f0 => burst_f0,
282 burst_f1 => burst_f1,
283 burst_f1 => burst_f1,
283 burst_f2 => burst_f2,
284 burst_f2 => burst_f2,
284 run => OPEN,
285 run => OPEN,
285 start_date => start_date,
286 start_date => start_date,
286 wfp_status_buffer_ready => wfp_status_buffer_ready,
287 wfp_status_buffer_ready => wfp_status_buffer_ready,
287 wfp_addr_buffer => wfp_addr_buffer,
288 wfp_addr_buffer => wfp_addr_buffer,
288 wfp_length_buffer => wfp_length_buffer,
289 wfp_length_buffer => wfp_length_buffer,
289
290
290 wfp_ready_buffer => wfp_ready_buffer,
291 wfp_ready_buffer => wfp_ready_buffer,
291 wfp_buffer_time => wfp_buffer_time,
292 wfp_buffer_time => wfp_buffer_time,
292 wfp_error_buffer_full => wfp_error_buffer_full,
293 wfp_error_buffer_full => wfp_error_buffer_full,
293 -------------------------------------------------------------------------
294 -------------------------------------------------------------------------
294 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
295 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
295 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
296 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
296 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
297 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
297 sample_f3_valid => sample_f3_val,
298 sample_f3_valid => sample_f3_val,
298 debug_vector => apb_reg_debug_vector
299 debug_vector => apb_reg_debug_vector
299 );
300 );
300
301
301 -----------------------------------------------------------------------------
302 -----------------------------------------------------------------------------
302 -----------------------------------------------------------------------------
303 -----------------------------------------------------------------------------
303 lpp_waveform_1 : lpp_waveform
304 lpp_waveform_1 : lpp_waveform
304 GENERIC MAP (
305 GENERIC MAP (
305 tech => tech,
306 tech => tech,
306 data_size => 6*16,
307 data_size => 6*16,
307 nb_data_by_buffer_size => nb_data_by_buffer_size,
308 nb_data_by_buffer_size => nb_data_by_buffer_size,
308 nb_snapshot_param_size => nb_snapshot_param_size,
309 nb_snapshot_param_size => nb_snapshot_param_size,
309 delta_vector_size => delta_vector_size,
310 delta_vector_size => delta_vector_size,
310 delta_vector_size_f0_2 => delta_vector_size_f0_2
311 delta_vector_size_f0_2 => delta_vector_size_f0_2
311 )
312 )
312 PORT MAP (
313 PORT MAP (
313 clk => clk,
314 clk => clk,
314 rstn => rstn,
315 rstn => rstn,
315
316
316 reg_run => '1',--run,
317 reg_run => '1',--run,
317 reg_start_date => start_date,
318 reg_start_date => start_date,
318 reg_delta_snapshot => delta_snapshot,
319 reg_delta_snapshot => delta_snapshot,
319 reg_delta_f0 => delta_f0,
320 reg_delta_f0 => delta_f0,
320 reg_delta_f0_2 => delta_f0_2,
321 reg_delta_f0_2 => delta_f0_2,
321 reg_delta_f1 => delta_f1,
322 reg_delta_f1 => delta_f1,
322 reg_delta_f2 => delta_f2,
323 reg_delta_f2 => delta_f2,
323
324
324 enable_f0 => enable_f0,
325 enable_f0 => enable_f0,
325 enable_f1 => enable_f1,
326 enable_f1 => enable_f1,
326 enable_f2 => enable_f2,
327 enable_f2 => enable_f2,
327 enable_f3 => enable_f3,
328 enable_f3 => enable_f3,
328 burst_f0 => burst_f0,
329 burst_f0 => burst_f0,
329 burst_f1 => burst_f1,
330 burst_f1 => burst_f1,
330 burst_f2 => burst_f2,
331 burst_f2 => burst_f2,
331
332
332 nb_data_by_buffer => nb_data_by_buffer,
333 nb_data_by_buffer => nb_data_by_buffer,
333 nb_snapshot_param => nb_snapshot_param,
334 nb_snapshot_param => nb_snapshot_param,
334 status_new_err => status_new_err,
335 status_new_err => status_new_err,
335
336
336 status_buffer_ready => wfp_status_buffer_ready,
337 status_buffer_ready => wfp_status_buffer_ready,
337 addr_buffer => wfp_addr_buffer,
338 addr_buffer => wfp_addr_buffer,
338 length_buffer => wfp_length_buffer,
339 length_buffer => wfp_length_buffer,
339 ready_buffer => wfp_ready_buffer,
340 ready_buffer => wfp_ready_buffer,
340 buffer_time => wfp_buffer_time,
341 buffer_time => wfp_buffer_time,
341 error_buffer_full => wfp_error_buffer_full,
342 error_buffer_full => wfp_error_buffer_full,
342
343
343 coarse_time => coarse_time,
344 coarse_time => coarse_time,
344 -- fine_time => fine_time,
345 -- fine_time => fine_time,
345
346
346 --f0
347 --f0
347 data_f0_in_valid => sample_f0_val,
348 data_f0_in_valid => sample_f0_val,
348 data_f0_in => sample_f0_data,
349 data_f0_in => sample_f0_data,
349 data_f0_time => sample_f0_time,
350 data_f0_time => sample_f0_time,
350 --f1
351 --f1
351 data_f1_in_valid => sample_f1_val,
352 data_f1_in_valid => sample_f1_val,
352 data_f1_in => sample_f1_data,
353 data_f1_in => sample_f1_data,
353 data_f1_time => sample_f1_time,
354 data_f1_time => sample_f1_time,
354 --f2
355 --f2
355 data_f2_in_valid => sample_f2_val,
356 data_f2_in_valid => sample_f2_val,
356 data_f2_in => sample_f2_data,
357 data_f2_in => sample_f2_data,
357 data_f2_time => sample_f2_time,
358 data_f2_time => sample_f2_time,
358 --f3
359 --f3
359 data_f3_in_valid => sample_f3_val,
360 data_f3_in_valid => sample_f3_val,
360 data_f3_in => sample_f3_data,
361 data_f3_in => sample_f3_data,
361 data_f3_time => sample_f3_time,
362 data_f3_time => sample_f3_time,
362 -- OUTPUT -- DMA interface
363 -- OUTPUT -- DMA interface
363
364
364 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
365 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
365 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
366 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
366 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
367 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
367 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
368 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
368 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
369 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
369 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
370 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
370 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
371 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
371 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
372 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
372
373
373 );
374 );
374
375
375 -----------------------------------------------------------------------------
376 -----------------------------------------------------------------------------
376 -- Matrix Spectral
377 -- Matrix Spectral
377 -----------------------------------------------------------------------------
378 -----------------------------------------------------------------------------
378 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
379 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
379 NOT(sample_f0_val) & NOT(sample_f0_val);
380 NOT(sample_f0_val) & NOT(sample_f0_val);
380 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
381 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
381 NOT(sample_f1_val) & NOT(sample_f1_val);
382 NOT(sample_f1_val) & NOT(sample_f1_val);
382 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
383 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
383 NOT(sample_f2_val) & NOT(sample_f2_val);
384 NOT(sample_f2_val) & NOT(sample_f2_val);
384
385
385
386
386 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
387 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
387 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
388 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
388 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
389 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
389
390
390 -----------------------------------------------------------------------------
391 -----------------------------------------------------------------------------
391 lpp_lfr_ms_1 : lpp_lfr_ms
392 lpp_lfr_ms_1 : lpp_lfr_ms
392 GENERIC MAP (
393 GENERIC MAP (
393 Mem_use => Mem_use,
394 Mem_use => Mem_use,
394 WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
395 WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
395 PORT MAP (
396 PORT MAP (
396 clk => clk,
397 clk => clk,
397 rstn => rstn,
398 rstn => rstn,
398
399
399 run => '1',--run_ms,
400 run => '1',--run_ms,
400
401
401 start_date => start_date,
402 start_date => start_date,
402
403
403 coarse_time => coarse_time,
404 coarse_time => coarse_time,
404
405
405 sample_f0_wen => sample_f0_wen,
406 sample_f0_wen => sample_f0_wen,
406 sample_f0_wdata => sample_f0_wdata,
407 sample_f0_wdata => sample_f0_wdata,
407 sample_f0_time => sample_f0_time,
408 sample_f0_time => sample_f0_time,
408 sample_f1_wen => sample_f1_wen,
409 sample_f1_wen => sample_f1_wen,
409 sample_f1_wdata => sample_f1_wdata,
410 sample_f1_wdata => sample_f1_wdata,
410 sample_f1_time => sample_f1_time,
411 sample_f1_time => sample_f1_time,
411 sample_f2_wen => sample_f2_wen,
412 sample_f2_wen => sample_f2_wen,
412 sample_f2_wdata => sample_f2_wdata,
413 sample_f2_wdata => sample_f2_wdata,
413 sample_f2_time => sample_f2_time,
414 sample_f2_time => sample_f2_time,
414
415
415 --DMA
416 --DMA
416 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
417 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
417 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
418 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
418 dma_fifo_ren => dma_fifo_ren(4), -- IN
419 dma_fifo_ren => dma_fifo_ren(4), -- IN
419 dma_buffer_new => dma_buffer_new(4), -- OUT
420 dma_buffer_new => dma_buffer_new(4), -- OUT
420 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
421 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
421 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
422 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
422 dma_buffer_full => dma_buffer_full(4), -- IN
423 dma_buffer_full => dma_buffer_full(4), -- IN
423 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
424 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
424
425
425
426
426
427
427 --REG
428 --REG
428 ready_matrix_f0 => ready_matrix_f0,
429 ready_matrix_f0 => ready_matrix_f0,
429 ready_matrix_f1 => ready_matrix_f1,
430 ready_matrix_f1 => ready_matrix_f1,
430 ready_matrix_f2 => ready_matrix_f2,
431 ready_matrix_f2 => ready_matrix_f2,
431 error_buffer_full => error_buffer_full,
432 error_buffer_full => error_buffer_full,
432 error_input_fifo_write => error_input_fifo_write,
433 error_input_fifo_write => error_input_fifo_write,
433
434
434 status_ready_matrix_f0 => status_ready_matrix_f0,
435 status_ready_matrix_f0 => status_ready_matrix_f0,
435 status_ready_matrix_f1 => status_ready_matrix_f1,
436 status_ready_matrix_f1 => status_ready_matrix_f1,
436 status_ready_matrix_f2 => status_ready_matrix_f2,
437 status_ready_matrix_f2 => status_ready_matrix_f2,
437 addr_matrix_f0 => addr_matrix_f0,
438 addr_matrix_f0 => addr_matrix_f0,
438 addr_matrix_f1 => addr_matrix_f1,
439 addr_matrix_f1 => addr_matrix_f1,
439 addr_matrix_f2 => addr_matrix_f2,
440 addr_matrix_f2 => addr_matrix_f2,
440
441
441 length_matrix_f0 => length_matrix_f0,
442 length_matrix_f0 => length_matrix_f0,
442 length_matrix_f1 => length_matrix_f1,
443 length_matrix_f1 => length_matrix_f1,
443 length_matrix_f2 => length_matrix_f2,
444 length_matrix_f2 => length_matrix_f2,
444
445
445 matrix_time_f0 => matrix_time_f0,
446 matrix_time_f0 => matrix_time_f0,
446 matrix_time_f1 => matrix_time_f1,
447 matrix_time_f1 => matrix_time_f1,
447 matrix_time_f2 => matrix_time_f2,
448 matrix_time_f2 => matrix_time_f2,
448
449
449 debug_vector => debug_vector_ms);
450 debug_vector => debug_vector_ms);
450
451
451 -----------------------------------------------------------------------------
452 -----------------------------------------------------------------------------
452 PROCESS (clk, rstn)
453 PROCESS (clk, rstn)
453 BEGIN
454 BEGIN
454 IF rstn = '0' THEN
455 IF rstn = '0' THEN
455 dma_fifo_data_forced_gen <= X"00040003";
456 dma_fifo_data_forced_gen <= X"00040003";
456 ELSIF clk'event AND clk = '1' THEN
457 ELSIF clk'event AND clk = '1' THEN
457 IF dma_fifo_ren(0) = '0' THEN
458 IF dma_fifo_ren(0) = '0' THEN
458 CASE dma_fifo_data_forced_gen IS
459 CASE dma_fifo_data_forced_gen IS
459 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
460 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
460 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
461 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
461 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
462 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
462 WHEN OTHERS => NULL;
463 WHEN OTHERS => NULL;
463 END CASE;
464 END CASE;
464 END IF;
465 END IF;
465 END IF;
466 END IF;
466 END PROCESS;
467 END PROCESS;
467
468
468 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
469 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
469 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
470 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
470 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
471 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
471 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
472 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
472 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
473 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
473
474
474 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
475 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
475
476
476 DMA_SubSystem_1 : DMA_SubSystem
477 DMA_SubSystem_1 : DMA_SubSystem
477 GENERIC MAP (
478 GENERIC MAP (
478 hindex => hindex,
479 hindex => hindex,
479 CUSTOM_DMA => 1)
480 CUSTOM_DMA => 1)
480 PORT MAP (
481 PORT MAP (
481 clk => clk,
482 clk => clk,
482 rstn => rstn,
483 rstn => rstn,
483 run => '1',--run_dma,
484 run => '1',--run_dma,
484 ahbi => ahbi,
485 ahbi => ahbi,
485 ahbo => ahbo,
486 ahbo => ahbo,
486
487
487 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
488 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
488 fifo_data => dma_fifo_data_debug, --fifo_data,
489 fifo_data => dma_fifo_data_debug, --fifo_data,
489 fifo_ren => dma_fifo_ren, --fifo_ren,
490 fifo_ren => dma_fifo_ren, --fifo_ren,
490
491
491 buffer_new => dma_buffer_new, --buffer_new,
492 buffer_new => dma_buffer_new, --buffer_new,
492 buffer_addr => dma_buffer_addr, --buffer_addr,
493 buffer_addr => dma_buffer_addr, --buffer_addr,
493 buffer_length => dma_buffer_length, --buffer_length,
494 buffer_length => dma_buffer_length, --buffer_length,
494 buffer_full => dma_buffer_full, --buffer_full,
495 buffer_full => dma_buffer_full, --buffer_full,
495 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
496 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
496 grant_error => dma_grant_error,
497 grant_error => dma_grant_error,
497 debug_vector => debug_vector(8 DOWNTO 0)
498 debug_vector => debug_vector(8 DOWNTO 0)
498 ); --grant_error);
499 ); --grant_error);
499
500
500 -----------------------------------------------------------------------------
501 -----------------------------------------------------------------------------
501 -- OBSERVATION for SIMULATION
502 -- OBSERVATION for SIMULATION
502 all_channel_sim: FOR I IN 0 TO 5 GENERATE
503 all_channel_sim: FOR I IN 0 TO 5 GENERATE
503 PROCESS (clk, rstn)
504 PROCESS (clk, rstn)
504 BEGIN -- PROCESS
505 BEGIN -- PROCESS
505 IF rstn = '0' THEN -- asynchronous reset (active low)
506 IF rstn = '0' THEN -- asynchronous reset (active low)
506 sample_f0_data_sim(I) <= (OTHERS => '0');
507 sample_f0_data_sim(I) <= (OTHERS => '0');
507 sample_f1_data_sim(I) <= (OTHERS => '0');
508 sample_f1_data_sim(I) <= (OTHERS => '0');
508 sample_f2_data_sim(I) <= (OTHERS => '0');
509 sample_f2_data_sim(I) <= (OTHERS => '0');
509 sample_f3_data_sim(I) <= (OTHERS => '0');
510 sample_f3_data_sim(I) <= (OTHERS => '0');
510 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
511 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
511 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
512 IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
512 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
513 IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
513 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
514 IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
514 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
515 IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
515 END IF;
516 END IF;
516 END PROCESS;
517 END PROCESS;
517 END GENERATE all_channel_sim;
518 END GENERATE all_channel_sim;
518 -----------------------------------------------------------------------------
519 -----------------------------------------------------------------------------
519
520
520 END beh;
521 END beh;
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